Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate, wherein the substrate comprises a display area and a peripheral area at least partially surrounding the display area; a first power line; and a plurality of sub-pixels. The first power line located in the peripheral area comprises the first part corresponding to the central area and the second part corresponding to the edge area, and the second part of the first power line corresponding to the edge area is connected with the sub-pixels arranged in the step shape in the edge area. Therefore, the length of the wires, connected with the first power lines, of the sub-pixel circuits of the sub-pixels in the edge area can be reduced, for example, the length of the first power lines which are electrically connected with the sub-pixel circuits and are switched in the row direction is saved; in this way, the difference between the voltages provided by the power lines and received by the sub-pixel circuits in the edge area and the sub-pixel circuits in the central area can be reduced, and then the effect of improving the brightness uniformity of the display panel is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] A display panel is a device with display function.

[0003] A display panel includes a substrate and a plurality of sub-pixels located on the substrate. The plurality of sub-pixels can emit light and realize a display function. Each sub-pixel includes a sub-pixel circuit and a light-emitting element.

[0004] However, in the above display panel, the voltages provided by the power lines received by the sub-pixel circuits in different areas vary greatly, resulting in poor brightness uniformity of the display panel. Summary of the Invention

[0005] The embodiments of the present application provide a display panel and a display device. The technical solution is as follows:

[0006] According to one aspect of the present application, a display panel is provided, comprising:

[0007] a substrate, the substrate comprising a display area and a peripheral area at least partially surrounding the display area, the peripheral area comprising a first peripheral area located on a first side of the display area, the display area comprising a central area and an edge area located on at least one side of the central area in a first direction;

[0008] a plurality of sub-pixels located on one side of the substrate and in the display area, at least one of the plurality of sub-pixels comprising a sub-pixel circuit and a light-emitting element, the sub-pixel circuit being configured to drive the light-emitting element, the plurality of sub-pixels being arranged into a plurality of sub-pixel rows and a plurality of sub-pixel columns, the first direction being a row direction of the sub-pixel rows, the column direction of the sub-pixel columns being a second direction, and in a portion of the sub-pixel rows close to the first peripheral area, the number of sub-pixels in each sub-pixel row located in the edge area gradually decreases along a direction close to the first peripheral area;

[0009] A first power line is located in the first peripheral area, and the first power line includes a first portion corresponding to the central area and a second portion corresponding to the at least one edge area, the first portion is connected to the first power sub-line in the central area, and the second portion is connected to the first power sub-line in the edge area.

[0010] Optionally, an edge of the second portion of the first power line close to the display area is a stepped edge, and some of the sub-pixel rows are arranged in a stepped shape and correspond to the stepped edge of the first power line.

[0011] Optionally, the stepped edge includes a plurality of continuous stepped edges, each of the stepped edges corresponds to a sub-pixel row in the partial sub-pixel rows, and among the plurality of stepped edges, the difference between the target distances of any two step edges ranges from 0 nanometers to 200 nanometers, and the target distance of the step edge is the shortest distance between the step edge and the edge of the corresponding sub-pixel row.

[0012] Optionally, the first power line includes a first sublayer and a second sublayer, the second sublayer is located along a side of the first sublayer away from the substrate, and the second portion of the first power line is located in the second sublayer.

[0013] Optionally, the first part of the first power line includes a first power first sub-section and a first power second sub-section, the first power first sub-section and the first power second sub-section are electrically connected through a first via, the first power first sub-section is located in the first sub-layer, and the first power second sub-section is located in the second sub-layer.

[0014] Optionally, the first power source first subsection includes a first branch and a second branch, and the first branch and the second branch are symmetrical with respect to a center line passing through the center of the display area.

[0015] Optionally, the peripheral area further includes a second peripheral area located on a side of the display area other than the first side, and the first peripheral area is connected to the second peripheral area;

[0016] The display panel also includes a second power line, which includes a second power first sub-section and a second power second sub-section. The second power second sub-section is located in the first peripheral area, and the second power first sub-section is at least located in the second peripheral area and at least partially surrounds the display area.

[0017] Optionally, the second power line further includes a second power third sub-portion in a grid shape, the second power third sub-portion is located in the second peripheral area and at least partially surrounds the display area;

[0018] The second power line further includes a grid-shaped second power fourth sub-section located in the display area, and the second power fourth sub-section is electrically connected to the second power third sub-section.

[0019] Optionally, the second power supply fourth sub-section includes a plurality of second power supply sub-lines, which extend along the second direction and are arranged along the first direction. The plurality of second power supply sub-lines include two adjacent second power supply sub-lines located in two adjacent sub-pixel columns. In the edge area, one end of each of the two adjacent second power supply sub-lines is electrically connected to the second power supply first sub-section, and the other end is electrically connected to the second power supply third sub-section.

[0020] Optionally, the second power supply fourth sub-section includes a plurality of second power supply auxiliary lines extending along the first direction and arranged along the second direction, the plurality of second power supply auxiliary lines are electrically connected to the plurality of second power supply sub-lines and form the grid-shaped second power supply fourth sub-section, the plurality of second power supply auxiliary lines and the plurality of second power supply sub-lines are located in different layers, and the plurality of second power supply auxiliary lines are electrically connected to the second power supply third sub-section.

[0021] Optionally, the display panel further includes a plurality of first connection lines, the plurality of first connection lines are located in the first peripheral area, and one end of one of the first connection lines is connected to the two adjacent second power sub-lines, and the other end is electrically connected to the second power first sub-section.

[0022] Optionally, the display panel includes a first conductive pattern, the first conductive pattern includes the first connecting line and the second power sub-line, and the line width of the first connecting line is greater than twice the line width of the second power sub-line.

[0023] Optionally, the display panel also includes a second conductive pattern, the second conductive pattern includes a second connecting line and the second power supply first sub-section, one end of the second connecting line is connected to the second power supply first sub-section, and the other end is connected to the first connecting line through a second via, and the size of the second via in the line width direction of the first connecting line is larger than the line width of the second power sub-line.

[0024] Optionally, the second power line further includes a second power fifth subsection, the second power fifth subsection being located at least in the second peripheral area and at least partially surrounding the display area, the second power fifth subsection being located on a side of the second power first subsection away from the substrate, and the second power fifth subsection being electrically connected to the second power first subsection;

[0025] The third subsection of the second power supply is electrically connected to the fifth subsection of the second power supply through at least one target wiring, and the at least one target wiring is located in the second peripheral area and at least on the second side of the display area, and the second side and the first side are two opposite sides of the display area.

[0026] Optionally, the display panel includes a plurality of first power sub-lines, which extend along the second direction and overlap and connect with the plurality of sub-pixel columns respectively. The first power sub-lines are connected to the second portion and form an integrated structure.

[0027] According to another aspect of the present application, a display device is provided, comprising any one of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 is a structural diagram of a display panel provided in an embodiment of the present application;

[0030] Figure 2 yes Figure 1 A schematic structural diagram of a partial area of ​​a display panel is shown;

[0031] Figure 3 yes Figure 2 A schematic diagram of an enlarged structure of a partial area of ​​the display panel shown;

[0032] Figure 4 is a structural diagram of a display panel provided in an embodiment of the present application;

[0033] Figure 5 yes Figure 4 A schematic structural diagram of a portion of the display panel shown;

[0034] Figure 6 is a structural diagram of another display panel provided in an embodiment of the present application;

[0035] Figure 7 yes Figure 6 A schematic diagram of an enlarged structure of a partial area of ​​the display panel shown;

[0036] Figure 8 yes Figure 6 Another schematic diagram of the enlarged structure of a partial area is shown;

[0037] Figure 9 yes Figure 6 An enlarged structural schematic diagram of a partial area of ​​a display panel is shown;

[0038] Figure 10 yes Figure 8A schematic diagram of an enlarged structure of a partial area of ​​a display panel is shown;

[0039] Figure 11 yes Figure 10 A schematic structural diagram of a film layer in a display panel shown;

[0040] Figure 12 yes Figure 10 Another structural diagram of the display panel shown;

[0041] Figure 13 yes Figure 10 A schematic diagram of the structure of another film layer in the display panel shown;

[0042] Figure 14 yes Figure 6 A schematic structural diagram of a film layer in a display panel shown;

[0043] Figure 15 yes Figure 6 A schematic diagram of the structure of another film layer in the display panel shown;

[0044] Figure 16 yes Figure 6 Another schematic diagram of a partial area enlarged structure of the display panel shown;

[0045] Figure 17 yes Figure 8 Another schematic diagram of an enlarged structure of a partial area;

[0046] Figure 18 yes Figure 17 Schematic diagram of the structure of a membrane layer;

[0047] Figure 19 yes Figure 17 Schematic diagram of the structure of another membrane layer;

[0048] Figure 20 yes Figure 17 Schematic diagram of the structure of another membrane layer;

[0049] Figure 21 is a structural schematic diagram of a display device provided in an embodiment of the present application;

[0050] Figure 22 yes Figure 21 A schematic diagram of an enlarged structure of a partial area of ​​the display device shown;

[0051] Figure 23 yes Figure 22 A schematic diagram of an enlarged structure of a partial area of ​​the display device shown;

[0052] Figure 24 yes Figure 23The figure shows an enlarged structural diagram of a partial area of ​​a display device.

[0053] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0055] Figure 1 is a structural diagram of a display panel provided in an embodiment of the present application, Figure 2 yes Figure 1 A schematic diagram of a structure of a partial area of ​​a display panel shown in FIG. Figure 2 for Figure 1 Structural diagram of region q1 in the middle), Figure 3 yes Figure 2 Please refer to the enlarged structural diagram of a part of the display panel shown in the figure. Figure 1 、 Figure 2 and Figure 3 The display panel includes a display area 11 and a peripheral area 12 surrounding the display area 11. The display area 11 has a plurality of sub-pixels 111 ( Figure 2 as well as Figure 3 The sub-pixel 111 shown in the figure may be at least part of the sub-pixel circuitry within the sub-pixel. Each sub-pixel may also include a light-emitting element and other structures, which are not limited in this embodiment of the present application. A first power line 13 and a second power line 14 are provided in the peripheral region 12 of the display panel. At the corners of the display panel, such as the left and right lower corners, this region may be referred to as a rounded corner region qc1. Multiple rows of sub-pixels 111 within the rounded corner region qc1 are arranged in a stepped manner, with the number of sub-pixels in the multiple rows of sub-pixels 111 gradually decreasing as they approach the first power line 13. The first power line 13 and the second power line 14 are located outside the bottom row of sub-pixels 111, i.e., on the side of the bottom row of sub-pixels 111 away from the other sub-pixels 111, and are electrically connected to the multiple sub-pixels 111. The first power line 13 and the second power line 14 are used to provide a power supply voltage provided by a flexible printed circuit board (FPC) to the multiple sub-pixels 111.

[0056] However, in the display panel of the above embodiment, the first power line 13 only extends to position A outside the rounded corner area qc1. Since there are multiple columns of sub-pixels 111 arranged in a stepped manner on the left side of position A, there is a large distance between position A and the edge of the display area 11. In addition, there is no first power line 13 below the multiple columns of sub-pixels 111 arranged in a stepped manner on the left side of position A, that is, the side of position A away from the center line v1. Therefore, the multiple columns of sub-pixels 111 need to first be connected to the line network of the power sub-lines located in the display area 11, and then cross to the right side of position A through the line network, and be connected to the first power line 13 below through the line network on the right side of position A. This will obviously increase the length of the connecting line between the sub-pixel 111 and the first power line 13, which will cause the voltage output by the first power line 13 to be lost. On the one hand, it will lead to increased power consumption of the display panel, and on the other hand, it will also lead to poor brightness uniformity in different areas of the display panel.

[0057] The embodiments of the present application provide a display panel and a display device, which can solve some problems existing in the above-mentioned related technologies.

[0058] Figure 4 is a structural diagram of a display panel provided in an embodiment of the present application, Figure 5 yes Figure 4 A structural diagram of a portion of the display panel shown in FIG. Figure 5 for Figure 4 A structural diagram of the middle region q2).

[0059] Please refer to Figure 4 and Figure 5 The display panel includes: a substrate 21, the substrate 21 includes a display area aa and a peripheral area wa at least partially surrounding the display area aa, the peripheral area wa includes a first peripheral area wa1 located on a first side ac1 of the display area aa, the display area aa includes a central area aa1 and an edge area aa2 located on at least one side of the central area aa1 in a first direction f1.

[0060] A plurality of sub-pixels sp are located on one side of the substrate 21 and in the display area aa. At least one of the plurality of sub-pixels sp includes a sub-pixel circuit and a light-emitting element. The sub-pixel circuit is configured to drive the light-emitting element. The plurality of sub-pixels sp are arranged into a plurality of sub-pixel rows h and a plurality of sub-pixel columns j. The first direction f1 is the row direction of the sub-pixel rows h, and the column direction of the sub-pixel columns j is the second direction f2. In a portion of the sub-pixel rows h near the first peripheral area wa1, the number of sub-pixels sp in the edge area aa2 of each sub-pixel row h gradually decreases along a direction f3 approaching the first peripheral area wa1. The portion of the sub-pixel rows h near the first peripheral area wa1 refers to a plurality of sub-pixel rows h in which the number of sub-pixels sp in the edge area aa2 gradually decreases along the direction f3. With this structure, the sub-pixel circuits in the plurality of sub-pixel circuit rows h can be arranged in a stepped manner, forming a display screen with rounded corners, thereby improving the user experience.

[0061] The first power line 22 is located in the first peripheral area wa1. The first power line 22 includes a first portion 221 corresponding to the central area aa1 and a second portion 222 corresponding to at least one edge area aa2. The first portion 221 is connected to the first power sub-line 23 in the central area aa1, and the second portion 222 is connected to the first power sub-line 23 in the edge area aa2. Furthermore, the first portion 221 and the second portion 222 of the first power line 22 can be integrally formed. The first peripheral area wa1 can be the lower frame of the display panel.

[0062] Compared to Figure 1 In the display panel shown, the first power line only extends to position A outside the rounded corner area. In the display panel provided in this embodiment, the first power line 22 extends to a position corresponding to at least one edge area aa2 and is connected to the first power sub-line 23 in the edge area aa2, which is equivalent to the first power line 22 extending to the rounded corner area qc2. This shortens the distance between the first power line 22 and the edge of the display area aa, and further shortens the length of the wiring connecting the sub-pixel sp in the edge area aa2 and the first power line 22, thereby reducing the signal loss of the first power line 22 received by these sub-pixels sp.

[0063] To summarize, in the display panel provided in the embodiment of the present application, the first power line located in the peripheral area includes a first part corresponding to the central area and a second part corresponding to the edge area. The second part of the first power line corresponding to the edge area is connected to the sub-pixels arranged in a stepped manner in the edge area, thereby reducing the length of the routing line connecting the sub-pixel circuit of the sub-pixel in the edge area and the first power line. For example, the length of the first power line electrically connected to multiple sub-pixel circuits and connected along the row direction is saved. In this way, the difference in voltage provided by the power line received by the sub-pixel circuit in the edge area and the sub-pixel circuit in the central area can be reduced, thereby achieving the effect of improving the brightness uniformity of the display panel.

[0064] It should be noted that the correspondence between the first portion 221 and the central area aa1 in the embodiments of the present application may mean that the orthographic projection of the first portion 221 along the second direction f2 on the edge adjacent to the display area aa and the first peripheral area wa1 is located on the edge of the central area aa1. Similarly, the correspondence between the second portion 222 and the edge area aa2 may mean that the orthographic projection of the second portion 222 along the second direction f2 on the edge adjacent to the display area aa and the first peripheral area wa1 is located on the edge of the edge area aa2.

[0065] The display panel provided in the embodiments of the present application can be an organic light-emitting diode (OLED) display panel, and the light-emitting elements are OLEDs. An OLED display panel includes multiple OLEDs arranged in an array, and each sub-pixel circuit can be used to drive one OLED. The voltage difference between the high-level VDD and low-level VSS connected to the OLED is one of the factors affecting screen brightness. Therefore, to increase screen brightness, the voltage difference between the high-level VDD and low-level VSS connected to the OLED must meet the requirements. However, loads such as resistance and capacitance on the display panel can cause a difference between the output voltage and the voltage received by the OLED. This results in a higher voltage being output to the sub-pixel circuit to compensate for voltage losses within the display panel. However, this undoubtedly increases the power consumption of the screen, and the voltage loss also affects the uniformity of the screen brightness. The display panel provided in the embodiments of the present application, by extending the first power line to the corresponding position of the edge area, allows the sub-pixel circuits of some sub-pixels in the edge area to be connected to the first power line there. This reduces the voltage loss in the sub-pixel circuits in the display area, thereby achieving the effect of reducing the power consumption of the display panel.

[0066] Of course, the display panel provided in the embodiment of the present application may also be other types of display panels, and the embodiment of the present application is not limited to this.

[0067] Figure 6is a structural diagram of another display panel provided in an embodiment of the present application. Figure 7 yes Figure 6 A schematic diagram of an enlarged structure of a partial area of ​​a display panel ( Figure 7 yes Figure 8 (enlarged diagram of the lower middle frame), Figure 8 yes Figure 6 Another schematic diagram of the enlarged structure of a partial area shown ( Figure 8 yes Figure 6 A schematic diagram of an enlarged structure of the middle area q3) please refer to Figure 6 、 Figure 7 as well as Figure 8 , wherein the edge of the second portion 222 of the first power line 22 on the side close to the display area aa is a stepped edge k, and the aforementioned portion of the sub-pixel rows h close to the first peripheral area wa1 is arranged in a stepped manner and corresponds to the stepped edge k of the first power line 22. This correspondence may mean that the shape of the stepped edge k is similar to the shape of the edge of the portion of the sub-pixel rows h arranged in a stepped manner facing the stepped edge k; or, this correspondence may mean that the stepped edge k includes a plurality of continuous stepped edges k1, the number of the plurality of stepped edges k1 being the same as the number of the portion of the sub-pixel rows h and corresponding one to one, and the sub-pixels of each sub-pixel row h are connected to the first power line 22 at the corresponding stepped edge k1 ( Figure 8 (not shown). Compared to a solution in which the edge of the second portion 222 of the first power line 22 on the side closest to the display area aa is parallel to the first direction f1, the stepped edge solution provided in the embodiment of the present application can reduce the distance between different sub-pixel rows in the edge area aa2 and the first power line 22 in the second direction f2, thereby reducing the voltage difference caused by the difference in the length of the connection line between the sub-pixel sp and the first power line 22, thereby further improving the brightness uniformity of different areas of the display panel.

[0068] Of course, the edge of the second portion 222 of the first power line 22 close to the display area aa may also be an edge parallel to the first direction f1, or the edge of the second portion 222 of the first power line 22 close to the display area aa may also be other shapes, and the embodiment of the present application is not limited to this.

[0069] In an exemplary embodiment, the stepped edge k includes a plurality of continuous stepped edges k1, each of which corresponds to a sub-pixel row h in a portion of the sub-pixel rows h near the first peripheral area wa1. The difference in target distance s1 between any two of the plurality of stepped edges k1 ranges from 0 nanometers to 200 nanometers, and the target distance s1 of the stepped edge k1 is the shortest distance between the stepped edge k1 and the edge of the corresponding sub-pixel row h. In other words, the target distance s1 of any two stepped edges k1 can be equal or close to each other. This can further reduce the voltage difference caused by the difference in length of the connection line between the sub-pixel sp and the first power line 22, thereby improving the brightness uniformity of different areas of the display panel.

[0070] Any stepped edge k1 can overlap with multiple sub-pixel rows h in the second direction f2. Among the multiple sub-pixel rows h overlapping with the stepped edge k1 in the second direction, the sub-pixel row h that is shortest in distance from any stepped edge k1 in the second direction f2 is the sub-pixel row h corresponding to any stepped edge k1.

[0071] In which, each stepped edge k1 can be L-shaped, that is, each stepped edge k1 can include a horizontal side and a hypotenuse, the horizontal side can be parallel to the first direction f1, the hypotenuse can have an angle with the first direction f1 (when the angle is 90 degrees, the hypotenuse is a vertical side), the horizontal side is connected to the hypotenuse, and the target distance s1 of the stepped edge k1 is the distance between the horizontal side and the edge of the corresponding sub-pixel row h in the second direction f2.

[0072] In an exemplary embodiment, the first power line 22 includes a first sublayer 22a and a second sublayer 22b, wherein the second sublayer 22b is located along a side of the first sublayer 22a away from the substrate 21, and the second portion 222 of the first power line 22 is located in the second sublayer 22b. The first portion 221 of the first power line 22 can be located in the first sublayer 22a, or the first portion 221 of the first power line 22 can be located in the second sublayer 22b, or the first portion 221 of the first power line 22 can be located in both the first sublayer 22a and the second sublayer 22b and electrically connected. Exemplarily, the display panel can include a first conductive pattern m1 and a second conductive pattern m2, wherein the first conductive pattern m1 is located on a side of the second conductive pattern m2 away from the substrate 21, the first sublayer 22a is located in the second conductive pattern m2, and the second sublayer 22b is located in the first conductive pattern m1.

[0073] The first conductive pattern m1 may be a second source-drain metal pattern, and the second conductive pattern m2 may be a first source-drain metal pattern. The second source-drain metal pattern and the first source-drain metal pattern may also include gate wiring and source wiring in a sub-pixel circuit, as well as gate and source structures in a thin film transistor (TFT), and the embodiments of the present application are not limited thereto.

[0074] Please refer to Figure 6 as well as Figure 9 , Figure 9 yes Figure 6 An enlarged structural diagram of a partial area of ​​the display panel shown ( Figure 9 yes Figure 6 ), wherein the first portion 221 of the first power line 22 includes a first power first sub-portion 2211 and a first power second sub-portion 2212, the first power first sub-portion 2211 and the first power second sub-portion 2212 are electrically connected via a first via c1, the first power first sub-portion 2211 is located on the first sub-layer 22a, and the first power second sub-portion 2212 is located on the second sub-layer 22b. In this way, a cross-layer electrical connection between the first power first sub-portion 2211 and the first power second sub-portion 2212 located on different layers is achieved. The first power first sub-portion 2211 can be connected to the control component 41 in the display panel to receive a signal transmitted by the control component 41 and transmit the signal to the first power second sub-portion 2212, or send a signal to the control component 41. The control component 41 may include a flexible printed circuit (FPC). The first via c1 may be a via on a film layer between the first power supply first sub-section 2211 and the first power supply second sub-section 2212 . The film layer may include an insulating layer or a planar layer, and this embodiment of the application does not limit this.

[0075] In an exemplary embodiment, please refer to Figure 6 and Figure 7The first sub-portion 2211 of the first power supply includes a first branch g1 and a second branch g2, and the first branch g1 and the second branch g2 are symmetrical with respect to a center line v1 passing through the center r1 of the display area aa. The first branch g1 and the second branch g2 can provide power supply voltage to the sub-pixels sp in two parts of the central area aa1 that are symmetrical with respect to the center line v1. In addition, in an exemplary embodiment, the display area aa includes two edge areas aa2 located on both sides of the central area aa1 in the first direction f1, and the first power line 22 includes two second parts 222 corresponding to the two edge areas aa2. The two second parts 222 can be symmetrical with respect to the center line v1. In this way, the difference in voltage provided by the power line received by the sub-pixels in the edge areas and the sub-pixels in the central area can be reduced in both edge areas aa2, thereby achieving the effect of improving the brightness uniformity of the display panel.

[0076] Optionally, the peripheral area wa also includes a second peripheral area wa2 located on the other side of the display area except the first side ac1, and the first peripheral area wa1 and the second peripheral area wa2 are connected. The display panel also includes a second power line 24, the second power line 24 includes a second power first sub-section 241 and a second power second sub-section 242, the second power second sub-section 242 is located in the first peripheral area wa1, and the second power first sub-section 241 is at least located in the second peripheral area wa2 and at least partially surrounds the display area aa. The second power first sub-section 241 may also include a portion located in the first peripheral area wa1, and the portion of the second power first sub-section 241 located in the first peripheral area wa1 may be electrically connected to the sub-pixel circuit of the sub-pixel in the edge area aa2. The second power first sub-section 241 may be connected to the control component 41 and receive signals provided by the control component 41, or send signals to the control component 41.

[0077] Alternatively, refer to Figure 6 and Figure 8 The second power line 24 also includes a grid-shaped second power third subsection 243. This second power third subsection 243 is located in the second peripheral area wa2 and at least partially surrounds the display area aa. Compared to a closed second power third subsection 243, this grid-shaped second power third subsection 243 can reduce its impact on other layers in the display panel. This grid-shaped second power third subsection 243 can be used to provide a stable low-level VSS signal to various areas within the display area.

[0078] Please refer to Figure 6 、 Figure 8 as well as Figure 10 , Figure 10 yes Figure 8 A schematic diagram of an enlarged structure of a partial area of ​​a display panel shown in FIG. Figure 10 yes Figure 8A structural diagram of the middle area q5).

[0079] Optionally, the second power line 24 further includes a grid-like fourth second power sub-section 244 located in the display area aa. The fourth second power sub-section 244 is electrically connected to the third second power sub-section 243. The fourth second power sub-section 244 includes a plurality of second power sub-lines 2441 extending along the second direction f2 and arranged along the first direction f1. The plurality of second power sub-lines 2441 include two adjacent second power sub-lines 2441 located in two adjacent sub-pixel columns. In the edge area aa2, each of the two adjacent second power sub-lines 2441 has one end electrically connected to the first second power sub-section 241 and the other end electrically connected to the third second power sub-section 243. The fourth second power sub-section 244 forms a grid-like structure in the display area aa, which reduces line resistance and avoids blocking the light-emitting areas of the sub-pixels.

[0080] In the central area aa1, one end of each of two adjacent second power sub-lines 2441 is electrically connected to the second power second sub-section 242, and the other end is electrically connected to the second power third sub-section 243. The second power second sub-section 242 can be connected to the control component 41 and receive signals provided by the control component 41, or send signals to the control component 41.

[0081] Optionally, the second power supply fourth sub-section 244 includes a plurality of second power supply auxiliary lines 2442 extending along the first direction f1 and arranged along the second direction f2. The plurality of second power supply auxiliary lines 2442 are electrically connected to the plurality of second power supply sub-lines 2441 to form a grid-like second power supply fourth sub-section 244. The plurality of second power supply auxiliary lines 2442 and the plurality of second power supply sub-lines 2441 are located on different layers and are electrically connected to the second power supply third sub-section 243. The second power supply auxiliary lines 2442 may be located within the second conductive pattern m2. The second power supply sub-lines 2441 may be located within the first conductive pattern m1, and furthermore, the second power supply sub-lines 2441 may be located on a side of the second power supply auxiliary lines 2442 away from the substrate 21. The second power supply sub-lines 2441 may not be connected to the sub-pixels sp, but may instead be connected to the grid-like second power supply third sub-section 243 and the second power supply second sub-section 242, but this is not a limitation in this embodiment of the present application.

[0082] It should be noted that the first power line 22 involved in the embodiment of the present application can be used to provide a high level, and the second power line can be used to provide a low level. The voltage of the high level is greater than the voltage of the low level. Exemplarily, the first power line 22 is a VDD power line, and the second power line 24 is a VSS power line. The second power line 24 can cooperate with the first power line 22 to provide a high level voltage and a low level voltage to the sub-pixel sp. This display panel with a VSS line set in the sub-pixel can be a source voltage pixel built-in (vss in panel, SIP) display panel, which can improve the voltage loss of the VSS power line and reduce the brightness difference between different areas of the display panel.

[0083] In an exemplary embodiment, please refer to Figure 10 The display panel further includes a plurality of first connection lines 27 , which are located in the first peripheral area wa1 , and one end of a first connection line 27 is connected to two adjacent second power sub-lines 2441 , and the other end is connected to the second power first sub-portion 241 .

[0084] In this structure, two adjacent second power sub-lines 2441 in the display area aa are connected to a first connecting line 27, and then connected to the second power first sub-section 241 through the first connecting line 27. This can reduce the number of circuits in the first peripheral area wa1, reduce the manufacturing difficulty of the circuits in the first peripheral area wa1, and simplify the circuit structure in the display panel.

[0085] In an exemplary embodiment, the display panel includes a first conductive pattern m1, which includes a first connection line 27 and a second power sub-line 2441. The width of the first connection line 27 is greater than twice the width of the second power sub-line 2441. This can reduce the resistance of the second power sub-line 2441.

[0086] The line width of the routing involved in the embodiment of the present application may refer to the dimension of the routing in a direction perpendicular to the extension direction. For example, the first connection line 27 extends in the second direction f2 along the column direction of the sub-pixel column, and the line width of the first connection line 27 is the dimension in the first direction f1 along the row direction of the sub-pixel circuit row. Similarly, the second connection line 28 extends in the column direction (second direction f2) of the sub-pixel circuit column, and the line width of the first connection line 27 is the dimension in the row direction (first direction f1) of the sub-pixel row. Figure 10 It can be seen that the line width of the first connecting line 27 is greater than the line width of the two second power sub-lines 2441, that is, it is twice the line width of one second power sub-line 2441. Compared with the solution of connecting the second power sub-lines 2441 through a connecting line with a similar line width to the second power sub-line 2441, the present application Figure 10In the illustrated embodiment, the voltage loss provided by the second power supply first sub-section 241 on the first connecting line 27 is reduced, thereby reducing the energy consumption of the display panel. Optionally, the line width of the first connecting line 27 ranges from 4 microns to 20 microns, and the line width of the second power supply sub-line 2441 is approximately 2 microns. In the display panel provided in the embodiment of the present application, the second power supply sub-line 2441 can be electrically connected to the second power supply first sub-section 241 via the first connecting line 27 having a greater line width than the second power supply sub-line 2441.

[0087] Optionally, the display panel further includes a second conductive pattern m2, the second conductive pattern m2 including a second connecting line 28 and a second power first sub-portion 241, one end of the second connecting line 28 is connected to the second power first sub-portion 241 and forms an integral structure, and the other end is connected to the first connecting line 27 through a second via hole c2, and the second via hole c2 is in the line width direction of the first connecting line 27 (the line width direction is in the width direction). Figure 10 The dimension of the second connecting line 28 in the direction parallel to the first direction f1 is greater than the width of the second power sub-line 2441. That is, when the second connecting line 28 is connected to the first connecting line 27, it can be connected through the second via hole c2 whose dimension is greater than the width of the second power sub-line 2441. Compared with the solution of connecting the second connecting line 28 and the first connecting line 27 through a via hole with the same width as the second power sub-line 2441, the present application Figure 10 In the illustrated scheme, the second connection line 28 and the first connection line 27 are connected by a larger via, which can reduce the contact resistance at the connection position between the second connection line 28 and the first connection line 27, and thus can also reduce the loss of the voltage provided by the first sub-section 241 of the second power supply, so as to reduce the power consumption of the display panel and improve the brightness uniformity of different areas of the display panel.

[0088] Optionally, the second via hole c2 is formed in the line width direction of the first connection line 27 (the line width direction is Figure 10 The size range of the second connecting line 28 and the first connecting line 27 is 3 microns to 20 microns. Compared with the via hole of about 2 microns to connect the second connecting line 28 and the first connecting line 27, the present application Figure 10 In the structure shown, the size of the transfer hole is increased, thereby reducing the contact resistance and achieving the effect of reducing the voltage loss of the second power line.

[0089] The second via hole c2 may be a via hole on a film layer between the first connection line 27 and the second connection line 28 . The film layer may include an insulating layer or a planar layer, etc. This embodiment of the present application does not limit this.

[0090] Alternatively, refer to Figure 6 and Figure 7The second power line 24 also includes a fifth sub-portion 245 of the second power supply. The fifth sub-portion 245 of the second power supply is located at least in the second peripheral area wa2 and at least partially surrounds the display area aa. The fifth sub-portion 245 of the second power supply is located on a side of the first sub-portion 241 of the second power supply away from the substrate 21 and is electrically connected to the first sub-portion 241 of the second power supply. The fifth sub-portion 245 of the second power supply and the first sub-portion 241 of the second power supply are located on different layers. For example, the fifth sub-portion 245 of the second power supply can be located in the first conductive pattern m1, and the first sub-portion 241 of the second power supply can be located in the second conductive pattern m2. The fifth sub-portion 245 of the second power supply and the first sub-portion 241 of the second power supply can be connected via a via. This improves the uniformity of the signals on the different lines of the second power line 24.

[0091] The second power supply third sub-section 243 and the second power supply fifth sub-section 245 are electrically connected via at least one target connection t1. The at least one target connection t1 is located in the second peripheral area wa2 and at least on the second side ac2 of the display area aa. The second side ac2 and the first side ac1 are opposite sides of the display area aa. The second power supply third sub-section 243 and the second power supply fifth sub-section 245 may be co-layered. For example, the second power supply third sub-section 243 and the second power supply fifth sub-section 245 may both be located within the first conductive pattern m1. The second power supply third sub-section 243 and the second power supply fifth sub-section 245 may be connected via the at least one target connection t1 on the second side ac2, opposite the first side ac1. This improves signal uniformity across different lines of the second power line 24. The at least one target connection t1 may also be located within the first conductive pattern m1.

[0092] Alternatively, refer to Figure 6 and Figure 10 The second power supply third sub-section 243 can also be connected to the second power supply first sub-section 241 through a third via c3. This can improve the uniformity of the signals on the different lines of the second power supply line 24. The third via c3 can be a via located in a film layer between the second power supply third sub-section 243 and the second power supply first sub-section 241. The film layer may include an insulating layer or a planar layer, etc., and this embodiment of the present application is not limited to this.

[0093] In an exemplary embodiment, the display panel includes a plurality of first power sub-lines 23. The plurality of first power sub-lines 23 extend along a second direction f2 and overlap and connect with a plurality of sub-pixel columns. The first power sub-lines 23 are connected to the second portion 222 of the first power line 22 and form an integral structure. The second portion 222 of the first power line 22 can be used to provide a power signal to the first power sub-line 23 in the display area aa. The first power sub-line 23 can transmit the power signal to the sub-pixel sp to drive the sub-pixel sp. The second portion 222 of the first power line 22 may include a second-portion first sub-portion 2221 and multiple second-portion second sub-portions 2222 extending from the second-portion first sub-portion 2221. The second-portion first sub-portion 2221 extends along the first direction f1, and the second-portion second sub-portions 2222 extend along the second direction f2. The multiple second-portion second sub-portions 2222 respectively correspond to multiple first power sub-lines 23 in the display area aa, and each second-portion second sub-portion 2222 is connected to the corresponding first power sub-line 23 to form an integral structure. Of course, in some exemplary embodiments, the first power sub-line 23 may extend from the display area aa to the first peripheral area wa1 and connect to the second portion 222 of the first power line 22 in the first peripheral area wa1 to form an integral structure. This embodiment of the present application is not limited to this.

[0094] In an exemplary embodiment, the second portion 222 of the first power line 22 extends to a position corresponding to the sub-pixel sp of the edge area aa2. Under such a structure, the first power line 22 may include a plurality of second-part second sub-portions 2222 facing the plurality of first power sub-lines 23 of the edge area aa2 in the second direction f2. For each first power sub-line 23 of the edge area aa2, it can be connected to the second-part second sub-portion 2222 facing the second direction f2. In this way, the length of the routing line connecting the sub-pixel circuit of the sub-pixel in the edge area and the first power line can be further reduced, thereby reducing the loss of the voltage provided by the first power line 22, thereby reducing the energy consumption of the display panel and improving the uniformity of the brightness of different areas of the display panel. Of course, the first power line 22 may also include multiple second parts and second sub-parts 2222 that are not directly opposite to the multiple first power sub-lines 23 in the edge area aa2 in the second direction f2. The first power sub-line 23 in the edge area aa2 can be connected to the second part 222 of the first power line 22 through the row-oriented routing in the first peripheral area wa1. The embodiment of the present application does not limit this.

[0095] In an exemplary embodiment, please refer to Figure 10The first power sub-line 23 and the two adjacent second power sub-lines 2441 are alternately arranged along the first direction f1. Since the first power sub-line 23 is connected to the first power line 22, the first power voltage VDD provided by the first power line 22 can be obtained. The second power sub-line 2441 is electrically connected to the second power first sub-portion 241, and the second power voltage VSS provided by the second power first sub-portion 241 can be obtained. In this way, the first power voltage VDD and the second power voltage VSS can be respectively provided to the sub-pixel circuits of multiple sub-pixels in the display area, and the loss of the first power voltage VDD and the second power voltage VSS obtained by the sub-pixel circuits in different areas is relatively small, thereby reducing the power consumption of the display panel, improving the uniformity of the brightness of the display panel in different areas, and improving the user experience.

[0096] It should be noted that in order to clearly show some structures, Figure 10 Only part of the circuit structure is shown. Figure 10 The structure of each film layer in the display panel shown can also be referred to Figure 11 、 Figure 12 as well as Figure 13 , Figure 11 yes Figure 10 A schematic diagram of the structure of a film layer in a display panel shown in FIG. Figure 11 is a schematic structural diagram of the second conductive pattern), Figure 12 yes Figure 10 Another structural diagram of the display panel shown in FIG. Figure 12 is a schematic diagram of a structure including vias, exemplary, Figure 12 It may be a structural diagram of a flat layer between the second conductive pattern and the first conductive pattern, the flat layer including a second via hole k2 and a third via hole k3). Figure 13 yes Figure 10 A schematic diagram of the structure of another film layer in the display panel shown in FIG. Figure 11 It can be a structural schematic diagram of the first conductive pattern).

[0097] also, Figure 6 In the display panel shown, the structure of each film layer can refer to Figure 14 as well as Figure 15 . Figure 14 yes Figure 6 A schematic diagram of the structure of a film layer in a display panel shown in FIG. Figure 14 is a schematic structural diagram of the second conductive pattern), Figure 15 yes Figure 6 A schematic diagram of the structure of another film layer in the display panel shown in FIG. Figure 11 is a structural schematic diagram of the first conductive pattern).

[0098] Please refer to Figure 10 as well as Figure 16 , Figure 16 yes Figure 6 Another partial area enlarged structural diagram of the display panel shown ( Figure 16 yes Figure 6 ), wherein the display panel further includes a gate-on-array (GOA) circuit 51, which can be located between the second power supply third subsection 243 and the second power supply fifth subsection 245. On this basis, the display panel provided in the embodiment of the present application can be a display panel that utilizes array-on-array technology. Array-on-array technology is a technology that integrates gate drive circuits onto the array substrate of a display panel. This technology has the advantages of low power consumption, high integration, reduced costs, and facilitates a narrow frame.

[0099] Figure 10 In the display panel shown, the electrical connection between two adjacent second power sub-lines 2441 and the second power first sub-section 241 is achieved through a first connecting line 27. However, other structures can also be used to achieve the electrical connection between two adjacent second power sub-lines 2441 and the second power first sub-section 241. For example, please refer to Figure 17 、 Figure 18 、 Figure 19 as well as Figure 20 , Figure 17 yes Figure 8 Another enlarged structural diagram of a partial area ( Figure 17 yes Figure 8 Another enlarged structural diagram of the middle area q5), Figure 18 yes Figure 17 Schematic diagram of the structure of a membrane layer ( Figure 18 yes Figure 17 A schematic structural diagram of a second conductive pattern, Figure 19 yes Figure 17 Schematic diagram of the structure of another membrane layer ( Figure 19 yes Figure 17 A schematic diagram of a via structure in FIG), Figure 20 yes Figure 17 Schematic diagram of the structure of another membrane layer ( Figure 20 yes Figure 17 In order to clearly illustrate some circuit structures, Figure 17 The entire structure of each film layer is not shown, but this is not a limitation. For the structure of each film layer, please refer to Figure 18 、 Figure 19 as well as Figure 20 .

[0100] In an exemplary embodiment, the second power supply fourth sub-section 244 includes a plurality of second power supply sub-lines 2441 extending along the second direction f2 and arranged along the first direction f1. The plurality of second power supply sub-lines 2441 include two adjacent second power supply sub-lines 2441 located in two adjacent sub-pixel columns. In the edge region aa2, one end of each of the two adjacent second power supply sub-lines 2441 is electrically connected to the second power supply first sub-section 241 and the other end is electrically connected to the second power supply third sub-section 243. In the central region aa1, one end of each of the two adjacent second power supply sub-lines 2441 is electrically connected to the second power supply second sub-section 242 and the other end is electrically connected to the second power supply third sub-section 243. Furthermore, the display panel may further include array substrate row connection lines u1, which may be connected to array substrate row circuits in the display panel. The array substrate row connection lines u1 may be located in the first conductive pattern m1.

[0101] Optionally, the display panel further includes a plurality of third connection lines 31, the plurality of third connection lines 31 being located in the first peripheral area wa1, with one end of each third connection line 31 connected to a second power sub-line 2441, and the other end of each third connection line 31 connected to the second power first sub-section 241. The plurality of third connection lines 31 may correspond to the plurality of second power sub-lines 2441, with one end of each third connection line 31 connected to a corresponding second power first sub-section 241 to electrically connect the second power sub-line 2441 with the second power first sub-section 241. The line width of a third connection line 31 may be greater than or equal to the line width of a second power sub-line 2441, and less than the line width of two second power sub-lines 2441.

[0102] The display panel includes a first conductive pattern m1, and the third connecting line 31 and the second power sub-line 2441 can be located within the first conductive pattern m1. Furthermore, the third connecting line 31 and the second power sub-line 2441 can be an integral structure. Furthermore, the two structures involved in the embodiments of the present application are an integral structure, which can mean that the two structures are made of the same material and formed through a single patterning process. The patterning process involved in the embodiments of the present application can include steps such as applying photoresist, exposing, developing, etching, and stripping the photoresist.

[0103] Optionally, the display panel further includes a second conductive pattern m2, which includes a fourth connecting line 32 and the second power supply first sub-section 241. One end of the fourth connecting line 32 is connected to the second power supply first sub-section 241 and forms an integral structure. The other end of the fourth connecting line 32 is connected to the third connecting line 31 via a fourth via c4. This achieves an electrical connection between the third connecting line 31 and the second power supply first sub-section 241 on a different layer. The fourth via c4 may be a via located in a film layer between the fourth connecting line 32 and the second power supply first sub-section 241. This film layer may include an insulating layer, a planar layer, or other film layer, and is not limited in this embodiment of the present application.

[0104] The display panel provided in the embodiment of the present application may include Figure 10 and Figure 17 At least one of the two structures shown can be used Figure 10 and Figure 17 At least one of the two structures shown is used to achieve electrical connection between the second power sub-line 2441 and the second power first sub-section 241.

[0105] To summarize, in the display panel provided in the embodiment of the present application, the first power line located in the peripheral area includes a first part corresponding to the central area and a second part corresponding to the edge area. The second part of the first power line corresponding to the edge area is connected to the sub-pixels arranged in a stepped manner in the edge area, thereby reducing the length of the routing line connecting the sub-pixel circuit of the sub-pixel in the edge area and the first power line. For example, the length of the first power line electrically connected to multiple sub-pixel circuits and connected along the row direction is saved. In this way, the difference in voltage provided by the power line received by the sub-pixel circuit in the edge area and the sub-pixel circuit in the central area can be reduced, thereby achieving the effect of improving the brightness uniformity of the display panel.

[0106] Figure 21 is a structural diagram of a display device provided in an embodiment of the present application, Figure 22 yes Figure 21 A schematic diagram of an enlarged structure of a partial area of ​​a display device shown in FIG. Figure 22 Can be Figure 21 A schematic diagram of an enlarged structure of the middle region q7), Figure 23 yes Figure 22 A schematic diagram of an enlarged structure of a partial area of ​​a display device shown in FIG. Figure 23 Can be Figure 22 Schematic diagram of the enlarged structure of the middle area q8), Figure 24 yes Figure 23 A schematic diagram of an enlarged structure of a partial area of ​​a display device shown in FIG. Figure 24 Can be Figure 23 (Schematic diagram of the enlarged structure of the middle area q9), please refer to Figure 21 、 Figure 22 、 Figure 23 as well as Figure 24 . The display device includes a control component 41 and any display panel 20 provided in the embodiments of the present application. The control component 41 can be used to connect to the first power line 22 and the second power line 24 in the display panel 20. The control component 41 can be combined with a flexible panel (Flexible On Panel, FOP). The display panel 20 also includes a bending portion 29. The bending portion 29 can be bent, and the control component 41 and other structures can be bent to the back of the display panel 20 to shorten the frame of the display panel 20.

[0107] The display device may include a second power supply first sub-section 241, a first portion 221 of the first power line 22, a second power supply second sub-section 242, etc. For details about the display panel, please refer to the above embodiments of the display panel, which will not be repeated here.

[0108] The display device can be a mobile phone, tablet computer, monitor, television, laptop computer, vertical display screen, outdoor display screen, smart watch, smart bracelet, camera, video camera and other electronic devices with display function, which are not listed here one by one.

[0109] Because the display device includes any of the display panels provided by the above-mentioned embodiments, it also has a similar effect, namely, it can reduce the length of the wiring connecting the sub-pixel circuits of the sub-pixels in the edge area to the first power line. For example, the length of the first power line that is electrically connected to multiple sub-pixel circuits and is transferred along the row direction can be reduced. This can reduce the difference in voltage provided by the power line received by the sub-pixel circuits in the edge area and the sub-pixel circuits in the central area, thereby achieving the effect of improving the brightness uniformity of the display panel. In addition, the display panel provided by the embodiment of the present application shortens the length of the wiring connecting these sub-pixels to the first power line by extending the first power line to the positions corresponding to the sub-pixels in the edge area, thereby reducing the voltage loss in the sub-pixels in the display area, thereby achieving the effect of reducing the power consumption of the display panel.

[0110] In this application, the term "at least one of A and B" simply describes an association relationship between associated objects, indicating that three possible relationships exist. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. Similarly, "at least one of A, B, and C" means that seven possible relationships exist, indicating: A exists alone, B exists alone, C exists alone, A and B exist simultaneously, A and C exist simultaneously, C and B exist simultaneously, and A, B, and C exist simultaneously. Similarly, "at least one of A, B, C, and D" means that fifteen possible relationships exist, indicating: A exists alone, B exists alone, C exists alone, D exists alone, A and B exist simultaneously, A and C exist simultaneously, A and D exist simultaneously, C and B exist simultaneously, D and B exist simultaneously, C and D exist simultaneously, C and D exist simultaneously, A, B, and C exist simultaneously, A, B, and D exist simultaneously, A, C, and D exist simultaneously, B, C, and D exist simultaneously, and A, B, C, and D exist simultaneously.

[0111] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0112] In this application, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise expressly defined.

[0113] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel includes: a substrate, the substrate comprising a display area and a peripheral area at least partially surrounding the display area, the peripheral area comprising a first peripheral area located on a first side of the display area, the display area comprising a central area and an edge area located on at least one side of the central area in a first direction; a plurality of sub-pixels located on one side of the substrate and in the display area, at least one of the plurality of sub-pixels comprising a sub-pixel circuit and a light-emitting element, the sub-pixel circuit being configured to drive the light-emitting element, the plurality of sub-pixels being arranged into a plurality of sub-pixel rows and a plurality of sub-pixel columns, the first direction being a row direction of the sub-pixel rows, the column direction of the sub-pixel columns being a second direction, and in a portion of the sub-pixel rows close to the first peripheral area, the number of sub-pixels in each sub-pixel row located in the edge area gradually decreases along a direction close to the first peripheral area; A first power line is located in the first peripheral area, and the first power line includes a first portion corresponding to the central area and a second portion corresponding to the at least one edge area, the first portion is connected to the first power sub-line in the central area, and the second portion is connected to the first power sub-line in the edge area.

2. The display panel according to claim 1, wherein: An edge of the second portion of the first power line close to the display area is a stepped edge, and some of the sub-pixel rows are arranged in a stepped shape and correspond to the stepped edge of the first power line.

3. The display panel according to claim 2, wherein: The stepped edge includes a plurality of continuous stepped edges, each of the stepped edges corresponds to a sub-pixel row in the partial sub-pixel rows, and the difference between the target distances of any two step edges among the plurality of stepped edges ranges from 0 nanometers to 200 nanometers, and the target distance of the stepped edge is the shortest distance between the step edge and the edge of the corresponding sub-pixel row.

4. The display panel according to claim 1, wherein: The first power line includes a first sublayer and a second sublayer, the second sublayer is located on a side of the first sublayer away from the substrate, and the second portion of the first power line is located on the second sublayer.

5. The display panel according to claim 4, wherein: The first part of the first power line includes a first power first sub-section and a first power second sub-section, the first power first sub-section and the first power second sub-section are electrically connected through a first via, the first power first sub-section is located in the first sub-layer, and the first power second sub-section is located in the second sub-layer.

6. The display panel according to claim 5, wherein: The first power supply first subsection includes a first branch and a second branch, and the first branch and the second branch are symmetrical with respect to a center line passing through the center of the display area.

7. The display panel according to claim 1, wherein: The peripheral area further includes a second peripheral area located on other sides of the display area except the first side, and the first peripheral area and the second peripheral area are connected; The display panel also includes a second power line, which includes a second power first sub-section and a second power second sub-section. The second power second sub-section is located in the first peripheral area, and the second power first sub-section is at least located in the second peripheral area and at least partially surrounds the display area.

8. The display panel according to claim 7, wherein: The second power line further includes a second power third sub-portion in a grid shape, the second power third sub-portion is located in the second peripheral area and at least partially surrounds the display area; The second power line further includes a grid-shaped second power fourth sub-section located in the display area, and the second power fourth sub-section is electrically connected to the second power third sub-section.

9. The display panel according to claim 8, wherein: The second power supply fourth sub-section includes a plurality of second power supply sub-lines, which extend along the second direction and are arranged along the first direction. The plurality of second power supply sub-lines include two adjacent second power supply sub-lines located in two adjacent sub-pixel columns. In the edge area, one end of each of the two adjacent second power supply sub-lines is electrically connected to the second power supply first sub-section, and the other end is electrically connected to the second power supply third sub-section.

10. The display panel according to claim 9, wherein: The second power supply fourth sub-section includes a plurality of second power supply auxiliary lines extending along the first direction and arranged along the second direction, the plurality of second power supply auxiliary lines are electrically connected to the plurality of second power supply sub-lines and form the grid-shaped second power supply fourth sub-section, the plurality of second power supply auxiliary lines and the plurality of second power supply sub-lines are located in different layers, and the plurality of second power supply auxiliary lines are electrically connected to the second power supply third sub-section.

11. The display panel according to claim 9, wherein The display panel further includes a plurality of first connection lines located in the first peripheral area, and one end of one of the first connection lines is connected to the two adjacent second power sub-lines, and the other end is connected to the second power first sub-section.

12. The display panel according to claim 11, wherein: The display panel includes a first conductive pattern, the first conductive pattern includes the first connecting line and the second power sub-line, and the line width of the first connecting line is greater than twice the line width of the second power sub-line.

13. The display panel according to claim 12, wherein: The display panel also includes a second conductive pattern, which includes a second connecting line and a second power supply first sub-section. One end of the second connecting line is connected to the second power supply first sub-section, and the other end is connected to the first connecting line through a second via. The size of the second via in the line width direction of the first connecting line is larger than the line width of the second power supply sub-line.

14. The display panel according to claim 8, wherein The second power line further includes a second power fifth subsection, the second power fifth subsection being located at least in the second peripheral area and at least partially surrounding the display area, the second power fifth subsection being located on a side of the second power first subsection away from the substrate, and the second power fifth subsection being electrically connected to the second power first subsection; The third subsection of the second power supply is electrically connected to the fifth subsection of the second power supply through at least one target wiring, and the at least one target wiring is located in the second peripheral area and at least on the second side of the display area, and the second side and the first side are two opposite sides of the display area.

15. The display panel according to claim 1, wherein The display panel includes a plurality of first power sub-lines extending along the second direction and respectively overlapping and connected with the plurality of sub-pixel columns. The first power sub-lines are connected to the second portion and form an integral structure.

16. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 15.

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