Display device

Abstract

The invention relates to a display device. A display device according to one embodiment is provided with: a wiring to which a signal or voltage is supplied; a plurality of sub-pixels each including a display element including an organic layer that emits light in response to application of a voltage, and a pixel circuit that drives the display element; and a dummy sub-pixel including the display element and a dummy pixel circuit. The pixel circuits and the dummy pixel circuits of the plurality of sub-pixels constitute a circuit array arranged along the wiring. The dummy pixel circuit is located at an end of the circuit column. In each of the plurality of sub-pixels, an electrical path from the wiring to the display element via the pixel circuit is formed. In the dummy sub-pixel, at least a portion of an electrical path from the wiring to the display element via the dummy pixel circuit is cut off.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2024-048066, filed on March 25, 2024, and incorporates by reference all the contents described in that Japanese Patent Application. Technical Field

[0003] Embodiments of the present invention relate to a display device. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. In such display devices, technologies that can improve yield and enhance reliability are required. Summary of the Invention

[0005] In general, according to an embodiment, a display device includes: wiring that supplies a signal or voltage; a plurality of sub-pixels, each of which includes a display element and a pixel circuit, the display element including an organic layer that emits light in response to the application of a voltage, and the pixel circuit driving the display element; and a dummy sub-pixel, which includes the display element and the dummy pixel circuit. The pixel circuits and the dummy pixel circuits of the plurality of sub-pixels constitute a circuit column arranged along the wiring. The dummy pixel circuit is located at the end of the circuit column. In each of the plurality of sub-pixels, an electrical path is formed from the wiring via the pixel circuit to the display element. In the dummy sub-pixel, at least a portion of the electrical path from the wiring via the dummy pixel circuit to the display element is cut off.

[0006] With such a structure, it is possible to improve the yield and enhance the reliability of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a diagram showing a configuration example of a display device according to one embodiment.

[0008] Figure 2 This is a circuit diagram showing an example of a configuration applicable to a pixel circuit.

[0009] Figure 3 This is a schematic plan view showing an example of an arrangement of three pixel circuits arranged for one pixel.

[0010] Figure 4 This is a schematic plan view showing an example of a layout of display elements including three sub-pixels included in one pixel.

[0011] Figure 5 It is along Figure 4A schematic cross-sectional view of the display device taken along line VV in FIG.

[0012] Figure 6 It is a schematic plan view showing the vicinity of the boundary between the display area and the peripheral area.

[0013] Figure 7 It is a schematic plan view showing a structure applicable to a dummy pixel.

[0014] Figure 8 This is a schematic plan view showing an example of an arrangement of three dummy pixel circuits arranged for one dummy pixel.

[0015] Figure 9 This is a circuit diagram showing an example of a configuration applicable to a dummy pixel circuit.

[0016] Figure 10 This is a schematic plan view showing an example of a configuration applicable to pixel circuits and dummy pixel circuits arranged near the boundary between a display area and a peripheral area.

[0017] Figure 11 yes Figure 10 An enlarged top view of the pixel circuit is shown.

[0018] Figure 12 yes Figure 10 An enlarged top view of the dummy pixel circuit is shown. DETAILED DESCRIPTION

[0019] Several embodiments will be described with reference to the accompanying drawings.

[0020] The disclosed content is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the essence of the invention are naturally within the scope of the present invention. Furthermore, in the drawings, the widths, thicknesses, shapes, etc. of various components may be schematically illustrated to clarify the description, compared to actual dimensions. However, this is merely an example and does not limit the interpretation of the present invention. In this specification and the drawings, components that perform the same or similar functions as those described in connection with the accompanying drawings are denoted by the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0021] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are indicated as necessary to facilitate understanding. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis is referred to as the Y-direction, and the direction along the Z-axis is referred to as the Z-direction. The Z-direction is the normal direction of the plane containing the X-direction and the Y-direction. Furthermore, viewing various elements parallel to the Z-direction is referred to as viewing from above.

[0022] The display device of each embodiment is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, car-mounted equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0023] Figure 1 This figure shows an example configuration of a display device DSP according to one embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 includes a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0024] In this embodiment, the substrate 10 and the display area DA are circular (perfectly circular) in plan view. However, the shapes of the substrate 10 and the display area DA in plan view are not limited to this example and may be other shapes such as rectangular, square, or elliptical.

[0025] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, the pixel PX includes a green sub-pixel SP1, a red sub-pixel SP2, and a blue sub-pixel SP3. However, the pixel PX may also include sub-pixels SP of other colors, such as white, in addition to, or in place of, the sub-pixels SP1, SP2, and SP3.

[0026] The display device DSP further includes a terminal portion T arranged in the peripheral area SA. The terminal portion T is connected to, for example, a flexible circuit board that supplies a voltage or a signal for driving the display device DSP.

[0027] Figure 2 This circuit diagram shows an example of the configuration of a pixel circuit PC that can be included in each of the sub-pixels SP (SP1, SP2, and SP3). The pixel circuit PC shown in this figure includes three thin-film transistors TR1, TR2, and TR3, and one storage capacitor Cst. Furthermore, as an example of wiring for supplying signals or voltages to the pixel circuit PC, the display device DSP includes a signal line SL, a power line PL, a reset line RST, and scan lines GL1 and GL2.

[0028] In the following description, one of the source / drain electrodes of thin-film transistors TR1, TR2, and TR3 is referred to as a first electrode, and the other is referred to as a second electrode. Similarly, one electrode of storage capacitor Cst is referred to as a first electrode, and the other is referred to as a second electrode.

[0029] The gate electrode of the thin film transistor TR1 is connected to the scanning line GL1 to which the scanning signal SG is supplied, and the gate electrode of the thin film transistor TR2 is connected to the scanning line GL2 to which the reset signal RG is supplied.

[0030] The first electrode of thin-film transistor TR1 is connected to signal line SL, which supplies a video signal Sdata. Video signal Sdata is a signal written into subpixel SP to display an image. The first electrode of thin-film transistor TR2 is connected to power line PL, which supplies drive voltage VDDEL. The first electrode of thin-film transistor TR3 is connected to reset line RST, which supplies reset voltage Vrst.

[0031] The second electrode of the thin-film transistor TR1 is connected to the gate electrode of the thin-film transistor TR2 and the first electrode of the storage capacitor Cst. The second electrode of the thin-film transistor TR2 is connected to the anode of the display element DE included in the sub-pixel SP and the second electrode of the storage capacitor Cst. The second electrode of the thin-film transistor TR3 is similarly connected to the anode of the display element DE and the second electrode of the storage capacitor Cst. The voltage VSSEL is supplied to the cathode of the display element DE.

[0032] It should be noted that the configuration of the pixel circuit PC is not limited to Figure 2 For example, the pixel circuit PC may include four or more transistors. In addition, the pixel circuit PC may include multiple storage capacitors Cst.

[0033] Figure 3 1 is a schematic plan view showing an example of the arrangement of the pixel circuit PC arranged for one pixel PX. Figure 3 In the example of FIG, the pixel circuits PC ( PC1 , PC2 , PC3 ) of the sub-pixels SP1 , SP2 , and SP3 are arranged in the X direction.

[0034] The pixel circuits PC1, PC2, and PC3 are connected to the display elements DE of the sub-pixels SP1, SP2, and SP3 via contact holes CH1, CH2, and CH3 provided in the organic insulating layer 12 described later, respectively. Figure 3 In the example shown in FIG. 1 , the contact holes CH1 , CH2 , and CH3 are arranged in the X direction. However, the arrangement of the contact holes CH1 , CH2 , and CH3 is not limited to this example.

[0035] Figure 4 1 is a schematic top view showing an example of the layout of the display elements DE (DE1, DE2, DE3) of the sub-pixels SP1, SP2, and SP3. Figure 4 In the example of FIG, the display elements DE1 and DE2 are arranged in the X direction with the display element DE3. In addition, the display elements DE1 and DE2 are arranged in the Y direction.

[0036] When the display elements DE1, DE2, and DE3 are arranged in this manner, columns in which the display elements DE1 and DE2 are alternately arranged in the Y direction and columns in which a plurality of display elements DE3 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. It should be noted that the layout of the display elements DE1, DE2, and DE3 is not limited to Figure 4 example.

[0037] The rib layer 5 is arranged in the display area DA. The rib layer 5 has a pixel opening AP1 surrounding the display element DE1, a pixel opening AP2 surrounding the display element DE2, and a pixel opening AP3 surrounding the display element DE3.

[0038] exist Figure 4 In the example shown, pixel opening AP2 is smaller than pixel opening AP1, and pixel opening AP3 is larger than pixel opening AP1. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP3 has the highest aperture ratio, and sub-pixel SP2 has the lowest aperture ratio. However, the relationship between the aperture ratios of sub-pixels SP1, SP2, and SP3 is not limited to this example.

[0039] Display element DE1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping with pixel opening AP1. Display element DE2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each overlapping with pixel opening AP2. Display element DE3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping with pixel opening AP3.

[0040] Grid-shaped partition walls 6 are arranged on the rib layer 5. The partition walls 6 overlap the rib layer 5 as a whole and have the same planar shape as the rib layer 5. Specifically, the partition walls 6 have openings surrounding the display elements DE1, DE2, and DE3. The partition walls 6 function as wiring to supply cathode voltage to the upper electrodes UE1, UE2, and UE3. The contact holes CH1, CH2, and CH3 overlap the rib layer 5 and the partition walls 6, respectively.

[0041] Figure 5 It is along Figure 4 A schematic cross-sectional view of the display device DSP along the VV line in FIG. A circuit layer 11 is arranged on the substrate 10. The circuit layer 11 includes Figure 2 The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that smoothes out the unevenness of the circuit layer 11.

[0042] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the organic insulating layer 12 through contact holes CH1, CH2, and CH3 (see FIG. Figure 3 and Figure 4 ) and connected to the pixel circuits PC1, PC2, and PC3 of the circuit layer 11.

[0043] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. This shape of the partition wall 6 is called a cantilever shape.

[0044] exist Figure 5 In the example, the lower portion 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Figure 5 In the example shown in FIG. 5 , both end portions of the bottom layer 63 protrude from the side surfaces of the shaft layer 64 .

[0045] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3.

[0046] The upper electrodes UE1, UE2, UE3 are in contact with the lower portion 61 of the partition wall 6. Specifically, the upper electrodes UE1, UE2, UE3 cover the bottom layer 63 protruding from the side surface of the shaft layer 64. The upper electrodes UE1, UE2, UE3 may further cover at least a portion of the side surface of the shaft layer 64.

[0047] Display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. Display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. Display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. Cap layers CP1, CP2, and CP3 each function as an optical adjustment layer, improving the efficiency of light extraction from the organic layers OR1, OR2, and OR3.

[0048] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0049] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located around the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located around the partition wall 6 (the portion constituting the display element DE2). In addition, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located around the partition wall 6 (the portion constituting the display element DE3). It should be noted that at least one of the laminate films FL1, FL2, and FL3 may not be arranged above the partition wall 6.

[0050] Seal layers SE11, SE12, and SE13 are respectively provided in sub-pixels SP1, SP2, and SP3. Seal layer SE11 continuously covers cap layer CP1 and the partition walls 6 surrounding sub-pixel SP1. Seal layer SE12 continuously covers cap layer CP2 and the partition walls 6 surrounding sub-pixel SP2. Seal layer SE13 continuously covers cap layer CP3 and the partition walls 6 surrounding sub-pixel SP3.

[0051] exist Figure 5 In the example shown in FIG1 , the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the display elements DE1 and DE3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6. Furthermore, the laminated film FL2 and the sealing layer SE12 on the partition wall 6 between the display elements DE2 and DE3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6.

[0052] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are continuously provided at least throughout the display area DA, and a portion thereof also reaches the peripheral area SA.

[0053] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed on the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0054] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material), such as epoxy resin or acrylic resin.

[0055] The lower electrodes LE1, LE2, and LE3 include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer is formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0056] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as a magnesium-silver alloy (MgAg). In this embodiment, the lower electrodes LE1, LE2, and LE3 correspond to anodes, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes.

[0057] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple light-emitting layers.

[0058] The cover layers CP1, CP2, and CP3 may have, for example, a laminated structure comprising multiple transparent layers. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers may have different refractive indices. For example, the refractive indices of these transparent layers may differ from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the cover layers CP1, CP2, and CP3 may be omitted.

[0059] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. As the metal material for the bottom layer 63, for example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used. As the metal material for the shaft layer 64, for example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used. It should be noted that the shaft layer 64 can be formed of an insulating material.

[0060] For example, the upper part 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. As the metal material for forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide for forming the upper layer, for example, ITO or IZO can be used. It should be noted that the upper part 62 can also have a single-layer structure of a metal material. In addition, the upper part 62 can include a layer formed of an insulating material.

[0061] A cathode voltage is supplied to the partition wall 6. This cathode voltage is supplied to the upper electrodes UE1, UE2, and UE3 that contact the lower part 61 respectively. Voltages corresponding to the video signal Sdata of the signal line SL are supplied to the lower electrodes LE1, LE2, and LE3 respectively through the pixel circuits PC (PC1, PC2, and PC3) of the sub-pixels SP1, SP2, and SP3.

[0062] The organic layers OR1, OR2, and OR3 emit light corresponding to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LEi and the upper electrode UEi, the light-emitting layer of the organic layer ORi emits light in the green wavelength region. If a potential difference is formed between the lower electrode LEj and the upper electrode UEj, the light-emitting layer of the organic layer ORj emits light in the red wavelength region. If a potential difference is formed between the lower electrode LEk and the upper electrode UEk, the light-emitting layer of the organic layer ORk emits light in the blue wavelength region.

[0063] e. As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 can emit light of the same color (for example, white). In this case, the display device DSP can include a color filter that converts the light emitted by the light-emitting layer into light of colors corresponding to the sub-pixels SP1, SP, and SP3. In addition, the display device DSP can also include a layer containing quantum dots, and the quantum dots are excited by the light emitted by the light-emitting layer to generate light of colors corresponding to the sub-pixels SP1, SP2, and SP3.

[0064] Figure 6 is a schematic plan view near the boundary between the display area DA and the peripheral area SA. In the present embodiment, the outer shape of the display area DA has a curved rounding portion RP (Japanese: ラウンド部). Specifically, as Figure 1As shown in FIG, when the display area DA is circular, the entire outer shape thereof corresponds to the rounded portion RP. As another example, the outer shape of the display area DA may include the rounded portion RP and a linear portion.

[0065] As described above, a plurality of pixels PX are arranged in the display area DA. Figure 6 As shown, it is arranged in a stepped manner.

[0066] A plurality of dummy pixels DPX that do not display an image (are not illuminated) are arranged in the peripheral area SA. The dummy pixels DPX are adjacent to the pixels PX arranged at the outermost periphery of the display area DA in the X or Y direction. In one example, the dummy pixels DPX are arranged so as to surround the display area DA. In this case, all of the pixels PX arranged at the outermost periphery of the display area DA are adjacent to the dummy pixels DPX. However, at least one of the pixels PX arranged at the outermost periphery of the display area DA may not be adjacent to the dummy pixel DPX.

[0067] Figure 7 This is a schematic top view showing a configuration applicable to a dummy pixel DPX. The dummy pixel DPX includes dummy sub-pixels DSP1, DSP2, and DSP3. Similar to sub-pixel SP1, dummy sub-pixel DSP1 includes display element DE1. Similar to sub-pixel SP2, dummy sub-pixel DSP2 includes display element DE2. Similar to sub-pixel SP3, dummy sub-pixel DSP3 includes display element DE3.

[0068] The layout of the display elements DE1, DE2, DE3 in the dummy pixel DPX is similar to that of, for example Figure 4 The layout of the display elements DE1, DE2, and DE3 in the pixel PX shown is the same. Figure 7 In the example, pixel openings AP1, AP2, and AP3 overlapping the display elements DE1, DE2, and DE3 of the dummy pixel DPX are provided in the rib layer 5. In addition, the display elements DE1, DE2, and DE3 of the dummy pixel DPX are respectively surrounded by the partition wall 6.

[0069] Figure 8 1 is a schematic top view showing an example of the configuration of the dummy pixel circuit DPC configured for one dummy pixel DPX. The dummy sub-pixels DSP1, DSP2, and DSP3 each include a dummy pixel circuit DPC (DPC1, DPC2, and DPC3). Figure 3 The pixel circuits PC1 , PC2 , and PC3 shown are similarly arranged in the X direction.

[0070] exist Figure 7 and Figure 8 In the example, no Figure 4 In this case, the display elements DE1, DE2, and DE3 of the dummy pixel DPX are not connected to the dummy pixel circuits DPC1, DPC2, and DPC3. As another example, contact holes CH1, CH2, and CH3 may be provided in the dummy pixel DPX, and the display elements DE1, DE2, and DE3 may be connected to the dummy pixel circuits DPC1, DPC2, and DPC3 through these contact holes.

[0071] Figure 9 : is a circuit diagram showing an example of a configuration applicable to dummy pixel circuits DPC (DPC1, DPC2, DPC3). Figure 2 The pixel circuit PC shown similarly includes thin film transistors TR1 , TR2 , TR3 and a storage capacitor Cst.

[0072] In the sub-pixels SP1, SP2, and SP3, an electrical path is formed from the wiring (signal line SL, power line PL, and reset wiring RST) that supplies signals or voltages related to driving the display element DE, through the pixel circuit PC, to the display element DE. On the other hand, in the dummy sub-pixel DSP, at least a portion of this electrical path is disconnected. As a result, the display element DE of the dummy sub-pixel DSP is not illuminated.

[0073] That is, in Figure 9 In the example of , cut-off portions C1, C2, C3, and C4 indicated by dot-dash circles are provided. In the cut-off portion C1, the electrical path between the dummy pixel circuit DPC and the signal line SL, specifically, the path between the thin-film transistor TR1 and the signal line SL, is cut off. In the cut-off portion C2, the electrical path between the dummy pixel circuit DPC and the power line PL, specifically, the path between the thin-film transistor TR2 and the power line PL, is cut off. In the cut-off portion C3, the electrical path between the dummy pixel circuit DPC and the reset wiring RST, specifically, the path between the thin-film transistor TR3 and the reset wiring RST, is cut off. Furthermore, in the cut-off portion C4, the path between the dummy pixel circuit DPC and the display element DE, specifically, the path between the thin-film transistors TR2 and TR3 and the display element DE, is cut off.

[0074] Figure 10 This is a schematic top view showing an example of the configuration of a pixel circuit PC and a dummy pixel circuit DPC that can be applied near the boundary between the display area DA and the peripheral area SA. In this example, one dummy pixel DPX is arranged outside a pixel PX arranged at the outermost periphery of the display area DA.

[0075] The signal line SL and the power line PL extend in the Y direction. The scanning lines GL1 and GL2 and the reset wiring RST extend in the X direction. The signal line SL and the power line PL are, for example, Figure 5 The scanning lines GL1 and GL2 and the reset line RST are formed of, for example, a second metal layer included in the circuit layer 11 .

[0076] Pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, DPC3 arranged in the X direction constitute a circuit column Rx, while pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, DPC3 arranged in the Y direction constitute a circuit column Ry.

[0077] Scan lines GL1 and GL2 and reset wiring RST extend across pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, and DPC3 that constitute circuit column Rx. From another perspective, pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, and DPC3 that constitute circuit column Rx are arranged along one scan line GL1, GL2, and reset wiring RST, respectively.

[0078] Signal lines SL and power lines PL extend across pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, and DPC3 that constitute circuit row Ry. From another perspective, pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, and DPC3 that constitute circuit row Ry are each arranged along a single signal line SL and power line PL.

[0079] exist Figure 10 In the example of FIG, the dummy pixel circuit DPC1 is located at the end of the circuit column Rx. Note that, for example, the dummy pixel circuit DPC3 is located at the end on the opposite side of the circuit column Rx.

[0080] In addition, Figure 10 In the example of FIG, dummy pixel circuits DPC1, DPC2, and DPC3 are respectively located at the ends of the circuit array Ry. The same configuration can be applied to the ends on the opposite side of the circuit array Ry.

[0081] Figure 11 yes Figure 10 The enlarged top view of the pixel circuit PC (PC1, PC2, PC3) shown in FIG. Figure 11 In the example of FIG. 1 , the pixel circuit PC includes semiconductor layers SC1 and SC2, a gate electrode GE, and an output electrode OE. These elements are included in Figure 5In the circuit layer 11 shown, for example, the output electrode OE is formed of the same first metal layer as the signal line SL and the power line PL. In addition, the gate electrode GE is formed of the same second metal layer as the scanning lines GL1 and GL2 and the reset line RST.

[0082] The semiconductor layer SC1 is connected to the signal line SL at the contact portion P1 and to the gate electrode GE at the contact portion P2. The semiconductor layer SC1 intersects the scanning line GL1 between the contacts P1 and P2. Figure 2 The thin film transistor TR1 is shown.

[0083] Semiconductor layer SC2 is connected to power line PL at contact portion P3, to reset line RST at contact portion P4, and to output electrode OE at contact portion P5. Contact portion P5 is located between contacts P3 and P4. Output electrode OE is connected to the lower electrodes (LE1, LE2, LE3) of the sub-pixel SP included in pixel circuit PC through contact holes (CH1, CH2, CH3) in organic insulating layer 12.

[0084] The semiconductor layer SC2 intersects with the gate electrode GE between the contact portions P3 and P5. Figure 2 The thin film transistor TR2 shown in FIG. In addition, the semiconductor layer SC2 intersects the scanning line GL2 between the contact portions P4 and P5. Thus, Figure 2 The thin film transistor TR3 is shown.

[0085] Figure 12 yes Figure 10 The dummy pixel circuit DPC (DPC1, DPC2, DPC3) is shown in the enlarged top view. The dummy pixel circuit DPC has semiconductor layers SC1, SC2, gate electrodes GE and output electrodes OE in the same manner as the pixel circuit PC. Figure 9 The circuits are cut off in the cut-off portions C1 , C2 , C3 , and C4 shown in FIG.

[0086] Specifically, no cutout portion C1 is provided. Figure 11 The contact portion P1 shown in FIG. Thus, the semiconductor layer SC1 is separated from the signal line SL. In addition, no contact portion P1 is provided in the cut portion C2. Figure 11 The contact portion P3 shown in FIG. Thus, the semiconductor layer SC2 is separated from the power line PL. In addition, no contact portion is provided in the cut-off portion C3. Figure 11 The contact portion P4 shown in FIG. 4 is provided. Thus, the semiconductor layer SC2 is separated from the reset wiring RST. In addition, no contact portion P4 is provided in the cut portion C4. Figure 11 The semiconductor layer SC2 is thus separated from the output electrode OE.

[0087] It should be noted that the dummy pixel circuit DPC does not necessarily need to have all of the cut-off portions C1, C2, C3, and C4. Furthermore, in the dummy pixel circuit DPC, the electrical path between the display element DE and the dummy pixel circuit DPC may be cut off in a manner different from that of the cut-off portions C1, C2, C3, and C4. For example, as described above, by not providing the contact holes (CH1, CH2, and CH3) in the dummy sub-pixel DSP, the electrical path between the display element DE and the dummy pixel circuit DPC can be cut off.

[0088] As described above, the display device DSP of this embodiment includes dummy pixels DPX outside the pixels PX arranged at the outermost periphery of the display area DA. This configuration can improve the yield and reliability of the display device DSP compared to a case without dummy pixels DPX.

[0089] Specifically, in a configuration without dummy pixels DPX, the thin-film transistors of the pixel circuits PC at the outermost periphery of the display area DA may be damaged by static electricity, potentially causing characteristic abnormalities. In this case, the pixel circuits PC may not function properly, potentially causing defects where the sub-pixels SP connected to the pixel circuits PC are either permanently off or permanently on.

[0090] In contrast, in the display device DSP of this embodiment, dummy pixel circuits DPC (DPC1, DPC2, and DPC3) are arranged outside the outermost pixel circuits PC. In this case, even if damage occurs due to static electricity, the damage is primarily borne by the dummy pixel circuits DPC. Therefore, the impact on the pixel circuits PC in the display area DA can be reduced, suppressing the occurrence of the aforementioned defects.

[0091] Furthermore, static electricity-induced damage is more likely to occur in a rounded portion of the display area DA. Therefore, when the display area DA is circular as in this embodiment, the effect obtained by providing the dummy pixels DPX becomes more significant.

[0092] Based on the display devices described above as embodiments of the present invention, any display devices and manufacturing methods that can be appropriately designed and modified by those skilled in the art also fall within the scope of the present invention as long as they include the gist of the present invention.

[0093] Within the scope of the present invention, those skilled in the art will be able to conceive of various variations, and it is understood that such variations also fall within the scope of the present invention. For example, solutions obtained by those skilled in the art by appropriately adding, deleting, or modifying the design of the above-mentioned embodiments, or solutions obtained by adding, omitting, or modifying the conditions of the above-mentioned embodiments, as long as they contain the gist of the present invention, are also within the scope of the present invention.

[0094] In addition, regarding other effects brought about by the methods described in the above-mentioned embodiments, regarding the effects that are clear based on the records in this specification, or the effects that can be appropriately thought of by those skilled in the art, it is of course understood that they are the effects brought about by the present invention.

Claims

1. A display device comprising: Wiring that supplies signals or voltages; a plurality of sub-pixels, each of the plurality of sub-pixels including a display element and a pixel circuit, the display element including an organic layer that emits light in response to application of a voltage, the pixel circuit driving the display element; and A dummy sub-pixel, comprising the display element and a dummy pixel circuit, The pixel circuits of the plurality of sub-pixels and the dummy pixel circuits constitute a circuit column arranged along the wiring. The dummy pixel circuit is located at the end of the circuit column, In each of the plurality of sub-pixels, an electrical path is formed from the wiring through the pixel circuit to the display element. In the dummy sub-pixel, at least a portion of an electrical path from the wiring to the display element via the dummy pixel circuit is cut off.

2. The display device according to claim 1, wherein In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the display element is cut off.

3. The display device according to claim 1, wherein In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the wiring is cut off.

4. The display device according to claim 3, wherein The wiring includes a signal line for supplying image signals to the plurality of sub-pixels. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the signal line is cut off.

5. The display device according to claim 3, wherein The wiring includes a power supply line to which a driving voltage supplied to the display elements of the plurality of sub-pixels is applied. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the power supply line is cut off. The display device according to claim 3 , wherein: The wiring includes a reset wiring for supplying a reset voltage to the display elements of the plurality of sub-pixels. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the reset wiring is cut off.

7. The display device according to any one of claims 1 to 6, wherein: The plurality of sub-pixels are arranged in a display area for displaying an image, The outer shape of the display area includes a non-linear rounded portion.

8. The display device according to claim 7, wherein: The display area has a circular shape.

9. A display device comprising: Wiring that supplies signals or voltages; a plurality of sub-pixels, each of the plurality of sub-pixels including a display element and a pixel circuit, the display element including an organic layer that emits light in response to application of a voltage, and the pixel circuit driving the display element; a dummy sub-pixel comprising the display element and a dummy pixel circuit; and a partition wall surrounding the display element of each of the plurality of sub-pixels, The pixel circuits of the plurality of sub-pixels and the dummy pixel circuits constitute a circuit column arranged along the wiring. The dummy pixel circuit is located at the end of the circuit column, In each of the plurality of sub-pixels, an electrical path is formed from the wiring through the pixel circuit to the display element. In the dummy sub-pixel, at least a portion of an electrical path from the wiring to the display element via the dummy pixel circuit is cut off.

10. The display device according to claim 9, wherein The partition wall also surrounds the display element of the dummy sub-pixel.

11. The display device according to claim 9, wherein The partition wall comprises: a conductive lower portion; and The upper portion is disposed on the lower portion and has an end portion protruding from a side surface of the lower portion.

12. The display device according to claim 11, wherein The lower portion comprises: a conductive base layer; and an axis layer disposed on the bottom layer, The bottom layer protrudes from a side of the shaft layer.

13. The display device according to claim 11, wherein The display element of each of the plurality of sub-pixels comprises: a lower electrode connected to the pixel circuit; an upper electrode facing the lower electrode and in contact with the lower portion of the partition wall; and The organic layer is located between the lower electrode and the upper electrode.

14. The display device according to claim 9, wherein In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the display element is cut off.

15. The display device according to claim 9, wherein In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the wiring is cut off.

16. The display device according to claim 15, wherein The wiring includes a signal line for supplying image signals to the plurality of sub-pixels. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the signal line is cut off.

17. The display device according to claim 15, wherein: The wiring includes a power supply line to which a driving voltage supplied to the display elements of the plurality of sub-pixels is applied. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the power supply line is cut off.

18. The display device according to claim 15, wherein The wiring includes a reset wiring for supplying a reset voltage to the display elements of the plurality of sub-pixels. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the reset wiring is cut off.

19. The display device according to any one of claims 9 to 18, wherein: The plurality of sub-pixels are arranged in a display area for displaying an image, The outer shape of the display area includes a non-linear rounded portion.

20. The display device according to claim 19, wherein The display area has a circular shape.

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