Pixel driving circuit, display panel and display device

Abstract

The invention relates to the technical field of display, and provides a pixel driving circuit, a display panel and a display device.The pixel driving circuit comprises a driving circuit, a refresh control circuit and a compensation circuit, and the driving circuit is connected with a first node, a second node and a third node; the driving circuit is used for inputting driving current to the third node by using the second node according to the signal of the first node; the refresh control circuit is connected with the first node, a fourth node and a third gate drive signal end, and the refresh control circuit is used for responding to a signal of the third gate drive signal end to communicate the first node with the fourth node; and the compensation circuit is connected with the third node, the fourth node and a first gate driving signal end, and is used for responding to a signal of the first gate driving signal end to communicate the third node with the fourth node. According to the pixel driving circuit, the refresh frequency of the display panel can be adjusted.

Description

Pixel driving circuit, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Art

[0002] In the related art, the display panel cannot adjust the refresh frequency of a local area, resulting in high power consumption of the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit includes:

[0006] a driving circuit connected to the first node, the second node, and the third node, the driving circuit being configured to input a driving current to the third node via the second node according to a signal of the first node;

[0007] a refresh control circuit, the refresh control circuit being connected to the first node, the fourth node, and a third gate drive signal terminal, the refresh control circuit being configured to connect the first node and the fourth node in response to a signal from the third gate drive signal terminal;

[0008] The compensation circuit is connected to the third node, the fourth node, and the first gate drive signal terminal, and is used to respond to the signal of the first gate drive signal terminal to connect the third node and the fourth node.

[0009] In an exemplary embodiment of the present disclosure, the refresh control circuit includes:

[0010] A ninth transistor has a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate connected to the third gate drive signal terminal.

[0011] In an exemplary embodiment of the present disclosure, the ninth transistor is an N-type transistor.

[0012] In an exemplary embodiment of the present disclosure, the pixel driving circuit is applied to a display panel;

[0013] In a low refresh cycle of the display panel, the refresh control circuit is used to turn off the third node and the fourth node at least in a data writing phase;

[0014] During a high refresh period of the display panel, the refresh control circuit is configured to conduct the third node and the fourth node at least during a data writing phase.

[0015] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes:

[0016] A first reset circuit is connected to the third node, the first initial signal terminal, and the first reset signal terminal. The first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the third node.

[0017] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes:

[0018] a data writing circuit connected to the data signal terminal, the second node, and the second gate driving signal terminal, wherein the data writing circuit is configured to respond to a signal from the second gate driving signal terminal to transmit the signal from the data signal terminal to the second node;

[0019] a light-emitting control circuit connected to the second node, the first power supply terminal, the third node, the light-emitting unit, and an enable signal terminal, the light-emitting control circuit being configured to connect the first power supply terminal and the second node in response to a signal from the enable signal terminal, and to connect the third node and the light-emitting unit in response to a signal from the enable signal terminal;

[0020] a second reset circuit connected to the light-emitting unit, the second initial signal terminal, and the second reset signal terminal, the second reset circuit being configured to respond to a signal from the second reset signal terminal to transmit the signal from the second initial signal terminal to the light-emitting unit;

[0021] a third reset circuit connected to the second node and a third initial signal terminal, the third reset circuit being configured to respond to a reset signal to transmit a signal from the third initial signal terminal to the second node;

[0022] The storage circuit is connected between the first node and the first power supply terminal.

[0023] In an exemplary embodiment of the present disclosure, the driving circuit includes:

[0024] a driving transistor, wherein a first electrode of the driving transistor is connected to the second node, a second electrode of the driving transistor is connected to the third node, and a gate of the driving transistor is connected to the first node;

[0025] The compensation circuit comprises:

[0026] a second transistor, wherein a first electrode of the second transistor is connected to the fourth node, a second electrode of the second transistor is connected to the third node, and a gate of the second transistor is connected to the first gate drive signal terminal;

[0027] The first reset circuit includes:

[0028] a first transistor, wherein a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode of the first transistor is connected to the third node, and a gate of the first transistor is connected to the first reset signal terminal;

[0029] The second reset circuit includes:

[0030] a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second initial signal terminal, a second electrode is connected to the light emitting unit, and a gate is connected to the second reset signal terminal;

[0031] The data writing circuit includes:

[0032] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data signal terminal, a second electrode of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to the second gate drive signal terminal;

[0033] The light emitting control circuit includes:

[0034] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply terminal, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to the enable signal terminal;

[0035] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the third node, a second electrode is connected to the light emitting unit, and a gate is connected to the enable signal terminal;

[0036] The third reset circuit is further connected to the second reset signal terminal, and is configured to respond to a signal from the second reset signal terminal to transmit a signal from the third initial signal terminal to the second node, wherein the third reset circuit includes:

[0037] an eighth transistor, having a first electrode connected to the third initial signal terminal, a second electrode connected to the second node, and a gate connected to the second reset signal terminal;

[0038] The storage circuit includes:

[0039] A capacitor, wherein a first electrode of the capacitor is connected to the first node, and a second electrode of the capacitor is connected to the first power supply terminal.

[0040] In an exemplary embodiment of the present disclosure, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

[0041] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned pixel driving circuit.

[0042] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits are arrayed along a first direction and a second direction, where the second direction intersects the first direction;

[0043] The display panel also includes a first gate line and a third gate line, the first gate line is connected to multiple first gate drive signal terminals in multiple pixel drive circuits distributed in the first direction, and the third gate line is connected to multiple third gate drive signal terminals in multiple pixel drive circuits distributed in the second direction.

[0044] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes:

[0045] substrate;

[0046] A pixel driving circuit is located on one side of the substrate, and the pixel driving circuit includes: a driving transistor, a second transistor, and a ninth transistor, wherein the first electrode of the ninth transistor is connected to the gate of the driving transistor, the first electrode of the second transistor is connected to the second electrode of the ninth transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor.

[0047] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0048] a first active layer located on one side of the base substrate, the first active layer comprising a third active portion, the third active portion being used to form a channel region of the driving transistor;

[0049] The second active layer is located on a side of the first active layer away from the base substrate, and the second active layer includes a ninth active portion, and the ninth active portion is used to form a channel region of the ninth transistor.

[0050] In an exemplary embodiment of the present disclosure, the second active layer further includes a second active portion, and the second active portion is used to form a channel region of the second transistor.

[0051] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor being connected to the data line, and a second electrode of the fourth transistor being connected to the first electrode of the driving transistor;

[0052] The display panel further includes:

[0053] a second gate line located on one side of the base substrate, an orthographic projection of the second gate line on the base substrate extending along a first direction, and a portion of the second gate line being used to form a gate of the fourth transistor;

[0054] In the same pixel driving circuit, the orthographic projection of the second gate line on the base substrate is located between the orthographic projection of the channel region of the second transistor on the base substrate and the orthographic projection of the channel region of the ninth transistor on the base substrate.

[0055] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0056] In the first direction of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the substrate is located between the orthographic projection of the channel region of the fourth transistor on the substrate and the orthographic projection of the channel region of the second transistor on the substrate.

[0057] In an exemplary embodiment of the present disclosure, the length direction of the channel region of the second transistor is the second direction, the length direction of the channel region of the ninth transistor is the first direction, and the first direction and the second direction intersect.

[0058] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0059] a first power line located on one side of the base substrate, the first power line being used to provide a high-level signal to the pixel driving circuit, wherein an orthographic projection of the first power line on the base substrate at least partially overlaps with an orthographic projection of the channel region of the ninth transistor on the base substrate;

[0060] The width of the channel region of the second transistor is greater than the width of the channel region of the ninth transistor, and / or the length of the channel region of the second transistor is greater than the length of the channel region of the ninth transistor.

[0061] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits distributed in an array in a first direction and a second direction, and the display panel further includes:

[0062] a first gate line located on one side of the base substrate, an orthographic projection of the first gate line on the base substrate extending along a first direction, and a portion of the first gate line used to respectively form gates of a plurality of second transistors in a plurality of pixel driving circuits distributed in the first direction;

[0063] A third gate line is located on one side of the base substrate, wherein the orthographic projection of the third gate line on the base substrate extends along a second direction, the second direction intersects the first direction, and the third gate line connects the gates of the plurality of ninth transistors in the plurality of pixel driving circuits distributed in the second direction.

[0064] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0065] a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a ninth bridge portion, the ninth bridge portion being connected to the first electrode of the ninth transistor and the gate of the driving transistor through via holes;

[0066] a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, the fifth conductive layer comprising a first power line, the first power line being used to provide a high-level signal to the pixel driving circuit;

[0067] The sixth conductive layer is located on a side of the fifth conductive layer away from the base substrate. The sixth conductive layer includes a third gate line connected to the gate of the ninth transistor.

[0068] In an exemplary embodiment of the present disclosure, an orthographic projection of the third gate line on the base substrate and an orthographic projection of the first power line on the base substrate at least partially overlap.

[0069] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0070] a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a second bridge portion and a ninth bridge portion, the second bridge portion being connected to the second electrode of the driving transistor and the second electrode of the second transistor through a via hole, respectively, and the ninth bridge portion being connected to the first electrode of the ninth transistor and the gate of the driving transistor through a via hole;

[0071] a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, the fifth conductive layer comprising a first power line, the first power line being used to provide a high-level signal to the pixel driving circuit;

[0072] The orthographic projection of the first power line on the base substrate and the orthographic projection of the second bridge portion on the base substrate at least partially overlap, and / or the orthographic projection of the first power line on the base substrate and the orthographic projection of the ninth bridge portion on the base substrate at least partially overlap.

[0073] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0074] The display panel further includes:

[0075] a first gate line located on one side of the base substrate, an orthographic projection of the first gate line on the base substrate extending along a first direction, and a portion of the first gate line being used to form a gate of the second transistor;

[0076] a second bridge portion, located on one side of the base substrate, the second bridge portion being connected to the second electrode of the driving transistor, the second electrode of the second transistor, and the second electrode of the first transistor through via holes;

[0077] The first gate line includes a first extending portion and a second extending portion, the first extending portion is used to form the gate of the second transistor, a size of an orthographic projection of the first extending portion on the substrate in a second direction is larger than a size of an orthographic projection of the second extending portion on the substrate in the second direction, and the second direction intersects the first direction;

[0078] The second bridging portion and the first gate line are located in different conductive layers. The second bridging portion includes a first sub-bridging portion. The orthographic projection of the first sub-bridging portion on the base substrate extends along the second direction. The orthographic projection of the first sub-bridging portion on the base substrate intersects with the orthographic projection of the second extension portion on the base substrate.

[0079] In an exemplary embodiment of the present disclosure, the second bridging portion further includes:

[0080] a second sub-bridge portion, the second sub-bridge portion being connected to the second electrode of the first transistor through a via;

[0081] a third sub-bridge portion, the third sub-bridge portion being connected to the second electrode of the second transistor and the second electrode of the driving transistor through a via hole;

[0082] In which, the first sub-bridge portion is connected between the second sub-bridge portion and the third sub-bridge portion, and an angle less than 180° is formed between the orthographic projection of the first sub-bridge portion on the substrate and the orthographic projection of the second sub-bridge portion on the substrate, and an angle less than 180° is formed between the orthographic projection of the first sub-bridge portion on the substrate and the orthographic projection of the third sub-bridge portion on the substrate.

[0083] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits arrayed in a first direction and a second direction, the pixel driving circuit further including a capacitor and a fourth transistor, wherein a first electrode of the capacitor is connected to a gate of the driving transistor, a second electrode of the capacitor is connected to a first power line, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0084] The display panel further includes:

[0085] a first conductive layer located on one side of the base substrate, the first conductive layer comprising a second gate line, an orthographic projection of the second gate line on the base substrate extending along a first direction, and a portion of the second gate line being used to form a gate of the fourth transistor;

[0086] a second conductive layer, the second conductive layer being located on a side of the first conductive layer away from the base substrate, the second conductive layer comprising a second conductive portion and a fourth gate line;

[0087] The orthographic projection of the fourth gate line on the substrate extends along the first direction, and a portion of the structure of the fourth gate line is used to form a bottom gate of the second transistor;

[0088] The second conductive portion includes a first sub-conductive portion and a second sub-conductive portion, the first sub-conductive portion is used to form a second electrode of the capacitor, and the second sub-conductive portion is connected between two adjacent first sub-conductive portions in the first direction;

[0089] The orthographic projection of the second gate line on the base substrate is located on a side of the orthographic projection of the fourth gate line on the base substrate away from the orthographic projection of the second conductive portion on the base substrate;

[0090] The orthographic projection of the fourth gate line on the base substrate forms a first groove on a side facing the orthographic projection of the second gate line on the base substrate, and the orthographic projection of the second conductive portion on the base substrate forms a second groove on a side facing the orthographic projection of the second gate line on the base substrate;

[0091] The orthographic projection of the first groove and the channel region of the fourth transistor on the base substrate is arranged opposite to each other in the second direction, and the first groove and the second groove are arranged opposite to each other in the second direction.

[0092] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0093] The display panel further includes:

[0094] a fifth conductive layer, located on one side of the base substrate, the fifth conductive layer comprising an eleventh bridge portion and a twelfth bridge portion, the eleventh bridge portion being connected to the first electrode of the fourth transistor through a first via hole, and the twelfth bridge portion being connected to the gate of the ninth transistor through a second via hole;

[0095] a sixth conductive layer, located on a side of the fifth conductive layer facing away from the base substrate, the sixth conductive layer comprising a third gate line and a data line, the data line being connected to the eleventh bridge portion through a third via hole, and the third gate line being connected to the twelfth bridge portion through a fourth via hole;

[0096] The distance between the orthographic projection of the third via hole on the base substrate and the orthographic projection of the first via hole on the base substrate is greater than the distance between the orthographic projection of the fourth via hole on the base substrate and the orthographic projection of the second via hole on the base substrate.

[0097] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes:

[0098] a first transistor, wherein a first electrode of the first transistor is connected to the first initial signal line, and a second electrode of the first transistor is connected to the second electrode of the driving transistor;

[0099] a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0100] a fifth transistor, a first electrode connected to the first power line, and a second electrode connected to the first electrode of the driving transistor;

[0101] a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the light-emitting unit;

[0102] a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the light-emitting unit;

[0103] an eighth transistor, a first electrode of which is connected to the third initial signal line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0104] a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line;

[0105] Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor and the ninth transistor are N-type transistors.

[0106] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a P-type transistor and an N-type transistor, and the display panel further includes:

[0107] a first active layer, located on one side of the base substrate, wherein a portion of the first active layer is used to form a channel region of a P-type transistor in the pixel driving circuit;

[0108] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein a portion of the first conductive layer is used to form a gate of a P-type transistor in the pixel driving circuit;

[0109] a second conductive layer, located on a side of the first conductive layer away from the base substrate, wherein a portion of the second conductive layer is used to form a bottom gate of an N-type transistor in the pixel driving circuit;

[0110] a second active layer, located on a side of the second conductive layer facing away from the base substrate, wherein a portion of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit;

[0111] a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein a portion of the third conductive layer is used to form a top gate of an N-type transistor in the pixel driving circuit;

[0112] The fourth conductive layer is located on a side of the third conductive layer away from the base substrate, and a portion of the structure of the fourth conductive layer is used to form a bridge portion connecting different transistors.

[0113] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0114] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0115] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0116] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0117] FIG2 is a timing diagram of some nodes in a driving method of the pixel driving circuit shown in FIG1 ;

[0118] FIG3 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0119] FIG4 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0120] FIG5 is a structural diagram of the shielding layer in FIG4 ;

[0121] FIG6 is a structural diagram of the first active layer in FIG4 ;

[0122] FIG7 is a structural diagram of the first conductive layer in FIG4 ;

[0123] FIG8 is a structural diagram of the second conductive layer in FIG4 ;

[0124] FIG9 is a structural diagram of the second active layer in FIG4 ;

[0125] FIG10 is a structural diagram of the third conductive layer in FIG4 ;

[0126] FIG11 is a structural diagram of the fourth conductive layer in FIG4 ;

[0127] FIG12 is a structural diagram of the fifth conductive layer in FIG4;

[0128] FIG13 is a structural diagram of the sixth conductive layer in FIG4;

[0129] FIG14 is a structural diagram of the shielding layer and the first active layer in FIG4 ;

[0130] FIG15 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG4 ;

[0131] FIG16 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG4 ;

[0132] FIG17 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG4 ;

[0133] FIG18 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG4 ;

[0134] FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG4 ;

[0135] FIG20 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG4 ;

[0136] FIG. 21 is a partial cross-sectional view of the display panel shown in FIG. 4 taken along the dotted line BB. DETAILED DESCRIPTION

[0137] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0138] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0139] As shown in Figure 1, it is a structural schematic diagram of an exemplary embodiment of the pixel driving circuit of the present invention. The pixel driving circuit includes: a driving circuit 1, a refresh control circuit 2, and a compensation circuit 3. The driving circuit 1 is connected to the first node N1, the second node N2, and the third node N3. The driving circuit is used to input a driving current to the third node N3 using the second node N2 according to the signal of the first node N1; the refresh control circuit 2 is connected to the first node N1, the fourth node N4, and the third gate driving signal terminal G3, and the refresh control circuit 2 is used to respond to the signal of the third gate driving signal terminal G3 to connect the first node N1 and the fourth node N4; the compensation circuit 3 is connected to the third node N3, the fourth node N4, and the first gate driving signal terminal G1, and the compensation circuit 3 is used to respond to the signal of the first gate driving signal terminal G1 to connect the third node N3 and the fourth node N4.

[0140] In this exemplary embodiment, when the display panel requires a low refresh rate, the refresh control circuit 2 can be configured to disconnect the third node N3 and the fourth node N4 at least during a data writing phase, thereby preventing the data signal terminal Da from writing a data signal to the first node N1, thereby enabling the display panel to display at a low refresh rate. When the display panel requires a high refresh rate, the refresh control circuit 2 can be configured to connect the third node N3 and the fourth node N4 at least during a data writing phase, thereby enabling the data signal terminal Da to normally input a data signal to the first node N1, thereby enabling the display panel to display at a high refresh rate.

[0141] In this exemplary embodiment, as shown in FIG1 , the refresh control circuit 2 includes a ninth transistor T9 , a first electrode of the ninth transistor T9 connected to the third node N3 , a second electrode connected to the fourth node N4 , and a gate connected to the third gate drive signal terminal G3 .

[0142] In this exemplary embodiment, as shown in FIG1 , the ninth transistor T9 is an N-type transistor. The N-type transistor has a relatively small leakage current, and this configuration can reduce the leakage current of the first node N1 through the ninth transistor T9.

[0143] In this exemplary embodiment, as shown in Figure 1, the pixel driving circuit also includes: a first reset circuit 4, the first reset circuit 4 is connected to the third node N3, the first initial signal terminal Vinit1, and the first reset signal terminal Re1, and the first reset circuit 4 is used to respond to the signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal Vinit1 to the third node N3.

[0144] In this exemplary embodiment, as shown in FIG1 , the pixel driving circuit is used to drive the light emitting unit OLED to emit light. The pixel driving circuit further includes: a data writing circuit 5 , a light emitting control circuit 6 , a second reset circuit 7 , a third reset circuit 8 , and a storage circuit 10 . The data write circuit 5 is connected to the data signal terminal Da, the second node N2, and the second gate drive signal terminal G2. The data write circuit 5 is used to respond to the signal of the second gate drive signal terminal G2 to transmit the signal of the data signal terminal Da to the second node N2; the light-emitting control circuit 6 is connected to the second node N2, the first power supply terminal VDD, the third node N3, the light-emitting unit, and the enable signal terminal EM. The light-emitting control circuit 6 is used to respond to the signal of the enable signal terminal EM to connect the first power supply terminal VDD and the second node N2, and to respond to the signal of the enable signal terminal EM to connect the third node N3 and the light-emitting unit; the second reset circuit 7 is connected to the light-emitting unit, the second initial signal terminal Vinit2, and the second reset signal terminal Re2. The second reset circuit 7 is used to respond to the signal of the second reset signal terminal Re2 to transmit the signal of the second initial signal terminal Vinit2 to the light-emitting unit; the third reset circuit 8 is connected to the second node N2 and the third initial signal terminal Vinit3. The third reset circuit 8 is used to respond to a reset signal to transmit the signal of the third initial signal terminal Vinit3 to the second node N2; the storage circuit 10 is connected between the first node N1 and the first power supply terminal VDD.

[0145] In this exemplary embodiment, as shown in FIG1 , the driving circuit 1 includes a driving transistor T3, wherein a first electrode of the driving transistor T3 is connected to the second node N2, a second electrode is connected to the third node N3, and a gate is connected to the first node N1. The compensation circuit 3 includes a second transistor T2, wherein a first electrode of the second transistor T2 is connected to the fourth node N4, a second electrode is connected to the third node N3, and a gate is connected to the first gate driving signal terminal G1. The first reset circuit 4 includes a first transistor T1, wherein a first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, a second electrode is connected to the third node N3, and a gate is connected to the first reset signal terminal Re1. The second reset circuit 7 includes a seventh transistor T7, wherein a first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, a second electrode is connected to the light-emitting unit, and a gate is connected to the second reset signal terminal Re2. The data writing circuit 5 includes a fourth transistor T4, wherein a first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode is connected to the second node N2, and a gate is connected to the second gate driving signal terminal G2. The light-emitting control circuit 6 includes a fifth transistor T5 and a sixth transistor T6. The first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate is connected to the enable signal terminal EM. The first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the light-emitting unit, and the gate is connected to the enable signal terminal EM. A third reset circuit 8 is also connected to the second reset signal terminal Re2. The third reset circuit 8 is configured to transmit the signal of the third initial signal terminal Vinit3 to the second node N2 in response to the signal of the second reset signal terminal Re2. The third reset circuit 8 includes an eighth transistor T8. The first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode is connected to the second node N2, and the gate is connected to the second reset signal terminal Re2. The storage circuit 10 includes a capacitor C. The first electrode of the capacitor C is connected to the first node N1, and the second electrode is connected to the first power supply terminal. One electrode of the light-emitting unit OLED is connected to the second electrode of the sixth transistor T6, and the other electrode of the light-emitting unit OLED is connected to the second power supply terminal VSS. The first power supply terminal VDD is a high-level power supply terminal, and the second power supply terminal VSS is a low-level power supply terminal.

[0146] In this exemplary embodiment, as shown in FIG1 , the first transistor T1 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0147] FIG2 is a timing diagram of some nodes in a driving method of the pixel driving circuit shown in FIG1. ​​In particular, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM.

[0148] The pixel driving circuit includes a first reset phase t1, a data writing phase t2, a third reset phase t3, and a light-emitting phase t4 during a high refresh rate driving period. During the first reset phase t1, the first gate driving signal terminal G1 and the third gate driving signal terminal G3 output high-level signals, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1, the second transistor T2, and the ninth transistor T9 are turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to the first node N1 via the first transistor T1, the second transistor T2, and the ninth transistor T9. During the data writing phase t2, the first gate driving signal terminal G1 and the third gate driving signal terminal G3 output high-level signals, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4, the second transistor T2, and the ninth transistor T9 are turned on, and the data signal terminal Da writes a compensation voltage Vdata+Vth to the first node N1 via the fourth transistor T4, the second transistor T2, and the ninth transistor T9, where Vdata is the voltage of the data signal on the data signal terminal and Vth is the threshold voltage of the driving transistor T3. In the third reset stage t3: the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. The third initial signal can improve the hysteresis problem of the driving transistor T3. In the light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current formula of the driving transistor is as follows: I=(μWCox / 2L)(Vgs-Vth) 2

[0149] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0150] During the high refresh frequency driving period of the pixel driving circuit, the third gate driving signal terminal G3 outputs a high level signal at least in the first reset phase t1 and the data writing phase t2, and the third gate driving signal terminal G3 can output a low level signal or a high level signal in other phases.

[0151] The pixel driving circuit also includes a first reset phase t1, a data writing phase t2, a third reset phase t3, and a light emitting phase t4 during a low refresh frequency driving period. During the low refresh frequency driving period, the third gate driving signal terminal G3 inputs a low-level signal to turn off the ninth transistor T9 at least during the first reset phase t1 and the data writing phase t2, thereby preventing the pixel driving circuit from resetting the first node N1 and rewriting a new data signal to the first node N1. Thus, the pixel driving circuit can achieve low-frequency driving.

[0152] During the low refresh frequency driving period of the pixel driving circuit, the third gate driving signal terminal G3 outputs a low level signal at least in the first reset phase t1 and the data writing phase t2. The third gate driving signal terminal G3 can output a low level signal or a high level signal in other phases.

[0153] This exemplary embodiment also provides a display panel, wherein the display panel includes the above-mentioned pixel driving circuit.

[0154] FIG3 is a schematic diagram illustrating the structure of an exemplary embodiment of a display panel according to the present disclosure. The display panel may include a plurality of pixel drive circuits pxij, wherein the plurality of pixel drive circuits pixij are arranged in an array along a first direction X and a second direction Y, where the second direction Y intersects the first direction X. For example, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0155] The display panel may also include a scanning drive circuit, a light-emitting drive circuit, a source drive circuit, and a frequency control circuit. The source drive circuit provides data signals to the data signal terminal of the pixel drive circuit through multiple data lines (Da1 to Dan); the scanning drive circuit provides first gate drive signals to the first gate drive signal terminal in the pixel drive circuit through multiple first gate lines (G11 to G1m), the first gate lines being connected to the gates of multiple second transistors in multiple pixel drive circuits distributed in a first direction. In addition, the scanning drive circuit may also provide gate drive signals to the pixel drive circuits in the same row through other scanning signal lines, the gate drive signals including one or more of a first reset signal at the first reset signal terminal, a second reset signal at the second reset signal terminal, and a second gate drive signal at the second gate drive signal terminal; the light-emitting drive circuit provides enable signals to the enable signal terminal in the pixel drive circuit through multiple enable signal lines (EM1 to EMo). The frequency control circuit provides a third gate driving signal to a third gate driving signal terminal in the pixel driving circuit through a plurality of third gate lines (G31-G3n), and the third gate lines are connected to the gates of a plurality of ninth transistors in a plurality of pixel driving circuits distributed in the second direction.

[0156] The display panel can achieve different refresh frequencies for different pixel drive circuit columns by controlling the signal of the third gate line.

[0157] It should be understood that in other exemplary embodiments, the third gate line may also extend along the first direction X, and the third gate line may be connected to the gates of multiple ninth transistors in multiple pixel driving circuits distributed in the first direction. The display panel may achieve different refresh frequencies for different pixel driving circuit rows by controlling the signal of the third gate line.

[0158] This exemplary embodiment further provides a display panel, which may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer stacked in sequence. Insulating layers may be provided between adjacent layers. As shown in Figures 4-20, Figure 4 is a structural layout of an exemplary embodiment of the display panel disclosed herein, Figure 5 is a structural layout of the blocking layer in Figure 4, Figure 6 is a structural layout of the first active layer in Figure 4, Figure 7 is a structural layout of the first conductive layer in Figure 4, Figure 8 is a structural layout of the second conductive layer in Figure 4, Figure 9 is a structural layout of the second active layer in Figure 4, Figure 10 is a structural layout of the third conductive layer in Figure 4, Figure 11 is a structural layout of the fourth conductive layer in Figure 4, Figure 12 is a structural layout of the fifth conductive layer in Figure 4, Figure 13 is a structural layout of the sixth conductive layer in Figure 4, Figure 14 is a structural layout of the blocking layer and the first active layer in Figure 4, and Figure 15 is a structural layout of the blocking layer, the first active layer, and the first conductive layer in Figure 4. 4 , FIG16 is the structural layout of the blocking layer, the first active layer, the first conductive layer, and the second conductive layer in FIG4 , FIG17 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG4 , FIG18 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG4 , FIG19 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG4 , and FIG20 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG4 .

[0159] The display panel may include a plurality of pixel driving circuits as shown in FIG1 . As shown in FIG4 , the display panel may include a plurality of pixel units distributed in a first direction X and a second direction Y. The pixel units may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently distributed in the first direction X. At least a portion of the structure of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in mirror symmetry along a mirror symmetry plane AA. The mirror symmetry plane AA may be perpendicular to the substrate. The orthographic projection of the first pixel driving circuit Pix1 on the substrate and the orthographic projection of the second pixel driving circuit Pix2 on the substrate may at least partially be arranged symmetrically along the intersection of the mirror symmetry plane AA and the substrate as an axis of symmetry. The first direction X and the second direction Y intersect. For example, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0160] As shown in FIG. 4 , 5 and 14 , the shielding layer includes a plurality of shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are connected to each other.

[0161] As shown in Figures 4, 6, 14 and 15, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, an eighteenth active portion 718 and a nineteenth active portion 719. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the tenth active portion 710 and the twelfth active portion 712 are connected to both ends of the eighth active portion 78. In the same pixel unit, two pixel driving circuits can share the same twelfth active portion 712; the eleventh active portion 7 11 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to the side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to the side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to the side of the fifth active portion 75 away from the third active portion 73. In the same pixel unit, two pixel driving circuits can share the same fifteenth active portion 715; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76, the seventeenth active portion 717 and the eighteenth active portion 718 are connected to both ends of the first active portion 71; and the nineteenth active portion 719 is connected between the third active portion 73 and the sixth active portion 76. The first active layer may be formed of polysilicon material. Accordingly, the first transistor T1 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be P-type low-temperature polysilicon thin film transistors.

[0162] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can shield the third active portion 73 from light, thereby improving the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure and can be connected to a stable voltage source to provide signal shielding for the pixel driving circuit.

[0163] As shown in Figures 4, 7, and 15, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line Re1 on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor C. The display panel can use the first conductive layer as a mask to conduct conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0164] As shown in Figures 4, 8, and 16, the second conductive layer may include: a fourth gate line 2G1, a second conductive portion 22, a third conductive portion 23, and a first initial signal line Vinit1. The orthographic projections of the fourth gate line 2G1 and the first initial signal line Vinit1 on the base substrate extend along the first direction X, and the fourth gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 1. The orthographic projection of the third conductive portion 23 on the base substrate is located between the orthographic projection of the fourth gate line 2G1 on the base substrate and the orthographic projection of the first initial signal line Vinit1 on the base substrate, and the third conductive portion 23 can be used to provide the third gate drive signal terminal in Figure 1. The second conductive portion 22 includes a first sub-conductive portion 221 and a second sub-conductive portion 222, and the second sub-conductive portion 222 is connected between two adjacent first sub-conductive portions 221 in the first direction X. The orthographic projection of the second gate line G2 on the substrate is located on a side of the orthographic projection of the fourth gate line 2G1 on the substrate that is away from the orthographic projection of the second conductive portion 22 on the substrate. The orthographic projection of the fourth gate line 2G1 on the substrate substrate is formed with a first groove 2G11 on a side facing the orthographic projection of the second gate line G2 on the substrate, and the orthographic projection of the second conductive portion 22 on the substrate substrate is formed with a second groove 224 on a side facing the orthographic projection of the second gate line G2 on the substrate. The first groove 2G11 and the orthographic projection of the channel region (fourth active portion 74) of the fourth transistor on the substrate substrate are arranged opposite to each other in the second direction Y, and the first groove 2G11 and the second groove 224 are arranged opposite to each other in the second direction Y. This arrangement can increase the distance between the fourth gate line 2G1 located at the first groove 2G11 and the second gate line G2, thereby reducing mutual interference of signals between the fourth gate line 2G1 and the second gate line G2, thereby improving the display effect of the display panel. The relative arrangement of structure A and structure B in the second direction can be understood as follows: the area covered by the infinite extension of structure A along the second direction overlaps the area covered by the infinite extension of structure B along the second direction. The orthographic projection of the first sub-conductive portion 221 on the base substrate can at least partially overlap the orthographic projection of the first conductive portion 11 on the base substrate. The first sub-conductive portion 221 is used to form the second electrode of capacitor C.

[0165] As shown in Figures 4, 9, and 17, the second active layer may include an active portion 9, which may include: a second active portion 92, a ninth active portion 99, a twentieth active portion 920, and a twenty-first active portion 921. The twentieth active portion 920 is connected to the side of the second active portion 92 away from the ninth active portion 99, and the twenty-first active portion 921 is connected to the side of the ninth active portion 99 away from the second active portion 92. The second active portion 92 is used to form the channel region of the second transistor T2, and the ninth active portion 99 is used to form the channel region of the ninth transistor T9. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 and the ninth transistor T9 may be N-type metal oxide thin film transistors. The orthographic projection of the fourth gate line 2G1 on the substrate may cover the orthographic projection of the second active portion 92 on the substrate, and a portion of the structure of the fourth gate line 2G1 may be used to form the bottom gate of the second transistor T2. The orthographic projection of the third conductive portion 23 on the base substrate covers the orthographic projection of the ninth active portion 99 on the base substrate, and a portion of the structure of the third conductive portion 23 is used to form the bottom gate of the ninth transistor T9.

[0166] As shown in Figures 4, 10, and 18, the third conductive layer may include a first gate line 3G1, a second initial signal line Vinit2, a third initial signal line Vinit3, and a fourth conductive portion 34. The orthographic projection of the first gate line 3G1 on the base substrate, the orthographic projection of the second initial signal line Vinit2 on the base substrate, and the orthographic projection of the third initial signal line Vinit3 on the base substrate may all extend along the first direction X. The first gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 1, the orthographic projection of the first gate line 3G1 on the base substrate may cover the orthographic projection of the second active portion 92 on the base substrate, and a partial structure of the first gate line 3G1 may be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 may be connected to the fourth gate line 2G1 through a via located in the frame area of ​​the display panel. The second initial signal line Vinit2 may be used to provide the second initial signal terminal in Figure 1, and the third initial signal line Vinit3 may be used to provide the third initial signal terminal in Figure 1. The orthographic projection of the fourth conductive portion 34 on the substrate covers the orthographic projection of the ninth active portion 99 on the substrate. Part of the structure of the fourth conductive portion 34 is used to form the top gate of the ninth transistor. In addition, the display panel can use the third conductive layer as a mask to perform a conductor process on the second active layer. That is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0167] As shown in Figures 4, 11, and 19, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, and a ninth bridge portion 49. The first bridge portion 41 is connected to the twelfth active portion 712 and the third initial signal line Vinit3 through vias, thereby connecting the third initial signal terminal and the first electrode of the eighth transistor T8. The second bridge portion 42 is connected to the nineteenth active portion 719, the twentieth active portion 920, and the seventeenth active portion 717 through vias, thereby connecting the second electrode of the second transistor T2, the second electrode of the driving transistor T3, and the second electrode of the first transistor T1. The third bridge portion 43 is connected to the eighteenth active portion 718 and the first initial signal line Vinit1 through vias, thereby connecting the first electrode of the first transistor T1 and the first initial signal terminal. The fourth bridge portion 44 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode and the second initial signal terminal of the seventh transistor T7. The fifth bridge portion 45 is connected to the thirteenth active portion 713 through a via to connect the first electrode of the fourth transistor T4. The sixth bridge portion 46 is connected to the eleventh active portion 711 and the tenth active portion 710 through vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 is connected to the second sub-conductive portion 222 and the fifteenth active portion 715 through vias, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. Two pixel driving circuits in the same pixel unit can share the same seventh bridge portion 47. The eighth bridge portion 48 is connected to the sixteenth active portion 716 through a via to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 connects the twenty-first active portion 921 and the first conductive portion 11 via vias, thereby connecting the gate of the driving transistor T3 and the first electrode of the ninth transistor T9. An opening 223 may be formed on the first sub-conductive portion 221, and a via connecting the ninth bridge portion 49 and the first conductive portion 11 extends through the opening 223. The tenth bridge portion 410 may connect the third conductive portion 23 and the fourth conductive portion 34 via vias, thereby connecting the gate of the ninth transistor T9. The fourth conductive layer may further include an initial connection line Vinitx, the orthographic projection of which on the base substrate extends along the second direction Y. There may be multiple initial connection lines Vinitx, and the initial connection lines Vinitx may be connected to initial signal lines intersecting with their orthographic projections on the base substrate via vias, thereby forming a grid structure of the initial signal lines. This arrangement can reduce the voltage difference between the initial signal terminals at different locations on the display panel. The initial signal lines include one or more of the first initial signal line, the second initial signal line, and the third initial signal line described above.For example, three adjacent columns of pixel driving circuits may be respectively provided with initial connection lines Vinitx, wherein one initial connection line Vinitx is connected to the first initial signal line, one initial connection line Vinitx is connected to the second initial signal line, and one initial connection line Vinitx is connected to the third initial signal line.

[0168] As shown in Figures 4, 12, and 20, the fifth conductive layer may include: an eleventh bridge portion 511, a twelfth bridge portion 512, a thirteenth bridge portion 513, and a first power line VDD. The eleventh bridge portion 511 is connected to the fifth bridge portion 45 via a first via H1, the twelfth bridge portion 512 is connected to the tenth bridge portion 410 via a second via H2, and the thirteenth bridge portion 513 is connected to the eighth bridge portion 48 via a via. The first power line VDD is used to provide the first power terminal shown in Figure 1. The orthographic projection of the first power line VDD on the substrate extends along the second direction Y. The first power line VDD is connected to the seventh bridge portion 47 via a via, thereby connecting to the first electrode of the fifth transistor.

[0169] As shown in Figures 4 and 13, the sixth conductive layer may include: a data line Da, a third gate line G3, and a fourteenth bridge portion 614. The orthographic projections of the data line Da and the third gate line G3 on the substrate may extend along the second direction Y. The data line Da is used to provide the data signal terminal in Figure 1, and the third gate line G3 is used to provide the third gate drive signal terminal in Figure 1. The data line Da may be connected to the eleventh bridge portion 511 through the third via H3 to connect the data signal terminal and the first electrode of the fourth transistor. The third gate line G3 may be connected to the twelfth bridge portion 512 through the fourth via H4 to connect the gate of the ninth transistor T9 and the third gate drive signal terminal. There may be multiple first power lines VDD, and the orthographic projections of the multiple first power lines VDD on the substrate extend along the second direction Y and are spaced apart along the first direction X. In adjacent pixel units in the first direction X, adjacent first power lines VDD may be connected to each other. The fourteenth bridge portion 614 can be connected to the thirteenth bridge portion 513 through a via hole to connect to the second electrode of the sixth transistor. The fourteenth bridge portion 614 can also be used to connect to the light emitting unit.

[0170] In this exemplary embodiment, as shown in Figure 4-20, the channel regions of the ninth transistor T9 and the second transistor T2 are located in the second active layer. It should be understood that in other exemplary embodiments, the channel regions of the ninth transistor T9 and the second transistor T2 can also be located in other active layers. For example, the channel regions of the ninth transistor T9 and the second transistor T2 can also be the first active layer.

[0171] In this exemplary embodiment, as shown in FIG. 4-20 , in the same pixel driving circuit, the orthographic projection of the second gate line G2 on the substrate is located between the orthographic projection of the channel region of the second transistor T2 on the substrate and the orthographic projection of the channel region of the ninth transistor T9 on the substrate.

[0172] In this exemplary embodiment, as shown in FIG. 4-20 , in the first direction X of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor T9 on the substrate is located between the orthographic projection of the channel region of the fourth transistor T4 on the substrate and the orthographic projection of the channel region of the second transistor T2 on the substrate.

[0173] In this exemplary embodiment, as shown in FIG. 4-20 , the length direction of the channel region of the second transistor T2 is the second direction Y, and the length direction of the channel region of the ninth transistor T9 is the first direction X.

[0174] In this exemplary embodiment, as shown in FIG4-20 , the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the channel region of the ninth transistor T9 on the substrate at least partially overlap; the width of the channel region of the second transistor T2 is greater than the width of the channel region of the ninth transistor T9, and / or the length of the channel region of the second transistor T2 is greater than the length of the channel region of the ninth transistor T9. In this exemplary embodiment, the width and length of the channel region of the ninth transistor T9 are set to be smaller. This setting can facilitate the orthographic projection of the first power line VDD on the substrate to overlap the orthographic projection of the channel region of the ninth transistor T9 on the substrate. On the one hand, the first power line VDD can reduce the impact of light on the output characteristics of the ninth transistor T9. On the other hand, the first power line VDD can also shield the ninth transistor T9 from interference from other signals.

[0175] In this exemplary embodiment, as shown in FIG. 4-20 , the third gate line G3 is located in the sixth conductive layer. It should be understood that in other exemplary embodiments, the third gate line G3 may also be located in other conductive layers, for example, the third gate line G3 may also be located in the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, etc. The orthographic projection of the third gate line G3 on the substrate may also extend along the first direction X.

[0176] 4-20 , the orthographic projection of the third gate line G3 on the substrate at least partially overlaps the orthographic projection of the first power line VDD on the substrate. The first power line VDD can shield the third gate line G3 from interference from other signals.

[0177] In this exemplary embodiment, as shown in FIG. 4-20 , the orthographic projection of the first power line VDD on the substrate at least partially overlaps the orthographic projection of the second bridge portion 42 on the substrate, and the orthographic projection of the first power line VDD on the substrate at least partially overlaps the orthographic projection of the ninth bridge portion 49 on the substrate. The first power line VDD can stabilize the voltage of the second bridge portion 42 and the ninth bridge portion 49, thereby improving the stability of the voltage at the first node N1 and the third node N3.

[0178] In this exemplary embodiment, as shown in FIG4-20 , the first gate line 3G1 includes a first extension portion 3G11 and a second extension portion 3G12. The first extension portion 3G11 is used to form the top gate of the second transistor T2. The orthographic projection of the first extension portion 3G11 on the substrate in the second direction Y is larger than the orthographic projection of the second extension portion 3G12 on the substrate in the second direction Y. The second bridge portion 42 includes a first sub-bridge portion 421. The orthographic projection of the first sub-bridge portion 421 on the substrate extends along the second direction Y. The orthographic projection of the first sub-bridge portion 421 on the substrate intersects with the orthographic projection of the second extension portion 3G12 on the substrate. This arrangement can reduce the overlapping area between the second bridge portion 42 and the first gate line 3G1, thereby reducing the coupling effect of the first gate line 3G1 on the third node N3, thereby improving the display quality of the display panel. The fourth gate line 2G1 can also include a third extension portion 2G13 and a fourth extension portion 2G14. The size of the orthographic projection of the third extension portion 2G13 on the substrate in the second direction Y is larger than the size of the orthographic projection of the fourth extension portion 2G14 on the substrate in the second direction Y. The orthographic projection of the first sub-bridge portion 421 on the substrate and the orthographic projection of the fourth extension portion 2G14 on the substrate intersect. This setting can also reduce the coupling effect of the fourth gate line 2G1 on the third node N3.

[0179] In this exemplary embodiment, as shown in Figure 4-20, the second bridge portion 42 also includes: a second sub-bridge portion 422 and a third sub-bridge portion 423, the second sub-bridge portion 422 is connected to the second electrode of the first transistor T1 through a via; the third sub-bridge portion 423 is connected to the second electrode of the second transistor T2 and the second electrode of the driving transistor T3 through a via; wherein the first sub-bridge portion 421 is connected between the second sub-bridge portion 422 and the third sub-bridge portion 423, and the orthographic projection of the first sub-bridge portion 421 on the substrate and the orthographic projection of the second sub-bridge portion 422 on the substrate form an angle a less than 180°, and the orthographic projection of the first sub-bridge portion 421 on the substrate and the orthographic projection of the third sub-bridge portion 423 on the substrate form an angle b less than 180°.

[0180] In this exemplary embodiment, as shown in FIG4-20 , the distance between the orthographic projection of the third via H3 on the substrate and the orthographic projection of the first via H1 on the substrate is greater than the distance between the orthographic projection of the fourth via H4 on the substrate and the orthographic projection of the second via H2 on the substrate. In this exemplary embodiment, the distance between the orthographic projection of the fourth via H4 on the substrate and the orthographic projection of the second via H2 on the substrate is set as small as possible, thereby facilitating increasing the area of ​​the third gate line G3 shielded by the first power line VDD, thereby improving the shielding effect of the first power line VDD on the third gate line G3.

[0181] As shown in FIG4-20 , the shielding layer may further include a connecting portion 82 connected between adjacent shielding portions 81. The orthographic projection of the connecting portion 82 on the base substrate extends along the second direction Y. The connecting portion 82 includes a first sub-connecting portion 821, a second sub-connecting portion 822, and a third sub-connecting portion 823 distributed in the direction of its extension. The first sub-connecting portion 821 is connected between the second sub-connecting portion 822 and the third sub-connecting portion 823. The orthographic projection of the first sub-connecting portion 821 on the base substrate in the first direction X is smaller than the orthographic projection of the second sub-connecting portion 822 on the base substrate in the first direction X. The orthographic projection of the first sub-connecting portion 821 on the base substrate in the first direction X is smaller than the orthographic projection of the third sub-connecting portion 823 on the base substrate in the first direction X. The orthographic projection of the via connecting between the tenth bridge portion 410 and the third conductive portion 23 on the substrate lies within the orthographic projection of the second sub-connection portion 822 on the substrate; the orthographic projection of the via connecting between the ninth bridge portion 49 and the twenty-first active portion 921 on the substrate lies within the orthographic projection of the second sub-connection portion 822 on the substrate; and the orthographic projection of the via connecting between the third bridge portion 43 and the first initial signal line Vinit1 on the substrate lies within the orthographic projection of the third sub-connection portion 823 on the substrate. This arrangement ensures uniform exposure of the three types of vias during the manufacturing exposure process, thereby improving the dimensional uniformity of the same type of vias.

[0182] It should be noted that, as shown in Figures 4, 19, and 20, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the sixth conductive layer facing away from the substrate represent vias connecting the sixth conductive layer to other layers facing the substrate. Different vias represented by black squares in different locations can penetrate different insulating layers.

[0183] FIG21 is a partial cross-sectional view of the display panel shown in FIG4 taken along dotted line BB. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, and a second planarization layer 109. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the passivation layer 107, the first planarization layer 108, the fifth conductive layer, the second planarization layer 109, and the sixth conductive layer are stacked in sequence. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure. The materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The materials of the first planarizing layer 108 and the second planarizing layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 97 can be a silicon oxide layer. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The first, second, and third conductive layers can be made of molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate thereof. The fourth, fifth, and sixth conductive layers can be made of a metal material, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate thereof, or a titanium / aluminum / titanium laminate thereof. The sheet resistance of any of the fourth, fifth, and sixth conductive layers can be less than the sheet resistance of any of the first, second, and third conductive layers.

[0184] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending in a straight line or bending along that direction.

[0185] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0186] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0187] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0188] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A pixel driving circuit, wherein: The pixel driving circuit includes: a driving circuit connected to the first node, the second node, and the third node, the driving circuit being configured to input a driving current to the third node via the second node according to a signal of the first node; a refresh control circuit, the refresh control circuit being connected to the first node, the fourth node, and a third gate drive signal terminal, the refresh control circuit being configured to connect the first node and the fourth node in response to a signal from the third gate drive signal terminal; The compensation circuit is connected to the third node, the fourth node, and the first gate drive signal terminal, and is used to respond to the signal of the first gate drive signal terminal to connect the third node and the fourth node.

2. The pixel driving circuit according to claim 1, wherein: The refresh control circuit includes: A ninth transistor has a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate connected to the third gate drive signal terminal.

3. The pixel driving circuit according to claim 2, wherein: The ninth transistor is an N-type transistor.

4. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit is applied to a display panel; In a low refresh cycle of the display panel, the refresh control circuit is used to turn off the third node and the fourth node at least in a data writing phase; During a high refresh period of the display panel, the refresh control circuit is configured to conduct the third node and the fourth node at least during a data writing phase.

5. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes: A first reset circuit is connected to the third node, the first initial signal terminal, and the first reset signal terminal. The first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the third node.

6. The pixel driving circuit according to claim 5, wherein: The pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes: a data writing circuit connected to the data signal terminal, the second node, and the second gate driving signal terminal, wherein the data writing circuit is configured to respond to a signal from the second gate driving signal terminal to transmit the signal from the data signal terminal to the second node; a light-emitting control circuit connected to the second node, the first power supply terminal, the third node, the light-emitting unit, and an enable signal terminal, the light-emitting control circuit being configured to connect the first power supply terminal and the second node in response to a signal from the enable signal terminal, and to connect the third node and the light-emitting unit in response to a signal from the enable signal terminal; a second reset circuit connected to the light-emitting unit, the second initial signal terminal, and the second reset signal terminal, the second reset circuit being configured to respond to a signal from the second reset signal terminal to transmit the signal from the second initial signal terminal to the light-emitting unit; a third reset circuit connected to the second node and a third initial signal terminal, the third reset circuit being configured to respond to a reset signal to transmit a signal from the third initial signal terminal to the second node; The storage circuit is connected between the first node and the first power supply terminal.

7. The pixel driving circuit according to claim 6, wherein: The driving circuit includes: a driving transistor, wherein a first electrode of the driving transistor is connected to the second node, a second electrode of the driving transistor is connected to the third node, and a gate of the driving transistor is connected to the first node; The compensation circuit comprises: a second transistor, wherein a first electrode of the second transistor is connected to the fourth node, a second electrode of the second transistor is connected to the third node, and a gate of the second transistor is connected to the first gate drive signal terminal; The first reset circuit includes: a first transistor, wherein a first electrode of the first transistor is connected to the first initial signal terminal, a second electrode of the first transistor is connected to the third node, and a gate of the first transistor is connected to the first reset signal terminal; The second reset circuit includes: a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second initial signal terminal, a second electrode is connected to the light emitting unit, and a gate is connected to the second reset signal terminal; The data writing circuit includes: a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data signal terminal, a second electrode of the fourth transistor is connected to the second node, and a gate of the fourth transistor is connected to the second gate drive signal terminal; The light emitting control circuit includes: a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply terminal, a second electrode of the fifth transistor is connected to the second node, and a gate of the fifth transistor is connected to the enable signal terminal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the third node, a second electrode is connected to the light emitting unit, and a gate is connected to the enable signal terminal; The third reset circuit is further connected to the second reset signal terminal, and is configured to respond to a signal from the second reset signal terminal to transmit a signal from the third initial signal terminal to the second node, wherein the third reset circuit includes: an eighth transistor, having a first electrode connected to the third initial signal terminal, a second electrode connected to the second node, and a gate connected to the second reset signal terminal; The storage circuit includes: A capacitor, wherein a first electrode of the capacitor is connected to the first node, and a second electrode of the capacitor is connected to the first power supply terminal.

8. The pixel driving circuit according to claim 7, wherein: The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

9. A display panel, wherein: The display panel comprises the pixel driving circuit according to any one of claims 1 to 8.

10. The display panel according to claim 9, wherein: The display panel includes a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are arrayed along a first direction and a second direction, wherein the second direction intersects the first direction; The display panel also includes a first gate line and a third gate line, the first gate line is connected to multiple first gate drive signal terminals in multiple pixel drive circuits distributed in the first direction, and the third gate line is connected to multiple third gate drive signal terminals in multiple pixel drive circuits distributed in the second direction.

11. A display panel, wherein: The display panel includes: substrate; A pixel driving circuit is located on one side of the substrate, and the pixel driving circuit includes: a driving transistor, a second transistor, and a ninth transistor, wherein the first electrode of the ninth transistor is connected to the gate of the driving transistor, the first electrode of the second transistor is connected to the second electrode of the ninth transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor.

12. The display panel according to claim 11, wherein: The display panel further includes: a first active layer located on one side of the base substrate, the first active layer comprising a third active portion, the third active portion being used to form a channel region of the driving transistor; The second active layer is located on a side of the first active layer away from the base substrate, and the second active layer includes a ninth active portion, and the ninth active portion is used to form a channel region of the ninth transistor.

13. The display panel according to claim 12, wherein: The second active layer further includes a second active portion, and the second active portion is used to form a channel region of the second transistor.

14. The display panel according to claim 11, wherein: The pixel driving circuit further includes a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a second gate line located on one side of the base substrate, an orthographic projection of the second gate line on the base substrate extending along a first direction, and a portion of the second gate line being used to form a gate of the fourth transistor; In the same pixel driving circuit, the orthographic projection of the second gate line on the base substrate is located between the orthographic projection of the channel region of the second transistor on the base substrate and the orthographic projection of the channel region of the ninth transistor on the base substrate.

15. The display panel according to claim 11, wherein The pixel driving circuit further includes a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; In the first direction of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the substrate is located between the orthographic projection of the channel region of the fourth transistor on the substrate and the orthographic projection of the channel region of the second transistor on the substrate.

16. The display panel according to claim 11, wherein: The length direction of the channel region of the second transistor is the second direction, the length direction of the channel region of the ninth transistor is the first direction, and the first direction and the second direction intersect.

17. The display panel according to claim 11, wherein: The display panel further includes: A first power line is located on one side of the substrate, and the first power line is used to supply The pixel driving circuit provides a high-level signal, and an orthographic projection of the first power line on the substrate and an orthographic projection of the ninth transistor channel region on the substrate at least partially overlap; The width of the channel region of the second transistor is greater than the width of the channel region of the ninth transistor, and / or the length of the channel region of the second transistor is greater than the length of the channel region of the ninth transistor.

18. The display panel according to claim 11, wherein: The display panel includes a plurality of pixel driving circuits distributed in an array in a first direction and a second direction, and the display panel further includes: a first gate line located on one side of the base substrate, an orthographic projection of the first gate line on the base substrate extending along a first direction, and a portion of the first gate line used to respectively form gates of a plurality of second transistors in a plurality of pixel driving circuits distributed in the first direction; A third gate line is located on one side of the base substrate, wherein the orthographic projection of the third gate line on the base substrate extends along a second direction, the second direction intersects the first direction, and the third gate line connects the gates of the plurality of ninth transistors in the plurality of pixel driving circuits distributed in the second direction.

19. The display panel according to claim 11, wherein: The display panel further includes: a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a ninth bridge portion, the ninth bridge portion being connected to the first electrode of the ninth transistor and the gate of the driving transistor through via holes; a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, the fifth conductive layer comprising a first power line, the first power line being used to provide a high-level signal to the pixel driving circuit; The sixth conductive layer is located on a side of the fifth conductive layer away from the base substrate. The sixth conductive layer includes a third gate line connected to the gate of the ninth transistor.

20. The display panel according to claim 19, wherein An orthographic projection of the third gate line on the base substrate and an orthographic projection of the first power line on the base substrate at least partially overlap.

21. The display panel according to claim 11, wherein The display panel further includes: The fourth conductive layer is located on one side of the base substrate, and the fourth conductive layer includes a second bridge portion and a ninth bridge portion, wherein the second bridge portion is connected to the driving transistor through a via hole. the second electrode of the ninth transistor and the second electrode of the second transistor, the ninth bridge portion being connected to the first electrode of the ninth transistor and the gate of the driving transistor through via holes respectively; a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, the fifth conductive layer comprising a first power line, the first power line being used to provide a high-level signal to the pixel driving circuit; The orthographic projection of the first power line on the base substrate and the orthographic projection of the second bridge portion on the base substrate at least partially overlap, and / or the orthographic projection of the first power line on the base substrate and the orthographic projection of the ninth bridge portion on the base substrate at least partially overlap.

22. The display panel according to claim 11, wherein The pixel driving circuit further includes a first transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a first gate line located on one side of the base substrate, an orthographic projection of the first gate line on the base substrate extending along a first direction, and a portion of the first gate line being used to form a gate of the second transistor; a second bridge portion, located on one side of the base substrate, the second bridge portion being connected to the second electrode of the driving transistor, the second electrode of the second transistor, and the second electrode of the first transistor through via holes; The first gate line includes a first extending portion and a second extending portion, the first extending portion is used to form the gate of the second transistor, a size of an orthographic projection of the first extending portion on the substrate in a second direction is larger than a size of an orthographic projection of the second extending portion on the substrate in the second direction, and the second direction intersects the first direction; The second bridging portion and the first gate line are located in different conductive layers. The second bridging portion includes a first sub-bridging portion. The orthographic projection of the first sub-bridging portion on the base substrate extends along the second direction. The orthographic projection of the first sub-bridging portion on the base substrate intersects with the orthographic projection of the second extension portion on the base substrate.

23. The display panel according to claim 22, wherein: The second bridging portion further includes: a second sub-bridge portion, the second sub-bridge portion being connected to the second electrode of the first transistor through a via; a third sub-bridge portion, the third sub-bridge portion being connected to the second electrode of the second transistor and the second electrode of the driving transistor through a via hole; In which, the first sub-bridge portion is connected between the second sub-bridge portion and the third sub-bridge portion, and an angle less than 180° is formed between the orthographic projection of the first sub-bridge portion on the substrate and the orthographic projection of the second sub-bridge portion on the substrate, and an angle less than 180° is formed between the orthographic projection of the first sub-bridge portion on the substrate and the orthographic projection of the third sub-bridge portion on the substrate.

24. The display panel according to claim 11, wherein The display panel includes a plurality of pixel driving circuits arrayed in a first direction and a second direction, the pixel driving circuit further including a capacitor and a fourth transistor, a first electrode of the capacitor connected to a gate of the driving transistor, a second electrode of the capacitor connected to a first power line, a first electrode of the fourth transistor connected to a data line, and a second electrode of the fourth transistor connected to the first electrode of the driving transistor; The display panel further includes: a first conductive layer located on one side of the base substrate, the first conductive layer comprising a second gate line, an orthographic projection of the second gate line on the base substrate extending along a first direction, and a portion of the second gate line being used to form a gate of the fourth transistor; a second conductive layer, the second conductive layer being located on a side of the first conductive layer away from the base substrate, the second conductive layer comprising a second conductive portion and a fourth gate line; The orthographic projection of the fourth gate line on the substrate extends along the first direction, and a portion of the structure of the fourth gate line is used to form a bottom gate of the second transistor; The second conductive portion includes a first sub-conductive portion and a second sub-conductive portion, the first sub-conductive portion is used to form a second electrode of the capacitor, and the second sub-conductive portion is connected between two adjacent first sub-conductive portions in the first direction; The orthographic projection of the second gate line on the base substrate is located on a side of the orthographic projection of the fourth gate line on the base substrate away from the orthographic projection of the second conductive portion on the base substrate; The orthographic projection of the fourth gate line on the substrate faces the second gate line. A first groove is formed on one side of the orthographic projection of the base substrate, and a second groove is formed on the side of the orthographic projection of the second conductive portion on the base substrate facing the orthographic projection of the second gate line on the base substrate; The orthographic projection of the first groove and the channel region of the fourth transistor on the base substrate is arranged opposite to each other in the second direction, and the first groove and the second groove are arranged opposite to each other in the second direction.

25. The display panel according to claim 11, wherein The pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a fifth conductive layer, located on one side of the base substrate, the fifth conductive layer comprising an eleventh bridge portion and a twelfth bridge portion, the eleventh bridge portion being connected to the first electrode of the fourth transistor through a first via hole, and the twelfth bridge portion being connected to the gate of the ninth transistor through a second via hole; a sixth conductive layer, located on a side of the fifth conductive layer facing away from the base substrate, the sixth conductive layer comprising a third gate line and a data line, the data line being connected to the eleventh bridge portion through a third via hole, and the third gate line being connected to the twelfth bridge portion through a fourth via hole; The distance between the orthographic projection of the third via hole on the base substrate and the orthographic projection of the first via hole on the base substrate is greater than the distance between the orthographic projection of the fourth via hole on the base substrate and the orthographic projection of the second via hole on the base substrate.

26. The display panel according to claim 11, wherein The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes: a first transistor, wherein a first electrode of the first transistor is connected to the first initial signal line, and a second electrode of the first transistor is connected to the second electrode of the driving transistor; a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor; a fifth transistor, a first electrode connected to the first power line, and a second electrode connected to the first electrode of the driving transistor; A sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the Light-emitting unit; a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the light-emitting unit; an eighth transistor, a first electrode of which is connected to the third initial signal line, and a second electrode of which is connected to the first electrode of the driving transistor; a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line; Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor and the ninth transistor are N-type transistors.

27. The display panel according to claim 11, wherein: The pixel driving circuit includes a P-type transistor and an N-type transistor, and the display panel further includes: a first active layer, located on one side of the base substrate, wherein a portion of the first active layer is used to form a channel region of a P-type transistor in the pixel driving circuit; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein a portion of the first conductive layer is used to form a gate of a P-type transistor in the pixel driving circuit; a second conductive layer, located on a side of the first conductive layer away from the base substrate, wherein a portion of the second conductive layer is used to form a bottom gate of an N-type transistor in the pixel driving circuit; a second active layer, located on a side of the second conductive layer facing away from the base substrate, wherein a portion of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit; a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein a portion of the third conductive layer is used to form a top gate of an N-type transistor in the pixel driving circuit; The fourth conductive layer is located on a side of the third conductive layer away from the base substrate, and a portion of the structure of the fourth conductive layer is used to form a bridge portion connecting different transistors.

28. A display device, wherein: The display device comprises the display panel according to any one of claims 9 to 27.

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