Display driving circuit, driving method and display device

Abstract

The invention discloses a display driving circuit, a driving method and a display device.The display driving circuit comprises a waveform adjusting circuit and a compensating circuit, and the waveform adjusting circuit is used for adjusting the power-on time of voltage waveforms of a common signal and a common electrode signal to be equal; or adjusting the power-on time of the voltage waveforms of the common signal and the shielding signal to be equal; and the compensation circuit performs operation processing on the received adjusting signal to generate a compensation signal, and outputs the compensation signal to the common electrode. Through the design, the problem of abnormal spikes of the data signals can be avoided, and the display image quality is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display driving circuit, a driving method, and a display device. Background Art

[0002] Liquid Crystal Display (LCD) panels have numerous advantages, including thinness, power efficiency, and radiation-free design, making them widely used. They are used, for example, in LCD televisions, mobile phones, digital cameras, monitors, and laptop screens, dominating the flat-panel display market. LCD panels have multiple conductive layers, including common and pixel electrodes on either side of the liquid crystal layer, a common electrode on the array substrate that forms a storage capacitor with the pixel electrode, and a shielding electrode that shields data and related signals in the event of erroneous liquid crystal deflection.

[0003] Due to the problem of abnormal spikes in the data signal, the liquid crystal display panel may have defects during display, affecting the display quality. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a display driving circuit, a driving method and a display device to avoid the problem of abnormal spikes in data signals and improve display quality.

[0005] The embodiment of the present application discloses a display driving circuit, which is used for a display device. The display device includes a power chip and a display panel. The display panel includes a common electrode, a common electrode and a shielding electrode. The power chip has a first power port, a second power port and a third power port. The first power port, the second power port and the third power port are used to provide a common signal, a common electrode signal and a shielding signal to the common electrode, the common electrode and the shielding electrode respectively. The display driving circuit includes a waveform adjustment circuit and a compensation circuit. The first receiving end of the waveform adjustment circuit is electrically connected to the first power port, and the second receiving end of the waveform adjustment circuit is electrically connected to the second power port or the third power port. The waveform adjustment circuit is used to convert the common signal and the shielding signal into a waveform adjustment signal. The power-on time of the voltage waveform of the common electrode signal is adjusted to be equal, or the power-on time of the voltage waveform of the common signal and the shielding signal is adjusted to be equal; the first output end of the waveform adjustment circuit outputs a first adjustment signal corresponding to the common signal, and the second output end of the waveform adjustment circuit outputs a second adjustment signal corresponding to the common electrode signal, or outputs a third adjustment signal corresponding to the shielding signal; the first interface of the compensation circuit is electrically connected to the first output end of the waveform adjustment circuit to receive the first adjustment signal; the second interface of the compensation circuit is electrically connected to the second output end of the waveform adjustment circuit to receive the second adjustment signal or the third adjustment signal; the compensation circuit generates a compensation signal after performing calculation processing on the received adjustment signal, and outputs the compensation signal to the common electrode.

[0006] Optionally, the waveform adjustment circuit includes a first switching circuit, a second switching circuit and a control unit, the input end of the first switching circuit is electrically connected to the first power port of the power chip and the first interface of the compensation circuit, respectively, and the output end of the first switching circuit is electrically connected to the second interface of the compensation circuit; the input end of the second switching circuit is electrically connected to the second power port or the third power port, and the output end of the second switching circuit is electrically connected to the second interface of the compensation circuit; the control unit is electrically connected to the first switching circuit and the second switching circuit at the same time, and controls the on and off of the first switching circuit and the second switching circuit respectively; and when the first switching circuit is turned on, the second switching circuit is disconnected; or, when the second switching circuit is turned on, the first switching circuit is disconnected.

[0007] Optionally, the first switching circuit includes a first MOS transistor, the input end of the first MOS transistor is electrically connected to the first power port of the power chip and the first interface of the compensation circuit respectively, the output end of the first MOS transistor is electrically connected to the second interface of the compensation circuit, and the control end of the first MOS transistor is connected to the control unit; the second switching circuit includes a second MOS transistor, the input end of the second MOS transistor is electrically connected to the second power port or the third power port, the output end of the second MOS transistor is electrically connected to the second interface of the compensation circuit, and the control end of the second MOS transistor is connected to the control unit.

[0008] Optionally, within the time 0-t1, the control unit controls the first switching circuit to be turned on and controls the second switching circuit to be turned off; after the time t1, the control unit controls the first switching circuit to be turned off and controls the second switching circuit to be turned on; wherein the time 0-t1 includes the power-on time of the common signal.

[0009] Optionally, both the first MOS transistor and the second MOS transistor are N-type MOS transistors.

[0010] Optionally, the waveform adjustment circuit includes a filtering unit, the filtering unit includes a resistor and a capacitor connected in series, and the capacitance value C of the capacitor and the resistance value R of the resistor meet the following conditions: ; When the power-on time of the voltage waveform of the common signal is greater than the power-on time of the voltage waveform of the common electrode signal or the power-on time of the voltage waveform of the shielding signal, the two ends of the filtering unit respectively serve as the second receiving end and the second output end of the waveform adjustment circuit; wherein, T2 is the power-on time of the voltage waveform of the common signal, and T1 is the power-on time of the voltage waveform of the common electrode signal or the power-on time of the voltage waveform of the shielding signal; when the power-on time of the voltage waveform of the common signal is less than the power-on time of the voltage waveform of the common electrode signal or the power-on time of the voltage waveform of the shielding signal, the two ends of the filtering unit respectively serve as the first receiving end and the first output end of the waveform adjustment circuit; wherein, T2 is the power-on time of the voltage waveform of the common electrode signal or the power-on time of the voltage waveform of the shielding signal, and T1 is the power-on time of the voltage waveform of the common signal.

[0011] Optionally, the waveform adjustment circuit also includes a third receiving end, and the three receiving ends of the waveform adjustment circuit are electrically connected to the three power ports of the power chip respectively. The waveform adjustment circuit is used to adjust the power-on time of the voltage waveforms of the common signal, the common electrode signal and the shielding signal to be equal.

[0012] Optionally, the compensation circuit includes an operational amplifier, the first input end of the operational amplifier is electrically connected to the first output end of the waveform adjustment circuit as the first interface, the second input end of the operational amplifier is electrically connected to the second output end of the waveform adjustment circuit as the second interface, and the output end of the operational amplifier is electrically connected to the common electrode.

[0013] The embodiment of the present application further discloses a driving method, which is used for the display driving circuit described above, and comprises the steps of: Receive the common signal and common electrode signal, or the common signal and shielding signal output by the power chip; Adjusting the power-on time of the voltage waveforms of the common signal and the common electrode signal to be equal, or adjusting the power-on time of the voltage waveforms of the common signal and the shielding signal to be equal; and The regulated signal is operated to generate a compensation signal, and the compensation signal is output to the common electrode.

[0014] An embodiment of the present application further discloses a display device, which includes a display panel and the display driving circuit as described above, wherein the display driving circuit is used to drive the display panel.

[0015] The advantageous effects of the embodiments of the present application are as follows: for a compensation design using a common electrode signal voltage to compensate for a common signal voltage, the embodiments of the present application adjust the power-up time of the common electrode signal voltage waveform and the power-up time of the common signal voltage waveform to be equal through a waveform adjustment circuit, so that the voltage difference between the common electrode signal and the common signal voltage is small during the rising process; the adjusted common signal and the common electrode signal are then transmitted to the compensation circuit for calculation to generate a compensation signal, so that the actual voltage of the common electrode after compensation does not have abnormal spikes, and thus the data signal does not have abnormal spikes, thereby avoiding deterioration in display quality. Similarly, for a compensation design using a shielding signal voltage to compensate for a common signal voltage, the embodiments of the present application adjust the power-up time of the common signal voltage waveform and the power-up time of the shielding signal voltage waveform to be equal through a waveform adjustment circuit, and then the adjusted common signal and the shielding signal are transmitted to the compensation circuit for calculation to generate a compensation signal, so that the actual voltage of the common electrode after compensation does not have abnormal spikes, and thus the data signal does not have abnormal spikes, thereby avoiding deterioration in display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings: Figure 1 is an exemplary waveform diagram; Figure 2 is a schematic diagram of a display driving circuit provided in the first embodiment of the present application; Figure 3 is a schematic diagram of another display driving circuit provided in the first embodiment of the present application; Figure 4 is a schematic diagram of a waveform adjustment circuit provided in the first embodiment of the present application; Figure 5 is a schematic diagram of another waveform adjustment circuit provided in the first embodiment of the present application; Figure 6 This is a waveform diagram provided by the first embodiment of the present application; Figure 7 is a schematic diagram of a compensation circuit provided in the first embodiment of the present application; Figure 8 This is a schematic diagram of the connection between a waveform adjustment circuit and a power chip provided in the first embodiment of the present application; Figure 9 is a schematic diagram of a display driving circuit provided in a second embodiment of the present application; Figure 10 is a schematic diagram of a driving method provided in the third embodiment of the present application; Figure 11 This is a schematic diagram of a display device provided in the fourth embodiment of the present application.

[0017] Among them, 10, display device; 20, display panel; 21, common electrode; 22, common electrode; 23, shielding electrode; 30, power chip; 31, first power port; 32, second power port; 33, third power port; 40, display driver circuit; 100, waveform adjustment circuit; 100A1, first receiving end; 100A2, second receiving end; 100A3, third receiving end; 100B1, first output end; 100B2, second output end; 110, first switching circuit ;111, first MOS tube;120, second switching circuit;121, second MOS tube;130, control unit;140, filtering unit;141, resistor;142, capacitor;200, compensation circuit;200A1, first interface;200A2, second interface;210, operational amplifier;220, auxiliary resistor;230, auxiliary capacitor;VCOM, common signal;AVCOM, common electrode signal;DBSCOM, shielding signal; compensation signal, CFCOM. DETAILED DESCRIPTION

[0018] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative. However, the present application can be implemented in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0019] In addition, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense, and may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0020] In LCD panels, the non-uniformity of electrical parameters and the long-term use of the common electrode can lead to common electrode voltage offsets, necessitating common electrode compensation to improve pixel drive voltage stability. In current common driver designs, since the common electrode, the common electrode, and the shield electrode are all provided by a power IC, the common electrode signal voltage can be used to compensate for the common signal voltage. For example, the signal voltage of the common electrode within the display panel can be fed back to compensate for the common electrode voltage, or the shield electrode signal voltage can be used to compensate for the common signal voltage.

[0021] Figure 1 is an exemplary waveform diagram, where the horizontal axis represents time and the vertical axis represents voltage. Figure 1As shown, in the compensation design that uses the common electrode signal voltage to compensate for the common signal voltage, the power-on time of the voltage waveform of the common signal VCOM-1 is inconsistent with the power-on time of the voltage waveform of the common electrode signal AVCOM-1. The power-on time of the voltage waveform of the common signal VCOM is significantly shorter than the power-on time of the voltage waveform of the common electrode signal AVCOM-1. There is a large difference in voltage between the common signal VCOM-1 and the common electrode signal AVCOM-1, resulting in the common electrode voltage CFCOM-1 compensated to the common electrode based on the common signal VCOM-1 and the common electrode signal AVCOM-1 being much larger than the voltage that the power chip originally needs to output to the common electrode, resulting in abnormal spikes in the voltage waveform of the common electrode voltage CFCOM-1. Since the data voltage is used to control the brightness of the display panel, and the common electrode voltage CFCOM-1 and the pixel electrode voltage TCOM-1 achieve brightness control by controlling the deflection of liquid crystal molecules, the data voltage and the common electrode voltage CFCOM-1 are related; when the power is turned on, the data voltage output by the source driver chip will follow the common electrode voltage CFCOM-1 to ensure that the data voltage and the common electrode voltage CFCOM-1 maintain the same voltage level. Therefore, when the voltage waveform of the common electrode voltage CFCOM-1 has an abnormal spike, the voltage waveform of the data voltage will also have an abnormal spike, resulting in an abnormal picture and affecting the display quality.

[0022] Similarly, in a compensation design that uses a shielding signal voltage to compensate for a common signal voltage, the power-on time of the voltage waveform of the common signal VCOM-1 is inconsistent with the power-on time of the voltage waveform of the shielding signal DBSCOM-1, which may also cause abnormal spikes in the voltage waveforms of the common electrode voltage CFCOM-1 and the data voltage.

[0023] Based on the above problems, the embodiments of the present application provide a display driving circuit, a driving method and a display device to avoid the problem of abnormal spikes in the data signal due to abnormal common electrode voltage, thereby improving the display quality.

[0024] like Figure 2 As shown, the first embodiment of the present application provides a display driving circuit 40, which is used for a display device 10. The display device 10 includes a power chip 30 and a display panel 20. The display panel 20 includes a common electrode 21, a common electrode 22 and a shielding electrode 23. The power chip 30 has a first power port 31, a second power port 32 and a third power port 33. The first power port 31, the second power port 32 and the third power port 33 are used to provide a common signal VCOM, a common electrode signal AVCOM and a shielding signal DBSCOM to the common electrode 21, the common electrode 22 and the shielding electrode 23, respectively.

[0025] The display panel 20 is a liquid crystal panel, specifically comprising an array substrate and a color filter substrate arranged relative to each other, and a liquid crystal layer arranged between the array substrate and the color filter substrate. The common electrode 21 is located on the color filter substrate, and controls the deflection of the liquid crystal molecules by charging the liquid crystal capacitor through the voltage difference between the common electrode 21 and the pixel electrode on the array substrate. The common electrode 22 is arranged on the array substrate as one of the electrodes of the storage capacitor, and charges the storage capacitor through the voltage difference between the common electrode 21 and the pixel electrode to maintain the voltage stability of the pixel electrode after the pixel switch is turned off. As for the shielding electrode 23, it can be located on the array substrate, and its main function is to shield the data signal and related signals when the liquid crystal molecules are incorrectly deflected.

[0026] In some embodiments, the display driver circuit 40 further includes a waveform adjustment circuit 100 and a compensation circuit 200. The first receiving terminal 100A1 of the waveform adjustment circuit 100 is electrically connected to the first power port 31 to receive the common signal VCOM; the second receiving terminal 100A2 of the waveform adjustment circuit 100 is electrically connected to the second power port 32 to receive the common electrode signal AVCOM; the waveform adjustment circuit 100 is configured to adjust the power-on time of the voltage waveforms of the common signal VCOM and the common electrode signal AVCOM to be equal. Furthermore, the first output terminal 100B1 of the waveform adjustment circuit 100 outputs a first adjustment signal corresponding to the common signal VCOM, that is, outputs the voltage waveform of the common signal VCOM after adjustment; and the second output terminal 100B2 of the waveform adjustment circuit 100 outputs a second adjustment signal corresponding to the common electrode signal AVCOM, that is, outputs the voltage waveform of the common electrode signal AVCOM after adjustment. Of course, if adjusting only one of the common signal VCOM and the common electrode signal AVCOM can make the power-on time of the voltage waveforms of the common signal VCOM and the common electrode signal AVCOM equal, then only one of the common signal VCOM and the common electrode signal AVCOM may be adjusted.

[0027] Correspondingly, the first interface 200A1 of the compensation circuit 200 is electrically connected to the first output terminal 100B1 of the waveform adjustment circuit 100 to receive the first adjustment signal; the second interface 200A2 of the compensation circuit 200 is electrically connected to the second output terminal 100B2 of the waveform adjustment circuit 100 to receive the second adjustment signal. The compensation circuit 200 processes the received first and second adjustment signals to generate a compensation signal CFCOM, and outputs the compensation signal CFCOM to the common electrode 21 to compensate for the voltage of the common electrode 21. In this case, the compensation signal CFCOM, i.e., the electrical signal of the common electrode 21, not only prevents spikes in the voltage waveform but also improves the stability of the pixel drive voltage.

[0028] like Figure 3 As shown, in other embodiments, the first receiving terminal 100A1 of the waveform adjustment circuit 100 is electrically connected to the first power port 31 to receive the common signal VCOM; the second receiving terminal 100A2 of the waveform adjustment circuit 100 is electrically connected to the third power port 33 to receive the shielding signal DBSCOM; the waveform adjustment circuit 100 is configured to adjust the power-on time of the voltage waveforms of the common signal VCOM and the shielding signal DBSCOM to be equal. The first output terminal 100B1 of the waveform adjustment circuit 100 outputs a first adjustment signal corresponding to the common signal VCOM, that is, outputs the voltage waveform of the common signal VCOM after adjustment; the second output terminal 100B2 of the waveform adjustment circuit 100 outputs a third adjustment signal corresponding to the shielding signal DBSCOM, that is, outputs the voltage waveform of the shielding signal DBSCOM after adjustment. Of course, if adjusting only one of the common signal VCOM and the shielding signal DBSCOM can make the power-on time of the common signal VCOM and the shielding signal DBSCOM equal, then adjusting only one of the common signal VCOM and the shielding signal DBSCOM can also be sufficient.

[0029] Correspondingly, the first interface 200A1 of the compensation circuit 200 is electrically connected to the first output terminal 100B1 of the waveform adjustment circuit 100 to receive the first adjustment signal; the second interface 200A2 of the compensation circuit 200 is electrically connected to the second output terminal 100B2 of the waveform adjustment circuit 100 to receive the third adjustment signal. The compensation circuit 200 processes the received first and third adjustment signals to generate a compensation signal CFCOM, and outputs the compensation signal CFCOM to the common electrode 21 to compensate for the voltage of the common electrode 21. In this case, the compensation signal CFCOM, i.e., the electrical signal of the common electrode 21, not only does not have spikes in the voltage waveform, but also improves the stability of the pixel drive voltage.

[0030] It should be noted that the display panel 20 may adopt a compensation design that compensates the common signal voltage by the common electrode signal voltage, or may adopt a compensation design that compensates the common signal voltage by the shielding signal voltage. Figure 2 The corresponding design is used to improve the abnormal spikes in the voltage waveform of the common electrode 21 and the voltage waveform of the data signal; for the latter, the Figure 3 The corresponding design is used to improve the abnormal spikes in the voltage waveform of the common electrode 21 and the voltage waveform of the data signal. Therefore, before designing the display driving circuit 40 in the embodiment of the present application, it is necessary to first understand the compensation design of the common electrode 21 in the display panel 20 so as to carry out targeted circuit design based on the specific compensation design.

[0031] Through the above design, for the compensation design of using the common electrode signal voltage to compensate for the common signal voltage, the embodiment of the present application adjusts the power-on time of the voltage waveform of the common electrode signal AVCOM and the power-on time of the voltage waveform of the common signal VCOM to an equal degree through the waveform adjustment circuit 100, so that the voltage difference between the common electrode signal AVCOM and the common signal VCOM is small during the rising process; then the adjusted common signal and common electrode signal are transmitted to the compensation circuit 200 for calculation to generate the compensation signal CFCOM to compensate for the voltage of the common electrode 21, so that the actual voltage of the common electrode 21 after compensation will not have abnormal spikes, and thus the data signal will not have abnormal spikes, thereby avoiding affecting the display quality. Similarly, for the compensation design of using the shielding signal voltage to compensate for the common signal voltage, the embodiment of the present application adjusts the power-on time of the voltage waveform of the common signal VCOM and the power-on time of the voltage waveform of the shielding signal DBSCOM to an equal degree through the waveform adjustment circuit 100, and then transmits the adjusted common signal and shielding signal to the compensation circuit 200 for calculation to generate the compensation signal CFCOM to compensate for the voltage of the common electrode 21, so that the actual voltage of the common electrode 21 after compensation will not have abnormal spikes, and thus the data signal will not have abnormal spikes, thereby avoiding affecting the display quality.

[0032] like Figure 4 and Figure 5 As shown, in the embodiment of the present application, the waveform adjustment circuit 100 includes a first switching circuit 110, a second switching circuit 120, and a control unit 130. The input end of the first switching circuit 110 is electrically connected to the first power port 31 of the power chip 30 and the first interface 200A1 of the compensation circuit 200, respectively. The output end of the first switching circuit 110 is electrically connected to the second interface 200A2 of the compensation circuit 200. It should be noted that the first power port 31 of the power chip 30 and the first interface 200A1 of the compensation circuit 200 are always connected.

[0033] When using Figure 2 When designing, if Figure 4 As shown, the input end of the second switching circuit 120 is electrically connected to the second power port 32 , and the output end of the second switching circuit 120 is electrically connected to the second interface 200A2 of the compensation circuit 200 .

[0034] When using Figure 3 When designing, if Figure 5As shown, the input end of the second switching circuit 120 is electrically connected to the third power port 33 , and the output end of the second switching circuit 120 is electrically connected to the second interface 200A2 of the compensation circuit 200 .

[0035] The control unit 130 is electrically connected to both the first switching circuit 110 and the second switching circuit 120, and controls the on and off of the first switching circuit 110 and the second switching circuit 120, respectively. When the first switching circuit 110 is on, the second switching circuit 120 is off; or, when the second switching circuit 120 is on, the first switching circuit 110 is off. In other embodiments, the first switching circuit 110 and the second switching circuit 120 may be connected to different control units for independent control.

[0036] In a specific embodiment, the first switching circuit 110 may be only a first MOS transistor 111, the input end of the first MOS transistor 111 being electrically connected to the first power port 31 of the power chip 30 and the first interface 200A1 of the compensation circuit 200, respectively; the output end of the first MOS transistor 111 being electrically connected to the second interface 200A2 of the compensation circuit 200; and the control end of the first MOS transistor 111 being connected to the control unit 130. The second switching circuit 120 may be only a second MOS transistor 121, the input end of the second MOS transistor 121 being electrically connected to the second power port 32 or the third power port 33; the output end of the second MOS transistor 121 being electrically connected to the second interface 200A2 of the compensation circuit 200; and the control end of the second MOS transistor 121 being connected to the control unit 130.

[0037] In this embodiment, the first MOS transistor 111 and the second MOS transistor 121 can both be N-type MOS transistors. When the control unit 130 outputs a high level to both the first MOS transistor 111 and the second MOS transistor 121, the first MOS transistor 111 and the second MOS transistor 121 are turned on, and the input and output ends are conductive. When the control unit 130 outputs a low level to both the first MOS transistor 111 and the second MOS transistor 121, the first MOS transistor 111 and the second MOS transistor 121 are turned off. Furthermore, by setting both the first MOS transistor 111 and the second MOS transistor 121 as N-type MOS transistors, selection and control are facilitated.

[0038] In this embodiment, the control unit 130 may be part of a timing control circuit that outputs a control signal according to a timing signal to control the first MOS transistor 111 and the second MOS transistor 121. In other embodiments, the control unit 130 may also be independently provided as a separate circuit structure.

[0039] In other embodiments, the first MOS transistor 111 and the second MOS transistor 121 can both be P-type MOS transistors. When the control unit 130 outputs a low level to the first MOS transistor 111 and the second MOS transistor 121, the first MOS transistor 111 and the second MOS transistor 121 are turned on, and the input end and the output end are connected; when the control unit 130 outputs a high level to the first MOS transistor 111 and the second MOS transistor 121, the first MOS transistor 111 and the second MOS transistor 121 are turned off.

[0040] In other embodiments, one of the first MOS transistor 111 and the second MOS transistor 121 may be an N-type MOS transistor and the other may be a P-type MOS transistor. The control unit 130 outputs a low level and a high level according to specific circumstances to separately control the first MOS transistor 111 and the second MOS transistor 121.

[0041] In some embodiments, the first switching circuit 110 and the second switching circuit 120 may be composed of multiple MOS transistors, or may be composed of single-pole double-throw switches, or may be composed of other switching structures. Alternatively, resistors, capacitors, and other structures may be added to the first switching circuit 110 and the second switching circuit 120 to achieve combined control. The specific design can be based on actual conditions and is not limited here.

[0042] Combine Figure 4 and Figure 6 As shown, Figure 6 FIG2 is a schematic diagram of the waveform of the signal output by the second output terminal of the waveform adjustment circuit. Taking the example of the electrical connection between the input terminal of the second switching circuit 120 and the second power port 32, during the time period 0-t1, the control unit 130 controls the first switching circuit 110 to be conductive and the second switching circuit 120 to be disconnected. At this time, the first power port 31 of the power chip 30 is connected not only to the first interface 200A1 of the compensation circuit 200, but also to the second interface 200A2 of the compensation circuit 200. This allows the first interface 200A1 of the compensation circuit 200 to receive the common signal VCOM, and the second interface 200A2 of the compensation circuit 200 also receives the common signal VCOM.

[0043] After time t1, the control unit 130 controls the first switching circuit 110 to be disconnected and the second switching circuit 120 to be connected. At this point, the first power port 31 of the power chip 30 is connected only to the first interface 200A1 of the compensation circuit 200, and the second power port 32 of the power chip 30 is connected to the second interface 200A2 of the compensation circuit 200. This allows the first interface 200A1 of the compensation circuit 200 to receive the common signal VCOM, and the second interface 200A2 of the compensation circuit 200 to receive the common electrode signal AVCOM.

[0044] The embodiment of the present application is designed as the waveform adjusting circuit 100. In the time period of 0-t1, the second interface 200A2 of the compensation circuit 200 receives the common signal VCOM. After the time t1, the second interface 200A2 of the compensation circuit 200 receives the common electrode signal AVCOM. That is, the signal received by the second interface 200A2 of the compensation circuit 200 is composed of the common signal VCOM and the common electrode signal AVCOM. The time period of 0-t1 is the power-up time period of the common signal VCOM, and the time period after t1 is the stable time period of the voltage waveform of the common electrode signal AVCOM. Of course, in another embodiment, in the time period of 0-t1, the second interface 200A2 of the compensation circuit 200 receives the common signal VCOM; and after the time t1, the second interface 200A2 of the compensation circuit 200 receives the common signal VCOM first and then receives the common electrode signal AVCOM.

[0045] Because the power-up time of the common electrode signal AVCOM is different from that of the common signal VCOM, the stable voltage of the common electrode signal AVCOM is equal to that of the common signal VCOM, and the voltage difference between the common electrode signal AVCOM and the common signal VCOM in the power-up time period is large, which leads to a large difference between the signals received by the first interface 200A1 and the second interface 200A2 of the compensation circuit 200, and further leads to an abnormal spike in the voltage of the compensation signal CFCOM output by the compensation circuit 200, that is, the voltage of the common electrode 21. The embodiment of the present application composes the signal received by the second interface 200A2 of the compensation circuit 200 of the power-up part of the common signal VCOM and the stable part of the common electrode signal AVCOM, so that the voltage difference between the signal received by the second interface 200A2 of the compensation circuit 200 and the signal received by the first interface 200A1 of the compensation circuit 200 is small or even does not exist in the power-up phase or the voltage stable phase, and further avoids the voltage waveform of the compensation signal CFCOM output by the compensation circuit 200 from generating a spike, and avoids the voltage waveform of the data signal from generating a spike.

[0046] In the embodiment of the present application, the time period of 0-t1 is the power-up time period of the common signal VCOM, and can also be understood as the time period before the backlight is started, and can be within 1us. Of course, in some embodiments, the time period of 0-t1 can also cover the power-up time period of the common signal VCOM and part of the stable voltage time period of the common signal VCOM.

[0047] When the input end of the second switching circuit 120 is electrically connected to the third power port 33, during the time period 0-t1, the second interface 200A2 of the compensation circuit 200 receives the common signal VCOM. After time t1, the second interface 200A2 of the compensation circuit 200 receives the shielding signal DBSCOM. In other words, the signal received by the second interface 200A2 of the compensation circuit 200 is composed of both the common signal VCOM and the shielding signal DBSCOM. By composing the signal received by the second interface 200A2 of the compensation circuit 200 with the power-up portion of the common signal VCOM and the stable portion of the shielding signal DBSCOM, the voltage difference between the signal received by the second interface 200A2 of the compensation circuit 200 and the signal received by the first interface 200A1 of the compensation circuit 200 is minimal or even non-existent, both during the power-up phase and during the voltage stabilization phase. This prevents spikes in the voltage waveform of the compensation signal CFCOM output by the compensation circuit 200.

[0048] like Figure 7 As shown, in the embodiment of the present application, the compensation circuit 200 includes an operational amplifier 210, and the first input end of the operational amplifier 210 serves as the first interface 200A1, which is electrically connected to the first output end 100B1 of the waveform adjustment circuit 100; the second input end of the operational amplifier 210 serves as the second interface 200A2, which is electrically connected to the second output end 100B2 of the waveform adjustment circuit 100, and the output end of the operational amplifier 210 is electrically connected to the common electrode 21.

[0049] When a compensation design is used to compensate the common signal voltage using the common electrode signal voltage, the second input terminal of the operational amplifier 210 receives a second adjustment signal composed of the common signal VCOM and the common electrode signal AVCOM. After performing an operation on the first adjustment signal (in this case, the common signal VCOM) and the second adjustment signal, the operational amplifier 210 outputs a compensation signal CFCOM to the common electrode 21. When a compensation design is used to compensate the common signal voltage using the shielding signal voltage, the second input terminal of the operational amplifier 210 receives a second adjustment signal composed of the common signal VCOM and the shielding signal DBSCOM. After performing an operation on the first adjustment signal (in this case, the common signal VCOM) and the second adjustment signal, the operational amplifier 210 outputs a compensation signal CFCOM to the common electrode 21.

[0050] In addition to the operational amplifier 210, the compensation circuit 200 also includes other components. For example, an auxiliary resistor 220 and an auxiliary capacitor 230 are connected in series between the second interface 200A2 of the compensation circuit 200 and the second output terminal 100B2 of the waveform adjustment circuit 100 to improve the stability of the second adjustment signal. Furthermore, the operational amplifier 210 has a positive power supply interface and a negative power supply interface. The positive power supply interface is connected to the power supply VCC, and the negative power supply interface is connected to ground. These details are not detailed here.

[0051] like Figure 8 As shown, in other embodiments, the waveform adjustment circuit 100 has three signal receiving terminals. Specifically, in addition to the first receiving terminal 100A1 and the second receiving terminal 100A2, the waveform adjustment circuit 100 also includes a third receiving terminal 100A3. The three receiving terminals (the first receiving terminal 100A1, the second receiving terminal 100A2, and the third receiving terminal 100A3) of the waveform adjustment circuit 100 are electrically connected to the three power ports (the first power port 31, the second power port 32, and the third power port 33) of the power chip 30, respectively. The waveform adjustment circuit 100 is used to adjust the power-on times of the voltage waveforms of the common signal VCOM, the common electrode signal AVCOM, and the shielding signal DBSCOM to be equal. With this design, the same waveform adjustment circuit 100 and the display driver circuit 40 can be applied to different types of common electrode 21 compensation designs, avoiding subsequent targeted design and adjustment.

[0052] Specifically, the power-on phase of the signal with the longest power-on time among the three signals, the common signal VCOM, the common electrode signal AVCOM and the shielding signal DBSCOM, can be combined with the stable voltage phase of the common electrode signal AVCOM and the shielding signal DBSCOM to generate the second adjustment signal. Other parts can be derived according to the above design, which will not be elaborated here.

[0053] Figure 9 A display driving circuit 40 is provided in the second embodiment of the present application. Different from the first embodiment, the waveform adjustment circuit 100 in the embodiment of the present application adjusts the power-on time of the signal in another way.

[0054] Specifically, the waveform adjustment circuit 100 includes a filter unit 140, and the filter unit 140 includes a resistor 141 and a capacitor 142 connected in series. The capacitance value C of the capacitor 142 and the resistance value R of the resistor 141 meet the following conditions: .

[0055] It should be noted that Figure 9The two ends of the filtering unit 140 are respectively electrically connected to the first receiving end 100A1 of the waveform adjustment circuit 100 and the first interface 200A1 of the compensation circuit 200 to adjust the voltage waveform of the common signal VCOM as an example. The embodiment of the present application is not limited to this case. The filtering unit 140 can also be set at other positions to adjust the voltage waveform of the common electrode signal AVCOM or the shielding signal DBSCOM.

[0056] In some embodiments, when a compensation design is adopted to compensate for the common signal VCOM voltage using the common electrode signal AVCOM voltage, if the power-on time of the voltage waveform of the common signal VCOM is greater than the power-on time of the voltage waveform of the common electrode signal AVCOM, the two ends of the filtering unit 140 are electrically connected to the second receiving end 100A2 of the waveform adjustment circuit 100 and the second interface 200A2 of the compensation circuit 200, respectively. It can also be understood that one end of the filtering unit 140 serves as the second receiving end 100A2 of the waveform adjustment circuit 100, and the other end serves as the second output end 100B2 of the waveform adjustment circuit 100, thereby receiving the common electrode signal AVCOM and adjusting the voltage waveform of the common electrode signal AVCOM; wherein T2 is the power-on time of the voltage waveform of the common signal VCOM, and T1 is the power-on time of the voltage waveform of the common electrode signal AVCOM.

[0057] If the power-on time of the voltage waveform of the common signal VCOM is less than the power-on time of the voltage waveform of the common electrode signal AVCOM, the two ends of the filtering unit 140 are electrically connected to the first receiving end 100A1 of the waveform adjustment circuit 100 and the first interface 200A1 of the compensation circuit 200 respectively. It can also be understood that one end of the filtering unit 140 serves as the first receiving end 100A1 of the waveform adjustment circuit 100, and the other end serves as the first output end 100B1 of the waveform adjustment circuit 100, thereby receiving the common signal VCOM and adjusting the voltage waveform of the common signal VCOM; wherein T2 is the power-on time of the voltage waveform of the common electrode signal AVCOM, and T1 is the power-on time of the voltage waveform of the common signal VCOM.

[0058] In other embodiments, when a compensation design is used to compensate for the voltage of the common signal VCOM using the voltage of the shielding signal DBSCOM, if the power-on time of the voltage waveform of the common signal VCOM is greater than the power-on time of the voltage waveform of the shielding signal DBSCOM, the two ends of the filtering unit 140 respectively serve as the second receiving end 100A2 and the second output end 100B2 of the waveform adjustment circuit 100, thereby receiving the shielding signal DBSCOM and adjusting the voltage waveform of the shielding signal DBSCOM; wherein T2 is the power-on time of the voltage waveform of the common signal VCOM, and T1 is the power-on time of the voltage waveform of the shielding signal DBSCOM.

[0059] If the power-on time of the voltage waveform of the common signal VCOM is less than the power-on time of the voltage waveform of the shielding signal DBSCOM, the two ends of the filtering unit 140 respectively serve as the first receiving end 100A1 and the first output end 100B1 of the waveform adjustment circuit 100, thereby receiving the common signal VCOM and adjusting the voltage waveform of the common signal VCOM; wherein T2 is the power-on time of the voltage waveform of the shielding signal DBSCOM, and T1 is the power-on time of the voltage waveform of the common signal VCOM.

[0060] In the embodiment of the present application, the resistor 141 and the capacitor 142 are connected in series between the path of the power chip 30 and the operational amplifier 210, with one end of the capacitor 142 connected to the power chip 30 and the other end grounded; the resistor 141 is connected between the power chip 30 and the capacitor 142. The embodiment of the present application increases the voltage power-on time through the above design, so that the power-on time of the signal with a shorter power-on time is extended, thereby overcoming the spike problem caused by the voltage difference between different signals during the power-on stage. Moreover, the embodiment of the present application can deal with the spike problem between various different signals by adjusting the capacitance value C of the capacitor 142 and the resistance value R of the resistor 141.

[0061] It should be noted that, in an embodiment of the present application, when one end of the filtering unit 140 serves as the first receiving end 100A1 of the waveform adjustment circuit 100, and the other end serves as the first output end 100B1 of the waveform adjustment circuit 100 and is electrically connected to the first interface 200A1 of the compensation circuit 200, the wiring connecting the second power port 32 or the third power port 33 and the second interface 200A2 of the compensation circuit 200 can be regarded as another part of the waveform adjustment circuit 100, and the end of the wiring connected to the second power port 32 or the third power port 33 serves as the second receiving end 100A2 of the waveform adjustment circuit 100, and the end of the wiring connected to the second interface 200A2 of the compensation circuit 200 serves as the second output end 100B2 of the waveform adjustment circuit 100.

[0062] Alternatively, when one end of the filtering unit 140 serves as the second receiving end 100A2 of the waveform adjustment circuit 100, and the other end serves as the second output end 100B2 of the waveform adjustment circuit 100 and is electrically connected to the second interface 200A2 of the compensation circuit 200, the wiring connecting the first power port 31 and the first interface 200A1 of the compensation circuit 200 can be regarded as another part of the waveform adjustment circuit 100, and the end of the wiring connected to the first power port 31 serves as the first receiving end 100A1 of the waveform adjustment circuit 100, and the end of the wiring connected to the first interface 200A1 of the compensation circuit 200 serves as the first output end 100B1 of the waveform adjustment circuit 100.

[0063] In other embodiments, a filter unit 140 may be simultaneously set between the first power port 31 and the first interface 200A1 of the compensation circuit 200, and a filter unit 140 may be set between the second power port 32 or the third power port 33 and the second interface 200A2 of the compensation circuit 200. By adjusting the resistance value and the capacitance value in the two filter units 140 respectively, the power-on time of the voltage waveforms of the signals output by the two filter units 140 can be made consistent.

[0064] For the capacitance value C of the capacitor and the resistance value R of the resistor, the condition is satisfied , the derivation process is as follows: ,Right now ,in is the voltage output by the filter unit, is the voltage that varies with time.

[0065] Set the voltage range to 0.1 to 0.9 For the power-on stage, t1 is 0.1 Time point, t2 is 0.9 At the time point of the power-on phase, the output voltage of the filter unit is It can be expressed as: .

[0066] Since the signal passing through the filter unit itself has a certain power-on time, the power-on time of the signal is set to t3. The total power-on time T in the filter unit can be expressed as .

[0067] Taking T1 as the power-on time of the voltage waveform of the common signal, T2 as the power-on time of the voltage waveform of the common electrode signal, and T2 being greater than T1, as an example, the filter unit is provided between the first power port and the first interface of the compensation circuit, ,Right now , combined with the formula It can be calculated Therefore, the problem of spikes between signals can be dealt with by adjusting the capacitance value C of the capacitor and the resistance value R of the resistor in the filtering unit.

[0068] Figure 10 A driving method for the above-mentioned display driving circuit is provided in the third embodiment of the present application. The driving method comprises the following steps: S1: Receives the common signal and common electrode signal output by the power chip, or receives the common signal and shielding signal output by the power chip; S2: adjusting the power-on time of the voltage waveforms of the common signal and the common electrode signal to be equal, or adjusting the power-on time of the voltage waveforms of the common signal and the shielding signal to be equal; S3: Calculating the adjusted signal to generate a compensation signal, and outputting the compensation signal to the common electrode.

[0069] Specifically, in step S1, if the compensation design is to use the common electrode signal voltage to compensate for the common signal voltage, the common signal and the common electrode signal output by the power chip are received through the waveform adjustment circuit; if the compensation design is to use the shielding signal voltage to compensate for the common signal voltage, the common signal and the shielding signal output by the power chip are received through the waveform adjustment circuit.

[0070] In step S2, if the compensation design uses the common electrode signal voltage to compensate for the common signal voltage, the waveform adjustment circuit adjusts the power-on time of the voltage waveforms of the common signal and the common electrode signal to be equal. This can be achieved by combining the voltage waveforms of the common signal and the common electrode signal using the design of the first embodiment to output a new signal, thereby adjusting the power-on time of the voltage waveforms of the common signal and the common electrode signal to be equal; or by increasing the power-on time of the signal using the design of the second embodiment to adjust the power-on time of the voltage waveforms of the common signal and the common electrode signal to be equal. If the compensation design uses the shielding signal voltage to compensate for the common signal voltage, the waveform adjustment circuit adjusts the power-on time of the voltage waveforms of the common signal and the shielding signal to be equal.

[0071] In step S3 , the compensation circuit receives the signal output by the waveform adjustment circuit to generate a compensation signal as a driving signal for the common electrode.

[0072] Figure 11 A fourth embodiment of the present application provides a display device 10 , which includes a display panel 20 and the display driving circuit 40 as described above. The display driving circuit 40 is used to drive the display panel 20 .

[0073] It should be noted that the limitations on the various steps involved in this solution do not limit the order of the steps without affecting the implementation of the specific solution. The steps written in front can be executed first, later, or even simultaneously. The solutions of different embodiments can be combined and applied without conflict. As long as this solution can be implemented, it should be regarded as falling within the scope of protection of this application.

[0074] The above content is a further detailed description of the present application in conjunction with specific optional implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be considered to fall within the scope of protection of the present application.

Claims

1. A display driver circuit for a display device, the display device comprising a power chip and a display panel, the display panel comprising a common electrode, a common electrode, and a shielding electrode, the power chip having a first power port, a second power port, and a third power port, the first power port, the second power port, and the third power port being used to provide a common signal, a common electrode signal, and a shielding signal to the common electrode, the common electrode, and the shielding electrode, respectively, wherein: The display driving circuit includes: a waveform adjustment circuit, wherein a first receiving end of the waveform adjustment circuit is electrically connected to the first power port, and a second receiving end of the waveform adjustment circuit is electrically connected to the second power port or the third power port, the waveform adjustment circuit being configured to adjust the power-on times of the voltage waveforms of the common signal and the common electrode signal to be equal, or to adjust the power-on times of the voltage waveforms of the common signal and the shielding signal to be equal; a first output end of the waveform adjustment circuit outputs a first adjustment signal corresponding to the common signal, and a second output end of the waveform adjustment circuit outputs a second adjustment signal corresponding to the common electrode signal, or outputs a third adjustment signal corresponding to the shielding signal; and A compensation circuit, wherein the first interface of the compensation circuit is electrically connected to the first output end of the waveform adjustment circuit to receive the first adjustment signal; the second interface of the compensation circuit is electrically connected to the second output end of the waveform adjustment circuit to receive the second adjustment signal or the third adjustment signal; the compensation circuit generates a compensation signal after performing calculation processing on the received adjustment signal, and outputs the compensation signal to the common electrode.

2. The display driving circuit according to claim 1, wherein: The waveform adjustment circuit includes a first switching circuit, a second switching circuit and a control unit, wherein the input end of the first switching circuit is electrically connected to the first power port of the power chip and the first interface of the compensation circuit respectively, and the output end of the first switching circuit is electrically connected to the second interface of the compensation circuit; The input end of the second switching circuit is electrically connected to the second power port or the third power port, and the output end of the second switching circuit is electrically connected to the second interface of the compensation circuit; The control unit is electrically connected to the first switching circuit and the second switching circuit at the same time, and controls the on and off of the first switching circuit and the second switching circuit respectively; and when the first switching circuit is turned on, the second switching circuit is turned off; or, when the second switching circuit is turned on, the first switching circuit is turned off.

3. The display driving circuit according to claim 2, wherein: The first switching circuit includes a first MOS transistor, wherein an input end of the first MOS transistor is electrically connected to the first power port of the power chip and the first interface of the compensation circuit respectively, an output end of the first MOS transistor is electrically connected to the second interface of the compensation circuit, and a control end of the first MOS transistor is connected to the control unit; The second switching circuit includes a second MOS transistor, an input end of the second MOS transistor is electrically connected to the second power port or the third power port, an output end of the second MOS transistor is electrically connected to the second interface of the compensation circuit, and a control end of the second MOS transistor is connected to the control unit.

4. The display driving circuit according to claim 2, wherein: During the time period 0-t1, the control unit controls the first switching circuit to be turned on and controls the second switching circuit to be turned off; after the time period t1, the control unit controls the first switching circuit to be turned off and controls the second switching circuit to be turned on; The time 0-t1 includes the power-on time of the common signal.

5. The display driving circuit according to claim 3, wherein: The first MOS transistor and the second MOS transistor are both N-type MOS transistors.

6. The display driving circuit according to claim 1, wherein: The waveform adjustment circuit includes a filtering unit, which includes a resistor and a capacitor connected in series. The capacitance value C of the capacitor and the resistance value R of the resistor meet the following conditions: ; When the power-on time of the voltage waveform of the common signal is greater than the power-on time of the voltage waveform of the common electrode signal or the power-on time of the voltage waveform of the shielding signal, the two ends of the filtering unit serve as the second receiving end and the second output end of the waveform adjustment circuit respectively; wherein T2 is the power-on time of the voltage waveform of the common signal, and T1 is the power-on time of the voltage waveform of the common electrode signal or the power-on time of the voltage waveform of the shielding signal; When the power-on time of the voltage waveform of the common signal is less than the power-on time of the voltage waveform of the common electrode signal or the power-on time of the voltage waveform of the shielding signal, the two ends of the filtering unit serve as the first receiving end and the first output end of the waveform adjustment circuit respectively; wherein, T2 is the power-on time of the voltage waveform of the common electrode signal or the power-on time of the voltage waveform of the shielding signal, and T1 is the power-on time of the voltage waveform of the common signal.

7. The display driving circuit according to claim 1, wherein: The waveform adjustment circuit also includes a third receiving end, and the three receiving ends of the waveform adjustment circuit are electrically connected to the three power ports of the power chip respectively. The waveform adjustment circuit is used to adjust the power-on time of the voltage waveforms of the common signal, the common electrode signal and the shielding signal to be equal.

8. The display driving circuit according to claim 1, wherein: The compensation circuit includes an operational amplifier, a first input end of the operational amplifier is electrically connected to the first output end of the waveform adjustment circuit as the first interface, a second input end of the operational amplifier is electrically connected to the second output end of the waveform adjustment circuit as the second interface, and an output end of the operational amplifier is electrically connected to the common electrode.

9. A driving method, used in the display driving circuit according to any one of claims 1 to 8, characterized in that: The driving method comprises the steps of: Receive the common signal and the common electrode signal output by the power chip, or receive the common signal and the shielding signal output by the power chip; Adjusting the power-on time of the voltage waveforms of the common signal and the common electrode signal to be equal, or adjusting the power-on time of the voltage waveforms of the common signal and the shielding signal to be equal; as well as The regulated signal is operated to generate a compensation signal, and the compensation signal is output to the common electrode.

10. A display device, characterized in that: The device comprises a display panel and a display driving circuit according to any one of claims 1 to 8, wherein the display driving circuit is used to drive the display panel.

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