IO port access method and system architecture based on DPU

Abstract

The invention provides an IO port access method and system architecture based on a DPU. The system architecture comprises a virtual machine, a DPU module and a host machine. The virtual machine is connected with the DPU module based on a preset data path and is used for running an application program to generate an IO port access request and sending the IO port access request to the DPU module based on the preset data path; the DPU module is arranged on the host machine and used for processing the IO port access request and sending a processing result to the virtual machine; the host machine is used for configuring the DPU module to establish the preset data path. According to the IO port access method based on the DPU and the system architecture provided by the invention, the IO access of the virtual machine is directly processed by DPU hardware, so that a large amount of overhead of system resources is avoided, the overall resource utilization rate of a host machine is improved, and the stability and reliability of the system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of virtual machines, in particular to an IO port access method and system architecture based on DPU. BACKGROUND

[0002] At present, the conventional method is that when the virtual machine performs port IO access, the virtual machine frequently exits mechanism is triggered, and the system exits to the host. The host then intercepts these access requests and processes them through software.

[0003] In the research process of conceiving and forming the present application, the applicant has found at least the following problems. This method has obvious performance bottlenecks. Due to the involvement of multiple context switches and the overhead of software processing, the efficiency of virtual machine port IO access is low, which seriously affects the overall system performance. In particular, in scenarios with extremely high IO performance requirements, such as cloud computing services in large-scale data centers, real-time data processing, etc., the existing method is difficult to meet the growing business demands. In the related technical field, many studies are devoted to improving the IO performance in the virtualization environment, but there is no mature and efficient solution to completely solve the problem of frequent exit of virtual machine port IO access to the host for processing. SUMMARY

[0004] To alleviate the above problems, the present application provides an IO port access system architecture based on DPU, comprising a virtual machine, a DPU module and a host; The virtual machine and the DPU module are connected based on a preset data path, and are used to run an application program to generate an IO port access request and send it to the DPU module based on the preset data path; The DPU module is arranged on the host and is used to process the IO port access request and send the processing result to the virtual machine; The host is used to configure the DPU module to establish the preset data path.

[0005] Optionally, the preset data path uses high-speed bus connection technology at the hardware layer to ensure the efficiency and low delay of data transmission.

[0006] Optionally, the DPU module includes a hardware processing module, which analyzes and processes the IO port access request according to a preset processing logic to obtain a processing result.

[0007] The application also provides a DPU-based IO port access method applied to a DPU module in the DPU-based IO port access system architecture. In response to the virtual machine initiating an IO port access request, the IO port access request is received based on a preset data path; The IO port access request is parsed and processed to obtain a processing result; The processing result is sent to the virtual machine.

[0008] Optionally, the virtual machine includes a plurality of virtual machines; the step of receiving the IO port access request based on the preset data path in response to the virtual machine initiating the IO port access request and the subsequent steps include: A hierarchical scheduling architecture is established, a service level agreement is allocated to the virtual machine, and existing resources including bus resources, cache resources and CPU resources are dynamically learned based on a reinforcement learning method; Based on the physical address of the virtual machine, the existing resource space is divided into a plurality of exclusive areas, higher weights are allocated to critical virtual machines and critical IO port access requests, and the allocation proportion of each area is dynamically adjusted according to the real-time cache access mode of the virtual machine; Tokens are allocated to each virtual machine at a fixed rate, and the tokens are allowed to be used by the virtual machine to compete for existing resources; Based on the lottery scheduling strategy, the virtual machine requesting the existing resources is selected by random extraction each time the resources are scheduled; Each virtual machine is allocated an exclusive request queue, and an independent scheduling algorithm is used to schedule the IO port access requests of the same virtual machine to the same processing unit.

[0009] Optionally, the step of dividing the existing resource space into a plurality of exclusive areas based on the physical address of the virtual machine, and allocating higher weights to critical virtual machines and critical IO port access requests, and dynamically adjusting the allocation proportion of each area according to the real-time cache access mode of the virtual machine includes: The Proportional Share algorithm is used to ensure the minimum resource allocation, the historical hit rate prediction algorithm is used to increase the weight of the virtual machine with high hit rate, and the cache line coloring strategy is used to realize the mapping of the address and the physical resource.

[0010] Optionally, the step of parsing and processing the IO port access request to obtain a processing result includes: The IO port access request is parsed and processed according to a preset processing logic to obtain a processing result.

[0011] Optionally, the step of parsing and processing the IO port access request according to a preset processing logic to obtain a processing result includes: For a read request, resolving a storage location of target data based on the IO disconnect access request; Data is read from the storage location and returned to the virtual machine through the preset data path.

[0012] Optionally, the step of parsing and processing the IO port access request according to a preset processing logic to obtain a processing result includes: For a write request, determining a storage location of the data to be written based on the IO disconnect access request; Write the data to be written to the specified location.

[0013] Optionally, before the step of receiving the IO port access request based on a preset data path in response to the virtual machine initiating the IO port access request, the step includes: A synchronization and coordination mechanism is constructed to achieve state synchronization and information interaction between the virtual machine, the host machine and the DPU module through hardware signals and control protocols.

[0014] This application connects a virtual machine and a DPU module via a preset data path, allowing the application to run and generate IO port access requests, which are then sent to the DPU module via the preset data path. The DPU module processes the IO port access requests and sends the results to the virtual machine. Virtual machine port IO access is directly handled by the DPU hardware, avoiding frequent virtual machine exits and the significant overhead caused by host software processing. This reduces the host's resource consumption in port IO access processing, allowing the host to allocate more computing resources to other critical tasks, improving the host's overall resource utilization, reducing the probability of system anomalies and errors, and improving system stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without inventive work.

[0016] Figure 1 This is a block diagram of the DPU-based IO port access system architecture according to an embodiment of the present application.

[0017] Figure 2 The flow chart of the method for IO port access based on DPU according to an embodiment of the present application.

[0018] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. The above-described drawings have shown the specific embodiments of the present application, and the following detailed description will be more detailed. These drawings and the written description are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0019] The exemplary embodiments will be described in detail herein with reference to the accompanying drawings. The following description is presented with reference to the accompanying drawings, in which the same numbers represent the same or similar elements throughout the several drawings. The embodiments described in the following exemplary embodiments are not meant to represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the appended claims.

[0020] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an "including a" statement does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element. Furthermore, components, features, elements with the same name in different embodiments of the present application can have the same meaning or different meanings, and the specific meaning thereof should be determined in the light of its explanation in the specific embodiment or further in the light of the context in the specific embodiment.

[0021] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are used solely to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the term "if," as used herein, may be interpreted as "upon," "when," or "in response to a determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprising" and "including" indicate the presence of the recited features, steps, operations, elements, components, items, types, and / or groups, but do not preclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups. The terms "or," "and / or," "including at least one of the following," etc., as used herein, may be interpreted as inclusive, meaning any one or any combination. For example, “comprising at least one of the following: A, B, C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”; and for another example, “A, B or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some manner.

[0022] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless clearly stated herein, the execution of these steps is not strictly limited in order, and they can be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or sub-steps or stages of other steps.

[0023] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0024] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0025] First embodiment This application provides an IO port access system architecture based on DPU. Figure 1 This is a block diagram of the DPU-based IO port access system architecture according to an embodiment of the present application.

[0026] like Figure 1 As shown, a DPU-based IO port access system architecture includes a virtual machine 1, a DPU module 2 and a host machine 3.

[0027] The Data Processing Unit (DPU) is a data-centric, specialized processor primarily used in data centers and cloud computing scenarios. It's designed to offload inefficient or incapable workloads from CPUs and GPUs (such as virtualization, networking, storage, and security tasks), thereby improving system efficiency and reducing overall costs. For example, in a virtualized environment, a new I / O access architecture is constructed. This architecture comprises virtual machines, a host machine, and a DPU. The virtual machine is responsible for running various applications and generating port I / O (IO) access requests. The host machine performs certain coordination and management tasks but no longer handles port I / O access processing. The DPU, as a core processing unit, is installed on the host machine and has the hardware capabilities to process port I / O accesses. The host machine configures the DPU to establish a pre-defined data path, enabling the virtual machine to directly send I / O port information to the DPU module for processing.

[0028] The virtual machine 1 is connected to the DPU module 2 based on a preset data path, and is used to run an application program to generate an IO port access request, and send the request to the DPU module 2 based on the preset data path. For example, when a virtual machine initiates a port IO access request, the request no longer triggers the virtual machine to frequently exit and enter the host processing process as in traditional methods. Instead, the request is transmitted directly to the DPU via a specially designed, pre-defined data path. This data path utilizes high-speed hardware-level connection technologies, such as high-speed buses, to ensure efficient data transmission and low latency. The DPU module 2 is set on the host machine 3, and is used to process the IO port access request and send the processing result to the virtual machine 1.

[0029] The DPU is pre-configured with a hardware processing module for port IO access. Upon receiving a port IO access request from a virtual machine, the hardware processing module quickly parses and processes the request based on pre-set processing logic.

[0030] The DPU module 2 is connected to the host machine 3 via hardware signals. The host machine 3 configures the DPU module 2 to establish a preset data path, allowing the virtual machine 1 to directly send IO port information to the DPU module 2 for processing. The host machine 3 can update its status information based on the processing results to maintain consistency with the virtual machine 1.

[0031] For example, to ensure collaborative operation between the virtual machine, host, and DPU, a synchronization and coordination mechanism is designed. Hardware signals and a specific control protocol enable state synchronization and information exchange among the three. For example, when the DPU completes a port IO access, it notifies the virtual machine and host via hardware signals, enabling them to promptly update relevant status information, ensuring system consistency and stability. Please refer to Figure 1 For example, the DPU module 2 may be provided with an IO port processing module so as to be able to process the IO port access request generated by the virtual machine 1 .

[0032] In this embodiment, by directly handing virtual machine port IO access to the DPU hardware for processing, the frequent virtual machine exits and the significant overhead caused by host software processing are avoided. Testing has shown that, under the same hardware environment and application load, compared to traditional methods, the port IO access latency of the simulated device is reduced by 10%, and the overall system IO performance is improved by 10%, which can better meet the needs of application scenarios with extremely high IO performance requirements, such as cloud computing services and real-time data analysis in large-scale data centers. This reduces the host's resource consumption in port IO access processing, allowing the host to allocate more computing resources to other critical tasks, thereby improving the host's overall resource utilization. By reducing the uncertainty caused by frequent virtual machine exits and complex software processing, the system is more stable and reliable when processing port IO access, reducing the probability of system anomalies and errors.

[0033] Optionally, the preset data path utilizes high-speed bus connection technology at the hardware layer to ensure high efficiency and low latency of data transmission.

[0034] For example, when a virtual machine initiates a port IO access request, the request no longer triggers the virtual machine to frequently exit and enter the host processing process as in traditional methods. Instead, the request is transmitted directly to the DPU via a specially designed, pre-defined data path. This data path utilizes high-speed hardware-level connection technologies, such as high-speed buses, to ensure efficient data transmission and low latency.

[0035] Optionally, the DPU module includes a hardware processing module, which parses and processes the IO port access request according to a preset processing logic to obtain a processing result.

[0036] For example, a hardware processing module for port IO access is pre-configured within the DPU. Upon receiving a port IO access request from a virtual machine, the hardware processing module quickly parses and processes the request based on pre-set processing logic.

[0037] Second embodiment The present application also provides a DPU-based IO port access method, which is applied to the DPU module in the above-mentioned DPU-based IO port access system architecture. Figure 2 This is a flow chart of a DPU-based IO port access method according to an embodiment of the present application.

[0038] like Figure 2 As shown, the DPU-based IO port access method includes: S10: In response to the virtual machine initiating an IO port access request, receiving the IO port access request based on a preset data path.

[0039] For example, when a virtual machine initiates a port IO access request, the request no longer triggers the virtual machine to frequently exit and enter the host machine processing process as in traditional methods. Instead, the request is directly transmitted to the DPU through a specially designed preset data path.

[0040] S20: Parse and process the IO port access request to obtain a processing result.

[0041] For example, a hardware processing module for port IO access is pre-configured within the DPU. Upon receiving a port IO access request from a virtual machine, the hardware processing module quickly parses and processes the request based on pre-set processing logic.

[0042] S30: Send the processing result to the virtual machine.

[0043] For example, to ensure collaborative operation between the virtual machine, host, and DPU, a synchronization and coordination mechanism is designed. Hardware signals and a specific control protocol enable state synchronization and information exchange among the three. For example, when the DPU completes a port IO access, it notifies the virtual machine and host via hardware signals, enabling them to promptly update relevant status information, ensuring system consistency and stability. In this embodiment, by directly handing over the virtual machine port IO access to the DPU hardware processing, the frequent virtual machine exit and the large overhead caused by the host software processing are avoided. Through testing, under the same hardware environment and application load, compared with the traditional way, the port IO access delay of the simulation device is reduced by 10%, the overall system IO performance is improved by 10%, which can better meet the demand of application scenarios with extremely high IO performance requirements, such as cloud computing services of large-scale data centers, real-time data analysis, etc. The resource consumption of the host in the port IO access processing is reduced, so that the host can allocate more computing resources to other critical tasks, and the overall resource utilization of the host is improved. Since the uncertainty caused by frequent virtual machine exit and complex software processing is reduced, the system is more stable and reliable when processing port IO access, and the probability of system exception and error is reduced.

[0044] Optionally, the virtual machine includes a plurality of virtual machines; the step of receiving the IO port access request based on the preset data channel in response to the virtual machine initiating the IO port access request and the following steps include: A hierarchical scheduling architecture is established, a service level agreement is allocated to the virtual machine, and existing resources including bus resources, cache resources and CPU resources are dynamically learned based on reinforcement learning. Based on the physical address of the virtual machine, the existing resource space is divided into a plurality of exclusive areas, higher weights are allocated to critical virtual machines and critical IO port access requests, and the allocation proportion of each area is dynamically adjusted according to the real-time cache access mode of the virtual machine. Tokens are allocated to each virtual machine at a fixed rate, and the virtual machine is allowed to use the tokens to compete for existing resources; Based on the lottery scheduling strategy, the virtual machine requesting the existing resources is selected by random drawing each time the resource is scheduled; Each virtual machine is allocated an exclusive request queue, and an independent scheduling algorithm is used to schedule the IO port access requests of the same virtual machine to the same processing unit.

[0045] Exemplarily, in the design of the hierarchical scheduling architecture, a global resource manager (GRM) can be arranged to be responsible for cross-resource type coordination (such as CPU and bus bandwidth linkage), and each resource manager (such as CPU Manager and Cache Manager) is responsible for the specific allocation of the resource. For example, when the CPU utilization of a virtual machine 1 exceeds 80%, the cache quota is automatically reduced and the bus bandwidth reservation is increased. The virtual machine can be allocated an SLA (service level agreement), such as "CPU utilization ≤ 70%, IO delay ≤ 5ms". Based on reinforcement learning, the resource allocation is dynamically adjusted to maximize the overall QoS satisfaction.

[0046] For example, the physical address-based partitioning (e.g., the first 1 / 3 of the L3 cache is given to virtual machine 1, and the last 2 / 3 is given to virtual machine 2) is implemented to achieve complete isolation and avoid cache pollution. Weighted Round Robin can be used: higher weights are assigned to critical virtual machines (e.g., virtual machine 1: 30%, virtual machine 2: 20%), and the allocation ratio is dynamically adjusted according to the real-time cache access pattern of the virtual machines to improve cache utilization and adapt to load changes.

[0047] For example, tokens can be allocated to each virtual machine, and tokens need to be consumed before data is sent. Tokens are replenished at a fixed rate. For example, a virtual machine is allocated a token generation rate of 100 Mbps, and the bucket capacity is 1 MB. The burst traffic can use the tokens in the bucket, but the long-term average bandwidth is limited by the generation rate, thereby smoothing the burst traffic and ensuring long-term fairness. For example, a high-priority queue (e.g., database requests of the first virtual machine) and a low-priority queue (e.g., backup tasks of the second virtual machine) are set. Virtual machines are allowed to compete for idle bandwidth, but critical virtual machines can preempt the bandwidth of low-priority virtual machines. When there is a request in the high-priority queue, the low-priority queue service is suspended, thereby ensuring the bandwidth of critical services and improving resource utilization.

[0048] For example, the Lottery Scheduling strategy can be used to determine which virtual machine's request to execute by randomly drawing "lottery" each time the scheduling is performed.

[0049] For example, each virtual machine can be allocated a dedicated request queue, each virtual machine corresponds to a processing queue, and an independent scheduling algorithm (e.g., CFS) is used. The global queue manager allocates processing units according to the resource state to avoid Head-of-Line Blocking, implement multi-queue scheduling, and reduce interference between virtual machines. Based on the NUMA (Non-Uniform Memory Access) architecture of the CPU core, local cache scheduling is prioritized, and IO requests of the same virtual machine can be scheduled to the same processing unit to utilize cache locality, bind requests of the same virtual machine to a fixed processing unit to improve cache hit rate, and reduce cache invalidation overhead.

[0050] Optionally, the steps of dividing the existing resource space into multiple exclusive areas based on the physical addresses of the virtual machines, assigning higher weights to critical virtual machines and critical IO port access requests, and dynamically adjusting the allocation ratio of each area according to the real-time cache access pattern of the virtual machines, and the previous steps include: The Proportional Share algorithm is used to guarantee minimum resource allocation, a prediction algorithm based on historical hit rate is used to increase the weight of virtual machines with high hit rate, and the address and physical resource mapping is realized through the cache line coloring strategy.

[0051] Exemplarily, in the existing resource allocation process, the Proportional Share algorithm can be used to guarantee minimum resource allocation, and when the resource is insufficient, the virtual machine with high priority is preferentially satisfied. A prediction algorithm based on historical hit rate (such as LRU-K) can be used to allocate more cache to the virtual machine with high hit rate. When the cache space is insufficient, the cache data of the secondary virtual machine is compressed to improve the cache utilization and adapt to the load change. The address and physical cache mapping can be realized through the cache line coloring (Cache Line Coloring), the cache space is statically divided into multiple areas, the cache is completely isolated, and the cache pollution is avoided.

[0052] Optionally, the step of analyzing and processing the IO port access request to obtain a processing result comprises: analyzing and processing the IO port access request according to a preset processing logic to obtain a processing result.

[0053] Exemplarily, the DPU is preconfigured with a hardware processing module for port IO access. When receiving the port IO access request of the virtual machine, the hardware processing module rapidly analyzes and processes the request according to the preset processing logic.

[0054] Optionally, the step of analyzing and processing the IO port access request according to a preset processing logic to obtain a processing result comprises: for a read request, based on the IO disconnected access request, analyzing the storage location of the target data; reading data from the storage location and returning to the virtual machine through the preset data channel.

[0055] Exemplarily, when receiving the port IO access request of the virtual machine, the hardware processing module rapidly analyzes and processes the request according to the preset processing logic. For example, for a read request, data is read from the corresponding hardware storage location and returned to the virtual machine through the preset data channel.

[0056] Optionally, the step of analyzing and processing the IO port access request according to a preset processing logic to obtain a processing result comprises: for a write request, based on the IO disconnected access request, determining the storage location of the to-be-written data; writing the to-be-written data into the specified location.

[0057] Exemplarily, after receiving the port IO access request of the virtual machine, the hardware processing module quickly analyzes and processes the request according to the preset processing logic. For example, for a write request, the data to be written is accurately written into the specified position. The entire processing process is implemented by hardware without software intervention, greatly improving the processing speed. Optionally, before the step of responding to the virtual machine initiating the IO port access request, the IO port access request is received based on a preset data channel, and the step further includes: A synchronization and coordination mechanism is constructed to realize the state synchronization and information interaction among the virtual machine, the host machine and the DPU module through hardware signals and control protocols.

[0058] Exemplarily, to ensure the cooperative work among the virtual machine, the host machine and the DPU, a synchronization and coordination mechanism is designed. Through hardware signals and specific control protocols, the state synchronization and information interaction among the three are realized. For example, after the DPU completes a port IO access processing, the virtual machine and the host machine are informed through hardware signals, so that they can update the relevant state information in time, ensuring the consistency and stability of the system. The application innovatively proposes the technical idea of directly transmitting the virtual machine port IO access to the DPU, breaking the traditional mode of relying on host software processing. A special data channel is constructed to realize the high-speed and low-latency connection between the virtual machine and the DPU, ensuring that the port IO access request can be quickly transmitted. A hardware processing module for port IO access in the DPU is designed, as well as a synchronization and coordination mechanism matched therewith, to ensure the efficient and stable operation of the entire system.

[0059] The application connects the virtual machine and the DPU module based on a preset data channel, which is used to run an application program to generate an IO port access request and send it to the DPU module based on the preset data channel. The DPU module is used to process the IO port access request and send the processing result to the virtual machine. The virtual machine port IO access is directly handed over to the DPU hardware processing, avoiding the large overhead caused by frequent exit of the virtual machine and host software processing. The resource consumption of the host machine in port IO access processing is reduced, so that the host machine can allocate more computing resources to other critical tasks, improve the overall resource utilization of the host machine, reduce the probability of system exceptions and errors, and improve the stability and reliability of the system.

[0060] It should be noted that in the present application, step codes such as S10, S20, etc. are adopted, the purpose is to more clearly and briefly express the corresponding content, and does not constitute a substantial limitation on the order. The person skilled in the art may perform S20 first and then perform S10, etc. when implementing, but these should be within the protection scope of the present application.

[0061] In the system embodiment provided in the present application, all technical features of any of the above method embodiments can be included, and the description and explanation content is basically the same as that of the above method embodiments, which will not be repeated here.

[0062] The present application also provides a computer program product, which comprises computer program code, when the computer program code runs on the computer, so that the computer executes the method in various possible embodiments as above.

[0063] The present application also provides a chip, comprising a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the device installed with the chip executes the method in various possible embodiments as above.

[0064] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided by the embodiments of the present application. The technical solutions provided by the present application can also be applied to other scenarios. For example, those skilled in the art can know that as the system architecture evolves and new business scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0065] The above sequence numbers of the embodiments of the present application are only for description, not representing the advantages and disadvantages of the embodiments.

[0066] The steps in the method of the embodiments of the present application can be adjusted in sequence, combined and reduced according to actual needs.

[0067] The units in the device of the embodiments of the present application can be combined, divided and reduced according to actual needs.

[0068] In the present application, for the same or similar term concept, technical solution and / or application scenario description, generally only the first time is described in detail, and for the sake of brevity, the repeated description is generally not repeated, and for the understanding of the technical solutions of the present application, the same or similar term concept, technical solution and / or application scenario description, etc. which is not described in detail later can refer to the relevant description before.

[0069] In the present application, the description of each embodiment has its own emphasis, and the parts not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0070] The various technical features of the technical solution of this application can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0071] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A DPU-based IO port access system architecture, characterized in that: Including virtual machine, DPU module and host machine; The virtual machine is connected to the DPU module based on a preset data path, and is used to run an application program to generate an IO port access request, and send the request to the DPU module based on the preset data path; The DPU module is provided on the host machine, and is used to process the IO port access request and send the processing result to the virtual machine; The host machine is used to configure the DPU module to establish the preset data path.

2. The DPU-based IO port access system architecture according to claim 1, characterized in that: The preset data path utilizes high-speed bus connection technology at the hardware layer to ensure high efficiency and low latency in data transmission.

3. The DPU-based IO port access system architecture according to claim 2, characterized in that: The DPU module includes a hardware processing module, which parses and processes the IO port access request according to a preset processing logic to obtain a processing result.

4. A DPU-based IO port access method, applied to a DPU module in a DPU-based IO port access system architecture according to any one of claims 1 to 3, the DPU-based IO port access method comprising: In response to the virtual machine initiating an IO port access request, receiving the IO port access request based on a preset data path; Parsing and processing the IO port access request to obtain a processing result; The processing result is sent to the virtual machine.

5. The DPU-based IO port access method according to claim 4, wherein: The virtual machine includes a plurality of virtual machines; the step of receiving the IO port access request based on a preset data path in response to the virtual machine initiating the IO port access request and the subsequent steps include: Establishing a hierarchical scheduling architecture to assign service level agreements to the virtual machines and dynamically learning existing resource allocation based on reinforcement learning, wherein the existing resources include bus resources, cache resources, and CPU resources; Based on the physical address of the virtual machine, the existing resource space is divided into multiple dedicated areas, higher weights are assigned to key virtual machines and key IO port access requests, and the allocation ratio of each area is dynamically adjusted according to the real-time cache access pattern of the virtual machine; Allocating tokens to each virtual machine at a fixed rate, and allowing the virtual machine to use the tokens to compete for available resources; Based on the lottery scheduling strategy, the virtual machine requesting existing resources is randomly selected each time resources are scheduled; A dedicated request queue is allocated to each virtual machine, and an independent scheduling algorithm is used to schedule IO port access requests of the same virtual machine to the same processing unit.

6. The DPU-based IO port access method according to claim 5, characterized in that: The steps of dividing the existing resource space into multiple exclusive areas based on the physical address of the virtual machine, assigning higher weights to access requests of key virtual machines and key IO ports, and dynamically adjusting the allocation ratio of each area according to the real-time cache access mode of the virtual machine and the steps before the steps include: The Proportional Share algorithm is used to ensure minimum resource allocation, the weight of virtual machines with high hit rates is increased based on the prediction algorithm of historical hit rates, and the mapping between addresses and physical resources is achieved through the cache line coloring strategy.

7. The DPU-based IO port access method according to claim 4, wherein: The step of parsing and processing the IO port access request to obtain a processing result includes: According to the preset processing logic, the IO port access request is parsed and processed to obtain a processing result.

8. The DPU-based IO port access method according to claim 7, wherein: The step of parsing and processing the IO port access request according to the preset processing logic to obtain a processing result includes: For a read request, resolving a storage location of target data based on the IO disconnect access request; Data is read from the storage location and returned to the virtual machine through the preset data path.

9. The DPU-based IO port access method according to claim 7, wherein: The step of parsing and processing the IO port access request according to the preset processing logic to obtain a processing result includes: For a write request, determining a storage location of the data to be written based on the IO disconnect access request; Write the data to be written to the specified location.

10. The DPU-based IO port access method according to any one of claims 4 to 9, characterized in that: Before the step of receiving the IO port access request based on a preset data path in response to the virtual machine initiating the IO port access request, the following steps are included: A synchronization and coordination mechanism is constructed to achieve state synchronization and information interaction between the virtual machine, the host machine and the DPU module through hardware signals and control protocols.

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