Domestic CPU (central processing unit) main and standby Flash starting system and method

Abstract

The invention discloses a domestic CPU (Central Processing Unit) main and standby Flash starting system and method. The system comprises a domestic CPU, a CPLD (Complex Programmable Logic Device), a main Flash, at least one standby Flash and a GPIO (General Purpose Input / Output) signal line. The CPLD expands a single-path SPI interface of the CPU into a multi-path SPI interface through logic programming, the main Flash stores main starting firmware, and the standby Flash stores independent standby firmware. During starting, the CPLD is preferentially connected with the main Flash; if the starting fails, the CPU sends a failure signal to the CPLD through the GPIO, the CPLD triggers the CPU to reset and switches the SPI signal to the standby Flash, and the CPU reloads the standby firmware to start. The SPI signal is dynamically managed through the CPLD, intelligent switching control is achieved, hardware limitation is broken through, and the starting reliability and stability of the system are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer startup, and particularly relates to a main-backup Flash startup system and method for a domestic CPU. BACKGROUND

[0002] In the design of a mainboard based on a domestic CPU (such as Loongson 3A6000), startup reliability is the key to ensuring stable operation of the system. However, some domestic CPUs (such as Loongson 3A6000) only support a single SPI interface, which leads to many technical problems due to this hardware limitation. The following takes the Loongson 3A6000 CPU as an example for illustration: 1. Physical limitation of single SPI interface The single SPI interface design of the Loongson 3A6000 CPU cannot directly support the simultaneous connection of main and backup Flash memories at the hardware level. This means that, during the startup process, the CPU can only access the main Flash memory through the unique SPI interface. Once the main Flash memory fails (for example, due to firmware damage, poor chip contact, or memory aging), the CPU will be unable to obtain valid startup firmware, directly leading to system startup failure and further causing system downtime.

[0003] 2. Serious dependence on startup reliability The traditional solution completely depends on the normal operation of a single Flash memory. If the main Flash memory fails in any way, the CPU will be stuck due to the inability to load the startup program, and the system stability cannot be guaranteed. This absolute dependence on a single Flash memory makes the system extremely vulnerable when facing hardware failures.

[0004] 3. Functional limitations of dedicated switching devices If a dedicated SPI signal switching device is used, although it can achieve the connection of multiple Flash memories, such devices have significant limitations. They lack programmability and cannot implement intelligent switching control logic based on startup failure signals, and cannot dynamically adjust the signal flow direction according to the startup state of the CPU. SUMMARY

[0005] The purpose of the present application is to overcome the above technical problems and provide a main-backup Flash startup system for a domestic CPU.

[0006] To achieve the above purpose, the technical solution adopted by the present application is as follows: A main-backup Flash startup system for a domestic CPU, comprising a domestic CPU, a CPLD device, a main Flash memory, at least one backup Flash memory, and a GPIO signal line. The domestically produced CPU has a single-channel SPI interface, which is electrically connected to the CPLD device via the SPI interface; the CPLD device is used to expand the single-channel SPI interface of the domestically produced CPU into a multi-channel SPI interface and realize switching control between the main Flash memory and the backup Flash memory; the main Flash memory is electrically connected to the domestically produced CPU via the SPI interface of the CPLD device, and is used to store the main startup firmware; The backup Flash memory is electrically connected to the domestic CPU through other SPI interfaces of the CPLD device, and each backup Flash memory is used to store independent backup startup firmware; the GPIO signal line is used to transmit startup failure signals and reset control signals between the domestic CPU and the CPLD device to achieve automatic switching of the primary and backup Flash memories.

[0007] Furthermore, the single-channel SPI interface of the domestic CPU is expanded into a multi-channel SPI interface by performing logic programming processing through programmable logic code inside the CPLD device.

[0008] Furthermore, the CPLD device performs logic programming processing inside through programmable logic code, including switching logic processing of the clock signal, chip selection signal, data input signal and data output signal of the SPI signal.

[0009] Furthermore, the domestically produced CPU is a Loongson processor.

[0010] Furthermore, the number of the multi-channel SPI interfaces is equal to the total number of the main Flash memory and all backup Flash memories.

[0011] The present invention also provides a domestic CPU main and standby Flash startup method, the steps are: S1: The domestic CPU is powered on and started, and the CPLD device switches the SPI signal to the main Flash memory first; S2: The domestic CPU starts by loading the firmware in the main Flash memory; S3: If the main Flash memory fails to start, the domestic CPU sends a startup failure signal to the CPLD device through the GPIO signal line; S4: After receiving the startup failure signal, the CPLD device operates the reset signal of the domestic CPU to trigger the CPU reset and switches the SPI signal to a backup Flash memory; S5: The CPLD device releases the reset signal of the domestic CPU, and the domestic CPU restarts and loads the firmware of the switched backup Flash memory through the CPLD device to start.

[0012] Further, the CPLD device in the step S4 is switched by programmable logic code for logic programming processing to realize the switching of the SPI signals, including the switching logic of the clock signal, the chip selection signal, the data input signal and the data output signal.

[0013] Further, the specific method of the step S4 is: S41: After the CPLD device receives the start failure signal sent by the domestic CPU, the internal logic circuit generates a control signal according to the preset switching logic, and prepares to switch the output target of the clock signal; S42: The CPLD device switches the output target of the clock signal from the main Flash memory to the selected standby Flash memory, so as to ensure that the clock signal can be correctly transmitted to the standby Flash memory; S43: The chip selection signal is synchronously switched according to the switched SPI_CLK signal, and the CPLD device controls the level of the chip selection signal through the internal logic, so as to ensure that only the selected standby Flash memory can respond to the SPI bus command, and other standby Flash memories are in the unselected state; S44: The CPLD device adjusts the level state of the data input signal and the data output signal according to the switching logic, so as to ensure the stability and reliability of the communication between the SPI bus and the standby Flash memory, and prevent data writing error or communication interruption; S45: The CPLD device completes the switching logic of all SPI signals, so as to ensure that a stable communication connection is established between the SPI bus and the standby Flash memory.

[0014] Further, in the step S5, if the switched standby Flash memory starts successfully after the domestic CPU is restarted, the system normally runs; if the domestic CPU fails to start the firmware of the switched standby Flash memory, the domestic CPU sends a start failure signal to the CPLD device through the GPIO signal line again, the CPLD device triggers the domestic CPU to reset again and switches the SPI signal to the next standby Flash memory.

[0015] Further, the step S6 of verifying whether the CPLD device can correctly receive the start failure signal of the domestic CPU and switch to the standby Flash memory for starting when the main Flash memory fails to start is further included.

[0016] The present application has the following beneficial effects: 1、The CPLD device of the application expands the original single SPI interface of the domestic CPU into a multi-channel SPI interface through internal logic programming. This expansion enables the CPU to simultaneously connect the main and standby Flash memories for startup. When the CPU is powered on, the CPLD preferentially switches the SPI signal to the main Flash; if the main Flash fails to start, the CPU notifies the CPLD through the GPIO signal, and the CPLD controls the reset signal and switches the SPI signal to the standby Flash, ensuring that the CPU can be restarted. This design significantly improves the reliability of CPU startup, avoids system startup failure due to single Flash failure, realizes flexible expansion of the SPI interface, and greatly improves system reliability.

[0017] 2、Compared with traditional dedicated SPI signal switching devices, the CPLD device of the application has a more flexible and intelligent logic control mode realized through internal code. The CPLD device can accurately control the signal flow direction according to actual needs, effectively handling the logic interaction and startup process between the CPU and the Flash. This innovative logic control mode not only simplifies hardware design, but also optimizes the startup process, improving the overall performance and stability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The system architecture block diagram of the first embodiment of the application.

[0019] Figure 2 The working flowchart of the first embodiment of the application.

[0020] Figure 3 The simulation timing diagram of the main Flash memory switching to the standby Flash memory of the application. DETAILED DESCRIPTION

[0021] The application will be described in detail below in conjunction with the drawings and embodiments. In order to more clearly and intuitively describe the technical solutions of the application, the following embodiments take the Loongson 3A6000 as an example to illustrate the domestic CPU. Embodiment One

[0022] A domestic CPU main and standby Flash startup system, as shown in Figure 1 , includes a Loongson 3A6000 CPU, a CPLD device, a main Flash memory, a standby Flash memory, and a GPIO signal line; the Loongson 3A6000 CPU has a single SPI interface, which is electrically connected to the CPLD device through the SPI interface.

[0023] The signal flow direction is logically programmed by code inside the CPLD device, including the switching logic processing of the clock signal (SPI CLK), chip selection signal (SPI CSN), data input signal (SPI DI) and data output signal (SPI DO) of the SPI signal, so as to expand the single-channel SPI interface of the Loongson 3A6000 CPU into a two-way SPI interface, and realize the switching control between the main Flash memory and the standby Flash memory.

[0024] The following is the core code of the CPLD device to realize the logical switching of the SPI signal: / *Assign the CPU_SPI_SDO signal of the CPU to the CPLD_QSPI_MOSI signal. In the CPLD, the signals are connected together after being converted by the logic circuit. * / assign CPLD_QSPI_MOSI = CPU_SPI_SDO; / *Assign the CPLD_QSPI_MISO signal to the CPU_SPI_SDI. In the CPLD, the signals are connected together after being converted by the logic circuit. * / assign CPU_SPI_SDI = CPLD_QSPI_MISO; *Define the spi_cs signal as high level when the current state is standby state and chip selection state, and non-S0 state. When the current state is start state, the chip selection signal is valid. * / wire spi_cs_High = current_state==S0_WAIT ||current_state==SPI_SEL ||current_state>S4_CPU_S0; / *Define the SPI clock idle state as high level to keep consistent with the main and standby Flash device clock idle state, and ensure signal compatibility. * / localparam SPI_CLK_IDLE_STATE = 1; / *Assign the CPU_SPI_SCK signal to the CPLD_QSPI_SCK. In the CPLD, the signals are connected together after being converted by the logic circuit. * / assign CPLD_QSPI_SCK =CPU_SPI_SCK; / * Define the idle state of the SPI chip select signal as high, keep the non-selected state, prevent unexpected data transmission on the bus. * / localparam SPI_CSN_IDLE_STATE = 1; / * If spi_cs_High = 1 or flash1_sel = 1, pull high (disable); otherwise, assign the CPU's CPU_SPI_CSN signal to the CPLD_QSPI_CS0N signal, select the main Flash to start * / assign CPLD_QSPI_CS0N = spi_cs_High | (flash1_sel? CPU_SPI_CSN : 1'h1); / * If spi_cs_High = 1 or flash1_sel = 0, pull high (disable); otherwise, assign the CPU's CPU_SPI_CSN signal to the CPLD_QSPI_CS1N signal, select the standby Flash to start * / assign CPLD_QSPI_CS1N = spi_cs_High | (flash1_sel? 1'h1 : CPU_SPI_CSN).

[0025] The main Flash memory is electrically connected to the Loongson 3A6000 CPU through one SPI interface of the CPLD device, and stores the main startup firmware; the standby Flash memory is connected to the Loongson 3A6000 CPU through another SPI interface of the CPLD device, and the standby Flash memory stores an independent standby startup firmware; the GPIO signal line is used to transmit startup failure signals and reset control signals between the Loongson 3A6000 CPU and the CPLD device, to realize automatic switching of the main and standby Flash memories.

[0026] The working principle of the embodiment is briefly described as follows: The Loongson 3A6000 CPU sends a startup instruction to the CPLD device through its single SPI interface, and the CPLD device preferentially switches the SPI signal to the main Flash memory; if the main Flash memory fails to start, the Loongson 3A6000 CPU sends a startup failure signal to the CPLD device through the GPIO signal line, the CPLD device responds by pulling down the CPU reset signal, and switches the SPI signal to any standby Flash memory; after the CPLD device releases the CPU reset signal, the Loongson 3A6000 CPU restarts and accesses the switched standby Flash memory through the CPLD device to start up.

[0027] In order to more clearly understand the technical solutions of the embodiments, the working method is explained in detail as follows: As Figure 2 indicated, a domestic CPU main and standby Flash starting method, steps are as follows: S1: Loongson 3A6000 CPU power-on starts, and a CPLD device preferentially switches an SPI signal to a main Flash memory; S2: Loongson 3A6000 CPU starts by loading firmware in the main Flash memory; S3: If the main Flash memory fails to start, Loongson 3A6000 CPU sends a starting failure signal to the CPLD device through a GPIO signal line; S4: After receiving the starting failure signal, the CPLD device operates a reset signal of Loongson 3A6000 CPU to trigger CPU reset and switches the SPI signal to a standby Flash memory; S5: The CPLD device releases the reset signal of Loongson 3A6000 CPU, and Loongson 3A6000 CPU restarts and starts by loading firmware of the switched standby Flash memory through the CPLD device.

[0028] As Figure 3 is a switching timing diagram of the main Flash memory grabbed by the simulation platform to the standby Flash memory, from Figure 3 we can see that the left side (time mark-100 to 3545 section) of the red line La is the timing signal of the main Flash memory, and from the time mark 3545 node, it is switched to the standby Flash memory, that is, the right side (time mark 3545 to 3950 section) of the red line La is the timing signal of the standby Flash memory.

[0029] Preferably, the CPLD device in the step S4 switches the SPI signal by logically programming the signal flow direction through internal code, including switching logic of a clock signal (SPI_CLK), a chip selection signal (SPI_CSN), a data input signal (SPI_DI) and a data output signal (SPI_DO), and the specific method is as follows: S41: After receiving the starting failure signal sent by Loongson 3A6000 CPU, the CPLD device generates a control signal according to the preset switching logic, and prepares to switch the output target of the clock signal (SPI_CLK) first; S42: The CPLD device switches the output target of the clock signal (SPI_CLK) from the main Flash memory to the selected standby Flash memory, ensuring that the clock signal can be correctly transmitted to the standby Flash memory; S43: The chip select signal (SPI_CSN) is synchronously switched according to the switched SPI_CLK signal. The CPLD device controls the level of the chip select signal (SPI_CSN) through internal logic, ensuring that only the selected standby Flash memory can respond to the SPI bus command, while other standby Flash memories are in an unselected state. S44: The CPLD device adjusts the level state of the data input signal (SPI_DI) and the data output signal (SPI_DO) according to the switching logic to ensure the stability and reliability of communication between the SPI bus and the standby Flash memory, preventing data write errors or communication interruptions. S45: The CPLD device completes the switching logic of all SPI signals to ensure a stable communication connection between the SPI bus and the standby Flash memory.

[0030] The CPLD device of the present embodiment expands the original single SPI interface of the Loongson 3A6000 CPU to a two-way SPI interface through internal logic programming. This expansion enables the Loongson 3A6000 CPU to simultaneously connect the main and standby Flash memories for startup. When the CPU is powered on, the CPLD device preferentially switches the SPI signal to the main Flash. If the main Flash fails to start, the CPU notifies the CPLD device through a GPIO signal, and the CPLD device controls the reset signal and switches the SPI signal to the standby Flash, ensuring that the Loongson 3A6000 CPU can be restarted. This design significantly improves the reliability of CPU startup, avoids system startup failure due to single Flash failure, realizes flexible expansion of the SPI interface, and greatly improves system reliability.

[0031] In addition, compared with traditional dedicated SPI signal switching devices, the CPLD device of the present embodiment has a more flexible and intelligent logic control method implemented through internal code. The CPLD device can accurately control the signal flow direction according to actual needs, effectively handling the logic interaction and startup process between the CPU and the Flash. This innovative logic control method not only simplifies hardware design, but also optimizes the startup process, improving the overall performance and stability of the system. Embodiment Two

[0032] The difference from the above embodiment one is that the CPLD device extends the single SPI interface of the Loongson 3A6000 CPU to a 2-way or more SPI interface, which can have multiple standby Flash memories, thereby being more stable and reliable. In specific work, if the switched standby Flash memory starts successfully, the system runs normally; if the switched standby Flash memory also fails to start, the Loongson 3A6000 CPU sends a start failure signal again through the GPIO, the CPLD device triggers a reset and switches to the next standby Flash, until all standby Flash memories are tried to start. Embodiment three

[0033] This embodiment adds a simulation verification module for the master-slave Flash memory switching function on the basis of the system described in embodiment one, for verifying the fault switching robustness of the system before hardware deployment. The specific verification process is as follows: 1. Simulation platform building The digital simulation environment of the CPU-CPLD-Flash system is built using EDA tools, specifically including: Loongson 3A6000 CPU behavior model, for simulating SPI interface and GPIO signal output; CPLD programmable logic code, same as embodiment one; Master Flash memory and standby Flash memory model, supporting firmware loading state feedback; Fault injection module, for simulating the failure scenario of the master Flash memory; 2. Fault injection and switching triggering Step 1: Initialize the simulation platform, and the CPLD device routes the SPI signal to the master Flash memory; Step 2: Force the master Flash memory to return a start failure state (such as a firmware verification error signal) through the fault injection module; Step 3: Monitor whether the CPU behavior model sends a start failure signal to the CPLD through the GPIO signal line; Step 4: Verify whether the CPLD device pulls down the CPU reset signal within the preset clock period after receiving the failure signal.

[0034] 3. SPI signal switching verification Monitor the key SPI signal timing output by the CPLD to verify the following logic: Clock signal (SPI_CLK) switching: the CPLD device switches the clock output target from the master Flash to the standby Flash, and there is no glitch in the switching process; Chip selection signal (SPI_CSN) synchronization: the chip selection signal completes level jump on the next clock rising edge after the SPI_CLK switching, ensuring that the standby Flash is selected (in this embodiment, low level is effective); Data input signal (SPI_DI) and data output signal (SPI_DO) state: the signal level is immediately adjusted to the default working state of the standby Flash after switching (in this embodiment, high level is set) 4. Switching success determination standard After the CPU reset is released, the starting firmware first instruction in the standby Flash memory is successfully read through the SPI bus, indicating that the simulation verification is successful, otherwise, it indicates that the simulation verification fails.

[0035] Through the simulation verification of this embodiment, it is confirmed that the CPLD device can intelligently trigger the switching action based on the GPIO signal of the CPU when the main Flash memory fails, and the verification process guarantees the high availability of the system in the real hardware environment.

[0036] It should be noted that the domestic CPU, CPLD device, Flash memory and the like of the present application are all through devices, which can be flexibly selected in actual application, and the above embodiments are only used for illustration.

[0037] Finally, it should be pointed out that: the above embodiments are only used to illustrate the present application and not to limit the technical solutions described in the present application; therefore, although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the present application can still be modified or replaced by equivalents; all technical solutions and improvements which do not deviate from the spirit and scope of the present application should be covered in the scope of claims of the present application.

Claims

1. A domestic CPU master-slave Flash boot system, characterized by: Includes domestic CPU, CPLD device, main Flash memory, at least one spare Flash memory and GPIO signal line; The domestically produced CPU has a single-channel SPI interface and is electrically connected to the CPLD device via the SPI interface; the CPLD device is used to expand the single-channel SPI interface of the domestically produced CPU into a multi-channel SPI interface and realize switching control between the main Flash memory and the backup Flash memory; The main Flash memory is electrically connected to the domestic CPU via an SPI interface of the CPLD device and is used to store the main startup firmware; The backup Flash memory is electrically connected to the domestic CPU through other SPI interfaces of the CPLD device, and each backup Flash memory is used to store independent backup startup firmware; the GPIO signal line is used to transmit startup failure signals and reset control signals between the domestic CPU and the CPLD device to achieve automatic switching of the primary and backup Flash memories.

2. The domestic CPU master-slave Flash boot system according to claim 1, characterized in that: The CPLD device internally expands the single-channel SPI interface of the domestic CPU into a multi-channel SPI interface by performing logic programming processing through programmable logic code.

3. The domestic CPU master-slave Flash boot system according to claim 2, characterized in that: The CPLD device internally performs logic programming processing through programmable logic code, including switching logic processing of the clock signal, chip selection signal, data input signal and data output signal of the SPI signal.

4. The domestic CPU master-slave Flash boot system according to claim 1, characterized in that: The domestically produced CPU is the Loongson processor.

5. The domestic CPU master-slave Flash boot system according to claim 1, characterized in that: The number of the multi-channel SPI interfaces is equal to the total number of the main Flash memory and all the backup Flash memories.

6. A domestic CPU master-slave Flash startup method, characterized in that: Applying the domestic CPU master-slave Flash boot system as described in claim 1, the steps are: S1: The domestic CPU is powered on and started, and the CPLD device switches the SPI signal to the main Flash memory first; S2: The domestic CPU starts by loading the firmware in the main Flash memory; S3: If the main Flash memory fails to start, the domestic CPU sends a startup failure signal to the CPLD device through the GPIO signal line; S4: After receiving the startup failure signal, the CPLD device operates the reset signal of the domestic CPU to trigger the CPU reset and switches the SPI signal to a backup Flash memory; S5: The CPLD device releases the reset signal of the domestic CPU, and the domestic CPU restarts and loads the firmware of the switched backup Flash memory through the CPLD device to start.

7. The method for booting a domestically produced CPU master / slave Flash according to claim 6, characterized in that: In step S4, the CPLD device performs logic programming processing through programmable logic code to realize the switching of SPI signals, including the switching logic of clock signal, chip select signal, data input signal and data output signal.

8. The method for booting a domestically produced CPU master / slave Flash according to claim 7, characterized in that: The specific method of step S4 is: S41: After the CPLD device receives the startup failure signal sent by the domestic CPU, the internal logic circuit first generates a control signal according to the preset switching logic to prepare to switch the output target of the clock signal; S42: The CPLD device switches the output destination of the clock signal from the main Flash memory to the selected backup Flash memory to ensure that the clock signal can be correctly transmitted to the backup Flash memory; S43: The chip select signal is switched synchronously according to the switched SPI_CLK signal. The CPLD device controls the chip select signal level through internal logic to ensure that only the selected standby Flash memory can respond to the SPI bus command, while other standby Flash memories are in an unselected state. S44: The CPLD device adjusts the level states of the data input signal and the data output signal according to the switching logic to ensure the stability and reliability of communication between the SPI bus and the backup Flash memory, thereby preventing data writing errors or communication interruptions. S45: The CPLD device completes the switching logic of all SPI signals to ensure a stable communication connection between the SPI bus and the backup Flash memory.

9. The method for booting a domestic CPU master / slave Flash according to any one of claims 6 to 8, characterized in that: In step S5, after the domestic CPU restarts, if the switched backup Flash memory starts successfully, the system runs normally; if the domestic CPU fails to load the firmware of the switched backup Flash memory to start, the domestic CPU again sends a startup failure signal to the CPLD device through the GPIO signal line, and the CPLD device again triggers the domestic CPU to reset and switches the SPI signal to the next backup Flash memory.

10. The method for booting the domestic CPU master / slave Flash according to claim 6, characterized in that: The method further includes step S6: verifying through a simulation verification module whether the CPLD device can correctly receive the startup failure signal of the domestic CPU and switch to the backup Flash memory for startup when the main Flash memory fails to start.

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