Display panel and display device

Abstract

The invention provides a display panel and a display device.A pixel circuit in the display panel comprises a driving module, a data writing module and an adjusting module, the first end of the data writing module is electrically connected with the first end of the driving module, and the first end of the adjusting module is electrically connected with at least one end of the driving module; signal lines in the display panel comprise a data signal line and an adjusting signal line, the data signal line is electrically connected with the second end of the data writing module, and the adjusting signal line is electrically connected with the second end of the adjusting module; the pixel circuit comprises a first pixel circuit and a second pixel circuit, the adjusting signal line comprises a first adjusting signal line and a second adjusting signal line, the first adjusting signal line is electrically connected with an adjusting module in the first pixel circuit, and the second adjusting signal line is electrically connected with an adjusting module in the second pixel circuit; signal potentials in the first adjustment signal line and the second adjustment signal line are different. The power consumption of the display panel is reduced by adjusting different pixel circuits to be connected to the adjusting signal lines with different potentials.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display panels have become widely used in people's production and daily life. Display panels involve various circuit structures and wiring connecting these circuit structures to realize the display function of the display panel. The circuit structures can be pixel circuits, etc.

[0003] In order to better meet people's needs, detailed adjustments can be made to the wiring in the display panel to ensure a better overall effect of the display panel. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device, which reduce the power consumption of the display panel by adjusting different pixel circuits to access adjustment signal lines with different potentials.

[0005] In a first aspect, an embodiment of the present invention provides a display panel including a pixel circuit and a signal line;

[0006] The pixel circuit includes a driving module, a data writing module and an adjustment module, wherein a first end of the data writing module is electrically connected to a first end of the driving module, and a first end of the adjustment module is electrically connected to at least one end of the driving module;

[0007] The signal line includes a data signal line and an adjustment signal line, the data signal line is electrically connected to the second end of the data writing module, and the adjustment signal line is electrically connected to the second end of the adjustment module;

[0008] The pixel circuit includes a first pixel circuit and a second pixel circuit, the adjustment signal line includes a first adjustment signal line and a second adjustment signal line, the first adjustment signal line is electrically connected to the second end of the adjustment module in the first pixel circuit, and the second adjustment signal line is electrically connected to the second end of the adjustment module in the second pixel circuit;

[0009] The signal potentials in the first adjustment signal line and the second adjustment signal line are different.

[0010] In a second aspect, an embodiment of the present invention provides a display device comprising the display panel of the first aspect.

[0011] The embodiment of the present application provides a display panel, a pixel circuit in the display panel comprises an adjusting module; wherein the pixel circuit comprises a first pixel circuit and a second pixel circuit, adjusting signal lines in the display panel comprise a first adjusting signal line and a second adjusting signal line, wherein the first adjusting signal line is electrically connected with the adjusting module in the first pixel circuit, and the second adjusting signal line is electrically connected with the adjusting module in the second pixel circuit; further, the signal potential in the first adjusting signal line and the second adjusting signal line is different, that is, the adjusting module in different pixel circuits can be connected with the adjusting signal lines of different potentials. The adjusting signal lines are differentially set, different adjusting signal lines provide different potentials according to the different requirements of the adjusting module electrically connected with the adjusting signal lines, so that the power consumption of the display panel as a whole is reduced.

[0012] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the drawings needed in the description of the embodiments are briefly introduced below. Obviously, the drawings introduced are only a part of the drawings of the embodiments to be described by the present application, and not all the drawings. Those skilled in the art can also obtain other drawings from these drawings without creating labor.

[0014] FIG. 1 is a structural schematic diagram of a display panel provided by the embodiment of the present application;

[0015] FIG. 2 is a circuit element diagram of a first pixel driving circuit provided by the embodiment of the present application;

[0016] FIG. 3 is a circuit element diagram of a second pixel driving circuit provided by the embodiment of the present application;

[0017] FIG. 4 is a circuit element diagram of a third pixel driving circuit provided by the embodiment of the present application;

[0018] FIG. 5 is an embodiment of the timing diagram of the signal provided to the pixel driving circuit shown in FIG. 2 in one driving period;

[0019] FIG. 6 is a film layer structure schematic diagram of the pixel circuit shown in FIG. 2 ;

[0020] FIG. 7is a cross-sectional schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0021] FIG. 8 Schematic diagram of a film layer stacking structure of a display panel provided by an embodiment of the present invention;

[0022] FIG. 9 yes FIG. 8 A structural diagram of the first part;

[0023] FIG. 10 yes FIG. 8 A structural diagram of the second part;

[0024] FIG. 11 yes FIG. 8 A structural diagram of the third part;

[0025] FIG. 12 yes FIG. 8 A structural diagram of the fourth part;

[0026] FIG. 13 yes FIG. 8 A structural diagram of the fifth part;

[0027] FIG. 14 yes FIG. 8 A structural diagram of the sixth part;

[0028] FIG. 15 yes FIG. 8 A structural diagram of the seventh part;

[0029] FIG. 16 yes FIG. 8 A structural diagram of the eighth part;

[0030] FIG. 17 yes FIG. 8 A structural diagram of the ninth part;

[0031] FIG. 18 yes FIG. 8 A structural diagram of the tenth part;

[0032] FIG. 8 yes FIG. 6 A schematic diagram of a stacking process from the second to the sixth part;

[0033] FIG. 7 yes FIG. 9 to FIG. 18 A schematic diagram of a stacking process from the second to the seventh parts;

[0034] FIG. 9 to FIG. 18 yes FIG. 19 Another schematic diagram of stacking of the second to ninth parts;

[0035] FIG. 8 is FIG. 10 to FIG. 14 Another structural schematic view of the eighth part in the first embodiment of the present application;

[0036] FIG. 19 is FIG. 10 A structural schematic view of the ninth part in the first embodiment of the present application;

[0037] FIG. 11 is FIG. 13 A laminated schematic view of the second part, the sixth part and the seventh part in the first embodiment of the present application;

[0038] FIG. 12 is FIG. 14 A laminated schematic view of the second part, the fourth part, the sixth part, the seventh part and the eighth part in the first embodiment of the present application; FIG. 11 A laminated schematic view of the eighth part and the ninth part in the first embodiment of the present application; FIG. 12 A laminated schematic view of the ninth part in the first embodiment of the present application;

[0039] FIG. 19 is FIG. 10 to FIG. 14 A laminated schematic view of the second part and the seventh part in the first embodiment of the present application;

[0040] FIG. 19 is FIG. 10 A laminated schematic view of the sixth part and the seventh part in the first embodiment of the present application;

[0041] FIG. 15 is FIG. 17 A laminated schematic view of the seventh part and the eighth part in the first embodiment of the present application;

[0042] FIG. 10 is FIG. 15 A laminated schematic view of the eighth part and the ninth part in the first embodiment of the present application;

[0043] FIG. 17 is A structural schematic view of a display module provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0045] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and in the above-described drawings are intended to distinguish similar objects and not necessarily to describe a particular sequential or chronological order. It is to be understood that the data thus used in the description can be interchanged, where appropriate, so that the embodiments of the application described herein can be carried out in other than the order shown or described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover a non-exclusive inclusion, for example, a system, product or apparatus that comprises a list of elements does not necessarily comprise only those elements but can include other elements not expressly listed or inherent to such system, product or apparatus.

[0046] Various modifications and changes can be made as would be obvious to a person skilled in the art without departing from the spirit and scope of the application. It is intended that the application encompass such modifications and changes as fall within the scope of the corresponding claims (technical solutions claimed to be protected) and their equivalents. It should be noted that the embodiments of the present application provide the implementation manners, which can be combined with each other without contradiction.

[0047] FIG. 10 is a structural schematic diagram of a display panel provided by an embodiment of the present application, FIG. 15 is a circuit element diagram of a first pixel driving circuit provided by an embodiment of the present application, FIG. 17 is a circuit element diagram of a second pixel driving circuit provided by an embodiment of the present application, FIG. 20 is a circuit element diagram of a third pixel driving circuit provided by an embodiment of the present application, FIG. 8 is an implementation manner of a signal provided to the pixel driving circuit shown in FIG. 10 is a timing diagram of the implementation manner of the signal of the pixel driving circuit shown in FIG. 14 is a timing diagram of the implementation manner of the signal of the pixel driving circuit shown in FIG. 15 is a film layer structure schematic diagram of the pixel circuit shown in FIG. 20 is a cross-sectional schematic diagram of a pixel circuit provided by an embodiment of the present application, FIG. 20 is a film layer structure schematic diagram of a display panel provided by an embodiment of the present application, referring to FIG. 10As shown, an embodiment of the present invention provides a display panel 10, which includes a pixel circuit 100 and a signal line 200; the pixel circuit 100 includes a driving module 101, a data writing module 102 and an adjustment module 103, the first end of the data writing module 102 is electrically connected to the first end of the driving module 101, and the first end of the adjustment module 103 is electrically connected to at least one end of the driving module 101; the signal line 200 includes a data signal line Data and an adjustment signal line, the data signal line Data is electrically connected to the second end of the data writing module 102, and the adjustment signal line is electrically connected to the second end of the adjustment module 103; the pixel circuit 100 includes a first pixel circuit 100a and a second pixel circuit 100b, the adjustment signal line includes a first adjustment signal line and a second adjustment signal line, the first adjustment signal line is electrically connected to the second end of the adjustment module 103 in the first pixel circuit 100a, and the second adjustment signal line is electrically connected to the second end of the adjustment module 103 in the second pixel circuit 100b; the signal potentials in the first adjustment signal line and the second adjustment signal line are different.

[0048] Among them, reference FIG. 14 As shown, the display panel 10 includes a pixel circuit 100, which is electrically connected to the light-emitting element 300 of the display panel 10 to drive the light-emitting element 300 and ensure the light-emitting display of the light-emitting element 300. Specifically, the display panel 10 also includes a signal line 200 configured to provide a voltage signal and / or a current signal to the pixel circuit 100, thereby ensuring the overall display effect of the display panel 10.

[0049] Among them, reference FIG. 15 As shown, the pixel circuit 100 includes a driving module 101, a data writing module 102 and an adjustment module 103. The data writing module 102 writes the data signal into the pixel circuit 100; the driving module 101 generates a driving current in combination with the written data signal, and the pixel circuit 100 then transmits the driving current to the light-emitting element 300, thereby controlling the light-emitting element 300 to perform light-emitting display; the adjustment module 103 is connected to the driving module 101 to ensure the stability of the driving module 101 during operation, thereby ensuring the stability and reliability of the pixel circuit 100, and thereby ensuring the display effect of the display panel 10.

[0050] Furthermore, the pixel circuit 100 has various configuration modes. FIG. 10 As shown, the pixel circuit 100 is illustrated as "8T1C", where "T" represents a transistor and "C" represents a storage capacitor. Based on the configuration of the pixel circuit 100, those skilled in the art can make adaptive adjustments as needed.

[0051] Exemplary, reference FIG. 15As shown, the pixel circuit 100 can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization transistor T5, a second light emitting control transistor T6, a reset transistor T7, a bias adjusting transistor T8 and a storage capacitor Cst. Specifically, for the working process of the pixel circuit 100, reference can be made to the following description in combination with FIG. 2. FIG. 15 For example, the scan signal line S1N can control the turn-on and turn-off of the initialization transistor T5 of the pixel circuit 100, and reset the gate potential of the driving transistor T3 when the initialization transistor T5 is turned on, i.e., transmit the initialization signal of the initialization signal line VREF1 to the initialization transistor T5, and reset the connection node (the first node N1) of the driving transistor T3, the initialization transistor T5, the threshold compensation transistor T4 and the storage capacitor Cst. The scan signal line SP controls the turn-on and turn-off of the data writing transistor T2 of the pixel circuit 100, and writes the data signal on the data signal line Data to the gate of the driving transistor T3 when the data writing transistor T2 is turned on. The scan signal line S2N can control the turn-on and turn-off of the threshold compensation transistor T4, and compensate the threshold voltage of the driving transistor T3 when the threshold compensation transistor T4 is turned on. At the same time, the scan signal line SP* controls the turn-on and turn-off of the reset transistor T7, and resets the anode of the light emitting element 300 connected to the pixel circuit 100 when the reset transistor T7 is turned on, i.e., transmits the reset signal of the reset signal line VREF2 to the anode of the light emitting element 300. The light emitting control signal line EMIT controls the turn-on and turn-off of the first light emitting control transistor T1 and the second light emitting control transistor T6, and transmits the power signal transmitted by the power signal line PVDD to the light emitting element 300 when the first light emitting control transistor T1 and the second light emitting control transistor T6 are controlled to be turned on, so as to realize the display and light emission of the light emitting element 300. Further, reference can be made to the following description in combination with FIG. 3. FIG. 15As shown, the pixel circuit 100 also includes a bias transistor T8. The scanning signal line SP* also controls the conduction or shutdown of the bias transistor T8 and performs bias adjustment on the driving transistor T3 when the bias transistor T8 is turned on. That is, the bias signal of the bias adjustment signal line DVH is transmitted to the bias transistor T8, and the connection node (second node N2) of the driving transistor T3, the first light-emitting control transistor T1, and the data writing transistor T2 is bias adjusted to ensure the working stability of the driving transistor T3. In other words, the bias signal of the bias adjustment signal line DVH includes an enable level and a disable level. The enable level can turn on the bias transistor T8; the disable level can turn off (or cut off) the bias transistor T8. By setting the bias transistor T8, the brightness of the first frame during image display can be improved, the brightness of the first frame can be avoided from being too low, and the consistency of the image display effect can be ensured. In addition, under low-frequency driving, leakage is more obvious. By controlling the bias transistor T8 to be turned on and using the bias transistor T8 to write a bias voltage to the source and / or drain of the driving transistor T3, the bias state of the driving transistor T3 can be maintained consistent with the bias state when the data voltage is just written, thereby improving the stability of the working state of the driving transistor T3, improving low-frequency flicker, and thus improving the picture display effect of the display panel 10.

[0052] Exemplary, reference FIG. 15 As shown, the initialization transistor T5 and the threshold compensation transistor T4 in the pixel circuit 100 are N-type transistors, and the remaining transistors are P-type transistors. The N-type transistor is an oxide transistor (Indium Gallium Zinc Oxide, IGZO), and the oxide transistor has advantages such as low leakage current; the P-type transistor is a low-temperature polysilicon transistor (Low Temperature Poly-Silicon, LTPS), and the low-temperature polysilicon transistor has advantages such as high switching speed, high carrier mobility and low power. In this way, the pixel circuit 100 can be compatible with the advantages of N-type transistors and P-type transistors. In addition, the threshold compensation transistor T4 and the initialization transistor T5 can be single-gate transistors or dual-gate transistors. When dual-gate transistors are used, the leakage current of the transistor is reduced and the display effect of the display panel is improved. The present invention is only illustrated by taking the example that the threshold compensation transistor T4 and the initialization transistor T5 are both top-bottom dual-gate transistors. Based on the specific type of the display panel 10, the embodiment of the present invention is not limited and can be adaptively adjusted according to actual production needs.

[0053] Further, combined FIG. 14As shown, the enable level can turn on the transistor, and the non-enable level can turn off (or cut off) the transistor. Among them, the non-enable level of the light emitting control signal EMIT is a high level, and the enable level is a low level; the enable level of the signal transmitted by the scanning signal line S1N and the scanning signal line S2N is a high level, and the non-enable level is a low level; the enable level of the signal transmitted by the scanning signal line SP and the scanning signal line SP* is a low level, and the non-enable level is a high level. Specifically, refer to FIG. 14 As shown, in a driving cycle Y of the pixel circuit 100, the gate signal transmitted by the light-emitting control signal line EMIT includes multiple non-enable level stages and multiple enable level stages, and the multiple non-enable level stages and the multiple enable level stages are alternately arranged, wherein, when the light-emitting control signal line EMIT is at the non-enable level, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned off, and when the light-emitting control signal line EMIT is at the enable level, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on.

[0054] Furthermore, in a driving cycle Y of the pixel driving circuit 100, a data writing phase Y1, a light emitting phase Y2 and a light emitting holding phase Y3 are included, wherein the data writing phase Y1 includes a non-enable level phase of the light emitting control signal EMIT, the light emitting phase Y2 includes an enable level phase of the light emitting control signal EMIT, and in the light emitting holding phase Y3, the light emitting control signal EMIT includes multiple non-enable level phases and at least one enable level phase ( FIG. 10 In the example of an enable level stage, the level of the bias adjustment signal line DVH in the data writing stage Y1 and the light emitting stage Y2 can be the same as or different from the level of the bias adjustment signal line DVH in the light emitting holding stage Y3. FIG. 14 (indicated in the middle).

[0055] Furthermore, the data writing phase Y1 includes a first bias adjustment phase Y11. In the first bias adjustment phase Y11, the signal transmitted by the scanning signal line SP* includes at least one low-level period, and during this period, the signal transmitted by the scanning signal line S2N includes at least one high-level period. In other words, in the first bias adjustment phase Y11, at least the bias transistor T8 and the threshold compensation transistor T4 are turned on, and the bias signal of the bias adjustment signal line DVH is transmitted to the driving transistor T3 through the bias transistor T8, and then transmitted to the gate of the driving transistor T3 through the threshold compensation transistor T4. That is, in the first bias adjustment phase Y11, the bias signal can bias the first node N1, the second node N2, and the third node N3.

[0056] The data writing phase Y1 also includes an initialization and second bias adjustment phase Y12. In the initialization and second bias adjustment phase Y12, the signal transmitted by the scanning signal line S2N includes at least one high-level period. At the same time, the signal transmitted by the scanning signal line S1N also includes at least one high-level period. In other words, in the initialization and second bias adjustment phase Y12, the initialization transistor T5 is turned on, and the later threshold compensation transistor T4 is also turned on. The initialization signal line VREF1 can adjust the gate of the driving transistor T3 through the initialization transistor T5. The initialization signal line VREF1 can also adjust the third node N3 through the initialization transistor T5 and the threshold compensation transistor T4.

[0057] The data writing phase Y1 also includes a data signal writing phase Y13, in which the signal transmitted by the scanning signal line S2 includes a high-level period, and the signal transmitted by the scanning signal line SP includes at least one low-level period. In other words, in the data signal writing phase Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4.

[0058] The data writing phase Y1 further includes a third bias adjustment phase Y14. In the third bias adjustment phase Y14, the signal transmitted by the scanning signal line SP* includes at least one low-level period. During this period, the bias transistor T8 can be used to further adjust the bias of the second node N2.

[0059] Furthermore, if a driving cycle Y of the pixel driving circuit 100 is a low-frequency cycle, the driving cycle Y includes a data writing stage Y1, a light-emitting stage Y2 and a light-emitting maintenance stage Y3; if a driving cycle Y of the pixel driving circuit 100 is a high-frequency cycle, the driving cycle Y includes a data writing stage Y1 and a light-emitting stage Y2.

[0060] Among them, reference FIG. 15 As shown, the driving transistor T3 in the pixel circuit 100 can be understood as the driving module 101, the data writing transistor T2 can be understood as the data writing module 102, and the first terminal ( FIG. 10 and FIG. 15 102a) and the first end of the driving module 101 ( FIG. 15 and FIG. 15 101a in FIG) is electrically connected. FIG. 15 and FIG. 14As shown, the signal line 200 includes a data signal line Data, which is electrically connected to the second end of the data writing module 102 (shown as 102b in the figure), that is, the data signal line Data is connected to the input end of the data writing crystal T2, and the data signal in the data signal line Data is written into the pixel circuit 100 through the data writing transistor T2.

[0061] refer to FIG. 14 and FIG. 14 As shown, the bias adjustment transistor T8 in the pixel circuit 100 can be understood as the adjustment module 103. FIG. 15 As shown, the first end of the regulating module 103 ( FIG. 21 103a) and the first end of the driving module 101 ( FIG. 8 101a in FIG) is electrically connected. FIG. 22 As shown, the first end of the regulating module 103 ( FIG. 8 103a) can also be connected to the second end of the driving module 101 ( FIG. 23 That is, the bias transistor T8 can be electrically connected to the third node N3 (the connection node of the driving transistor T3, the second light-emitting control transistor T6, and the threshold compensation transistor T4), or it can be electrically connected to the second node N2 (the connection node of the driving transistor T3 and the data writing transistor T2). FIG. 8 and FIG. 10 As shown, the signal line 200 includes an adjustment signal line, which is electrically connected to the second end of the adjustment module 103 (shown as 103b in the figure). When the adjustment module 103 is a bias adjustment transistor T8, the adjustment signal line can be understood as a bias adjustment signal line DVH, which is electrically connected to the input end of the bias adjustment transistor T8.

[0062] refer to FIG. 14 As shown, the first light emitting control transistor T1 in the pixel circuit 100 can also be understood as the regulating module 103, wherein the first terminal ( FIG. 15 103a) and the first end of the driving module 101 ( FIG. 21 to FIG. 23 101a in FIG) is electrically connected. FIG. 21 As shown, the signal line includes an adjustment signal line, and the adjustment signal line is connected to the second end ( FIG. 10 to FIG. 15 When the adjustment module 103 is the first light-emitting control transistor T1, the adjustment signal line can be understood as the power signal line PVDD, and the power signal line PVDD is electrically connected to the input end of the first light-emitting control transistor T1.

[0063] Therefore, the setting position of the adjusting module 103 in the pixel circuit 100 is flexible, and the position thereof can be adjusted flexibly according to requirements.

[0064] Further, referring to FIG. 22 illustrated, FIG. 22 The provided nested structure diagram includes a plurality of pixel circuits 100, and the pixel circuits 100 include a first pixel circuit 100a and a second pixel circuit 100b. The first pixel circuit 100a and the second pixel circuit 100b can be electrically connected to light emitting elements 300 of different colors, respectively. The adjusting signal line includes a first adjusting signal line electrically connected to the first pixel circuit 100a and a second adjusting signal line electrically connected to the second pixel circuit 100b. As described above, the adjusting signal line can be a bias adjusting signal line DVH, that is, the first adjusting signal line is a wire electrically connected to the input end of the bias adjusting transistor T8 in the first pixel circuit 100a, and the second adjusting signal line is a wire electrically connected to the input end of the bias adjusting transistor T8 in the second pixel circuit 100b. The adjusting signal line can also be a power signal line PVDD, that is, the first adjusting signal line is a wire electrically connected to the input end of the first light emitting control transistor T1 in the first pixel circuit 100a, and the second adjusting signal line is a wire electrically connected to the input end of the first light emitting control transistor T1 in the second pixel circuit 100b. The specific type of the adjusting signal line can be adjusted differently according to different display panels 10. Further, the signal potentials in the first adjusting signal line and the second adjusting signal line are different, that is, the adjusting signal lines connected to different pixel circuits 100 in the display panel 10 can provide different electrical signals. Therefore, the potential signals provided by the adjusting signal lines electrically connected thereto can be adjusted differently according to the requirements of the pixel circuit 100. In this way, the adjusting signal line and the pixel circuit 100 can be connected adaptively to provide more adaptive adjusting signals for the pixel circuit 100, thereby reducing the overall power consumption of the display panel 10. Further, different pixel circuits 100 can be connected to light emitting elements 300 of different colors. If the same current signal is connected to the pixel circuit 100 of the light emitting element 300 of different colors, in combination with the self-light emitting power consumption of the light emitting element 300 of different colors, the display panel 10 will have a heating color deviation problem. Therefore, the adjusting signal lines connected to different pixel circuits 100 in the display panel 10 provide different electrical signals, which can also improve the heating color deviation of the display panel 10, thereby ensuring the overall display effect of the display panel 10.

[0065] Specifically, referring to FIG. 21 illustrated, the display panel 10 is provided by a plurality of film layers. FIG. 10 The film layer structure of the pixel circuit 100 illustrated in the figure can be corresponding FIG. 15A pixel circuit 100 is provided. The film layer structure of the pixel circuit 100 is arranged on one side of a substrate 400, and from the substrate 400 to the light-emitting side of the display panel 10, there can be, in sequence, a zeroth metal layer 420, a first semiconductor layer 421, a first metal layer 422, a second metal layer 423, a second semiconductor layer 424, a third metal layer 425, a first source-drain electrode layer 426, a second source-drain electrode layer 427, and a third source-drain electrode layer 428, and an insulating layer 410 arranged between the above film layers. It should be noted that, FIG. 14 In the present embodiment, the cross-sectional view of a partial structure in the pixel circuit 100 is taken as an example, and all the transistors in the pixel circuit 100 are not shown one by one. For the film layer structure of the specific pixel circuit 100, adaptive adjustments can be made according to actual needs, such as adding or removing some film layers, and any one of the above film layers can contain at least one sublayer, and the present embodiment does not make specific limitations thereon.

[0066] FIG. 22 is FIG. 23 is a structural schematic diagram of a first part in the present embodiment, FIG. 10 is FIG. 15 is a structural schematic diagram of a second part in the present embodiment, FIG. 15 is FIG. 15 is a structural schematic diagram of a third part in the present embodiment, FIG. 15 is FIG. 14 is a structural schematic diagram of a fourth part in the present embodiment, FIG. 14 is FIG. 14 is a structural schematic diagram of a fifth part in the present embodiment, FIG. 14 is FIG. 15 is a structural schematic diagram of a sixth part in the present embodiment, FIG. 15 is FIG. 15 is a structural schematic diagram of a seventh part in the present embodiment, FIG. 15 is FIG. 22 is a structural schematic diagram of an eighth part in the present embodiment, FIG. 22 is FIG. 22 is a structural schematic diagram of a ninth part in the present embodiment, FIG. 22 is FIG. 23 is a structural schematic diagram of a tenth part in the present embodiment.

[0067] In the present embodiment, FIG. 23 shows a film layer structure schematic diagram of the display panel 10 as a whole. Since the display panel 10 is arranged by overlapping multiple film layers, in order to clearly understand the specific arrangement position of the film layers, FIG. 10 , FIG. 15 , FIG. 14 The different film layers in the display panel 10 are shown one by one from the bottom to the top. Specifically, reference is made to FIG. 22The specific film layer structure of the zeroth metal layer 420, the first semiconductor layer 421, the first metal layer 422, the second metal layer 423, the second semiconductor layer 424, the third metal layer 425, the first source-drain electrode layer 426, the second source-drain electrode layer 427, the third source-drain electrode layer 428, and the anode RE in the light-emitting element 300 is shown one by one, so that the film layer relationship in the display panel 10 and the specific arrangement of the pixel circuit 100 can be more accurately understood.

[0068] Further, FIG. 23 is FIG. 10 A schematic diagram of a stack of the second to sixth portions in the display panel 10 is shown in FIG. 12, which shows the film layer arrangement positions of the transistors in the pixel circuit 100 and the connection relationship between the transistors. FIG. 15 、 FIG. 15 For example, the active layers of the first light-emitting control transistor T1, the data write transistor T2, the driving transistor T3, the second light-emitting control transistor T6, the reset transistor T7, and the bias adjustment transistor T8 are shown in FIG. 13. FIG. 15 The active layers of the first light-emitting control transistor T1, the data write transistor T2, the driving transistor T3, the second light-emitting control transistor T6, the reset transistor T7, and the bias adjustment transistor T8 are shown in FIG. 13. FIG. 15 The active layers of the first light-emitting control transistor T1, the data write transistor T2, the driving transistor T3, the second light-emitting control transistor T6, the reset transistor T7, and the bias adjustment transistor T8 are shown in FIG. 13. FIG. 14 The active layers of the threshold compensation transistor T4 and the initialization transistor T5 are shown in FIG. 14. FIG. 14 and FIG. 14 The active layers of the threshold compensation transistor T4 and the initialization transistor T5 are shown in FIG. 14. FIG. 14 and FIG. 15 The position of the capacitor substrate of the storage capacitor Cst in the pixel circuit 100 is also shown in FIG. 14. FIG. 15 The above film layers are stacked and displayed.

[0069] As described above, in the pixel circuit 100, the driving module 101 can be the driving transistor T3, and the data write module 102 can be the data write transistor T2. The film layer arrangement positions of the driving transistor T3 and the data write transistor T1, etc. can be referred to FIG. 13. FIG. 15 、 FIG. 15The signal lines 200 in the display panel 10 also include a data signal line Data, which is electrically connected to the input end of the data writing transistor T1. Since the first pixel circuit 100a and the second pixel circuit 100b are used to drive different light emitting elements 300, the data signal line Data can also include a first data signal line Data1 electrically connected to the first pixel circuit 100a and a second data signal line Data2 electrically connected to the second pixel circuit 100b. Referring to FIG. 22 、 FIG. 22 and FIG. 22 , the input end (a1 in the first pixel circuit 100a) of the data writing transistor T2 is electrically connected to the first data signal line Data1 (a2 in the third source-drain electrode layer 428) through the data signal transfer part (a5 in the first source-drain electrode layer 426) in the first pixel circuit 100a. The input end (a3 in the second pixel circuit 100b) of the data writing transistor T2 is electrically connected to the second data signal line Data2 (a4 in the third source-drain electrode layer 428) through the data signal transfer part (a6 in the first source-drain electrode layer 426) in the second pixel circuit 100b. FIG. 22 FIG. 23 FIG. 23 FIG. 23 FIG. 24 FIG. 8

[0070] As for the adjustment module 103, it has various settings. The adjustment module 103 can be a bias adjustment transistor T8, and the adjustment module 103 can also be the first light emitting control transistor T1. While the adjustment module 103 has various settings, the adjustment signal line electrically connected to the adjustment module 103 also has various settings. The adjustment signal line can be a bias adjustment signal line DVH, or the adjustment signal line can be a power supply signal line PVDD.

[0071] FIG. 25 is FIG. 8 a schematic diagram of a stack of the second to seventh parts. Referring to FIG. 22 、 FIG. 23 、 FIG. 26 and FIG. 25 , an example is given in which the adjustment module 103 is a bias adjustment transistor T8, in which case the adjustment signal line is a bias adjustment signal line DVH.

[0072] In which, referring to FIG. 27 , the bias adjustment transistor T8 in the first pixel circuit 100a and the bias adjustment transistor T8 in the second pixel circuit 100b are respectively connected to different bias adjustment signal lines DVH, and the different bias adjustment signal lines DVH transmit different potential signals. Specifically, in combination with FIG. 25 、 FIG. 28 and​​​​​​FIG. 25 As shown, the input end (indicated as b1 in the figure) of the bias adjustment transistor T8 in the first pixel circuit 100a is electrically connected with the bias adjustment adapter (indicated as b2 in the figure) of the bias adjustment signal line DVH in the first pixel circuit 100a. FIG. 29 As shown, the input end (indicated as b1 in the figure) of the bias adjustment transistor T8 in the first pixel circuit 100a is electrically connected with the bias adjustment adapter (indicated as b2 in the figure) of the bias adjustment signal line DVH in the first pixel circuit 100a. FIG. 25 As shown, the input end (indicated as b1 in the figure) of the bias adjustment transistor T8 in the first pixel circuit 100a is electrically connected with the bias adjustment adapter (indicated as b2 in the figure) of the bias adjustment signal line DVH in the first pixel circuit 100a. FIG. 8 to FIG. 29 As shown, the input end (indicated as b1 in the figure) of the bias adjustment transistor T8 in the first pixel circuit 100a is electrically connected with the bias adjustment adapter (indicated as b2 in the figure) of the bias adjustment signal line DVH in the first pixel circuit 100a. FIG. 2 As shown, the input end (indicated as b1 in the figure) of the bias adjustment transistor T8 in the first pixel circuit 100a is electrically connected with the bias adjustment adapter (indicated as b2 in the figure) of the bias adjustment signal line DVH in the first pixel circuit 100a. FIG. 3 As shown, the input end (indicated as b1 in the figure) of the bias adjustment transistor T8 in the first pixel circuit 100a is electrically connected with the bias adjustment adapter (indicated as b2 in the figure) of the bias adjustment signal line DVH in the first pixel circuit 100a. FIG. 10 As shown, the input end (indicated as b1 in the figure) of the bias adjustment transistor T8 in the first pixel circuit 100a is electrically connected with the bias adjustment adapter (indicated as b2 in the figure) of the bias adjustment signal line DVH in the first pixel circuit 100a. FIG. 14 As shown, the input end (indicated as b1 in the figure) of the bias adjustment transistor T8 in the first pixel circuit 100a is electrically connected with the bias adjustment adapter (indicated as b2 in the figure) of the bias adjustment signal line DVH in the first pixel circuit 100a. FIG. 15 , FIG. 20 and FIG. 21 As shown, the input end (indicated as b4 in the figure) of the bias adjustment transistor T8 in the second pixel circuit 100b is electrically connected with the bias adjustment adapter (indicated as b6 in the figure) of the bias adjustment signal line DVH in the second pixel circuit 100b. FIG. 22 As shown, the input end (indicated as b4 in the figure) of the bias adjustment transistor T8 in the second pixel circuit 100b is electrically connected with the bias adjustment adapter (indicated as b6 in the figure) of the bias adjustment signal line DVH in the second pixel circuit 100b. FIG. 10 As shown, the input end (indicated as b4 in the figure) of the bias adjustment transistor T8 in the second pixel circuit 100b is electrically connected with the bias adjustment adapter (indicated as b6 in the figure) of the bias adjustment signal line DVH in the second pixel circuit 100b. FIG. 14 As shown, the input end (indicated as b4 in the figure) of the bias adjustment transistor T8 in the second pixel circuit 100b is electrically connected with the bias adjustment adapter (indicated as b6 in the figure) of the bias adjustment signal line DVH in the second pixel circuit 100b. FIG. 15 As shown, the input end (indicated as b4 in the figure) of the bias adjustment transistor T8 in the second pixel circuit 100b is electrically connected with the bias adjustment adapter (indicated as b6 in the figure) of the bias adjustment signal line DVH in the second pixel circuit 100b. FIG. 20 As shown, the input end (indicated as b4 in the figure) of the bias adjustment transistor T8 in the second pixel circuit 100b is electrically connected with the bias adjustment adapter (indicated as b6 in the figure) of the bias adjustment signal line DVH in the second pixel circuit 100b. FIG. 24 As shown, the input end (indicated as b4 in the figure) of the bias adjustment transistor T8 in the second pixel circuit 100b is electrically connected with the bias adjustment adapter (indicated as b6 in the figure) of the bias adjustment signal line DVH in the second pixel circuit 100b. FIG. 10 As shown, the input end (indicated as b4 in the figure) of the bias adjustment transistor T8 in the second pixel circuit 100b is electrically connected with the bias adjustment adapter (indicated as b6 in the figure) of the bias adjustment signal line DVH in the second pixel circuit 100b. FIG. 15 and FIG. 15 As shown, the bias adjustment signal line DVH electrically connected with the first pixel circuit 100a and the bias adjustment signal line DVH electrically connected with the second pixel circuit 100b are different, and the two can transmit different potential signals. By setting different bias adjustment signal lines DVH, different bias signals can be provided to different pixel circuits 100, thereby realizing differential bias adjustment of different pixel circuits 100, and ensuring that the adjustment of the pixel circuit 100 is more reliable, improving the working effect of the pixel circuit 100, and thereby ensuring the display effect of the display panel 10.

[0073] FIG. 15 is another stack diagram of the second to ninth parts in the figure, FIG. 15 is another structure diagram of the eighth part in the figure, FIG. 14 is a structure diagram of the ninth part in the figure. Reference is made to FIG. 14 , FIG. 24 , FIG. 24 , FIG. 24 , FIG. 24 , FIG. 24 , FIG. 24As shown, to adjust the module 103 is the first light-emitting control transistor T1 is illustrated, in this case, the adjustment signal line is the power signal line PVDD.

[0074] Further, FIG. 24 is a film layer structure formed by the first semiconductor layer 421 to the third source-drain electrode layer 428 stacked of the display panel 10, wherein the first semiconductor layer 421 to the first source-drain electrode layer 426 can refer to FIG. 24 as shown, and the second source-drain electrode layer 427 can refer to FIG. 4 as shown, the third source-drain electrode layer 428 can refer to FIG. 10 as shown.

[0075] Specifically, referring to FIG. 15 as shown, the first light-emitting control transistor T1 in the first pixel circuit 100a and the first light-emitting control transistor T1 in the second pixel circuit 100b are connected to different power signal lines PVDD respectively, and the different power signal lines PVDD transmit different potential signals.

[0076] Specifically, in combination with FIG. 14 , FIG. 21 to FIG. 23 , FIG. 25 to FIG. 28 , FIG. 10 and FIG. 15 as shown, the input end of the first light-emitting control transistor T1 in the first pixel circuit 100a ( FIG. 15 shown as c1 in) is electrically connected to the power adjustment adapter of the power signal line PVDD ( FIG. 26 shown as c2 in) in FIG. 26 , and FIG. 15 the power adjustment adapter of the power signal line PVDD ( FIG. 15 shown as c2 in) is also electrically connected to the adapter ( FIG. 14 shown as c3 in) in FIG. 14 , FIG. 27 the adapter ( FIG. 27 shown as c3 in) is also electrically connected to the adapter ( FIG. 14 shown as c4 in) in FIG. 14 , FIG. 15 the adapter ( FIG. 15 shown as c4 in) is further electrically connected to the power via hole of the power adjustment structure ( FIG. 27 shown as c5 in) in FIG. 27 , FIG. 15 the power via hole of the power adjustment structure ( FIG. 15 shown as c5 in) is electrically connected to the power via hole of the power signal line PVDD ( FIG. 22 shown as c6 in) in FIG. 22 , realizing the electrical connection relationship between the power signal line PVDD and the first light-emitting control transistor T1. At the same time, in combination withFIG. 28 、 FIG. 28 、 FIG. 22 、 FIG. 22 and FIG. 23 As shown, the input terminal ( FIG. 23 c7 in the figure) and FIG. 29 Power supply regulation adapter of the power signal line PVDD ( FIG. 29 (shown as c8 in FIG) is electrically connected, and FIG. 10 Power supply regulation adapter of the power signal line PVDD ( FIG. 15 c8) also with FIG. 15 The transfer part ( FIG. 26 (shown as c9 in FIG) is electrically connected, FIG. 26 The transfer part ( FIG. 15 c9) also with FIG. 15 The transfer part ( FIG. 14 (shown as c10 in FIG) is electrically connected, FIG. 14 The transfer part ( FIG. 27 c10 in the figure) and then FIG. 27 Power vias in the power regulation structure ( FIG. 14 (shown as c11 in FIG) is electrically connected, FIG. 14 Power vias in the power regulation structure ( FIG. 15 In the figure, c11 is shown) FIG. 15 Power vias for the power signal line PVDD ( FIG. 27 (shown as c12 in FIG) to realize the electrical connection relationship between the power signal line PVDD and the first light emitting control transistor T1. FIG. 27 As shown, the power signal line PVDD electrically connected to the first pixel circuit 100a and the power signal line PVDD electrically connected to the second pixel circuit 100b are different, and the two can transmit different potential signals. By providing different power signal lines PVDD, different power signals can be provided to different pixel circuits 100. The power signal can be provided differently according to the driving requirements of the pixel circuit 100, effectively reducing the power consumption of the display panel 10, improving the operating performance of the pixel circuit 100, and thus ensuring the display effect of the display panel 10.

[0077] In summary, embodiments of the present invention provide a display panel in which adjustment signal lines connected to adjustment modules in different pixel circuits can input signals of different potentials. By differentially configuring the adjustment signal lines, the differentiated potential signal requirements of different pixel circuits can be met. Providing differentiated potentials helps reduce the overall power consumption of the display panel and ensures the display quality of the display panel.

[0078] FIG. 15 yes FIG. 15A schematic diagram of a stack of the second, sixth and seventh parts, FIG. 22 yes FIG. 22 Part II, Part IV, Part VI, Part VII and FIG. 28 Part Eight and FIG. 28 A schematic diagram of a stacking layer in the ninth part, FIG. 22 yes FIG. 22 A schematic diagram of a stack of the second and seventh parts, ​ yes ​ A schematic diagram of a stack of the sixth and seventh parts, ​ yes ​ A schematic diagram of a stack of the seventh and eighth parts, ​ yes ​ A schematic diagram of the eighth and ninth parts of the stacking, refer to ​ As shown. The regulation module 103 includes a bias regulation transistor T8; the regulation signal line includes a first bias regulation signal line DVH1 and a second bias regulation signal line DVH2, the first bias regulation signal line DVH1 is electrically connected to the second end of the bias regulation transistor T8 in the first pixel circuit 100a, the second bias regulation signal line DVH2 is electrically connected to the second end of the bias regulation transistor T8 in the second pixel circuit 100b, and the signal potentials in the first bias regulation signal line DVH1 and the second bias regulation signal line DVH2 are different; and / or, the regulation module 103 includes a first emission control transistor T1, the regulation signal line includes a first power signal line PVDD1 and a second power signal line PVDD2, the first power signal line PVDD1 is electrically connected to the second end of the first emission control transistor T1 in the first pixel circuit 100a, the second bias regulation signal line PVDD2 is electrically connected to the second end of the first emission control transistor T1 in the second pixel circuit 100b, and the signal potentials in the first power signal line PVDD1 and the second power signal line PVDD2 are different.

[0079] When the regulating module 103 includes the bias regulating transistor T8, the corresponding regulating signal line includes the bias regulating signal line DVH. ​ and ​ When the bias adjustment transistor T8 is electrically connected to the second node N2 or the third node N3, the second end of the bias adjustment transistor T8 (ie, the second end 103b of the adjustment module 103) is electrically connected to the bias adjustment signal line DVH.

[0080] refer to ​ 、 ​ 、 ​ 、 ​ 、 ​ and ​As shown, the bias adjustment signal line DVH includes a first bias adjustment signal line DVH1 and a second bias adjustment signal line DVH2, wherein the first bias adjustment signal line DVH1 is electrically connected to the bias adjustment transistor T8 in the first pixel circuit 100a, and the second bias adjustment signal line DVH2 is electrically connected to the bias adjustment transistor T8 in the second pixel circuit 100b.

[0081] Further, combined with reference ​ 、 ​ 、 ​ 、 ​ and ​ As shown, for the first pixel circuit 100a, the input terminal ( ​ b1 in the figure) and ​ The bias adjustment switching portion of the first bias adjustment signal line DVH1 ( ​ (shown as b3 in FIG) is electrically connected, ​ The bias adjustment switching portion of the first bias adjustment signal line DVH1 ( ​ b3 in the figure) and ​ The bias via of the first bias adjustment signal line DVH1 in ​ For the first pixel circuit 100a, the stacking relationship of the bias adjustment transistor T8 and the first bias adjustment signal line DVH1 on the film layer can refer to ​ ( ​ Similarly, in the second pixel circuit 100b, the stacking relationship of the bias adjustment transistor T8 and the second bias adjustment signal line DVH2 on the film layer can be referred to. ​ ( ​ The area indicated by mark d2).

[0082] Optional, reference ​ As shown, the first pixel circuit 100a and the second pixel circuit 100b are connected to the first bias adjustment signal line DVH1 and the second bias adjustment signal line DVH2, respectively. That is, different pixel circuits 100 can be independently provided with bias adjustment signal lines DVH. ​As shown, the pixel circuit 100 in the display panel 10 may further include a third pixel circuit 100c and a fourth pixel circuit 100d, wherein along the extension direction of the scanning signal line, the first pixel circuit 100a, the second pixel circuit 100b, the third pixel circuit 100c and the fourth pixel circuit 100d constitute a minimum repetition period of the pixel circuit 100. The first pixel circuit 100a is electrically connected to the first bias adjustment signal line DVH1, the second pixel circuit 100b is electrically connected to the second bias adjustment signal line DVH2, and the bias adjustment transistor T8 in the third pixel circuit 100c is also electrically connected to the second bias adjustment signal line DVH2 ( ​ The fourth pixel circuit 100d is also electrically connected to the second bias adjustment signal line DVH2 ( ​ In other words, based on the bias signal requirements of different pixel circuits 100, at least some of the pixel circuits 100 can be electrically connected to different bias adjustment signal lines DVH, thereby reducing the overall power consumption of the display panel 10. If the bias signal requirements of some pixel circuits 100 vary slightly, these pixel circuits 100 can be connected to the same bias adjustment signal line DVH, thereby reducing the difficulty of wiring configuration of the display panel 10.

[0083] When the regulating module 103 includes the first light emitting control transistor T1, the corresponding regulating signal line includes the power signal line PVDD. ​ When , the second end of the first light emitting control transistor T1 (ie, the second end 103b of the regulating module 103) is electrically connected to the power signal line PVDD.

[0084] Further, combined ​ 、 ​ 、 ​ 、 ​ 、 ​ As shown, for the input terminal ( ​ Indicated by c1) and ​ Power supply regulation adapter of the power signal line PVDD ( ​ The specific relationship between the film layers of the electrical connection can be referred to ​ As shown ( ​ The area indicated by mark e1). ​ Power supply regulation adapter of the power signal line PVDD ( ​ c2 in the figure) and ​ The transfer part ( ​ The specific relationship between the film layers of the electrical connection can be referred to ​ As shown ( ​ The area indicated by mark e3).​ The transfer part ( ​ c3) also with ​ The transfer part ( ​ The specific relationship between the layers of the electrical connection can be referred to ​ As shown ( ​ (the area indicated by mark e4 in the figure). ​ The transfer part ( ​ c4 in the figure) and then ​ Power vias in the power regulation structure ( ​ The specific relationship between the layers of the electrical connection can be referred to ​ As shown ( ​ The area indicated by mark e7 in the figure). ​ Power vias in the power regulation structure ( ​ In the figure, c5 is shown) ​ Power vias for the power signal line PVDD ( ​ The specific relationship between the film layers of the electrical connection can be referred to ​ As shown ( ​ Similarly, the input terminal ( ​ c7 in the figure) and ​ Power supply regulation adapter of the power signal line PVDD ( ​ The specific relationship between the layers of the electrical connection can be referred to ​ As shown ( ​ The area indicated by mark e2). ​ Power supply regulation adapter of the power signal line PVDD ( ​ c8) also with ​ The transfer part ( ​ The specific relationship between the film layers of the electrical connection can be referred to ​ As shown ( ​ The area indicated by mark e5 in the figure). ​ The transfer part ( ​ c9) also with ​ The transfer part ( ​ The specific relationship between the film layers of the electrical connection can be referred to ​ As shown ( ​ (the area indicated by mark e6 in the figure). ​ The transfer part ( ​ c10 in the figure) and then ​ Power vias in the power regulation structure ( ​ The specific relationship between the layers of the electrical connection can be found in​ As shown ( ​ The area indicated by mark e8). ​ Power vias in the power regulation structure ( ​ In the figure, c11 is shown) Figure 23 Power vias for the power signal line PVDD ( Figure 23 The specific relationship between the film layers of the electrical connection can be referred to Figure 29 As shown ( Figure 29 (the area indicated by mark e10 in the figure).

[0085] Optional, reference Figures 25 to 29 As shown, the first pixel circuit 100a and the second pixel circuit 100b are connected to the first power signal line PVDD1 and the second power signal line PVDD2 respectively, that is, different pixel circuits 100 can be independently provided with power signal lines PVDD. Figures 25 to 29 As shown, the pixel circuit 100 in the display panel 10 may further include a third pixel circuit 100c and a fourth pixel circuit 100d, wherein along the extension direction of the scanning signal line, the first pixel circuit 100a, the second pixel circuit 100b, the third pixel circuit 100c, and the fourth pixel circuit 100d constitute a minimum repetition period of a pixel circuit 100. The first pixel circuit 100a is electrically connected to the first power signal line PVDD1, the second pixel circuit 100b is electrically connected to the second power signal line PVDD2, and the third power signal line PVDD3 electrically connected to the third pixel circuit 100c is electrically connected to the second power signal line PVDD2. In other words, based on the different power signal requirements of different pixel circuits 100, at least some of the pixel circuits 100 can be adjusted to be electrically connected to different power signal lines PVDD, thereby reducing the overall power consumption of the display panel 10. If the power signal requirements of some pixel circuits 100 vary slightly, these pixel circuits 100 can be connected to the same power signal line PVDD, thereby reducing the difficulty of wiring configuration of the display panel 10.

[0086] Furthermore, the adjustment module 103 may also include a bias adjustment transistor T8 and a first light-emitting control transistor. The corresponding adjustment signal lines may then include a bias adjustment signal line DVH and a power signal line PVDD. In this case, in addition to different bias adjustment signal lines DVH electrically connected to different pixel circuits 100 having their potentials differentiated, different PVDDs electrically connected to different pixel circuits 100 also have their potentials differentiated. This allows the display panel 10 to further reduce power consumption.

[0087] Combine Figure 14 、 Figure 15 、 Figure 22 and Figure 23As shown, the first adjustment signal line (the first bias adjustment signal line DVH1 or the first power signal line PVDD1) includes a first adjustment sub-portion and a second adjustment sub-portion which are disposed in different layers and electrically connected; the first adjustment sub-portion extends along a first direction X1, the second adjustment sub-portion extends along a second direction X2, and the first direction X1 and the second direction X2 intersect; and / or, the second adjustment signal line (the second bias adjustment signal line DVH2 or the second power signal line PVDD2) includes a third adjustment sub-portion and a fourth adjustment sub-portion which are disposed in different layers and electrically connected, the third adjustment sub-portion extends along the first direction X1, and the fourth adjustment sub-portion extends along the second direction X2.

[0088] In the adjustment signal line, the bias adjustment signal line DVH and the power signal line PVDD can be used, and at least part of the lines in the bias adjustment signal line DVH and / or the power signal line PVDD can be arranged in a "mesh" manner, so as to reduce the resistance of the signal line and ensure the stability and reliability of the signal transmission on the signal line. Further, at least part of the lines in the first adjustment signal line and / or the second adjustment signal line connecting different pixel circuits 100 can be arranged in a "mesh" manner.

[0089] Specifically, taking the bias adjustment signal line DVH as an example, referring to Figure 14 and Figure 15 As shown, the first bias adjustment signal line DVH1 includes a first adjustment sub-portion DVH1a and a second adjustment sub-portion DVH1b, the first adjustment sub-portion DVH1a of the bias adjustment signal line DVH is disposed in the film layer where the third metal layer 425 is located, and the second adjustment sub-portion DVH1b of the bias adjustment signal line DVH is disposed in the film layer where the fourth metal layer 426 is located, so that the first adjustment sub-portion DVH1a and the second adjustment sub-portion DVH1b which both transmit the bias adjustment signal are disposed in different layers and have different extension directions. Referring to Figure 14 and Figure 15 As shown, the first adjustment sub-portion DVH1a and the second adjustment sub-portion DVH1b which both transmit the bias adjustment signal are also electrically connected through the bias adjustment adapter (b3 shown in Figure 15 ), so that the bias adjustment signal line DVH which is electrically connected to the first pixel circuit 100a is a line arranged in a "mesh" manner, and the reliability of the signal transmission is ensured. Alternatively, referring to Figure 14 and Figure 15As shown, the second bias adjustment signal line DVH2 can also include a first adjustment section DVH2a and a second adjustment section DVH2b. The bias adjustment signal line DVH electrically connected to the second pixel circuit 100b is a "grid" arranged trace, ensuring the reliability of signal transmission. Alternatively, the bias adjustment signal line DVH electrically connected to the first pixel circuit 100a is a "grid" arranged trace, and the bias adjustment signal line DVH electrically connected to the second pixel circuit 100b is also a "grid" arranged trace.

[0090] Specifically, taking the adjustment signal line as an example of the power supply signal line PVDD, it can be referred to Figure 22 and Figure 23 As shown, the first power supply signal line PVDD1 includes a first adjustment section PVDD1a and a second adjustment section PVDD1b. The first adjustment section PVDD1a of the power supply signal line PVDD is arranged in the film layer where the second source-drain electrode layer 427 is located, and the second adjustment section PVDD1b of the power supply signal line PVDD is arranged in the film layer where the third source-drain electrode layer 428 is located. In this way, the first adjustment section DVH1a and the second adjustment section DVH1b of the power supply signal line PVDD are arranged in different layers and have different extension directions. It can be referred to Figure 22 and Figure 23 As shown, the first adjustment section PVDD1a and the second adjustment section PVDD1b of the power supply signal line PVDD are electrically connected through the cross-layer electrical connection part 500, so that the power supply signal line PVDD electrically connected to the first pixel circuit 100a is a "grid" arranged trace, ensuring the reliability of signal transmission. Alternatively, it can be referred to Figure 22 and Figure 23 As shown, the second power supply signal line PVDD2 can also include a first adjustment section PVDD2a and a second adjustment section PVDD2b. The power supply signal line PVDD electrically connected to the second pixel circuit 100b can also be a "grid" arranged trace, ensuring the reliability of signal transmission. Alternatively, the power supply signal line PVDD electrically connected to the first pixel circuit 100a is a "grid" arranged trace, and the power supply signal line PVDD electrically connected to the second pixel circuit 100b can also be a "grid" arranged trace.

[0091] As shown in Figure 14 and Figure 15 The adjustment module 103 includes a bias adjustment transistor T8, the first adjustment section DVH1a and the third adjustment section DVH2a are arranged along the second direction X2, and the second adjustment section DVH1b and the fourth adjustment section DVH2b are arranged along the first direction X1.

[0092] Further, it can be referred to Figure 2 and Figure 3As shown, the regulating module 103 includes a bias regulating transistor T8, and the regulating signal line electrically connected to the regulating module 103 includes a bias regulating signal line DVH. Figure 14 and Figure 15 As shown, the first regulating sub-section DVH1a, the second regulating sub-section DVH1b, the third regulating sub-section DVH2a and the fourth regulating sub-section DVH2b all transmit the bias signal of the bias regulating signal line DVH.

[0093] Among them, reference Figure 14 As shown, the first regulating sub-section DVH1a is biased via ( Figure 14 b2 in the figure) is electrically connected to the first pixel circuit 100a, and the third adjustment sub-unit DVH2a is connected to the first pixel circuit 100a through the bias via ( Figure 14 The first adjustment sub-unit DVH1a and the third adjustment sub-unit DVH2a are arranged along the second direction X2, so that the arrangement of the different bias adjustment signal lines DVH is relatively regular and convenient for electrical connection with different pixel circuits 100.

[0094] For further reference, Figure 15 As shown, the second adjustment sub-section DVH1b and the bias adjustment adapter ( Figure 15 b3 in the figure) is electrically connected, and the bias adjustment adapter ( Figure 15 The fourth regulating sub-section DVH2b is electrically connected to the bias regulating adapter ( Figure 15 ), and the bias adjustment adapter ( Figure 15 The second and fourth adjustment sub-sections DVH1b and DVH2b are arranged along the first direction X1, so that the different bias adjustment signal lines DVH can be arranged regularly in the display panel 10.

[0095] In general, the first adjustment section DVH1a, the second adjustment section DVH1b, the third adjustment section DVH2a and the fourth adjustment section DVH2b all transmit bias adjustment signal lines DVH and are arranged evenly and regularly. While ensuring electrical connection, the process preparation cost of the display panel 10 can also be reduced.

[0096] refer to Figure 22 and Figure 23 The regulating module 103 includes a first light emitting control transistor T1; a first regulating sub-section PVDD1a and a third regulating sub-section PVDD2a arranged along a first direction X1; and a second regulating sub-section PVDD1b and a fourth regulating sub-section PVDD2b arranged along the first direction X1.

[0097] Further, referring to Figure 4 illustrated, the adjusting module 103 includes a first light-emitting control transistor T1, and the adjusting signal line electrically connected with the adjusting module 103 includes a power supply signal line PVDD. Therefore, in combination with Figure 22 and Figure 23 , the first adjusting sub-part PVDD1a, the second adjusting sub-part PVDD1b, the third adjusting sub-part PVDD2a and the fourth adjusting sub-part PVDD2b all transmit the power supply signal of the power supply signal line PVDD.

[0098] Wherein, referring to Figure 22 illustrated, the first adjusting sub-part PVDD1a is electrically connected with the second adjusting sub-part PVDD1b arranged in different layers through a corresponding power supply connecting part 500, and the third adjusting sub-part PVDD2a is also electrically connected with the fourth adjusting sub-part PVDD2b arranged in different layers through a corresponding power supply connecting part 500. Referring to Figure 22 illustrated, the first adjusting sub-part PVDD1a and the third adjusting sub-part PVDD2a are arranged along the first direction X1, so that the arrangement mode of different power supply signal lines PVDD is more regular, and it is also convenient to be electrically connected with different pixel circuits 100. Further, referring to Figure 23 illustrated, the second adjusting sub-part PVDD1b and the fourth adjusting sub-part PVDD2b are arranged along the first direction X1, so that different power supply signal lines PVDD can be regularly arranged in the display panel 10.

[0099] In general, the first adjusting sub-part PVDD1a, the second adjusting sub-part PVDD1b, the third adjusting sub-part PVDD2a and the fourth adjusting sub-part PVDD2b all transmit the power supply signal line PVDD, and are regularly arranged, and in the case of ensuring the electrical connection relationship, the process preparation cost of the display panel 10 can also be reduced.

[0100] Referring to Figure 1 , Figure 8 , Figures 14 to 18 , Figure 22 and Figure 23 illustrated, the display panel 10 further includes a light-emitting element 300, the light-emitting element 300 is electrically connected with the pixel circuit 100; the light-emitting element 300 includes a first color light-emitting element 301 and a second color light-emitting element 302, the first color light-emitting element 301 is electrically connected with the first pixel circuit 100a, and the second color light-emitting element 302 is electrically connected with the second pixel circuit 100b; the light-emitting efficiency of the first color light-emitting element 301 is less than the light-emitting efficiency of the second color light-emitting element 302; the distribution density of the second adjusting sub-part is greater than the distribution density of the fourth adjusting sub-part.

[0101] Wherein, referring to Figure 1As shown, the display panel 10 comprises a plurality of light emitting elements 300, the light emitting elements 300 are electrically connected with the pixel circuits 100, the pixel circuits 100 drive the light emitting elements 300 to emit light for display. Further, the light emitting elements 300 comprise first color light emitting elements 301 and second color light emitting elements 302, the light emitting colors of the first color light emitting elements 301 and the second color light emitting elements 302 are different, so as to realize the color display effect of the display panel 10.

[0102] Further, referring to Figures 9 to 18 As shown, the first color light emitting elements 301 are electrically connected with the first pixel circuits 100a, for details, referring to Figure 18 As shown Figure 18 The anode RE of the light emitting element 300 is shown, the first color light emitting elements 301 are electrically connected with the first pixel circuits 100a through the first anode connecting parts 601. Figure 15 The first anode connecting parts 601 are electrically connected with the first anode switching parts 602 in the first pixel circuits 100a, so as to realize the electrical connection between the first color light emitting elements 301 and the first pixel circuits 100a. Similarly, referring to Figures 9 to 18 As shown, the second color light emitting elements 302 are electrically connected with the second pixel circuits 100b, for details, referring to Figure 18 As shown, the second color light emitting elements 302 are electrically connected with the second pixel circuits 100b through the second anode connecting parts 603. Figure 15 The second anode connecting parts 603 are electrically connected with the second anode switching parts 604 in the second pixel circuits 100b, so as to realize the electrical connection between the second color light emitting elements 302 and the second pixel circuits 100b.

[0103] Optionally, the light emitting elements 300 further comprise third color light emitting elements 303, the pixel circuits 100 comprise third pixel circuits 100c, wherein the third color light emitting elements 303 are electrically connected with the third pixel circuits 100c. For details, referring to Figure 18 As shown, the third color light emitting elements 303 are electrically connected with the third pixel circuits 100c through the third anode connecting parts 605. Figure 15 The third anode connecting parts 605 are electrically connected with the third anode switching parts 606 in the third pixel circuits 100c, so as to realize the electrical connection between the third color light emitting elements 303 and the third pixel circuits 100c.

[0104] The light emitting efficiency of the first color light emitting elements 301 is less than the light emitting efficiency of the second color light emitting elements 302, for example, the first color light emitting elements 301 can emit blue light, and the second color light emitting elements 302 can emit red light or green light. In order to balance the overall display effect of the display panel 10, the distribution density of the second adjusting parts can be set to be greater than the distribution density of the fourth adjusting parts.

[0105] For details, referring to Figure 14 and Figure 15As shown, when the adjustment signal line is the bias adjustment signal line DVH, the second adjustment sub-section DVH1b is electrically connected to the bias adjustment transistor T8 in the first pixel circuit 100a, that is, the signal input into the second adjustment sub-section DVH1b is used to drive the first color light emitting element 301 to emit light. The fourth adjustment sub-section DVH2b is electrically connected to the bias adjustment transistor T8 in the second pixel circuit 100b, that is, the signal input into the fourth adjustment sub-section DVH2b is used to drive the second color light emitting element 302 to emit light. Since the luminous efficiency of the first color light emitting element 301 is lower than the luminous efficiency of the second color light emitting element 302, the distribution density of the second adjustment sub-section DVH1b is adjusted to be greater than the distribution density of the fourth adjustment sub-section DVH2b. Combined Figure 15 As shown, along the second direction X2, the number of the second adjusting sections DVH1b is greater than the number of the fourth adjusting sections DVH2b.

[0106] refer to Figures 2 to 4 、 Figure 15 As shown, the pixel circuit 100 also includes an anode reset module 104, a first end of the anode reset module 104 is electrically connected to the anode of the light-emitting element 300; the signal line 200 also includes an anode reset signal line VREF2, the anode reset signal line VREF2 is electrically connected to the second end of the anode reset module 104; the anode reset signal line VREF2 includes a first anode reset sub-portion VREF2a extending along the second direction X2; the second adjustment sub-portion DVH1b, the fourth adjustment sub-portion DVH2b and the first anode reset sub-portion VREF2a are arranged along the first direction X1.

[0107] For further reference, Figures 2 to 4 As shown, the pixel circuit 100 further includes an anode reset module 104. The first terminal ( Figures 2 to 4 104a in FIG) is electrically connected to the anode of the light emitting element 300, and the anode reset signal line VREF2 is electrically connected to the second end of the anode reset module 104 ( Figures 2 to 4 The anode reset module 104 includes an anode reset transistor T7. When the anode reset transistor T7 is turned on, the reset signal transmitted in the anode reset signal line VREF2 resets the anode of the light emitting element 300.

[0108] For further reference, Figure 10 and Figure 15 As shown, the anode reset signal line VREF2 includes a first anode reset sub-portion VREF2a extending along the second direction X2, the first anode reset sub-portion VREF2a is electrically connected to the first reset via 702 through the first reset connection portion 701, and the first reset via 702 is electrically connected to the input terminal of the anode reset transistor T7 (reference Figure 10The middle 703 is electrically connected, so as to realize the electrical connection relationship between the anode reset signal line VREF2 and the anode reset transistor T7.

[0109] Further, the second adjusting part DVH1b, the fourth adjusting part DVH2b and the first anode reset part VREF2a all extend along the second direction X2, and the second adjusting part DVH1b, the fourth adjusting part DVH2b and the first anode reset part VREF2a are all located at the film layer where the first source-drain electrode layer 426 is located. In this way, the second adjusting part DVH1b, the fourth adjusting part DVH2b and the first anode reset part VREF2a are arranged along the first direction X1, as shown in the reference Figure 15 As shown, the arrangement mode can be: the second adjusting part DVH1b, the fourth adjusting part DVH2b, the second adjusting part DVH1b and the first anode reset part VREF2a. In the case of ensuring that the number of the second adjusting part DVH1b is greater than the number of the fourth adjusting part DVH2b, all signal lines extending along the second direction X2 can also be arranged and set, which reflects the reasonable design of the display panel 10 on the space wiring.

[0110] Reference Figure 12 and Figure 15 As shown, the anode reset signal line VREF2 further includes a second anode reset part VREF2b extending along the first direction X1, and the second anode reset part VREF2b is arranged in a layer different from the first anode reset part VREF2a and is electrically connected.

[0111] Further, as shown in the reference Figure 12 As shown, the anode reset signal line VREF2 further includes a second anode reset part VREF2b extending along the first direction X1, and the second anode reset part VREF2b is electrically connected with the first anode reset part VREF2a, and both of them jointly transmit the reset signal provided by the anode reset signal line VREF2. As shown in the reference Figure 12 As shown, the second anode reset part VREF2b extends along the second direction X2 and is arranged at the film layer where the second metal layer 423 is located, and as shown in the reference Figure 15 As shown, the first anode reset part VREF2a extends along the first direction X1 and is arranged at the film layer where the first source-drain metal layer 426 is located. That is, the two routing parts of the anode reset signal line VREF2 are arranged at different film layers, and the extension directions of the two routing parts are different. By arranging the anode reset signal line VREF2 as a "grid" routing, the resistance on the signal line can be reduced, and the stability and reliability of the signal transmission on the anode reset signal line VREF2 can be ensured.

[0112] Reference Figure 22 and Figure 23As shown, the display panel 10 further comprises an additional adjusting structure 800, the additional adjusting structure 800 comprising a first additional adjusting part 810 and a second additional adjusting part 820; the first additional adjusting part 810 is electrically connected with the second adjusting part, and the second additional adjusting part 820 is electrically connected with the fourth adjusting part.

[0113] Further, the display panel 10 comprises the additional adjusting structure 800, the additional adjusting structure 800 being used for electrically connecting the adjusting signal lines arranged in different film layers, so as to ensure stable transmission of the adjusting signal lines. Wherein, the additional adjusting structure 800 comprises the first additional adjusting part 810 and the second additional adjusting part 820, the first additional adjusting part 810 being electrically connected with the second adjusting part in the first pixel circuit 100a, and the second additional adjusting part 820 being electrically connected with the fourth adjusting part in the second pixel circuit 100b.

[0114] For example, as shown in FIG. 1 and FIG. 2, the display panel 10 comprises a plurality of pixel circuits 100, and each pixel circuit 100 comprises a first pixel circuit 100a and a second pixel circuit 100b. Figure 22 and Figure 23 For example, as shown in FIG. 1 and FIG. 2, the display panel 10 comprises a plurality of pixel circuits 100, and each pixel circuit 100 comprises a first pixel circuit 100a and a second pixel circuit 100b. Figure 23 For example, as shown in FIG. 1 and FIG. 2, the display panel 10 comprises a plurality of pixel circuits 100, and each pixel circuit 100 comprises a first pixel circuit 100a and a second pixel circuit 100b. Figure 23 For example, as shown in FIG. 1 and FIG. 2, the display panel 10 comprises a plurality of pixel circuits 100, and each pixel circuit 100 comprises a first pixel circuit 100a and a second pixel circuit 100b.

[0115] Further, the adjusting signal line can also be a bias adjusting signal line DVH, in this case (not shown in the figure) the first additional adjusting part 810 is electrically connected with the second adjusting part DVH1b in the first pixel circuit 100a, and the second additional adjusting part 820 is electrically connected with the fourth adjusting part DVH2b in the second pixel circuit 100b.

[0116] In this way, the display panel 10 ensures that the connection of each wire is more stable and reliable by setting the additional adjusting structure 800, thereby embodying the display effect of the display panel 10.

[0117] For example, as shown in FIG. 1 and FIG. 2, the display panel 10 comprises a plurality of pixel circuits 100, and each pixel circuit 100 comprises a first pixel circuit 100a and a second pixel circuit 100b. Figure 22 For example, as shown in FIG. 1 and FIG. 2, the display panel 10 comprises a plurality of pixel circuits 100, and each pixel circuit 100 comprises a first pixel circuit 100a and a second pixel circuit 100b.

[0118] Further, for example, as shown in FIG. 1 and FIG. 2, the display panel 10 comprises a plurality of pixel circuits 100, and each pixel circuit 100 comprises a first pixel circuit 100a and a second pixel circuit 100b. Figure 22As shown, the first additional adjusting part 810 and the second additional adjusting part 820 are respectively used for electrical connection with the partial adjusting signal line, and are arranged in the same layer. In the case of not affecting the required electrical connection relationship, the film layer quantity of the display panel 10 can also be effectively reduced, which is beneficial to realize the thin design of the display panel 10. Moreover, the first additional adjusting part 810 and the second additional adjusting part 820 are arranged in the same layer, and can be prepared synchronously in the process preparation process of the display panel 10, thereby reducing the process cost of the display panel 10.

[0119] Reference Figures 2 to 18 As shown, the display panel 10 further includes a substrate 400; the pixel circuit 100 includes at least one first type transistor 110 and at least one second type transistor 120, the first type transistor 110 includes a first active layer POLY and a first gate M1, and the second type transistor 120 includes a second active layer IGZO, a second top gate MG and a second bottom gate MC. The first gate M1 is located on the side of the first active layer POLY close to the substrate 400 or on the side of the first active layer POLY away from the substrate 400. The second top gate MC is located on the side of the second active layer IGZO away from the substrate 400, and the second bottom gate MC is located on the side of the second active layer IGZO close to the substrate 400. The display panel 10 further includes a zeroth metal layer 420, a first semiconductor layer 421, a first metal layer 422, a second metal layer 423, a second semiconductor layer 424, a third metal layer 425, a first source-drain electrode layer 426, a second source-drain electrode layer 427 and a third source-drain electrode layer 428. The zeroth metal layer 420 is located on the side of the first active layer POLY close to the substrate 400. The first active layer POLY is located on the first semiconductor layer 421. The first gate M1 is located on the first metal layer 422. The second bottom gate MC is located on the second metal layer 423. The second active layer IGZO is located on the second semiconductor layer 424. The second top gate MC is located on the third metal layer 425. The first source-drain electrode layer 426 is located on the side of the third metal layer 425 away from the substrate 400. The second source-drain electrode layer 427 is located on the side of the first source-drain electrode layer 426 away from the substrate 400. The third source-drain electrode layer 428 is located on the side of the second source-drain electrode layer 427 away from the substrate 400. The first adjusting part is located in at least one of the zeroth metal layer 420, the first metal layer 422, the second metal layer 423, the third metal layer 425 and the second source-drain electrode layer 427. The second adjusting part is located in the first source-drain electrode layer 426 or the third source-drain electrode layer 428. The third adjusting part is located in at least one of the zeroth metal layer 420, the first metal layer 422, the second metal layer 423, the third metal layer 425 and the second source-drain electrode layer 427. The fourth adjusting part is located in the first source-drain electrode layer 426 or the third source-drain electrode layer 428.

[0120] Among them, reference Figure 7 As shown, the pixel circuit 100 includes a first-type transistor 110 and a second-type transistor 120. The first-type transistor 110 includes a first active layer POLY, and the second-type transistor 120 includes a second active layer IGZO. The first active layer POLY may include a silicon semiconductor, and the second active layer IGZO may include an oxide semiconductor. Further, the first-type transistor 110 includes a first gate M1. The first gate M1 is located on a side of the first active layer POLY close to the substrate 400 or on a side of the first active layer POLY away from the substrate 400. Figure 7 The second type transistor 120 further includes a second top gate MG and a second bottom gate MC. Figure 7 As shown, the second top gate MC is located on a side of the second active layer IGZO away from the substrate 400 , and the second bottom gate MC is located on a side of the second active layer IGZO close to the substrate 400 .

[0121] For example, combined Figures 2 to 18 As shown, the first type transistor 110 includes a first light emission control transistor T1, a driving transistor T3, a data writing transistor T2, a second light emission control transistor T6, a reset transistor T7 and a bias adjustment transistor T8, and the second type transistor 10 includes an initialization transistor T5 and a threshold compensation transistor T4.

[0122] Specific, combined Figure 6 and Figure 7 As shown, the display panel 10 further includes a zero metal layer 420, a first semiconductor layer 421, a first metal layer 422, a second metal layer 423, a second semiconductor layer 424, a third metal layer 425, a first source-drain electrode layer 426, a second source-drain electrode layer 427, and a third source-drain electrode layer 428 stacked on one side of the substrate 400. Figures 6 to 18 As shown, the first active layer POLY can be located in the film layer where the first semiconductor layer 421 is located, the first gate M1 can be located in the film layer where the first metal layer 422 is located, the second active layer IGZO can be located in the film layer where the second semiconductor layer 424 is located, the second top gate MG can be located in the film layer where the third metal layer 425 is located, and the second bottom gate MC can be located in the film layer where the second metal layer 423 is located. Furthermore, the display panel 10 also includes a light shielding layer M0, and the light shielding layer M0 can be located in the module where the zeroth metal layer 420 is located. Among them, the first source and drain electrode layer 426 can also be understood as the M2 layer in the display panel 10, the second source and drain electrode layer 427 can also be understood as the M3 layer in the display panel 10, and the third source and drain electrode layer 428 can also be understood as the M4 layer in the display panel 10. Reference Figure 6 and Figure 7As shown, the first capacitor substrate Cst1 in the storage capacitor Cst in the pixel circuit 100 is located in the film layer where the first metal layer 422 is located, and the second capacitor substrate Cst2 is located in the film layer where the second metal layer 423 is located. Further, referring to Figures 2 to 7 As shown, the anode RE in the light emitting element 300 is located in the anode electrode layer 429, and the anode electrode layer 429 is located in the film layer where the third source-drain electrode layer 428 is located away from the substrate 400.

[0123] Further, the first adjustment sub-portion and the third adjustment sub-portion are located in at least one of the zeroth metal layer 420, the first metal layer 422, the second metal layer 423, the third metal layer 425, and the second source-drain electrode layer 427, so that the setting positions of the first adjustment sub-portion and the second adjustment sub-portion are flexible. For example, referring to Figure 14 As shown, taking the adjustment signal line as the bias adjustment signal line DVH as an example, the first adjustment sub-portion DVH1a and the second adjustment sub-portion DVH2a are both located in the film layer where the third metal layer 425 is located. For example, referring to Figure 22 As shown, taking the adjustment signal line as the power supply signal line PVDD as an example, the first adjustment sub-portion PVDD1a and the second adjustment sub-portion PVDD2a are both located in the film layer where the second source-drain electrode layer 427 is located.

[0124] Further, the second adjustment sub-portion and the fourth adjustment sub-portion are located in the first source-drain electrode layer 426 or the third source-drain electrode layer 428, so that the setting positions of the second adjustment sub-portion and the fourth adjustment sub-portion are flexible. For example, referring to Figure 15 As shown, taking the adjustment signal line as the bias adjustment signal line DVH as an example, the second adjustment sub-portion DVH1b and the fourth adjustment sub-portion DVH2b are both located in the film layer where the first source-drain electrode layer 426 is located. For example, referring to Figure 22 As shown, taking the adjustment signal line as the power supply signal line PVDD as an example, the second adjustment sub-portion PVDD1b and the fourth adjustment sub-portion PVDD2b are both located in the film layer where the third source-drain electrode layer 428 is located.

[0125] It should be noted that, Figures 2 to 18 As shown, all the examples are explained taking the pixel circuit 100 including both the first type transistor 110 and the second type transistor 120 as an example. The pixel circuit 100 in the display panel 10 can also include only the first type transistor 110, or only the second type transistor 120. Further, referring to Figure 5 , Figure 6 , Figures 15 to 17As shown, the display panel 10 includes the first source-drain electrode layer 426, the second source-drain electrode layer 427, and the third source-drain electrode layer 428, that is, the display panel 10 includes three source-drain electrode layers. In other types of display panels 10, two source-drain electrode layers can also be included. The specific film layer arrangement of the display panel 10 can be adaptively adjusted according to actual needs.

[0126] The first adjustment subpart and the third adjustment subpart are arranged in the same layer, and the second adjustment subpart and the fourth adjustment subpart are arranged in the same layer.

[0127] As shown above, the first adjustment subpart and the third adjustment subpart are located in at least one of the zeroth metal layer 420, the first metal layer 422, the second metal layer 423, the third metal layer 425, and the second source-drain electrode layer 427. Among them, referring to Figure 14 As shown, taking the bias adjustment signal line DVH as an example, the first adjustment subpart DVH1a and the second adjustment subpart DVH2a are both located in the film layer where the third metal layer 425 is located. In this way, the arrangement of the first adjustment subpart DVH1a and the second adjustment subpart DVH2a can reduce the overall film layer thickness of the display panel 10, and the first adjustment subpart DVH1a and the second adjustment subpart DVH2a can also be prepared synchronously, reducing the process preparation cost of the display panel 10. Further, referring to Figure 22 As shown, taking the bias adjustment signal line DVH as an example, the first adjustment subpart DVH1a and the second adjustment subpart DVH2a are both located in the film layer where the third metal layer 425 is located. In this way, the arrangement of the first adjustment subpart DVH1a and the second adjustment subpart DVH2a can reduce the overall film layer thickness of the display panel 10, and the first adjustment subpart DVH1a and the second adjustment subpart DVH2a can also be prepared synchronously, reducing the process preparation cost of the display panel 10. Further, referring to

[0128] Further, the second adjustment subpart and the fourth adjustment subpart are located in the first source-drain electrode layer 426 or the third source-drain electrode layer 428. Among them, referring to Figure 15 As shown, taking the bias adjustment signal line DVH as an example, the first adjustment subpart DVH1a and the second adjustment subpart DVH2a are both located in the film layer where the third metal layer 425 is located. In this way, the arrangement of the first adjustment subpart DVH1a and the second adjustment subpart DVH2a can reduce the overall film layer thickness of the display panel 10, and the first adjustment subpart DVH1a and the second adjustment subpart DVH2a can also be prepared synchronously, reducing the process preparation cost of the display panel 10. Further, referring to Figure 22As shown, taking the adjustment signal line as the power signal line PVDD as an example, the second adjustment sub-portion PVDD1b and the fourth adjustment sub-portion PVDD2b are located in the film layer where the third source-drain electrode layer 428 is located. In this way, the arrangement of the second adjustment sub-portion PVDD1b and the fourth adjustment sub-portion PVDD2b can reduce the overall film layer thickness of the display panel 10, and the second adjustment sub-portion PVDD1b and the fourth adjustment sub-portion PVDD2b can also be prepared synchronously, thereby reducing the process preparation cost of the display panel 10

[0129] Referring to Figures 1 to 18 As shown, the display panel 10 further includes a plurality of sub-pixels 700; the signal line 200 includes a plurality of data signal lines Data, the plurality of data signal lines Data are arranged along a first direction X1 and extend along a second direction X2, the first direction X1 and the second direction X2 intersect; the same data signal line Data is electrically connected with a plurality of sub-pixels 700 of the same light-emitting color arranged along the second direction X2.

[0130] Referring to Figure 1 As shown, the display panel 10 further includes a plurality of sub-pixels 700, and the signal line 200 includes a plurality of data signal lines Data arranged along the first direction X1, wherein the data signal line Data is electrically connected with the pixel circuit 100 in the sub-pixel 700.

[0131] Further, the same data signal line Dta in the display panel 10 is electrically connected with a plurality of sub-pixels 700 of the same light-emitting color arranged along the second direction X2. That is, the sub-pixels 700 of the same light-emitting color are connected to the same data signal, and the sub-pixels 700 of different light-emitting colors can be connected to different data signals. The display panel 10 can provide different sub-pixels 700 with data signals from the plurality of data signal lines Data independently, so as to achieve better display effect of the display panel 10, so that the display of the display panel 10 is clearer and more vivid, and the power consumption of the display panel 10 can also be effectively reduced.

[0132] Further, referring to Figures 1 to 18 As shown, the sub-pixel 700 includes the pixel circuit 100 and the light-emitting element 300 electrically connected, a plurality of pixel circuits 100 arranged along the second direction X2 are electrically connected with a plurality of light-emitting elements 300 of the same light-emitting color, and are electrically connected with the same data signal line Data; the light-emitting element 300 includes a first color light-emitting element 301 and a second color light-emitting element 302, the first color light-emitting element 301 and the second color light-emitting element 302 are arranged alternately along the second direction X2, and the first color light-emitting element 301 and the second color light-emitting element 302 arranged alternately along the second direction X2 are respectively electrically connected with the pixel circuit 100 located in different pixel circuit columns.

[0133] Specifically, referring to Figure 1As shown, the sub-pixel 700 includes the pixel circuit 100 and the light emitting element 300 electrically connected, and the sub-pixel 700 of different light emitting colors is formed according to the light emitting element 300 capable of emitting different colors. Referring to Figure 18 As shown, for the specific arrangement position of the light emitting element 300, the anode RE of the light emitting element 300 is taken as an example for illustration. The light emitting element 300 includes the first color light emitting element 301 and the second color light emitting element 302, and the first color light emitting element 301 and the second color light emitting element 302 are arranged alternately along the second direction X2. Further, referring to Figures 8 to 18 As shown, the first color light emitting element 301 and the second color light emitting element 302 arranged alternately along the second direction X2 are electrically connected to the pixel circuit 100 located in different pixel circuit columns, that is, the light emitting element 300 of different colors is electrically connected to the pixel circuit 100 of different colors.

[0134] Further, referring to Figure 17 As shown, the plurality of pixel circuits 100 arranged along the second direction X2 are electrically connected to the plurality of light emitting elements 300 of the same light emitting color, and are electrically connected to the same data signal line Data. That is, the same data signal line Data is electrically connected to the same column of pixel circuits 100. The same column of pixel circuits 100 is electrically connected to the light emitting element 300 of the same color. In this way, the sub-pixel 700 of the same light emitting color is connected to the same data signal.

[0135] Referring to Figure 7 and Figure 18 As shown, the light emitting element 300 includes the anode RE, the anode RE includes the anode main body part 910 and the anode connecting part 920 connected; the display panel 10 further includes the pixel limiting layer 411 and the plurality of pixel openings 412 arranged in the pixel limiting layer 411, along the thickness direction of the display panel 10, the anode main body part 910 overlaps the pixel opening 412, and the anode connecting part 920 does not overlap the pixel opening 412; the anode connecting part 920 is electrically connected to the pixel circuit 100; the light emitting element 300 includes the first light emitting element 300A and the second light emitting element 300B, and the first light emitting element 300A and the second light emitting element 300B have the same light emitting color; the first light emitting element 300A and the second light emitting element 300B are arranged staggered in the first direction X1 and the second direction X2, and the length of the anode connecting part 920 of the first light emitting element 300A is greater than the length of the anode connecting part 920 of the second light emitting element 300B.

[0136] Among them, referring to Figure 7As shown, the anode RE of the light emitting element 300 is electrically connected with the pixel circuit 100, and the pixel defining layer 411 in the display panel 10 is located on the side of the anode RE away from the substrate 400. The pixel defining layer 411 includes a pixel opening 412, and the pixel opening 412 exposes part of the anode RE. In the thickness direction of the display panel 10, the anode main part 910 overlaps the pixel opening 412, and the anode connecting part 920 does not overlap the pixel opening 412. Referring to Figure 18 As shown, Figure 18 The film layer structure of the anode RE is shown.

[0137] Further, referring to Figure 18 As shown, the light emitting element 300 includes a first light emitting element 300A and a second light emitting element 300B, and the first light emitting element 300A and the second light emitting element 300B have the same light emitting color. Figure 18 The position of the anode RE corresponds to the setting position of the light emitting element 300. The first light emitting element 300A and the second light emitting element 300B are staggered in the first direction X1 and the second direction X2. Referring to Figure 18 As shown, Figure 18 In the case where the first light emitting element 300A and the second light emitting element 300B are both first color light emitting elements 301, the first light emitting element 300A is electrically connected with the pixel circuit 100 through the anode connecting part 920, that is, the first light emitting element 300A is electrically connected with the pixel circuit 100 through the anode connecting part 920 extending to the via in the z region in the figure. The second light emitting element 300B is electrically connected with the pixel circuit 100 through the anode connecting part 920 extending to the via in the z region in the figure. In combination with Figure 18 As shown, the length of the anode connecting part 920 of the first light emitting element 300A is greater than the length of the anode connecting part 920 of the second light emitting element 300B, which ensures that light emitting elements 300 of the same color can be electrically connected with the pixel circuits 100 in the same pixel circuit column, and ensures the display effect of the display panel 10.

[0138] Continuing to refer to Figure 18 As shown, the display panel 10 further includes a virtual anode connecting part 930 located on one side of the anode connecting part 920 of the second light emitting element 300B; the length of the anode connecting part 920 of the first light emitting element 300A is L1, and the sum of the lengths of the anode connecting part 920 of the second light emitting element 300B and the virtual anode connecting part 930 is L2; wherein |L1-L2| / L1≤20%.

[0139] Further, referring to Figure 30As shown, the display panel 10 further comprises a virtual anode connecting part 930, and the virtual anode connecting part 930 is located on one side of the anode connecting part 920 of the second light emitting element 300B. The total length of the virtual anode connecting part 930 and the anode connecting part 920 of the second light emitting element 300B is the same as or close to the length of the anode connecting part 920 of the first light emitting element 300A, so as to ensure the wire balance of the display panel 10 at the film layer of the anode electrode layer 429, and improve the display balance of the display panel 10 as a whole, and further improve the display effect of the display panel 10 as a whole.

[0140] Based on the same inventive concept, the embodiment of the present application also provides a display device, Figure 30 is a structural schematic diagram of a display device provided by the embodiment of the present application, as ​ shown, the display device 1 comprises the display panel 10 described in any of the above embodiments, therefore, the display device 1 provided by the embodiment of the present application has the corresponding beneficial effects in the above embodiments, which will not be repeated here. The display device 1 can be a mobile phone, a computer, a smart wearable device (for example, a smart watch) and a vehicle-mounted display device, etc.

[0141] Note that the above are only preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: including pixel circuits and signal lines; The pixel circuit includes a driving module, a data writing module and an adjustment module, wherein a first end of the data writing module is electrically connected to a first end of the driving module, and a first end of the adjustment module is electrically connected to at least one end of the driving module; The signal line includes a data signal line and an adjustment signal line, the data signal line is electrically connected to the second end of the data writing module, and the adjustment signal line is electrically connected to the second end of the adjustment module; The pixel circuit includes a first pixel circuit and a second pixel circuit, the adjustment signal line includes a first adjustment signal line and a second adjustment signal line, the first adjustment signal line is electrically connected to the second end of the adjustment module in the first pixel circuit, and the second adjustment signal line is electrically connected to the second end of the adjustment module in the second pixel circuit; The signal potentials in the first adjustment signal line and the second adjustment signal line are different.

2. The display panel according to claim 1, wherein: The adjustment module includes a bias adjustment transistor; the adjustment signal line includes a first bias adjustment signal line and a second bias adjustment signal line, the first bias adjustment signal line is electrically connected to the second end of the bias adjustment transistor in the first pixel circuit, the second bias adjustment signal line is electrically connected to the second end of the bias adjustment transistor in the second pixel circuit, and the signal potentials in the first bias adjustment signal line and the second bias adjustment signal line are different; And / or, the adjustment module includes a first light-emitting control transistor, the adjustment signal line includes a first power signal line and a second power signal line, the first power signal line is electrically connected to the second end of the first light-emitting control transistor in the first pixel circuit, the second bias adjustment signal line is electrically connected to the second end of the first light-emitting control transistor in the second pixel circuit, and the signal potentials in the first power signal line and the second power signal line are different.

3. The display panel according to claim 1, wherein: The first regulating signal line includes a first regulating section and a second regulating section that are arranged in different layers and are electrically connected; the first regulating section extends along a first direction, the second regulating section extends along a second direction, and the first direction and the second direction intersect; And / or, the second regulation signal line includes a third regulation section and a fourth regulation section that are arranged in different layers and are electrically connected, the third regulation section extends along the first direction, and the fourth regulation section extends along the second direction.

4. The display panel according to claim 3, wherein: The regulation module includes a bias regulation transistor; The first adjusting section and the third adjusting section are arranged along the second direction; The second adjusting section and the fourth adjusting section are arranged along the first direction.

5. The display panel according to claim 3, wherein: The regulating module includes a first light emitting control transistor; The first adjustment section and the third adjustment section are arranged along the first direction; The second adjusting section and the fourth adjusting section are arranged along the first direction.

6. The display panel according to claim 3, wherein: The display panel further includes a light emitting element, wherein the light emitting element is electrically connected to the pixel circuit; The light-emitting element includes a first color light-emitting element and a second color light-emitting element, the first color light-emitting element is electrically connected to the first pixel circuit, and the second color light-emitting element is electrically connected to the second pixel circuit; The luminous efficiency of the first color light emitting element is lower than the luminous efficiency of the second color light emitting element; The distribution density of the second adjustment section is greater than the distribution density of the fourth adjustment section.

7. The display panel according to claim 6, wherein: The pixel circuit further includes an anode reset module, a first end of which is electrically connected to the anode of the light-emitting element; the signal line further includes an anode reset signal line, which is electrically connected to the second end of the anode reset module; The anode reset signal line includes a first anode reset segment extending along the second direction; The second regulating sub-section, the fourth regulating sub-section, and the first anode resetting sub-section are arranged along the first direction.

8. The display panel according to claim 7, wherein: The anode reset signal line further includes a second anode reset sub-portion extending along the first direction. The second anode reset sub-portion is disposed in a different layer from the first anode reset sub-portion and is electrically connected to the first anode reset sub-portion.

9. The display panel according to claim 3, wherein: The display panel further includes an additional adjustment structure, wherein the additional adjustment structure includes a first additional adjustment sub-section and a second additional adjustment sub-section; The first additional regulating sub-section is electrically connected to the second regulating sub-section, and the second additional regulating sub-section is electrically connected to the fourth regulating sub-section.

10. The display panel according to claim 9, wherein: The first additional adjustment section and the second additional adjustment section are arranged in the same layer and arranged along the first direction.

11. The display panel according to claim 3, wherein: The display panel further includes a substrate; The pixel circuit includes at least one first-type transistor and at least one second-type transistor, the first-type transistor includes a first active layer and a first gate, the second-type transistor includes a second active layer, a second top gate, and a second bottom gate, the first gate is located on a side of the first active layer close to the substrate or on a side of the first active layer away from the substrate, the second top gate is located on a side of the second active layer away from the substrate, and the second bottom gate is located on a side of the second active layer close to the substrate; The display panel further includes a zero metal layer, a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a first source-drain electrode layer, a second source-drain electrode layer, and a third source-drain electrode layer; the zero metal layer is located on a side of the first active layer close to the substrate, the first active layer is located on the first semiconductor layer, the first gate is located on the first metal layer, the second bottom gate is located on the second metal layer, the second active layer is located on the second semiconductor layer, the second top gate is located on the third metal layer, the first source-drain electrode layer is located on a side of the third metal layer away from the substrate, the second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the substrate, and the third source-drain electrode layer is located on a side of the second source-drain electrode layer away from the substrate; The first adjustment sub-section is located in at least one of the zero metal layer, the first metal layer, the second metal layer, the third metal layer, and the second source-drain metal layer; The second regulating portion is located in the first source-drain metal layer or the third source-drain metal layer; The third adjustment sub-section is located in at least one of the zero metal layer, the first metal layer, the second metal layer, the third metal layer, and the second source-drain metal layer; The fourth adjustment portion is located in the first source-drain metal layer or the third source-drain metal layer.

12. The display panel according to claim 11, wherein: The first adjustment sub-section and the third adjustment sub-section are arranged on the same layer, and the second adjustment sub-section and the fourth adjustment sub-section are arranged on the same layer.

13. The display panel according to claim 1, wherein The display panel further includes a plurality of sub-pixels; The signal lines include a plurality of data signal lines, the plurality of data signal lines are arranged along a first direction and extend along a second direction, and the first direction and the second direction intersect; The same data signal line is electrically connected to a plurality of sub-pixels emitting light of the same color arranged along the second direction.

14. The display panel according to claim 13, wherein: The sub-pixel includes the pixel circuit and the light-emitting element electrically connected, The plurality of pixel circuits arranged along the second direction are electrically connected to the plurality of light-emitting elements of the same light-emitting color and are electrically connected to the same data signal line; The light-emitting elements include first color light-emitting elements and second color light-emitting elements, the first color light-emitting elements and the second color light-emitting elements are alternately arranged along the second direction, and the first color light-emitting elements and the second color light-emitting elements alternately arranged along the second direction are electrically connected to the pixel circuits located in different pixel circuit columns.

15. The display panel according to claim 14, wherein: The light emitting element includes an anode, wherein the anode includes an anode main portion and an anode connecting portion connected to each other; The display panel further includes a pixel defining layer and a plurality of pixel openings provided in the pixel defining layer, wherein along a thickness direction of the display panel, the anode main portion overlaps with the pixel openings, and the anode connecting portion does not overlap with the pixel openings; The anode connecting portion is electrically connected to the pixel circuit; The light-emitting element includes a first light-emitting element and a second light-emitting element, and the first light-emitting element and the second light-emitting element emit the same light color; the first light-emitting element and the second light-emitting element are staggered in the first direction and the second direction, and the length of the anode connecting portion of the first light-emitting element is greater than the length of the anode connecting portion of the second light-emitting element.

16. The display panel according to claim 15, wherein: The display panel further includes a dummy anode connecting portion, the dummy anode connecting portion being located on one side of the anode connecting portion of the second light emitting element; The length of the anode connecting portion of the first light-emitting element is L1, and the sum of the lengths of the anode connecting portion and the dummy anode connecting portion of the second light-emitting element is L2; Among them, |L1-L2| / L1≤20%.

17. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 16.

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