GOA circuit and driving method thereof, display panel and display equipment

Abstract

The invention discloses a GOA circuit and a driving method thereof, a display panel and a display device, and relates to the technical field of display, the circuit comprises a cascade transmission module integrated with a cascade transmission transistor, the drain electrode of the cascade transmission transistor is electrically connected with a first node, and the source electrode of the cascade transmission transistor is electrically connected with a second node; the grid control end of the output module is electrically connected with the second node; the transmission ends on the two sides of the potential control module are electrically connected with the first node and the low-potential line respectively, and the high-potential end of the potential control module is electrically connected with the high-potential line. The potential control module is used for transmitting a high-potential signal of a high-potential line to the first node in a cascade transmission stage, so that the cascade transmission transistor transmits the high-potential signal to the output module through the second node; and transmitting a low-potential signal of the low-potential line to the first node after the cascade transmission is completed, so that the potential of a second node electrically connected with the source electrode of the cascade transmission transistor is continuously lowered, and the display quality is improved by eliminating threshold voltage drift caused by voltage imbalance of the cascade transmission transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a GOA circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] The rapid development of display technology has led to increasing user requirements for the display quality of display panels.

[0003] In display panels currently driven by GOA (Gate Driver on Array), the stage transfer transistors of the stage transfer module are in a negative bias state for a long time, causing the first node P connected to the drain of the stage transfer transistor to maintain a high potential, resulting in a long-term imbalance in the three-terminal voltage of the stage transfer transistor. This voltage imbalance further causes the threshold voltage of the stage transfer transistor to drift, seriously affecting its switching performance. When the threshold voltage of the stage transfer transistor drifts severely, the stage transfer transistor may not be able to effectively shut down when it needs to be turned off, causing the high potential to abnormally leak to the second node Q. The second node Q serves as the electrical connection node between the stage transfer module and the output module. When its potential is pulled high, it will abnormally turn on the output module, thereby causing the output of the timing control signal connected to the output module to be disordered, seriously affecting the normal display of the display panel, causing the display panel to exhibit abnormal display problems such as screen flickering, afterimages, or uneven brightness.

[0004] Therefore, how to eliminate the threshold voltage drift of the stage-pass transistor caused by voltage imbalance to improve the display quality of the display panel is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The main purpose of this application is to provide a GOA circuit and its driving method, a display panel and a display device, aiming to eliminate the threshold voltage drift problem caused by long-term negative bias of the stage transistor to improve the display quality of the display panel.

[0006] To achieve the above objectives, the present application provides a GOA circuit, which includes:

[0007] a stage transmission module, the stage transmission module comprising a stage transmission transistor, the drain of the stage transmission transistor being electrically connected to the first node, and the source of the stage transmission transistor being electrically connected to the second node;

[0008] an output module, wherein a gate control terminal of the output module is electrically connected to the second node;

[0009] A potential control module, two side transmission ends of the potential control module are electrically connected with the first node and a low potential line respectively, a high potential end of the potential control module is electrically connected with a high potential line, the potential control module is configured to transmit a high potential signal of the high potential line to the first node in a stage transmission phase so that the stage transmission transistor transmits the high potential signal to the output module through the second node, and transmit a low potential signal of the low potential line to the first node after the stage transmission is completed so that the potential of the second node to which the source of the stage transmission transistor is electrically connected is continuously pulled down.

[0010] In an embodiment, the GOA circuit comprises a potential pull-down control end, and the potential control module comprises a first thin film transistor and a second thin film transistor.

[0011] The first pass-through end of the first thin film transistor constitutes the high potential end of the potential control module and the high potential line, the gate end of the first thin film transistor is electrically connected with a previous stage gate signal end, and the second pass-through end of the first thin film transistor constitutes one of the two side transmission ends and the first node.

[0012] The first pass-through end of the second thin film transistor is electrically connected with the first node, the second pass-through end of the second thin film transistor constitutes the other of the two side transmission ends and the low potential line, and the gate end of the second thin film transistor is electrically connected with the potential pull-down control end.

[0013] In an embodiment, when the potential pull-down control end is any one of the current stage gate signal end, the next stage gate signal end and the timing control end, the gate of the stage transmission transistor is electrically connected with the previous stage gate signal end.

[0014] In an embodiment, when the potential pull-down control end is the next stage gate signal end, the gate of the stage transmission transistor is electrically connected with the drain of the stage transmission transistor.

[0015] In an embodiment, the stage transmission module further comprises a third thin film transistor, the first pass-through end of the third thin film transistor is electrically connected with the low potential line, and the second pass-through end of the third thin film transistor is electrically connected with the second node.

[0016] The output module comprises a fourth thin film transistor and a capacitor, the gate end of the fourth thin film transistor and the first end of the capacitor are electrically connected with the second node, the first pass-through end of the fourth thin film transistor is electrically connected with a timing control end, and the second pass-through end of the fourth thin film transistor and the second end of the capacitor are electrically connected with a current stage gate signal end respectively.

[0017] Further, to achieve the above object, the application also provides a GOA circuit driving method applied to any one of the GOA circuits, the GOA circuit driving method comprising:

[0018] transmitting, by the potential control module, a high potential signal of a high potential line to the first node for a stage transmission transistor in the stage transmission module to transmit the high potential signal to the output module via the second node;

[0019] after the stage transmission is completed, transmitting, by the potential control module, a low potential signal of a low potential line to the first node to continuously pull down the potential of the second node to which the source of the stage transmission transistor is electrically connected.

[0020] In an embodiment, the potential control module comprises a second thin film transistor, the stage transmission module comprises a third thin film transistor, and the step of transmitting, by the potential control module, the low potential signal of the low potential line to the first node to continuously pull down the potential of the second node to which the source of the stage transmission transistor is electrically connected comprises:

[0021] when the stage behind gate signal of the stage behind gate signal end and the pull-down control signal of the potential pull-down control end are both effective levels, enabling the third thin film transistor to transmit the low potential signal of the low potential line to the second node to which the source of the stage transmission transistor is electrically connected under the drive of the stage behind gate signal, and enabling the second thin film transistor to transmit the low potential signal to the first node to which the source of the stage transmission transistor is electrically connected under the drive of the pull-down control signal;

[0022] maintaining the potential of the second node to be continuously pulled down according to the low potential signals accessed by the first node and the second node.

[0023] In an embodiment, the step of maintaining the potential of the second node to be continuously pulled down according to the low potential signals accessed by the first node and the second node comprises:

[0024] in response to the stage in front gate signal provided by the stage in front gate signal end to the gate of the stage transmission transistor being switched from an effective potential to an ineffective level, determining that the gate potential of the stage transmission transistor is a low potential of the ineffective level, the drain potential of the stage transmission transistor is the low potential signal accessed by the first node, and the drain potential of the stage transmission transistor is the low potential signal accessed by the second node, to maintain the off state of the stage transmission transistor;

[0025] enabling the potential of the second node to be continuously pulled down in the off state.

[0026] In addition, to achieve the above object, the application further provides a display panel, comprising a color film substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color film substrate, and the array substrate comprises the GOA circuit according to any one of the above.

[0027] In addition, to achieve the above object, the application further provides a display device comprising the display panel.

[0028] Or a memory, a processor and a charging driver stored on the memory and executable on the processor, when the processor executes the charging driver, the steps of the GOA circuit driving method are realized.

[0029] In the GOA circuit of the application, a potential control module is arranged, and in the stage transmission stage, the high potential signal of the high potential line is transmitted to the first node through the potential control module, so that when the stage transmission transistor in the stage transmission module is turned on, the high potential signal can be transmitted to the output module through the electrically connected first node to realize normal display driving, and after the stage transmission is completed, the low potential signal of the low potential line is transmitted to the first node through the potential control module, so that the potential of the second node connected to the source electrode of the stage transmission transistor is continuously pulled down, so that a zero bias state is formed between the drain electrode (connected to the first node) and the source electrode (connected to the second node) of the stage transmission transistor, effectively avoiding the threshold voltage drift of the stage transmission transistor caused by voltage imbalance, thereby stabilizing the switching performance of the stage transmission transistor, completely blocking the abnormal leakage path of the high potential signal to the second node, thereby avoiding the output module from being mistakenly opened due to the abnormal rise of the potential of the second node, and finally ensuring the accuracy of the GOA circuit timing output, and significantly improving the display quality of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings incorporated in and forming a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor.

[0032] Figure 1 is a structural block diagram of the first embodiment of the GOA circuit of the application;

[0033] Figure 2 is a schematic diagram of the GOA circuit involved in the embodiment of the application;

[0034] Figure 3is a GOA circuit diagram related to the current stage gate signal end of the potential pull-down control end;

[0035] Figure 4 is Figure 3 is a signal waveform schematic diagram related to the circuit diagram shown in the figure;

[0036] Figure 5 is a GOA circuit diagram related to the next stage gate signal end of the potential pull-down control end;

[0037] Figure 6 is Figure 5 is a signal waveform schematic diagram related to the circuit diagram shown in the figure;

[0038] Figure 7 is a GOA circuit diagram related to the timing control end of the potential pull-down control end;

[0039] Figure 8 is Figure 7 is a signal waveform schematic diagram related to the circuit diagram shown in the figure;

[0040] Figure 9 is another GOA circuit diagram related to the next stage gate signal end of the potential pull-down control end;

[0041] Figure 10 is a structural schematic diagram of a display device related to the embodiment scheme of the present application.

[0042] Explanation of reference numerals:

[0043] 10, stage transmission module; 20, output module; 30, potential control module; V0, potential pull-down control end; T0, stage transmission transistor; T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; T4, fourth thin film transistor; C1, capacitor; VGH, high potential line; VGL, low potential line.

[0044] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0046] It should be noted that if the application embodiments have directionality indications (such as up, down, left, right, front, back, etc.), the directionality indications are only used to explain the relative position relationship, motion condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directionality indications will also change accordingly.

[0047] In addition, if the application embodiments have descriptions of "first", "second", etc., the descriptions of "first", "second", etc. are only for description purposes and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the application.

[0048] The exemplary embodiments will be described in detail hereinafter with reference to the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0049] In recent years, with the rapid development of display technology, high refresh rate displays gradually become the mainstream demand of the market due to their smoother visual experience in dynamic pictures, faster response speed, and reduced visual fatigue. However, high refresh rate also brings higher power consumption problems, especially in mobile devices, notebook computers and other application scenarios with high requirements for endurance, high power consumption has become one of the key factors restricting the popularization of high refresh rate.

[0050] The rapid development of display technology makes users increasingly demanding on the display quality of display panels.

[0051] In a display panel currently driven by a GOA (Gate Driver on Array), a stage transmission transistor of a stage transmission module is in a negative bias state for a long time, which causes a first node P connected to a drain of the stage transmission transistor to continuously maintain a high potential, so that a three-terminal voltage of the stage transmission transistor is unbalanced for a long time. The voltage imbalance state further causes a threshold voltage of the stage transmission transistor to drift, which seriously affects the switching performance of the stage transmission transistor. When the threshold voltage of the stage transmission transistor drifts seriously, the stage transmission transistor may not be effectively turned off when it needs to be turned off, causing abnormal leakage of the high potential to a second node Q. The second node Q is an electrical connection node of the stage transmission module and an output module, and when the potential of the second node Q is pulled high, the output module is abnormally turned on, which causes the timing control signal output by the output module to be disordered, seriously affects the normal display of the display panel, and causes the display panel to present abnormal display problems such as flicker, residual image, or uneven brightness.

[0052] Therefore, to solve the technical problem of threshold voltage drift of the stage transmission transistor caused by voltage imbalance, the present application provides a GOA circuit and a driving method thereof, a display panel, and a display device.

[0053] The present application provides a GOA circuit, which refers to Figure 1 Figure 1 is a structural block diagram of a first embodiment of the GOA circuit of the present application. The GOA circuit comprises:

[0054] a stage transmission module 10, the stage transmission module 10 comprising a stage transmission transistor T0, a drain of the stage transmission transistor T0 being electrically connected to a first node, and a source of the stage transmission transistor T0 being electrically connected to a second node.

[0055] In the present embodiment, referring to Figure 1 ​The stage transmission module 10 is provided with a stage transmission transistor T0, and the drain of the stage transmission transistor T0 is electrically connected with the first node, and the source of the stage transmission transistor T0 is electrically connected with the second node, and bears the signal cascade transmission function between adjacent GOA units. Specifically, when the stage transmission transistor T0 is connected with the previous stage GOA unit of the GOA unit where the stage transmission transistor T0 is located and outputs the previous stage gate signal Gn-1 through the previous stage gate signal end, it is determined that the GOA unit where the stage transmission transistor T0 is located is in the stage transmission stage, and the stage transmission transistor T0 and the potential control module 30 electrically connected with the first node are synchronously turned on according to the previous stage gate signal Gn-1 in the stage transmission stage, so that the high potential signal of the high potential line VGH is transmitted to the second node in turn through the turned-on potential control module 30, the first node and the turned-on stage transmission transistor T0, so as to provide a stable trigger signal for the output module 20 electrically connected with the second node, avoid the signal delay or loss problem caused by the poor stage transmission path in the traditional GOA circuit, and cooperate with the low potential adjustment of the subsequent potential control module 30, so that the stage transmission transistor T0 is zero in the non-working stage, and the voltage offset problem caused by the long-term voltage imbalance is fundamentally solved, and the display defects such as high / low temperature flash screen and horizontal line abnormality caused by the voltage offset problem are completely eliminated, and the long-term stability of the cascade signal transmission of the GOA circuit is ensured.

[0056] The output module 20, the gate control end of the output module 20 is electrically connected with the second node.

[0057] In the embodiment, referring to Figure 1 , the accurate control of the current stage gate signal Gn output is realized through the electrical connection between the gate control end of the output module 20 and the second node. Specifically, based on the potential change of the second node received by the gate control end of the output module 20, the conduction and turn-off of the output module 20 are controlled in real time, when the second node is at a high level due to the transmission of the high potential signal by the stage transmission module 10, the output module 20 is effectively turned on, the timing control signal connected with the output module 20 is converted into the current stage gate signal Gn meeting the display requirements, and is transmitted to the display area of the display panel to drive the pixel unit electrically connected with the current stage gate row, realizing the normal display driving of the display panel; on the contrary, when the second node is pulled down to a low potential signal, the output module 20 immediately switches from the conduction state to the cut-off state to stop the output of the current stage gate signal Gn, ensuring the normal driving of the display panel row by row.

[0058] A potential control module 30, two sides of the transmission end of the potential control module 30 are electrically connected with the first node and the low potential line VGL respectively, the high potential end of the potential control module 30 is electrically connected with the high potential line VGH, the potential control module 30 is set to transmit the high potential signal of the high potential line VGH to the first node in the stage transmission stage so that the stage transmission transistor T0 transmits the high potential signal to the output module 20 via the second node, and transmit the low potential signal of the low potential line VGL to the first node after the stage transmission is completed to make the potential of the second node electrically connected with the source of the stage transmission transistor T0 continuously low.

[0059] In the embodiment, the two sides of the transmission end of the potential control module 30 are electrically connected with the first node and the low potential line VGL respectively, and the high potential end of the potential control module 30 is electrically connected with the high potential line VGH, so that the high potential signal of the high potential line VGH can be transmitted to the first node in the stage transmission stage, ensuring that the high potential signal can be provided to the output module 20 electrically connected with the second node when the stage transmission transistor T0 is turned on, realizing the compatibility of the original working logic of the GOA circuit and ensuring the normal progress of the signal cascade transmission; and the low potential signal of the low potential line VGL is transmitted to the first node by the potential control module 30 after the stage transmission is completed, so as to realize the potential of the second node electrically connected with the source of the stage transmission transistor T0 continuously low, fundamentally avoid the voltage offset problem of the stage transmission transistor T0 caused by long-term voltage imbalance, stabilize the switching performance of the stage transmission transistor T0, completely block the abnormal leakage path of the high potential signal to the second node, so as to avoid the output module 20 being mistakenly turned on due to the abnormal rise of the potential of the second node, and finally ensure the accuracy of the timing output of the GOA circuit, and significantly improve the display quality of the display panel.

[0060] Further, in some possible embodiments, referring to Figure 2 , the GOA circuit includes a potential pull-down control end V0, and the potential control module 30 includes a first thin film transistor T1 and a second thin film transistor T2.

[0061] The first pass-through end of the first thin film transistor T1 constitutes the high potential end of the potential control module 30 and is electrically connected with the high potential line VGH, the gate end of the first thin film transistor T1 is electrically connected with the previous stage gate signal end, and the second pass-through end of the first thin film transistor T1 constitutes one of the two sides of the transmission end and is electrically connected with the first node.

[0062] In the embodiment, the first thin film transistor T1 is set to have the gate end electrically connected with the front-stage gate signal end under the synergic control of the potential pull-down control end V0 and the front-stage gate signal end, the first pass end of the first thin film transistor T1 is electrically connected with the high potential line VGH, and the second pass end of the first thin film transistor T1 is electrically connected with the first node. Since the front-stage gate signal provided by the front-stage gate signal end is in the effective level in the stage transmission stage, the first thin film transistor T1 is switched from the cut-off state to the on state at this time, so that the high potential signal of the high potential line VGH can be stably transmitted to the first node without loss through the on first thin film transistor T1. The stage transmission transistor T0 in the stage transmission module 10 is also on when the front-stage gate signal is in the effective level or the potential signal of the first node is in the high potential signal, and then the high potential signal of the first node is smoothly transmitted to the second node, so as to ensure that the output module 20 normally outputs the current stage gate signal Gn when the second node is in the high potential signal.

[0063] The first pass end of the second thin film transistor T2 is electrically connected with the first node, the second pass end of the second thin film transistor T2 is electrically connected with the low potential line VGL to constitute the other side transmission end of the two side transmission ends, and the gate end of the second thin film transistor T2 is electrically connected with the potential pull-down control end V0.

[0064] In the embodiment, the pull-down control signal output by the potential pull-down control end V0 is directly transmitted to the gate end of the second thin film transistor T2. The pull-down control signal is an invalid level to continuously maintain the off state of the second thin film transistor T2 in the stage transmission stage, so as to avoid the interference of the low potential line VGL on the high potential state of the second node, and ensure that the signal transmission in the stage transmission stage is not affected. After the stage transmission is completed, the pull-down control signal is switched from the invalid level to the effective level to turn on the second thin film transistor T2, and the low potential signal of the low potential line VGL is provided to the first node through the turned-on second thin film transistor T2, and then the drain potential of the stage transmission transistor T0 electrically connected to the first node is pulled down. Since the gate signal of the previous stage is switched from the effective level to the invalid level when the stage transmission is completed, and the gate of the stage transmission transistor T0 is controlled by the gate signal of the previous stage or the potential of the first node, the gate of the stage transmission transistor T0 will be turned off synchronously with the invalidation of the gate signal of the previous stage or the pull-down of the potential of the first node, that is, the gate potential of the stage transmission transistor T0 is also pulled down, and the second node connected to the source of the stage transmission transistor T0 is also synchronously lowered to the low potential due to the turn-off of the stage transmission transistor T0. Finally, the drain, source and gate potentials of the stage transmission transistor T0 are all stably maintained at the low potential, that is, the voltages of the three terminals of the stage transmission transistor T0 are completely zero, which completely avoids the voltage offset problem of the stage transmission transistor T0 caused by long-term bearing voltage difference, and eliminates the display abnormalities such as high-temperature flash screen and low-temperature horizontal lines from the root. In addition, through the timely turn-off of the stage transmission transistor T0 and the low potential maintenance of the second node, the output module 20 is completely closed after the stage transmission is completed, and the current stage gate signal is output without abnormality, which eliminates the picture ghosting or confusion, and significantly improves the display quality.

[0065] Further, in some possible embodiments, the gate of the stage transmission transistor T0 is electrically connected to any one of the current stage gate signal end, the previous stage gate signal end and the timing control end.

[0066] In the embodiment, with reference to Figure 3 and Figure 4When the gate of the stage transmission transistor T0 is electrically connected with the previous stage gate signal end, the potential pulling-down control end V0 can be flexibly configured as the current stage gate signal end. In the stage transmission stage, the previous stage gate signal Gn-1 is an effective level, and the stage transmission transistor T0 and the first thin film transistor T1 are synchronously turned on under the driving of the previous stage gate signal Gn-1 being the effective level, so as to transmit the high potential signal of the high potential line VGH to the first node, conduct the high potential signal to the second node through the stage transmission transistor T0, and trigger the output module 20 to output the current stage gate signal Gn; next, when the current stage gate signal Gn is output (i.e. when the stage transmission is completed), the current stage gate signal Gn is directly triggered to turn on the second thin film transistor T2 from the invalid level to the effective level, and the low potential signal of the low potential line VGL is transmitted to the first node; at this time, the previous stage gate signal Gn-1 has been an invalid low level, the gate potential of the stage transmission transistor T0 is lowered to the low level and is cut off, the drain electrode of the stage transmission transistor T0 electrically connected with the first node is pulled down to the low potential, the source electrode of the stage transmission transistor T0 electrically connected with the second node is synchronously lowered to the low potential with the discharge of the output module 20, and finally the stage transmission transistor T0 realizes three-terminal voltage difference zero because the gate, the drain and the source are all low potentials, thereby completely suppressing the voltage offset problem and eliminating the display abnormalities such as high-temperature flash screen and low-temperature flash screen caused thereby, and significantly improving the display quality. In addition, the potential pulling-down control end V0 is configured as the current stage gate signal end in the application, so that the pulling-down action is strictly synchronized with the output completion time of the current stage gate signal Gn, the response speed is fast, there is no additional time delay, it is suitable for small and medium-sized panels with high driving precision requirements, and the pulling-down lag problem caused by external signal interference is avoided.

[0067] In specific embodiments, the current stage gate signal Gn provided by the current stage gate signal end is used as the conduction trigger signal of the second thin film transistor T2. When the stage 1 in the stage transmission process is in the stage 1, Figure 4 In the stage 1, since the signal waveform of the previous stage gate signal Gn-1 is switched from the low potential to the high potential, i.e. the previous stage gate signal Gn-1 is the effective level, at this time, the stage transmission transistor T0 and the first thin film transistor T1 are turned on under the driving of the previous stage gate signal Gn-1 being the effective level, so as to sequentially charge the second node through the first thin film transistor T1, the first node and the stage transmission transistor T0 from the high potential signal provided by the high potential line VGH, so that the fourth thin film transistor T4 in the output module 20 is normally opened according to the obtained high potential signal; next, when the stage 2 in the stage transmission process is in the stage 2, Figure 4In stage 2 of the waveform in FIG. 6, the signal waveform of the previous-stage gate signal G n-1 is switched from high potential to low potential, that is, the previous-stage gate signal G n-1 is at an invalid level. At this time, the stage transmission transistor T 0 and the first thin film transistor T 1 are maintained in an off state. Since the capacitor C 1 in the output module 20 can continue to supply power to the fourth thin film transistor T 4 by storing the capacitor C 1 amount when the stage transmission transistor T 0 is off, the fourth thin film transistor T 4 continues to be in an on state, and outputs the timing signal CKA provided by the timing control end (that is, the stage 2 waveform of the waveform CKA in FIG. 6, also referred to as an effective level) as the current-stage gate signal G n. At this time, the second thin film transistor T 2 is turned on when the current-stage gate signal G n is at the effective level, so that the low potential signal provided by the low potential line VGL is written to the first node through the turned-on second thin film transistor T 2. Figure 4 In stage 3 of the waveform in FIG. 6, the first node continues to be in a low potential state until the previous-stage gate signal G n-1 of the next frame is at the effective level, and the steps of stages 1 to 3 are repeated. That is, the stage transmission transistor T 0 is set to be in stage 3 of the waveform in FIG. 6 for a long time after the stage transmission is completed, so as to ensure that the three-terminal voltage difference of the stage transmission transistor T 0 is 0, and Vth shift (that is, voltage offset) does not occur, which can effectively improve the display problem caused by the voltage offset of the stage transmission transistor T 0. Figure 4 Figure 4 In another embodiment, with reference to FIG. 7 and FIG. 8,

[0068] In another embodiment, with reference to FIG. 7 and FIG. 8, Figure 5 and Figure 6 When the gate of the stage transmission transistor T 0 is electrically connected to the previous-stage gate signal end, the control end V 0 can be flexibly configured as the next-stage gate signal end. The timing characteristic that the next-stage gate signal G n+1 of the next-stage gate signal end naturally lags behind the current-stage gate signal G n ensures that the second thin film transistor T 2 is turned on only after the current-stage gate signal G n is completely output, avoiding the interference of the pull-down action on the high potential of the second node in the signal G n output stage. At the same time, the gate of the stage transmission transistor T 0 is controlled by the previous-stage gate signal G n-1, and is reliably turned on in the stage transmission stage. After the stage transmission is completed, the stage transmission transistor T 0 is turned off with the invalidation of the previous-stage gate signal G n-1, and forms a timing closed loop with the pull-down action triggered by the next-stage gate signal G n+1, further ensuring the integrity of the signal transmission, and being suitable for a display panel in a wide-temperature complex environment, which can be understood as a low-temperature display scene or a high-temperature display scene.

[0069] In a specific embodiment, the next-stage gate signal G n+1 provided by the next-stage gate signal end is used as the turn-on trigger signal of the second thin film transistor T 2. When the stage transmission transistor T 0 is in stage 2 of the waveform in FIG. 6, the next-stage gate signal G n+1 provided by the next-stage gate signal end is used as the turn-on trigger signal of the second thin film transistor T 2. Figure 6 ​In the stage 1, since the signal waveform of the front-stage gate signal Gn-1 switches from a low potential to a high potential, that is, the front-stage gate signal Gn-1 is at an effective level, at this time, the stage pass transistor T0 and the first thin film transistor T1 are turned on under the driving of the front-stage gate signal Gn-1 at an effective level, so that the high potential signal provided by the high potential line VGH is sequentially charged to the second node through the first thin film transistor T1, the first node, and the stage pass transistor T0, so that the second node triggers the fourth thin film transistor T4 in the output module 20 to be normally turned on according to the obtained high potential signal; next, when in Figure 6 In the second stage, the signal waveform of the front-stage gate signal Gn-1 switches from a high potential to a low potential, that is, the front-stage gate signal Gn-1 is at an invalid level. At this time, the stage-pass transistor T0 and the first thin-film transistor T1 remain in the off state. Since the capacitor C1 in the output module 20 can continue to supply power to the fourth thin-film transistor T4 through the stored amount of the capacitor C1 when the stage-pass transistor T0 is turned off, the fourth thin-film transistor T4 continues to be in the on state and the timing signal CKA (i.e. Figure 6 The waveform CKA in the stage 2 waveform involved, also called the effective level) is output as the current stage gate signal Gn, at this time the second thin film transistor T2 is in the invalid level (ie the gate signal Gn+1 of the subsequent stage) Figure 6 The gate signal Gn+1 in the waveform is in the phase 2 waveform involved) and the cut-off state is maintained, that is, the potential of the first node is maintained at a high level in phase 2; subsequently, when in the phase 2 waveform Figure 6 In the stage 3, the gate signal Gn+1 of the subsequent stage switches from the invalid level to the valid level (i.e. Figure 6 The waveform Gn+1 in the waveform of the stage 3 involved is used to make the second thin film transistor T2 turn on when the back-stage gate signal Gn+1 is at an effective level, and the low potential signal provided by the low potential line VGL is written into the first node via the turned-on second thin film transistor T2 until the front-stage gate signal Gn-1 of the next frame is at an effective level, and the steps of stages 1 to 3 are repeated. That is, the present application sets the stage transfer transistor T0 to be in a long-term state after the stage transfer is completed. Figure 6 In stage 3, the voltage difference between the three terminals of the stage pass transistor T0 is ensured to be 0, and no Vthshift (ie, voltage offset) occurs, which can effectively improve the display problem caused by the voltage offset of the stage pass transistor T0.

[0070] In yet another embodiment, referring to Figure 7 as well as Figure 8When the gate of the stage transmission transistor T0 is electrically connected with the previous stage gate signal end, the potential of the control end V0 can be flexibly configured as a timing control end. In the stage transmission stage, the stage transmission transistor T0 and the first thin film transistor T1 are synchronously turned on under the triggering of the effective level of the previous stage gate signal, so as to transmit the high potential signal of the high potential line VGH to the first node and then to the second node through the stage transmission transistor T0, and trigger the output module 20 to output the current stage gate signal Gn. In the stage transmission completion stage, due to the periodic characteristics of the timing signal CKA of the timing control end, the effective level of the timing signal CKA is strictly synchronized with the overall panel driving rhythm, and the second thin film transistor T2 is turned on only when the current stage gate signal Gn is at the effective level, so as to lower the potential of the first node, so that the stage transmission transistor T0 is zeroed due to the low potential of the gate, drain and source, thereby completely suppressing the voltage offset problem and preventing the display abnormalities such as high-temperature flashing screen and low-temperature flashing screen, and significantly improving the display quality. In addition, the periodic characteristics of the timing signal CKA can be used to adapt to the driving requirements of different resolution (such as 4K, 8K) panels by adjusting the period of the timing signal, and the lowering action is highly matched with the overall scanning rhythm of the panel, thereby further reducing the power consumption of the circuit.

[0071] In specific embodiments, the timing signal CKA provided by the timing control end serves as the turn-on triggering signal of the second thin film transistor T2. When the stage 1 in the stage transmission stage is reached, Figure 8 In the stage 1, the signal waveform of the previous stage gate signal Gn-1 is switched from low potential to high potential, that is, the previous stage gate signal Gn-1 is at the effective level, at this time, the stage transmission transistor T0 and the first thin film transistor T1 are turned on under the driving of the effective level of the previous stage gate signal Gn-1, so as to sequentially charge the second node through the first thin film transistor T1, the first node and the stage transmission transistor T0 from the high potential signal provided by the high potential line VGH, so that the second node triggers the fourth thin film transistor T4 in the output module 20 to normally open according to the obtained high potential signal. Figure 8 In the stage 2, the signal waveform of the previous stage gate signal Gn-1 is switched from high potential to low potential, that is, the previous stage gate signal Gn-1 is at the invalid level, at this time, the stage transmission transistor T0 and the first thin film transistor T1 maintain the off state, and since the capacitor C1 in the output module 20 can continue to supply power to the fourth thin film transistor T4 through the stored capacitor C1 amount when the stage transmission transistor T0 is off, the fourth thin film transistor T4 continues to be in the on state, and outputs the timing signal CKA provided by the timing control end as the current stage gate signal Gn, that is, the stage 2 waveform involved in the waveform CKA in the stage 2, also known as the effective level. At this time, the second thin film transistor T2 is turned on when the timing signal CKA is at the effective level, so that the low potential signal provided by the low potential line VGL is written into the first node through the turned-on second thin film transistor T2. Figure 8 In the stage 2, the signal waveform of the previous stage gate signal Gn-1 is switched from high potential to low potential, that is, the previous stage gate signal Gn-1 is at the invalid level, at this time, the stage transmission transistor T0 and the first thin film transistor T1 maintain the off state, and since the capacitor C1 in the output module 20 can continue to supply power to the fourth thin film transistor T4 through the stored capacitor C1 amount when the stage transmission transistor T0 is off, the fourth thin film transistor T4 continues to be in the on state, and outputs the timing signal CKA provided by the timing control end as the current stage gate signal Gn, that is, the stage 2 waveform involved in the waveform CKA in the stage 2, also known as the effective level. At this time, the second thin film transistor T2 is turned on when the timing signal CKA is at the effective level, so that the low potential signal provided by the low potential line VGL is written into the first node through the turned-on second thin film transistor T2.Figure 8 In stage 3 of FIG. 6, the first node continues to maintain the low potential state until the next stage gate signal Gn-1 is at the effective level, and the steps of stages 1-3 are repeated. That is, the stage transfer transistor T0 is set to be in the long-term low potential state after the stage transfer is completed. Figure 8 In stage 3 of FIG. 6, the three-terminal voltage difference of the stage transfer transistor T0 is ensured to be 0, and the Vth shift (i.e., voltage offset) does not occur, which can effectively improve the display problem of the stage transfer transistor T0 caused by the voltage offset.

[0072] Further, in some possible embodiments, referring to FIG. 7, the gate of the stage transfer transistor T0 is electrically connected to the drain of the stage transfer transistor T0. Figure 9 When the potential pull-down control end V0 is the next stage gate signal end, the gate of the stage transfer transistor T0 is electrically connected to the drain of the stage transfer transistor T0.

[0073] In the present embodiment, since the drain of the stage transfer transistor T0 is electrically connected to the first node, if the gate of the stage transfer transistor T0 is electrically connected to the drain of the stage transfer transistor T0, that is, the gate of the stage transfer transistor T0 is short-circuited to the first node, to avoid the second thin film transistor T2 from being turned off during the current stage gate signal Gn output stage and thus pulling down the potential of the second node to affect the normal turn-on of the output module 20, the present application limits the potential pull-down control end V0 electrically connected to the gate end of the second thin film transistor T2 to be only the next stage gate signal end, so as to ensure that the turn-on of the second thin film transistor T2 is controlled only by the next stage gate signal (i.e., the effective level) provided by the next stage gate signal end, and thus the second node is stably maintained at the high potential during the current stage gate signal Gn output stage. That is, the hysteresis characteristic of the next stage gate signal Gn+1 ensures that the second thin film transistor T2 is turned on only after the current stage gate signal Gn output is completed, at which time the first node is pulled down to the low potential line VGL. Since the gate end and the drain of the stage transfer transistor T0 are both electrically connected to the first node, the gate potential and the drain potential of the stage transfer transistor T0 are pulled down synchronously with the first node. The third thin film transistor T3 electrically connected to the second node in the stage transfer module 10 is turned on synchronously under the drive of the next stage gate signal Gn+1 to pull down the potential of the second node electrically connected to the source of the stage transfer transistor T0 to the low potential line VGL, so that the three-terminal voltage difference of the stage transfer transistor T0 is zeroed due to the low potential of the gate, the drain and the source, and the voltage offset problem is completely inhibited, and the display abnormalities such as high-temperature flashing and low-temperature flashing caused thereby are eliminated, and the display quality is significantly improved.

[0074] Further, in some possible embodiments, referring to FIG. 7, the gate of the stage transfer transistor T0 is electrically connected to the drain of the stage transfer transistor T0. Figure 2The stage transmission module 10 further comprises a third thin film transistor T3, a first path end of the third thin film transistor T3 being electrically connected with the low potential line VGL, and a second path end of the third thin film transistor T3 being electrically connected with the second node; the output module 20 comprises a fourth thin film transistor T4 and a capacitor C1, a gate end of the fourth thin film transistor T4 and a first end of the capacitor C1 being electrically connected with the second node, a first path end of the fourth thin film transistor T4 being electrically connected with a time sequence control end, and a second path end of the fourth thin film transistor T4 and a second end of the capacitor C1 being respectively electrically connected with a current stage gate signal end.

[0075] In the embodiment, referring to Figure 2 , the GOA circuit further comprises a third thin film transistor T3, a fourth thin film transistor T4 and a capacitor C1, and a pull-down maintaining module. Figure 2 The third thin film transistor T3, the fourth thin film transistor T4, the capacitor C1 and the pull-down maintaining module work together to further improve the display quality. Specifically, the first path end of the third thin film transistor T3 is electrically connected with the low potential line VGL, and the second path end of the third thin film transistor T3 is electrically connected with the second node. When the stage transmission is completed, the third thin film transistor T3 is turned on, so that the potential of the second node is rapidly pulled to the low potential through the turned-on third thin film transistor T3, thereby avoiding the abnormal opening of the output module 20 caused by the residual high potential of the second node, and strengthening the accurate control of the potential of the second node. In the output module 20, the gate of the fourth thin film transistor T4 and the first end of the capacitor C1 are connected with the second node, the first path end of the fourth thin film transistor T4 is connected with the time sequence control end, and the second path end of the fourth thin film transistor T4 and the second end of the capacitor C1 are connected with the current stage gate signal end. Thus, the capacitor C1 can maintain the stable potential of the second node through charge storage after obtaining the high potential of the second node, so as to ensure the continuous and reliable opening of the fourth thin film transistor T4, stably convert the time sequence signal CKA of the time sequence control end into the current stage gate signal Gn output, and avoid the distortion of the current stage gate signal Gn caused by the fluctuation of the potential of the second node. The pull-down maintaining module cooperates with the output module 20 and the stage transmission module 10 to ensure the high potential of the second node to drive the current stage gate signal Gn output in the stage transmission stage, and rapidly pull down the potential of the second node after the stage transmission is completed, so as to cooperate with the pull-down action of the potential control module 30 on the first node, so that the stage transmission transistor T0 realizes the three-terminal voltage difference zero because the gate, the drain and the source are all low potentials, thereby completely suppressing the voltage offset problem, ensuring the timing accuracy and signal stability of the current stage gate signal Gn output, and significantly improving the driving reliability and display quality of the GOA circuit.

[0076] Further, based on the first embodiment of the GOA circuit, the second embodiment of the GOA circuit driving method is proposed.

[0077] The GOA circuit driving method of the present application is applied to any one of the GOA circuits described above, is executed by a display device applied to the GOA circuit, and comprises the following implementation steps S10 to S20.

[0078] Step S10: In the stage transfer phase, a high potential signal of the high potential line VGH is transmitted to the first node by the potential control module 30 so that the stage transfer transistor T0 in the stage transfer module 10 transmits the high potential signal to the output module 20 via the second node.

[0079] In the embodiment, the high potential signal of the high potential line VGH is transmitted to the first node in the stage transfer phase, which ensures that the output module 20 electrically connected to the second node can be provided with the high potential signal when the stage transfer transistor T0 is turned on, realizes the compatibility with the original working logic of the GOA circuit, and ensures the normal progress of the signal cascade transmission.

[0080] Step S20: After the stage transfer is completed, a low potential signal of the low potential line VGL is transmitted to the first node by the potential control module 30 so that the potential of the second node electrically connected to the source of the stage transfer transistor T0 is continuously pulled low.

[0081] In the embodiment, the low potential signal of the low potential line VGL is transmitted to the first node by the potential control module 30 after the stage transfer is completed, thereby realizing the continuous pulling low of the potential of the second node electrically connected to the source of the stage transfer transistor T0, fundamentally avoiding the voltage offset problem of the stage transfer transistor T0 caused by long-term voltage imbalance, stabilizing the switching performance of the stage transfer transistor T0, completely blocking the abnormal leakage path of the high potential signal to the second node, thereby avoiding the output module 20 from being mistakenly turned on due to the abnormal rise of the potential of the second node, and finally ensuring the accuracy of the timing output of the GOA circuit and significantly improving the display quality of the display panel.

[0082] Further, in some other possible embodiments, the potential control module 30 comprises a second thin film transistor T2, the stage transfer module 10 comprises a third thin film transistor T3, and the step S20 of transmitting the low potential signal of the low potential line VGL to the first node by the potential control module 30 to continuously pull low the potential of the second node electrically connected to the source of the stage transfer transistor T0 can further comprise the following implementation steps S201 to S202.

[0083] Step S201: when the back-stage gate signal of the back-stage gate signal end and the pull-down control signal of the potential pull-down control end V0 are both effective levels, enabling the third thin film transistor T3 to transmit the low potential signal of the low potential line VGL to the second node electrically connected to the drain of the stage transmission transistor T0 under the driving of the back-stage gate signal, and enabling the second thin film transistor T2 to transmit the low potential signal to the first node electrically connected to the source of the stage transmission transistor T0 under the driving of the pull-down control signal.

[0084] In the embodiment, referring to Figure 2 When the back-stage gate signal and the pull-down control signal are both effective levels, the third thin film transistor T3 transmits the low potential signal of the low potential line VGL to the second node electrically connected to the drain of the stage transmission transistor T0 under the driving of the back-stage gate signal, and the second thin film transistor T2 transmits the low potential signal to the first node electrically connected to the source of the stage transmission transistor T0 under the driving of the pull-down control signal, so that the residual high potential of the first node and the second node can be quickly eliminated, the drain and the source potential of the stage transmission transistor T0 are synchronously reduced to the low level, the three-terminal voltage difference is instantaneously reset to zero under the low potential state of the gate of the stage transmission transistor T0 at this time, and the generation of voltage offset is inhibited from the root.

[0085] It should be noted that the pull-down control signal can be any one of the current-stage gate signal Gn, the back-stage gate signal Gn+1 and the timing signal CKA.

[0086] Step S202: maintaining the potential of the second node to be continuously pulled down according to the low potential signals accessed by the first node and the second node.

[0087] In the embodiment, the low potential signals stably accessed by the first node and the second node are used to build a "double maintenance" mechanism to maintain the second node to be continuously at a low potential. Specifically, the low potential of the first node keeps the stage transmission transistor T0 in an off state, blocking the conduction path of the high potential signal to the second node, thereby avoiding the potential of the second node from rising from the source; and the low potential accessed by the second node directly inhibits the potential drift of the second node due to the parasitic capacitor C1 or interference, thereby ensuring that the second node always maintains a low level after stage transmission, providing a clean initial state for the stage transmission process of the next-stage GOA unit, completely eliminating the risk of the output module 20 being mistakenly turned on due to the abnormal potential of the second node, further ensuring the stability of the GOA circuit timing control, and improving the reliability and picture quality of the display panel.

[0088] Further, in some possible embodiments, the step S202 of maintaining the potential of the second node at the low potential signal can further include the following steps S2021 and S2022.

[0089] The step S2021 includes: in response to the change of the gate-first signal provided by the gate-first signal terminal to the gate of the stage transmission transistor T0 from the effective potential to the invalid level, determining that the gate potential of the stage transmission transistor T0 is the low potential of the invalid level, the drain potential of the stage transmission transistor T0 is the low potential signal connected to the first node, and the source potential of the stage transmission transistor T0 is the low potential signal connected to the second node, so as to maintain the off state of the stage transmission transistor T0.

[0090] In the embodiment, in response to the change of the gate-first signal provided by the gate-first signal terminal to the gate of the stage transmission transistor T0 from the effective potential to the invalid level, the gate potential of the stage transmission transistor T0 can be accurately obtained to be reduced to the low potential synchronously when the gate-first signal is at the invalid level, the drain potential of the stage transmission transistor T0 is the low potential signal connected to the first node, and the source potential of the stage transmission transistor T0 is the low potential signal connected to the second node, so that the stage transmission transistor T0 forms a balanced state of “gate-drain-source all at low potential”, and the stage transmission transistor T0 can be quickly and stably maintained in the off state after the stage transmission is completed, the abnormal leakage path of the high potential signal from the first node to the second node is completely blocked, the voltage offset problem caused by the incomplete off state of the stage transmission transistor T0 is avoided from the root, and the display quality of the display panel is significantly improved.

[0091] The step S2022 includes: enabling the potential of the second node to be continuously pulled down in the off state.

[0092] In the embodiment, the potential of the second node is continuously pulled down when the stage transmission transistor T0 is in the off state, the output module 20 is prevented from being mistakenly turned on due to the abnormal potential of the second node, the output disorder of the current stage gate-first signal Gn is avoided, and a clean and stable initial potential environment is provided for the stage transmission process of the next stage GOA unit.

[0093] In summary, the potential control module 30 is arranged in the GOA circuit, and the high potential signal of the high potential line VGH is transmitted to the first node through the potential control module 30 in the stage transmission stage, so that the stage transmission transistor T0 in the stage transmission module 10 can transmit the high potential signal to the output module 20 through the electrically connected first node to realize normal display driving, and the low potential signal of the low potential line VGL is transmitted to the first node through the potential control module 30 after the stage transmission is completed, so that the potential of the second node connected to the source of the stage transmission transistor T0 is continuously pulled down, so that the zero bias state is formed between the drain (connected to the first node) and the source (connected to the second node) of the stage transmission transistor T0, which effectively avoids the threshold voltage drift of the stage transmission transistor T0 caused by voltage imbalance, thereby stabilizing the switching performance of the stage transmission transistor T0, completely blocking the abnormal leakage path of the high potential signal to the second node, thereby avoiding the output module 20 from being mistakenly opened due to the abnormal rise of the potential of the second node, and finally ensuring the accuracy of the timing output of the GOA circuit, and significantly improving the display quality of the display panel.

[0094] In addition, the application further provides a display panel, which comprises a color film substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color film substrate, and the array substrate comprises the GOA circuit of any one of the above.

[0095] In addition, the application further provides a display device. Please refer to Figure 10 , Figure 10 is a structural schematic diagram of a display device related to the embodiment scheme of the application. The display device of the embodiment of the application can be a device running the GOA circuit driving method locally.

[0096] As Figure 10 shown, the display device of the embodiment of the application can comprise a display panel, or a processor 1001 such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004 and a memory 1005. The communication bus 1002 is used to realize the connection and communication among these components. The user interface 1003 can comprise a display screen (Display) and an input unit such as a keyboard (Keyboard), and the optional user interface 1003 can further comprise a standard wired interface and a wireless interface. The network interface 1004 can optionally comprise a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0097] The memory 1005 is disposed on the display device main body, and a program is stored on the memory 1005, which, when executed by the processor 1001, implements corresponding operations. The memory 1005 is also used to store parameters for use by the display device. The memory 1005 can be a high-speed RAM memory or a stable memory (non-volatile memory) such as a disk memory. The memory 1005 can also be an optional storage device independent of the aforementioned processor 1001.

[0098] Those skilled in the art can understand that Figure 10 The display device structure shown in the above embodiments does not constitute a limitation on the display device, and can include more or fewer components than shown, or combine certain components, or different component arrangements.

[0099] As Figure 10 As shown, the memory 1005 as a storage medium can include an operating system, a network communication module, a user interface module, and a charging driver.

[0100] In the display device shown in Figure 10 The processor 1001 can be used to call the charging driver stored in the memory 1005 and execute the steps of the GOA circuit driving method as described above.

[0101] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles, or systems that include a series of elements not only include those elements, but also include other elements not explicitly listed, or other elements inherent to such processes, methods, articles, or systems. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or system that includes the element.

[0102] The above-mentioned embodiment numbers of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0103] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software and a necessary general hardware platform, of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a disk, an optical disk) as described above, and includes a plurality of instructions for causing a display device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application.

[0104] The above merely provides the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structure or equivalent flowchart transformation based on the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A GOA circuit, characterized in that: The GOA circuit includes: a stage transmission module, the stage transmission module comprising a stage transmission transistor, the drain of the stage transmission transistor being electrically connected to the first node, and the source of the stage transmission transistor being electrically connected to the second node; an output module, wherein a gate control terminal of the output module is electrically connected to the second node; A potential control module, wherein the transmission ends on both sides of the potential control module are electrically connected to the first node and the low potential line respectively, and the high potential end of the potential control module is electrically connected to the high potential line. The potential control module is configured to transmit the high potential signal of the high potential line to the first node during the stage transmission stage so that the stage transmission transistor can transmit the high potential signal to the output module via the second node, and after the stage transmission is completed, transmit the low potential signal of the low potential line to the first node so that the potential of the second node electrically connected to the source of the stage transmission transistor is continuously pulled down.

2. The GOA circuit according to claim 1, wherein: The GOA circuit includes a potential-lowering control terminal, and the potential control module includes a first thin-film transistor and a second thin-film transistor; The first channel end of the first thin film transistor constitutes the high potential end of the potential control module and is electrically connected to the high potential line, the gate end of the first thin film transistor is electrically connected to the previous gate signal end, and the second channel end of the first thin film transistor constitutes one of the two transmission ends and is electrically connected to the first node; The first channel end of the second thin film transistor is electrically connected to the first node, the second channel end of the second thin film transistor constitutes the other side transmission end of the two side transmission ends and is electrically connected to the low potential line, and the gate end of the second thin film transistor is electrically connected to the potential pull-down control end.

3. The GOA circuit according to claim 2, wherein: When the potential-lowering control terminal is any one of the current-stage gate signal terminal, the subsequent-stage gate signal terminal, and the timing control terminal, the gate of the stage-pass transistor is electrically connected to the previous-stage gate signal terminal.

4. The GOA circuit according to claim 2, wherein: When the potential-lowering control terminal is the subsequent-stage gate signal terminal, the gate of the stage-pass transistor is electrically connected to the drain of the stage-pass transistor.

5. The GOA circuit according to claim 1, wherein: The stage transmission module further includes a third thin film transistor, wherein a first channel end of the third thin film transistor is electrically connected to the low potential line, and a second channel end of the third thin film transistor is electrically connected to the second node; The output module includes a fourth thin film transistor and a capacitor, the gate terminal of the fourth thin film transistor and the first end of the capacitor are electrically connected to the second node, the first channel end of the fourth thin film transistor is electrically connected to the timing control end, and the second channel end of the fourth thin film transistor and the second end of the capacitor are respectively electrically connected to the current stage gate signal end.

6. A GOA circuit driving method, characterized in that: The GOA circuit driving method is applied to the GOA circuit according to any one of claims 1 to 5, and the GOA circuit driving method includes: In the stage transmission phase, the high potential signal of the high potential line is transmitted to the first node through the potential control module so that the stage transmission transistor in the stage transmission module transmits the high potential signal to the output module via the second node; After the stage transfer is completed, the potential control module transmits a low potential signal of the low potential line to the first node so that the potential of the second node electrically connected to the source of the stage transfer transistor is continuously pulled down.

7. The GOA circuit driving method according to claim 6, wherein: The potential control module includes a second thin film transistor, and the stage transmission module includes a third thin film transistor. The step of transmitting the low potential signal of the low potential line to the first node through the potential control module so as to continuously lower the potential of the second node electrically connected to the source of the stage transmission transistor includes: When the rear-stage gate signal of the rear-stage gate signal terminal and the pull-down control signal of the potential pull-down control terminal are both at valid levels, the third thin-film transistor is enabled to transmit the low-potential signal of the low-potential line to the second node electrically connected to the source of the stage-pass transistor under the drive of the rear-stage gate signal, and the second thin-film transistor is enabled to transmit the low-potential signal to the first node electrically connected to the source of the stage-pass transistor under the drive of the pull-down control signal; The potential of the second node is kept continuously low according to the low potential signals inputted into the first node and the second node.

8. The GOA circuit driving method according to claim 7, wherein: The step of maintaining the potential of the second node continuously low according to the low potential signals connected to the first node and the second node comprises: In response to the pre-stage gate signal provided by the pre-stage gate signal terminal to the gate of the stage pass transistor being switched from a valid potential to an invalid level, determining that the gate potential of the stage pass transistor is a low potential of the invalid level, the drain potential of the stage pass transistor is a low potential signal connected to the first node, and the drain potential of the stage pass transistor is a low potential signal connected to the second node, so as to maintain the cut-off state of the stage pass transistor; The potential of the second node is enabled to be continuously pulled down in the cut-off state.

9. A display panel, characterized in that: The display panel includes a color filter substrate, a liquid crystal layer and an array substrate. The liquid crystal layer is provided between the array substrate and the color filter substrate. The array substrate includes the GOA circuit according to any one of claims 1 to 5.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9; or, A memory, a processor, and a charging driver program stored in the memory and executable on the processor, wherein the processor implements the steps of the GOA circuit driving method according to any one of claims 6 to 8 when executing the charging driver program.

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