Gray code synchronization detection method and device, equipment and medium
By obtaining the timing parameters and path delay time of the Gray code generation circuit, determining the maximum path delay deviation, and using a synchronization strategy to adjust the circuit, the reliability problem of the Gray code synchronization chain is solved and high-reliability data transmission is achieved.
Patent Information
- Application Number
- CN202511076711.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-01
- Publication Date
- 2025-10-17
AI Technical Summary
In the existing technology, Gray code synchronization chains have combinational logic delays or routing deviations during the synthesis or routing process, resulting in multi-bit transitions in adjacent clock cycles, reducing reliability and posing the risk of data errors. Static timing analysis tools fail to effectively detect such problems.
By obtaining the timing parameters of the Gray code generation circuit, the path delay time and the maximum path delay deviation are determined. Based on this, the Gray code synchronization strategy is determined and the circuit is adjusted, including timing constraints and path layout strategies, to ensure the single-bit change characteristics.
The reliability of the Gray code synchronization chain is improved, the risk of data errors is avoided, the correct judgment of the empty and full status of the FIFO is ensured, and a high-reliability design guarantee is provided.
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Figure CN120811560A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of communication, in particular to a Gray code synchronization detection method, device, equipment and medium. BACKGROUND
[0002] Asynchronous First In First Out (FIFO) uses Gray code to encode read-write pointers, ensuring that there is only 1bit change between adjacent states, reducing the metastability risk of cross-clock domain transmission. However, there is a combination logic delay or wiring deviation in the synthesis or wiring process, resulting in multiple bit jumps of Gray code in adjacent clock cycles. The delay deviation between different bits of the Gray code synchronization chain is ignored in the conventional synthesis and timing analysis tool and static timing analysis, resulting in reduced reliability of the Gray code synchronization chain, and even the risk of data error.
[0003] Therefore, how to check the delay deviation between different bits of the Gray code synchronization chain to improve reliability is an urgent problem for those skilled in the art to solve. SUMMARY
[0004] The purpose of the present application is to provide a Gray code synchronization detection method, device, equipment and medium to solve the problem of reduced reliability and the risk of data error caused by delay deviation between different bits of the Gray code synchronization.
[0005] To solve the above technical problems, the present application provides a Gray code synchronization detection method applied to a plurality of Gray code generation circuits, each comprising a Gray code generation register and an asynchronous register, and each using different clock parameters; the data output end of the Gray code generation register is connected to the data input end of the asynchronous register; the method comprises:
[0006] Obtaining the timing parameters of a plurality of Gray code synchronization paths composed of Gray code generation registers and asynchronous registers in a plurality of Gray code generation circuits;
[0007] Determining the corresponding path delay time according to the timing parameters of the plurality of Gray code synchronization paths, and determining the maximum path delay deviation based on the plurality of path delay times;
[0008] Determining the Gray code synchronization strategy according to the relationship between the maximum path delay deviation and the preset path delay deviation, and adjusting the Gray code generation circuit based on the Gray code synchronization strategy.
[0009] On the one hand, the timing parameters are used to represent the data propagation time parameters between the Gray code generation register and the asynchronous register; the collection process of the timing parameters comprises:
[0010] acquire a first level register of an asynchronous register corresponding to the asynchronous advanced first-in first-out write pointer;
[0011] set a bit width parameter of the gray code generation register, and each of the plurality of first level registers corresponds to a bit width parameter;
[0012] poll the data propagation time parameter of the data output terminal of the plurality of gray code generation registers to the data input terminal of the corresponding connected first level register to serve as the timing parameter.
[0013] On the other hand, the timing parameter of the plurality of gray code synchronization paths is determined according to the path delay time of the corresponding path, which includes:
[0014] determine the first path delay time of the first clock source through the clock input terminal and the data output terminal of the current gray code generation register, and reaching the data input terminal of the corresponding first level register;
[0015] determine the first clock delay time of the first clock source reaching the clock input terminal of the current gray code generation register;
[0016] determine the second clock delay time of the second clock source reaching the clock input terminal of the first level register;
[0017] determine the path delay time of the gray code synchronization path corresponding to the current gray code generator based on the first path delay time, the first clock delay time and the second clock delay time.
[0018] On the other hand, the determination process of the first path delay time specifically includes:
[0019] based on the logic synthesis tool to grab the path timing report, wherein the path timing report is the timing report of the first path of the first clock source through the clock input terminal and the data output terminal of the current gray code generation register, and reaching the data input terminal of the corresponding first level register;
[0020] extract the arrival time of the first path according to the path timing report as the first path delay time.
[0021] On the other hand, the determination process of the first path delay time specifically includes:
[0022] add the first clock delay time and the first path delay time to obtain the first delay time;
[0023] Subtracting the first delay time and the second clock delay time obtains a second delay time as the path delay time.
[0024] On the other hand, determining a maximum path delay deviation based on the plurality of path delay times, comprising:
[0025] Determining a maximum path delay time and a minimum path delay time among the plurality of path delay times;
[0026] Determining a maximum path delay deviation according to the maximum path delay time and the minimum path delay time.
[0027] On the other hand, determining a Gray code synchronization strategy according to the relationship between the maximum path delay deviation and a preset path delay deviation, and adjusting the Gray code generation circuit based on the Gray code synchronization strategy, comprising:
[0028] In the case that the maximum path delay deviation is less than or equal to the preset path delay deviation, determining that the plurality of Gray code generation circuits are synchronized;
[0029] In the case that the maximum path delay deviation is greater than the preset path delay deviation, determining that the plurality of Gray code generation circuits have a potential multi-bit flip risk;
[0030] Determining a timing constraint synchronization strategy and a path layout strategy based on the multi-bit flip risk, and adjusting the Gray code generation circuit according to the timing constraint synchronization strategy and / or the path layout strategy;
[0031] Correspondingly, the determination process of the timing constraint synchronization strategy, comprising:
[0032] Pre-determining a clock deviation corresponding to the first clock source and the second clock source;
[0033] Adjusting the clock deviation according to a first adjustment step to determine an adjusted clock deviation;
[0034] Determining a new first clock source according to the adjusted clock deviation and the second clock source;
[0035] Applying the new first clock source to the Gray code generation register to realize the timing constraint synchronization strategy;
[0036] Correspondingly, the determination process of the path layout strategy, comprising:
[0037] Determining a path length between a data output end of the Gray code generation register and a data input end of the first level register;
[0038] shorten the path length according to the second adjustment step to obtain an adjusted path length;
[0039] wire the first level register and the gray code generation register according to the adjusted path length to implement a path layout strategy.
[0040] To solve the above technical problems, the application further provides a detection device for gray code synchronization, which is applied to multiple gray code generation circuits, and includes gray code generation registers and asynchronous registers, and each uses different clock parameters; a data output end of the gray code generation register is connected to a data input end of the asynchronous register; the device includes:
[0041] an acquisition module, which is used to acquire timing parameters of multiple gray code synchronization paths composed of gray code generation registers and asynchronous registers in multiple gray code generation circuits;
[0042] a determination module, which is used to determine corresponding path delay times according to the timing parameters of the multiple gray code synchronization paths, and determine a maximum path delay deviation based on the multiple path delay times;
[0043] a processing module, which is used to determine a gray code synchronization strategy according to a relationship between the maximum path delay deviation and a preset path delay deviation, and adjust the gray code generation circuit based on the gray code synchronization strategy.
[0044] To solve the above technical problems, the application further provides an electronic device, which includes:
[0045] a memory, which is used to store a computer program;
[0046] a processor, which is used to execute the computer program to implement the steps of the detection method for gray code synchronization.
[0047] To solve the above technical problems, the application further provides a computer readable storage medium, which has a computer program stored thereon, and the computer program is executed by a processor to implement the steps of the detection method for gray code synchronization.
[0048] The beneficial effects of the present application are that, first, automatic timing analysis is performed in multiple Gray code generation circuits, the path information and clock arrival information corresponding to the timing parameters are automatically extracted based on the timing parameters of multiple Gray code synchronization paths composed of Gray code generation registers and asynchronous registers in multiple Gray code circuits, manual checking errors are avoided, and the checking accuracy is improved. Secondly, the path delay time corresponding to the timing parameters of the multiple Gray code synchronization paths is determined, and the clock cycle is used for judgment, which can effectively identify and quantify the path delay time of different clock domains, prevent data statistical errors, and also improve the accuracy of data collection. Based on the maximum path delay deviation determined by the multiple path delay times, the maximum delay deviation between different bits corresponding to different asynchronous registers is determined while realizing cross-clock domain data transmission, ensuring the single-bit change characteristic of the Gray code. Finally, the Gray code synchronization strategy is determined according to the relationship between the maximum path delay deviation and the preset path delay deviation. If it is less than or equal to, it means that the Gray code synchronization is detected and meets the design requirements. If it is greater than, it means that there is a potential multi-bit flip risk, which leads to the error of the empty and full state judgment of the FIFO. The Gray code generation circuit is adjusted and processed by using the Gray code synchronization strategy, which reduces the risk of data errors in the design and provides strong protection for high reliability design. In summary, the delay deviation detection process between different bits of the Gray code synchronization chain is filled, the reliability is improved, and the risk of data errors is avoided.
[0049] The collection process of the timing parameters is based on the polling of the paths of N Gray code generation registers to the first level register to realize automatic collection and improve the accuracy and flexibility of the collection process. Based on the above three delay time determination processes, the path delay time is finally determined, which can actively identify the delay time of the Gray code synchronization path compared with the traditional STA method, so as to calculate the maximum path delay deviation and ensure the single-bit change characteristic. The path timing report is grabbed through the logic synthesis tool, the timing, area and power consumption are optimized, the design is ensured to meet the functional requirements, and the physical function can be efficiently realized. The timing parameters are extracted from the path timing report, which ensures that the circuit can work normally under the specified clock frequency. The different strategy adjustment and strategy determination process of adjusting and processing the Gray code generation circuit based on the Gray code synchronization strategy reduces the maximum path delay deviation and also ensures the reliability of the adjustment and processing.
[0050] In addition, the present application also provides a Gray code synchronization detection device, equipment and medium, which has the same beneficial effects as the above-mentioned Gray code synchronization detection method. BRIEF DESCRIPTION OF DRAWINGS
[0051] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0052] Figure 1 A flowchart of a Gray code synchronization detection method provided by an embodiment of the present invention;
[0053] Figure 2 A schematic structural diagram of a Gray code generation circuit provided by an embodiment of the present invention;
[0054] Figure 3 A schematic diagram of a Gray code synchronization path provided by an embodiment of the present invention;
[0055] Figure 4 A schematic diagram of a path for determining a first path delay time provided by an embodiment of the present invention;
[0056] Figure 5 A schematic diagram of a path for determining a first clock delay time provided by an embodiment of the present invention;
[0057] Figure 6 A schematic diagram of a path for determining a second clock delay time provided by an embodiment of the present invention;
[0058] Figure 7 A structural diagram of a Gray code synchronization detection device provided by an embodiment of the present invention;
[0059] Figure 8 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.
[0061] The core of the present invention is to provide a Gray code synchronization detection method, device, equipment and medium to solve the problem that the delay deviation between different bits of Gray code synchronization leads to reduced reliability and the risk of data errors.
[0062] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0063] In modern digital systems, asynchronous FIFOs are widely used to solve the problem of multi-bit data exchange between different clock domains to avoid metastability issues that may arise from cross-clock-domain data transmission. Since there is no fixed phase relationship between different clock domains, directly transmitting multi-bit data may cause metastability when registers are sampled, which in turn affects system reliability. Therefore, the design of asynchronous FIFOs usually uses Gray Code to encode read and write pointers to ensure that only 1 bit changes between adjacent states, thereby reducing the risk of metastability during cross-clock-domain transmission.
[0064] In FIFO read-write management, the write pointer needs to be synchronized across clock domains to the read clock domain, and vice versa. To ensure data stability, a two-level register synchronization chain is usually used to implement cross-clock-domain transmission. However, if the synchronization chain has excessive combinational logic delay or routing deviation during synthesis or placement and routing (P&R), it may cause the synchronized Gray Code to have multi-bit jumps (i.e., non-single-bit changes) within adjacent clock cycles, thereby disrupting the FIFO's empty and full state judgment logic. This anomaly may cause the FIFO read pointer or write pointer to enter an unknown state, ultimately leading to serious problems such as data overwrite or read underflow.
[0065] To prevent the risks caused by synchronization chain delay mismatch, a "max_delay" constraint is usually imposed on the synchronization chain in the design to limit the maximum delay difference between different bit Gray Code signals. However, existing synthesis and timing analysis tools (such as Synopsys Design Compiler) usually skip timing checks for paths declared as asynchronous, which means that even if a "max_delay" constraint is imposed, if the constraint is not applied correctly or the P&R tool does not strictly optimize the layout of the synchronization registers, the actual delay of the synchronization chain may still exceed the limit, thereby disrupting the single-bit jump feature of the Gray Code. Since static timing analysis (STA) tools skip the analysis of asynchronous paths by default, this type of problem may not be directly exposed in the regular timing report, resulting in potential risks that are not discovered in time before tape-out.
[0066] Currently, the conventional static timing analysis mainly focuses on timing closure, and there is no special checking mechanism for the maximum delay skew between different bits of the Gray code synchronization chain. Although the simulation method can expose some timing problems under specific test vectors, it cannot guarantee comprehensive coverage of all timing corner cases. The Gray code synchronization detection method provided by the present application can solve the above technical problems.
[0067] Figure 1 A flowchart of a Gray code synchronization detection method provided by an embodiment of the present application is shown in Figure 1 application to a plurality of Gray code generation circuits, including a Gray code generation register and an asynchronous register, and each uses different clock parameters; the data output end of the Gray code generation register is connected to the data input end of the asynchronous register; the method comprises:
[0068] S11: obtaining timing parameters of a plurality of Gray code synchronization paths composed of Gray code generation registers and asynchronous registers in the plurality of Gray code generation circuits;
[0069] S12: determining corresponding path delay times according to the timing parameters of the plurality of Gray code synchronization paths, and determining a maximum path delay skew based on the plurality of path delay times;
[0070] S13: determining a Gray code synchronization strategy according to the relationship between the maximum path delay skew and a preset path delay skew, and adjusting the Gray code generation circuit based on the Gray code synchronization strategy.
[0071] Specifically, the plurality of Gray code generation circuits, Figure 2 A structural schematic diagram of a Gray code generation circuit provided by an embodiment of the present application is shown in Figure 2 There are N bit Gray code generation circuits in one Gray code generation circuit, including a Gray code generation register and an asynchronous register. The Gray code generation register and the asynchronous register have different clock source parameters, and in Figure 2 the first clock source (CLK_A) and the second clock source (CLK_B) are used, which constitutes an asynchronous FIFO. The Gray code generation register works under the first clock source, is used to generate a Gray code register, and the input signal is converted into a Gray code through encoding logic. The asynchronous register at least includes a first level register, and the asynchronous register is synchronized under the second clock source, and is connected with the Gray code generation register through a logic gate, and the logic gate is used for further processing and synchronization of the Gray code when crossing the clock domain, to ensure the stability of the data. The data output end of the Gray code generation register is connected to the data input end of the asynchronous register.
[0072] The timing parameters of the multiple Gray code synchronization paths composed of the Gray code generation registers and the asynchronous registers are obtained in the multiple Gray code generation circuits, one Gray code generation circuit includes one Gray code synchronization path, and the timing parameters of the Gray code synchronization path include a data arrival time, a clock arrival time, and the like. The timing parameters are top indicators for measuring whether the timing of the combinational logic converges. The timing parameters can be the time when the data arrives or the arrival time set by different clock sources.
[0073] The multiple timing parameters in step S12 determine the corresponding path delay times. The path delay time is the data propagation time from the data output end of the Gray code generation register to the data input end of the first level register. Figure 2 The path delay times corresponding to the same clock source in the N asynchronous registers are determined, that is, the N path delay times. The maximum path delay deviation is determined in the N path delay times. The determination of the path delay time is the data propagation time from the data output end of the Gray code generation register to the data input end of the first level register.
[0074] In step S13, the Gray code synchronization strategy is determined according to the relationship between the maximum path delay deviation and the preset path delay deviation. When the maximum path delay deviation is greater than the preset path delay deviation, it indicates that there is a risk of multi-bit transition across the clock domain, and the adjustment strategy of the Gray code synchronization needs to be designed. When the maximum path delay deviation is less than or equal to the preset path delay deviation, it indicates that there is no multi-bit transition, that is, the Gray code synchronization. The adjustment strategy of the Gray code synchronization adjusts the Gray code generation circuit. The adjustment includes timing constraints and optimized layout and wiring.
[0075] In addition, the detection method provided in the embodiment can be after the synthesis and timing analysis tool and the static timing analysis, or before or in the middle, which is not limited herein.
[0076] The beneficial effects of the embodiments of the present invention are as follows: first, automated timing analysis is performed in multiple Gray code generation circuits, and based on the timing parameters of multiple Gray code synchronization paths composed of Gray code generation registers and asynchronous registers in multiple Gray code circuits, the path information and clock arrival information corresponding to the timing parameters are automatically extracted, thereby avoiding errors in manual inspection and improving inspection accuracy. Secondly, the corresponding path delay time is determined according to the timing parameters of multiple Gray code synchronization paths. Here, by judging the clock cycle, it is possible to effectively identify and quantify different path delay times across clock domains, thereby preventing data statistical errors and improving the accuracy of collected data. Based on multiple path delay times, the maximum path delay deviation is determined. While realizing cross-clock domain data transmission, the maximum delay deviation between different bits corresponding to different asynchronous registers is determined to ensure the single-bit change characteristics of the Gray code. Finally, the Gray code synchronization strategy is determined based on the relationship between the maximum path delay deviation and the preset path delay deviation. If it is less than or equal to, it means that Gray code synchronization is detected, which meets the design requirements. If the value is greater than , it indicates a potential risk of multiple bit flips, leading to incorrect judgments about the FIFO's empty or full state. This Gray code synchronization strategy is used to adjust the Gray code generation circuit, reducing the risk of data errors in the design and providing strong support for high-reliability designs. In short, the delay deviation detection process between different bits in the Gray code synchronization chain is improved, improving reliability while avoiding the risk of data errors.
[0077] In some embodiments, the timing parameters are used to characterize the data propagation time parameters between the Gray code generation register and the asynchronous register. The acquisition process of the timing parameters includes:
[0078] Get the first-level register of the asynchronous register corresponding to the asynchronous first-in-first-out write pointer;
[0079] Setting a bit width parameter of a Gray code generating register, wherein each of the plurality of first-level registers corresponds to a bit width parameter;
[0080] The data propagation time parameters from the data output terminals of the plurality of Gray code generating registers to the data input terminals of the corresponding first-level registers are collected by polling to serve as timing parameters.
[0081] It should be noted that the first level register set of the asynchronous FIFO write pointer Gray code synchronization is obtained and stored in the list gray_sync_reg_list. Assuming that the Gray code register bit width is N, each register corresponds to a bit of the Gray code, there are N elements in the list, and the specific content is: gray_sync_reg_list=[Gray_sync1_REG[0], Gray_sync1_REG[1], …, Gray_sync1_REG[N-1]]. The above register list is the key part of the Gray code synchronization chain, and subsequent timing analysis will be carried out around them.
[0082] The data path delay of the N registers is calculated by polling all elements in the list gray_sync_reg_list, that is, the data propagation time from the Q end of the Gray code generation register to the D end of the first level register. Figure 3 A schematic diagram of a Gray code synchronization path is provided for the embodiment of the present application, and the i-th path is taken as an example. The path is Gray_gen_REG[i] / Q→Gray_sync1_REG[i] / D.
[0083] The collection process of the timing parameters provided by the embodiment is based on polling the paths of the N Gray code generation registers to the first level register, so as to realize automatic collection and improve the accuracy and flexibility of the collection process.
[0084] In some embodiments, the path delay time of the corresponding path is determined according to the timing parameters of the plurality of Gray code synchronization paths, including:
[0085] The first path delay time is determined, in which the first clock source passes through the clock input end and the data output end of the current Gray code generation register and reaches the data input end of the corresponding first level register;
[0086] The first clock delay time is determined, in which the first clock source reaches the clock input end of the current Gray code generation register;
[0087] The second clock delay time is determined, in which the second clock source reaches the clock input end of the first level register;
[0088] The path delay time of the Gray code synchronization path corresponding to the current Gray code generator is determined based on the first path delay time, the first clock delay time and the second clock delay time.
[0089] Specifically, the data reaches the path delay, Figure 4 A determination path schematic diagram of the first path delay time is provided for the embodiment of the present application, as shown in Figure 4The first path delay time data_arrival is shown in FIG. 2, which is the first path delay time from the clock input end Gray_gen_REG[i] / CP of the i-th Gray code generation register Gray_gen_REG[i] to the data input end of the corresponding first level register Gray_sync1_REG[i] / D.
[0090] The Gray code generation register clock arrival delay time, Figure 5 A first clock delay time determination path diagram provided for the embodiment of the present application is shown in FIG. 3. Figure 5 The first clock delay time gray_gen_cp_delay is shown in FIG. 3, which is the first clock delay time from the clock input end Gray_gen_REG[i] / CP of the i-th Gray code generation register Gray_gen_REG[i] to the corresponding first clock delay time.
[0091] The first level register clock arrival delay time, Figure 6 A second clock delay time determination path diagram provided for the embodiment of the present application is shown in FIG. 4. Figure 6 The second clock delay time data_capture_clk_delay is shown in FIG. 4, which is the arrival time from the clock input end Gray_sync1_REG[i] / CP of the i-th Gray code generation register Gray_sync1_REG[i] to the second clock delay time.
[0092] Based on the above three delay times, the path delay time of the corresponding Gray code synchronization path of the i-th Gray code generator is determined. The calculation process here can be addition, subtraction, etc., which is not limited.
[0093] The determination process based on the above three delay times provided by the embodiment is used to finally determine the path delay time. Compared with the traditional STA method, the delay time of the Gray code synchronization path can be actively identified to calculate the maximum path delay deviation and ensure the single bit change characteristic.
[0094] In some embodiments, the determination process of the first path delay time specifically includes:
[0095] Based on the logic synthesis tool to grab the path timing report, wherein the path timing report is the timing report of the first path from the clock input end and the data output end of the current Gray code generation register to the data input end of the corresponding first level register by the first clock source;
[0096] According to the path timing report, the arrival time of the first path is extracted as the first path delay time.
[0097] On the basis of the above embodiments, the path timing report, i.e. the timing report of path delay, is captured based on a logic synthesis tool (such as a Design Compiler (DC) tool). The logic synthesis tool is a tool for converting design intent into a circuit netlist that can be used for layout and routing. The timing report is a document or data file used in digital integrated circuit design to evaluate and verify the timing performance of a circuit. It provides detailed information about each timing path in the circuit, including delay, clock information, etc., to help designers ensure that the circuit can work normally at the specified clock frequency.
[0098] The arrival time of the first path is extracted according to the path timing report as the first path delay time, and the first path is Figure 4 the path corresponding to the arrow in the middle. It can be described by TCL script instruction as: set data_arrival [get_attribute[get_timing_path-to$gray_sync_reg / D]arrival].
[0099] Similarly, in the process of determining the first clock delay time and the second clock delay time, it is also realized based on the corresponding path timing report. Respectively, TCL script instruction is described as: set gray_gen_reg_cp [get_attribute[ get_timing_path-to$gray_sync_reg / D]startpoint];
[0100] Set gray_gen_cp_delay[get_attribute[get_timing_path-to$gray_gen_reg_cp-from[get_clocks $gray_gen_reg_clk]]arrival] to obtain the first clock delay time.
[0101] data_capture_clk_delay[get_attribute[get_timing_path-to$gray_sync_reg / CP-from[get_clocks $gray_sync_reg_clk]]arrival] to obtain the second clock delay time.
[0102] The embodiment provided by the embodiment provided by the logical synthesis tool captures the path timing report, optimizes the timing, area and power consumption, ensures that the design meets the functional requirements, and efficiently realizes the physical function. The extraction of the timing parameter of the path timing report ensures that the circuit can work normally at the specified clock frequency.
[0103] In some embodiments, determining the path delay time of the Gray code synchronization path corresponding to the current Gray code generator based on the first path delay time, the first clock delay time and the second clock delay time comprises:
[0104] Adding the first clock delay time and the first path delay time to obtain the first delay time;
[0105] Subtracting the first delay time and the second clock delay time to obtain the second delay time as the path delay time.
[0106] Adding the first clock delay time and the first path delay time to obtain the first delay time, subtracting the second clock delay time from the first delay time to obtain the second delay time as the path delay time, and the calculation process is the data path delay of Gray_gen_REG[i] / Q->Gray_sync1_REG[i] / D: gray_gen_cp_delay+data_arrival-data_capture_clk_delay.
[0107] The TCL script instruction can be described as: set slack[expr{$gray_gen_cp_delay+ $data_arrival-$data_capture_clk_latency}].
[0108] The embodiment provided by the embodiment provided by the logical synthesis tool captures the path timing report, optimizes the timing, area and power consumption, ensures that the design meets the functional requirements, and efficiently realizes the physical function. The extraction of the timing parameter of the path timing report ensures that the circuit can work normally at the specified clock frequency.
[0109] In some embodiments, determining the maximum path delay deviation based on a plurality of path delay times comprises:
[0110] Determining the maximum path delay time and the minimum path delay time in the plurality of path delay times;
[0111] Determining the maximum path delay deviation according to the maximum path delay time and the minimum path delay time.
[0112] It should be noted that the maximum path delay deviation is determined by sorting the path delay times of the N first-level registers, extracting the maximum path delay time and the minimum path delay time, and reflecting the maximum propagation delay difference between different bits of the Gray code synchronization path. As to why only the path between the first-level register and the Gray code generation register is determined in this embodiment, the second-level register and the first-level register belong to the same clock source, and the path deviation between them is almost small enough to affect the Gray code multiple bit transition, so only the path between the first-level register and the Gray code generation register is considered.
[0113] The determination process provided by the embodiment based on the maximum path delay deviation determined by the plurality of path delay times can reflect the maximum propagation delay difference between different bits of the Gray code synchronization path, and improve the judgment accuracy and reliability of the Gray code synchronization.
[0114] In some embodiments, the Gray code synchronization strategy is determined according to the relationship between the maximum path delay deviation and the preset path delay deviation, and the Gray code generation circuit is adjusted based on the Gray code synchronization strategy, including:
[0115] In the case that the maximum path delay deviation is less than or equal to the preset path delay deviation, the plurality of Gray code generation circuits are determined to be synchronized;
[0116] In the case that the maximum path delay deviation is greater than the preset path delay deviation, it is determined that the plurality of Gray code generation circuits have a potential multi-bit flip risk;
[0117] The timing constraint synchronization strategy and the path layout strategy are determined based on the multi-bit flip risk, and the Gray code generation circuit is adjusted according to the timing constraint synchronization strategy and / or the path layout strategy;
[0118] Correspondingly, the determination process of the timing constraint synchronization strategy includes:
[0119] The clock deviation corresponding to the first clock source and the second clock source is determined in advance;
[0120] The clock deviation is adjusted according to the first adjustment step to determine the adjusted clock deviation;
[0121] A new first clock source is determined according to the adjusted clock deviation and the second clock source;
[0122] The new first clock source is applied to the Gray code generation register to realize the timing constraint synchronization strategy;
[0123] Correspondingly, the determination process of the path layout strategy includes:
[0124] determine a path length between a data output end of the gray code generation register and a data input end of the first level register;
[0125] shorten the path length according to a second adjustment step to obtain an adjusted path length;
[0126] perform wiring processing on the first level register and the gray code generation register according to the adjusted path length to implement the path layout strategy.
[0127] Specifically, in the case that the maximum path delay deviation is greater than the preset path delay deviation, it is determined that the plurality of gray code generation circuits have a potential multi-bit flip risk. Based on such flip risk, two strategies can be determined, one is a timing constraint synchronization strategy, and the other is a path layout strategy. The gray code generation circuit is adjusted according to one of the two strategies or a combination of the two strategies.
[0128] For the timing constraint synchronization strategy, the clock deviation of the first clock source and the second clock source is determined in advance, and the clock deviation is adjusted according to a first adjustment step, which can increase the clock deviation to determine a new first clock source. After applying the first clock source to the gray code generation register, a new round of corresponding path delay time is collected.
[0129] For the path layout strategy, the path length between the data output end of the gray code generation register and the data input end of the first level register needs to be determined, and the path length is shortened according to a second adjustment step to shorten the wiring length corresponding to the path between the gray code generation register and the first level register for wiring processing.
[0130] Regarding the preset path delay deviation, it can be set as a percentage of a normal clock period, such as 0.9, or other parameters, which are not limited here and can be modified according to actual conditions.
[0131] In some embodiments, the gray code generation circuit is adjusted according to the timing constraint synchronization strategy and the path layout strategy, comprising:
[0132] In the timing constraint synchronization strategy, the adjustment times are obtained, and when the adjustment times reach a preset adjustment times, and the new maximum path delay deviation under each adjustment time is greater than the preset path delay deviation, it is determined that the timing constraint synchronization strategy is invalid;
[0133] The new first clock source of the first adjustment times in the timing constraint synchronization strategy is applied to the gray code generation register, and the wiring processing is performed using the path length of the first adjustment in the path layout strategy to obtain a new maximum path delay deviation, and returning to the step of determining the gray code synchronization strategy according to the relationship between the maximum path delay deviation and the preset path delay deviation.
[0134] Specifically, considering that the layout routing processing cost is large, the adjustment of the timing constraint synchronization strategy is preferentially performed, after multiple adjustments, and when the number of adjustments reaches a preset number of adjustments, and the maximum path delay deviation under each number of adjustments is greater than a preset path delay deviation, it is indicated that the deviation corresponding to each adjustment exists multi-bit jump. Therefore, it is necessary to return to the new first clock source corresponding to the first number of adjustments of the timing constraint synchronization strategy, and the path length of the first adjustment is routed using the path layout strategy. The adjustment process is the same as the above embodiment, and is not limited here.
[0135] The two strategies are mixed in the embodiment, and in the case where the timing constraint synchronization strategy is invalid, the new first clock source under the first number of adjustments and the path length of the first adjustment are routed based on the timing constraint synchronization strategy to obtain a new maximum path delay deviation, thereby avoiding potential multi-bit flip risk.
[0136] The different strategy adjustments and strategy determination processes of the Gray code generation circuit based on the Gray code synchronization strategy in the embodiment reduce the maximum path delay deviation while ensuring the reliability of the adjustment processing.
[0137] The above detailed description of the detection method of the Gray code synchronization corresponds to each embodiment, and on this basis, the application also discloses a detection device of Gray code synchronization corresponding to the above method, Figure 7 A structure diagram of a detection device of Gray code synchronization provided for the embodiment of the application is shown in FIG. 1. Figure 7 As shown in the figure, it is applied to a plurality of Gray code generation circuits, and includes a Gray code generation register and an asynchronous register, and each uses different clock parameters; the data output end of the Gray code generation register is connected to the data input end of the asynchronous register; the detection device of Gray code synchronization includes:
[0138] The acquisition module 11 is configured to acquire timing parameters of a plurality of Gray code synchronization paths composed of the Gray code generation register and the asynchronous register in the plurality of Gray code generation circuits;
[0139] The determination module 12 is configured to determine corresponding path delay times according to the timing parameters of the plurality of Gray code synchronization paths, and determine a maximum path delay deviation based on the plurality of path delay times;
[0140] The processing module 13 is configured to determine a Gray code synchronization strategy according to the relationship between the maximum path delay deviation and a preset path delay deviation, and perform adjustment processing on the Gray code generation circuit based on the Gray code synchronization strategy.
[0141] Since the embodiments of the device part correspond to the embodiments of the method part described above, the embodiments of the device part are described with reference to the embodiments of the method part described above, and will not be described here again.
[0142] For the detection device of the Gray code synchronization provided by the present application, please refer to the above-mentioned method embodiments, and the present application will not be described here again, which has the same beneficial effects as the above-mentioned Gray code synchronization detection method.
[0143] Figure 8 The structural diagram of an electronic device provided by the embodiments of the present application is shown in FIG. 1, which includes: Figure 8
[0144] The memory 21 is configured to store a computer program.
[0145] The processor 22 is configured to execute the computer program to implement the steps of the Gray code synchronization detection method.
[0146] The electronic device provided by the embodiments of the present application can include but is not limited to a smart phone, a tablet computer, a notebook computer, or a desktop computer, etc.
[0147] The processor 22 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 22 can be implemented in at least one of a hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array. The processor 22 can also include a main processor and a coprocessor. The main processor is a processor for processing data in a wake-up state, also known as a central processing unit (CPU). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 22 can be integrated with a graphics processing unit (GPU) for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 22 can also include an artificial intelligence (AI) processor for processing machine learning-related computing operations.
[0148] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used to store the following computer program 211, wherein, after the computer program is loaded and executed by the processor 22, it can implement the relevant steps of the Gray code synchronization detection method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include but is not limited to data involved in the Gray code synchronization detection method, etc.
[0149] In some embodiments, the electronic device may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a power supply 26 , and a communication bus 27 .
[0150] Those skilled in the art will understand that Figure 8 The structure shown in the figure does not constitute a limitation of the electronic device, and may include more or fewer components than shown in the figure.
[0151] The processor 22 implements the Gray code synchronization detection method provided by any of the above embodiments by calling the instructions stored in the memory 21 .
[0152] For an introduction to an electronic device provided by the present invention, please refer to the above method embodiment, and the present invention will not be described in detail here. It has the same beneficial effects as the above Gray code synchronization detection method.
[0153] Furthermore, the present invention also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by the processor 22 , the steps of the above-mentioned Gray code synchronization detection method are implemented.
[0154] It can be understood that if the method in the above embodiment is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the present application or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and performs all or part of the steps of the method of each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.
[0155] For the computer readable storage medium provided by the present application, please refer to the above method embodiment, and the present application will not be repeated here, which has the same beneficial effects of the above-mentioned gray code synchronization detection method.
[0156] The above provides a detailed introduction to the gray code synchronization detection method, device, equipment and medium provided by the present application. The embodiments in the specification are described in a progressive manner, and each embodiment mainly explains the difference from other embodiments. The same or similar parts of each embodiment can be referred to. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the related parts can be referred to the method part. It should be pointed out that for ordinary skilled in the art, without departing from the principle of the present application, the present application can be improved and modified, and these improvements and modifications also fall within the protection scope of the present application.
[0157] It should be further pointed out that in the present specification, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "include" "contain" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitation, the element defined by the sentence "including a…" does not exclude the presence of other identical elements in the process, method, article or equipment including the element.
Claims
1. A method for detecting Gray code synchronization, characterized in that: Applicable to multiple Gray code generation circuits, including Gray code generation registers and asynchronous registers, each using different clock parameters; The data output terminal of the Gray code generating register is connected to the data input terminal of the asynchronous register; the method comprises: obtaining timing parameters of a plurality of Gray code synchronization paths composed of Gray code generation registers and asynchronous registers in a plurality of Gray code generation circuits; Determining corresponding path delay times according to timing parameters of a plurality of Gray code synchronization paths, and determining a maximum path delay deviation based on the plurality of path delay times; A Gray code synchronization strategy is determined according to the relationship between the maximum path delay deviation and the preset path delay deviation, and the Gray code generation circuit is adjusted based on the Gray code synchronization strategy.
2. The Gray code synchronization detection method according to claim 1, wherein: The timing parameters are used to characterize the data propagation time parameters between the Gray code generation register and the asynchronous register; the acquisition process of the timing parameters includes: Get the first-level register of the asynchronous register corresponding to the asynchronous first-in-first-out write pointer; Setting a bit width parameter of a Gray code generating register, wherein each of the plurality of first-level registers corresponds to a bit width parameter; The data propagation time parameters from the data output terminals of the plurality of Gray code generating registers to the data input terminals of the corresponding first-level registers are collected by polling to serve as the timing parameters.
3. The Gray code synchronization detection method according to claim 2, characterized in that: Determining corresponding path delay times based on timing parameters of multiple Gray code synchronization paths includes: Determine a first path delay time of a first clock source passing through a clock input terminal and a data output terminal of a current Gray code generating register and reaching a data input terminal of a corresponding first-level register; Determining a first clock delay time corresponding to the first clock source reaching a clock input terminal of a current Gray code generating register; determining a second clock delay time for a second clock source to reach a clock input terminal of the first level register; The path delay time of the Gray code synchronization path corresponding to the current Gray code generator is determined based on the first path delay time, the first clock delay time, and the second clock delay time.
4. The method for detecting Gray code synchronization according to claim 3, wherein: The process of determining the first path delay time specifically includes: Capturing a path timing report based on a logic synthesis tool, wherein the path timing report is a timing report of a first path from a first clock source through a clock input terminal and a data output terminal of a current Gray code generating register and reaching a data input terminal of a corresponding first-level register; The arrival time of the first path is extracted according to the path timing report to serve as the first path delay time.
5. The method for detecting Gray code synchronization according to claim 3, wherein: Determining a path delay time of a Gray code synchronization path corresponding to the current Gray code generator based on the first path delay time, the first clock delay time, and the second clock delay time includes: Adding the first clock delay time and the first path delay time to obtain a first delay time; The first delay time and the second clock delay time are subtracted to obtain a second delay time as the path delay time.
6. The Gray code synchronization detection method according to claim 5, characterized in that: Determines the maximum path delay deviation based on multiple path delay times, including: determining a maximum path delay time and a minimum path delay time among a plurality of path delay times; A maximum path delay deviation is determined according to the maximum path delay time and the minimum path delay time.
7. The Gray code synchronization detection method according to any one of claims 3 to 6, characterized in that: Determining a Gray code synchronization strategy according to a relationship between a maximum path delay deviation and a preset path delay deviation, and adjusting the Gray code generation circuit based on the Gray code synchronization strategy, including: When the maximum path delay deviation is less than or equal to a preset path delay deviation, determining that the plurality of Gray code generating circuits are synchronized; When the maximum path delay deviation is greater than the preset path delay deviation, determining that a plurality of Gray code generation circuits have a potential multi-bit flip risk; Determining a timing constraint synchronization strategy and a path layout strategy based on the multi-bit flip risk, and adjusting the Gray code generation circuit according to the timing constraint synchronization strategy and / or the path layout strategy; Correspondingly, the process of determining the timing constraint synchronization strategy includes: Predetermining a clock deviation corresponding to the first clock source and the second clock source; Adjusting the clock deviation according to a first adjustment step to determine an adjusted clock deviation; determining a new first clock source according to the adjusted clock deviation and the second clock source; Applying a new first clock source to the Gray code generating register to implement a timing constraint synchronization strategy; Correspondingly, the process of determining the path layout strategy includes: determining a path length between a data output terminal of the Gray code generating register and a data input terminal of the first level register; shortening the path length according to a second adjustment step to obtain an adjusted path length; The first level registers and the Gray code generation registers are wired according to the adjusted path lengths to implement a path layout strategy.
8. A Gray code synchronization detection device, characterized in that: Applicable to multiple Gray code generation circuits, including Gray code generation registers and asynchronous registers, each using different clock parameters; The data output terminal of the Gray code generating register is connected to the data input terminal of the asynchronous register; the device comprises: An acquisition module, configured to acquire timing parameters of a plurality of Gray code synchronization paths composed of Gray code generation registers and asynchronous registers in a plurality of Gray code generation circuits; a determination module, configured to determine corresponding path delay times according to timing parameters of a plurality of Gray code synchronization paths, and determine a maximum path delay deviation based on the plurality of path delay times; The processing module is used to determine a Gray code synchronization strategy according to the relationship between the maximum path delay deviation and the preset path delay deviation, and adjust the Gray code generation circuit based on the Gray code synchronization strategy.
9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the Gray code synchronization detection method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for detecting Gray code synchronization according to any one of claims 1 to 7 are implemented.