A device expansion system, data processing method and device, and electronic device

Abstract

The application discloses a device expansion system, a data processing method and device, and electronic equipment, and relates to the technical field of computers, and comprises configuring multiple uplink and multiple downlink on a switching device, the multiple uplink is used for connecting multiple different core processors, and the downlink is used for connecting an expansion group comprising multiple expansion devices of the multiple core processors; the core processor can share access to all expansion devices connected by the downlink of the switching device through the non-transparent bridge function of the switching device; when any core processor fails, the other normal processor core can normally access the expansion device corresponding to the failed core processor, so that the expansion device cannot be accessed due to the failure of the core processor, and the safety of the expansion device is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a device expansion system, data processing method, apparatus, and electronic device. Background Technology

[0002] With the development of server intelligence, more and more expansion devices are being added to servers, such as high-speed serial computer expansion bus standard (PCIe) devices like Graphics Processing Units (GPUs) and Data Processing Units (DPUs). However, due to the limited access resources of the expansion devices of the core processor in the server, how to expand server devices has become a key research topic.

[0003] In related technologies, a switching device is attached to the core processor of a server to extend the access resources of the extended devices connected to the core processor. However, in servers with multiple core processors, if any core processor fails, the extended devices connected to the switching device attached to the failed core processor will become inaccessible, reducing the security of the extended devices. Summary of the Invention

[0004] This application provides a device expansion system, data processing method, apparatus, and electronic device to at least solve the problem in the related art that when any core processor malfunctions, the expansion devices connected to the switching devices under the malfunctioning core processor cannot be accessed, thus reducing the security of the expansion devices.

[0005] This application provides a device expansion system, including: multiple core processors and switching devices;

[0006] The switching equipment includes multiple uplinks and multiple downlinks;

[0007] Multiple uplinks are used to connect multiple core processors;

[0008] Multiple downlinks are used to connect an expansion group of multiple core processors, and the expansion group includes multiple expansion devices;

[0009] The non-transparent bridge function of the switching equipment is enabled;

[0010] Any core processor can access various expansion devices in the expansion groups of other core processors besides itself, based on the non-transparent bridge function of the switching device;

[0011] When any one of the multiple core processors fails, the normal core processors in the multiple core processors use the switching device to access the various expansion devices in the expansion group of the failed core processor.

[0012] This application also provides a data processing method applied to the device extension system described above, the method comprising:

[0013] When any core processor in the device expansion system malfunctions, the normal core processors in the device expansion system access each expansion device in the expansion group of the malfunctioning core processor through the switching device.

[0014] Back up the running data of each extended device in the extended group of the abnormal core processor to the preset backup cache;

[0015] Once the faulty core processor recovers, it retrieves the runtime data from the preset backup cache.

[0016] Restore the runtime data to each extended device;

[0017] The device expansion system includes multiple core processors and switching devices. The switching devices include multiple uplinks and multiple downlinks. The multiple uplinks are used to connect multiple core processors. The multiple downlinks are used to connect expansion groups of multiple core processors. The expansion groups include multiple expansion devices. The non-transparent bridge function of the switching devices is enabled. Any core processor can access each expansion device in the expansion group of other core processors (excluding the core processor itself) based on the non-transparent bridge function of the switching devices.

[0018] This application also provides a data processing apparatus for use in the aforementioned equipment extension system, the apparatus comprising:

[0019] The access module is used to access each expansion device in the expansion group of the abnormal core processor through the switching device when any core processor in the device expansion system malfunctions.

[0020] The backup module is used to back up the running data of each extended device in the extended group of the abnormal core processor to a preset backup cache.

[0021] The acquisition module is used to retrieve runtime data from a preset backup cache after the abnormal core processor recovers to normal.

[0022] The recovery module is used to restore runtime data to various extended devices;

[0023] The device expansion system includes multiple core processors and switching devices. The switching devices include multiple uplinks and multiple downlinks. The multiple uplinks are used to connect multiple core processors. The multiple downlinks are used to connect expansion groups of multiple core processors. The expansion groups include multiple expansion devices. The non-transparent bridge function of the switching devices is enabled. Any core processor can access each expansion device in the expansion group of other core processors (excluding the core processor itself) based on the non-transparent bridge function of the switching devices.

[0024] This application also provides a computing device, including: a chassis and an expansion system for the above-mentioned device;

[0025] The equipment expansion system is deployed inside the chassis.

[0026] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above data processing methods.

[0027] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described data processing methods.

[0028] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described data processing methods.

[0029] By configuring multiple uplinks and multiple downlinks on the switching device, the uplinks connect multiple different core processors, and the downlinks connect multiple core processors to an expansion group including multiple expansion devices. The core processors can share access to all expansion devices connected to the downlinks of the switching device through the non-transparent bridge function of the switching device. When any core processor fails, other normal processor cores can still access the expansion devices corresponding to the failed core processor, thus avoiding the expansion devices becoming inaccessible due to core processor failure and improving the security of the expansion devices. Attached Figure Description

[0030] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a device expansion system provided in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of another device expansion system provided in an embodiment of this application;

[0033] Figure 3 A schematic diagram of an exemplary device expansion system provided in this application embodiment;

[0034] Figure 4 A schematic diagram of another exemplary device expansion system provided in this application embodiment;

[0035] Figure 5 A flowchart illustrating the data processing method provided in an embodiment of this application;

[0036] Figure 6 This is a schematic diagram of the structure of the data processing apparatus provided in the embodiments of this application;

[0037] Figure 7 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0038] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0040] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0041] Artificial Intelligence (AI) servers are computing devices specifically designed to process and run AI tasks. They typically feature multiple Graphics Processing Units (GPUs), accelerator cards, and smart network interface cards (NICs). These are designed to efficiently execute complex AI algorithms such as large-scale data processing, machine learning, and deep learning. With the rapid development of large language model technologies, AI servers are placing increasingly higher demands on the memory capacity of single-machine GPUs, consequently increasing the required number of GPUs. Configuring multiple GPUs on a single server reduces the number of other peripherals that can be configured. Therefore, it is common practice to connect a switching device to the server's core processor (CPU) to extend the access resources of the core processor's extended devices. However, in servers with multi-core processors, if any core processor malfunctions, the extended devices connected to the switching device attached to the malfunctioning core processor will become inaccessible, reducing the security of the extended devices.

[0042] To address the aforementioned technical problems, embodiments of this application provide a device expansion system, data processing method, apparatus, and electronic device. This system configures multiple uplinks and multiple downlinks on the switching device. The uplinks connect multiple different core processors, and the downlinks connect expansion groups consisting of multiple core processors and multiple expansion devices. The core processors can share access to all expansion devices connected to the downlinks of the switching device through the non-transparent bridge function of the switching device. When any core processor fails, other normal processor cores can still access the expansion devices corresponding to the failed core processor, thus preventing expansion devices from becoming inaccessible due to core processor failure and improving the security of the expansion devices.

[0043] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] This application provides a device expansion system for expanding computing devices such as servers with multi-core processor architectures.

[0045] like Figure 1 The diagram shown is a structural schematic of a device expansion system provided in an embodiment of this application. The system includes multiple core processors and switching devices.

[0046] The switching device includes multiple uplinks and multiple downlinks; the multiple uplinks are used to connect multiple core processors; the multiple downlinks are used to connect multiple core processor expansion groups, and the expansion groups include multiple expansion devices; the non-transparent bridge function of the switching device is enabled; any core processor can access each expansion device in the expansion group of other core processors (excluding the core processor itself) based on the non-transparent bridge function of the switching device; when any core processor in the multiple core processors malfunctions, the normal core processors in the multiple core processors can access each expansion device in the expansion group of the malfunctioning core processor through the switching device.

[0047] It should be noted that in practical applications, the switching device can specifically be a PCIe Switch chip. The PCIe Switch chip is a key component for implementing PCIExpress (PCIe) signal switching and port expansion. It allows multiple expansion devices to be connected to a single PCIe port, or multiple devices to be connected to a host system. Expansion devices include PCIe devices such as network cards, storage devices, and GPUs. The specific expansion devices included in each core processor's expansion group can be determined based on the core processor's own device expansion requirements.

[0048] Specifically, the non-transparent bridge translates I / O addresses between different address spaces, allowing any core processor in the system to access various extended devices in other core processor extension groups. For example, core processor A, which could originally only access extended devices within its own extension group, can access extended devices in core processor B's extension group through the non-transparent bridge. This is because the non-transparent bridge effectively integrates and translates the different address spaces of different core processors and their extension groups, enabling each core processor to access extended devices in other core processor extension groups, thus achieving cross-processor sharing of extended device resources within the system.

[0049] Based on the above embodiments, as an implementable approach, in one embodiment, the downlink includes a first connector interface on the switching device, a connector, and a second connector interface on the expansion device.

[0050] For example, such as Figure 2 The diagram shown is a schematic diagram of an exemplary device expansion system provided in an embodiment of this application. Taking the MCIO connector as an example, the switching device connects to an expansion device with a second connector interface through multiple first connector interfaces. The switching device not only connects to the expansion device with the second connector interface through the first connector interface and the connector, but also connects to the core processor with the second connector interface through the first connector interface and the connector.

[0051] Specifically, by using connectors to connect expansion devices, when it is necessary to add expansion devices or replace faulty devices, quick assembly and disassembly can be achieved through connectors, reducing operational difficulty and improving the decoupling capability of the system.

[0052] Specifically, in one embodiment, the slot expansion card is connected to the connector via a second connector interface; the downlink port of the slot expansion card includes multiple expansion slots that conform to the expansion standards of the switching equipment.

[0053] The slot expansion card is also known as the Riser card. The upper row of the slot expansion card is the MCIO connector, and the lower row is the standard PCIe SLOT card slot (expansion slot). The SLOT card slot PIN definition conforms to the PCIe CEM specification standard SLOT card slot PIN definition requirements. The MICO connector that connects to the PCIe Switch board (switching device) conforms to the NVIDIA MGX specification requirements MCIO PIN definition requirements, and can be flexibly connected to the PCIe Switch board.

[0054] Specifically, by connecting a slot expansion card to the downlink of the switching device, the device expansion capability of the device expansion system provided in this application embodiment can be further improved.

[0055] Specifically, in one embodiment, the expansion device includes a storage backplane; the storage backplane is provided with a plurality of hard drives; the storage backplane is connected to a connector via a second connector interface.

[0056] Specifically, the storage backplane can be an NVMe backplane, supporting up to eight 2.5-inch PCIe X4 NVMe hard drives. The upstream row has two MICO connectors, and the downstream row has eight SFF8639 connectors. The upstream MCIO connectors comply with the NVIDIA MGX specification requirements for MCIO PIN definition, allowing for flexible connection to PCIe Switch cards.

[0057] Among them, such as Figure 3The diagram shows another device expansion system provided in this application embodiment. Taking a dual-CPU motherboard (CPU0 and CPU1) as an example, each CPU directly outputs a PCIe x16 slot to a 104-lane PCIe switch. The PCIe switch expands to include 4 x PCIe x4 NVMe hard drives, a PCIe x16 smart network card, 3 x PCIe x16 slots, and 1 x PCIe x8 slot. The CPU can also have a USB interface and an M.2 interface. The USB interface is used to connect external USB devices, and the M.2 interface is used to connect M.2 storage devices. To further improve the CPU's ability to mount GPUs and the security of GPU data, each CPU can also mount multiple GPU devices through another switch. The specific number of mounted GPUs can be selected according to actual needs.

[0058] Based on the above embodiments, as an implementable approach, in one embodiment, the switching device has multiple mutually isolated logical domains; by configuring the hardware pins of the switching device, multiple uplinks are divided into multiple logical domains, and an address translation channel is established between the mutually isolated logical domains, thereby enabling the non-transparent bridge function of the switching device.

[0059] It should be noted that the switching equipment has multiple pre-defined logical domains. These logical domains are initially independent and isolated from each other, each with its own address space and data transmission path. Different logical domains cannot directly interact with each other, thus ensuring basic signal isolation.

[0060] Specifically, this application aims to enable shared access by multiple core processors to all extended devices connected to the downlink of a switching device. This is achieved by physically configuring the hardware pins of the switching device (e.g., through hardware jumpers and pin level settings) to allocate multiple uplinks to different logical domains. For example, the uplink connecting core processor A is assigned to logical domain 1, and the uplink connecting core processor B is assigned to logical domain 2, thus establishing a correspondence between each logical domain and a specific core processor, achieving physical-level link-logical-domain binding.

[0061] Furthermore, after completing the uplink segmentation, address translation channels are established between these isolated logical domains. The core function of this channel is to convert and map device addresses within different logical domains. When a core processor in one logical domain (e.g., logical domain 1) needs to access an extended device in another logical domain (e.g., logical domain 2), the address translation channel can convert the access address of the source logical domain into an address format recognizable by the target logical domain, and perform reverse address conversion when transmitting response information.

[0062] Specifically, the non-transparent bridge function of the switching device is activated through a hardware configuration process involving logical domain isolation, uplink partitioning, and address translation channel establishment. At this point, the non-transparent bridge can achieve cross-domain address resolution and data forwarding while maintaining the independence of each logical domain. This allows different core processors to securely and accurately access extended devices in other logical domains through their corresponding uplinks, logical domains, and address translation channels. This ensures that multi-core processors can share extended resources while avoiding address conflicts and data interference through logical domain isolation.

[0063] Based on the above embodiments, as one implementable approach, in one embodiment, the system further includes:

[0064] The management and control module is used to obtain the current status information and routing allocation information of the switching devices, and to perform routing management and control on the switching devices based on the current status information and routing allocation information.

[0065] Specifically, the management and control module can be implemented based on the Baseboard Management Controller (BMC), which is a dedicated device in computing devices such as servers that is responsible for hardware monitoring, management and control.

[0066] Specifically, the management and control module establishes a connection with the switching equipment through a preset communication link to obtain the current status information and routing allocation information of the switching equipment.

[0067] The current status information of the switching equipment includes link status information, equipment operation status information, and function activation status information. Link status information includes the connectivity and signal transmission quality of each uplink and downlink, reflected by transmission rate and bit error rate. Equipment operation status information includes the operating temperature, power supply voltage, and presence of hardware faults of the switching equipment's core chip. Function activation status includes whether the non-transparent bridge function is properly enabled. Routing allocation information includes path mapping relationships, load distribution information, and abnormal routing information. Path mapping relationships indicate which uplinks and downlinks have established data transmission paths, such as core processor A accessing the extended device connected to downlink 2 via uplink 1. Load distribution information includes real-time data traffic for each route, such as uplink 1 currently having a load rate of 30% and downlink 4 having a load rate of 80%. Abnormal routing information includes routes that are unusable due to link failures or core processor malfunctions, such as uplink 2 being disabled due to a core processor B malfunction.

[0068] Specifically, in one embodiment, a bus link is provided between the management control module and the switching device; the management control module obtains the current status information and routing allocation information of the switching device through the bus link.

[0069] For example, such as Figure 4 The diagram shown is a schematic of another exemplary device expansion system provided in this application embodiment. The management and control module is deployed on the motherboard and communicates with the switching device through the I2C bus.

[0070] Specifically, in one embodiment, the management control module is specifically used for:

[0071] Based on the current status information of the switching device, determine whether the switching device meets the preset route allocation conditions; if it is determined that the switching device meets the preset route allocation conditions, perform route allocation on the normal core processors of the uplink connection of the switching device according to the route allocation information, so that all normal core processors have the access conditions to each extended device of the downlink connection of the switching device.

[0072] Routing management control includes route allocation.

[0073] Specifically, the management and control module compares the current status information of the switching equipment with preset routing allocation conditions to determine whether these conditions are met. These routing allocation conditions are trigger thresholds for normal system operation. For example, the trigger conditions for routing allocation are met when a new core processor is detected to be connected, an existing core processor is abnormally taken offline, a link fault is recovered, or the number of expanded devices changes. This judgment process ensures that routing allocation is performed only when necessary, avoiding invalid operations that could affect system stability. It also needs to determine whether the switching equipment is currently in a normal state. If the switching equipment is confirmed to be in a normal state, routing allocation is performed to ensure the security of the routing allocation.

[0074] Furthermore, once the allocation conditions are confirmed, the management and control module plans access paths for normal core processors based on the current routing allocation information. The core objective of routing allocation is to ensure that each downlink-connected extended device can be accessed by a normal core processor. For example, if a core processor malfunctions, the extended devices it originally accessed can be allocated to other normal core processors, and the newly allocated path must achieve cross-domain access through the non-transparent bridging function of the switching device.

[0075] For example, taking the device expansion system provided in this application embodiment as an example, which includes two core processors (CPU1 and CPU2), the downlink connected devices of the switching device are 8 NVMe hard drives, evenly distributed in a 4+4 configuration across two uplink PCIe x16 lanes, with PCIe devices on 3 × PCIe x16 SLOT + 1 × PCIe x8 SLOT. If CPU0 and CPU1 are normally connected to the switching device via the PCIe x16 uplink, then CPU0 and CPU1 can operate all devices connected to the downlink of the switching device through the PCIe Switch. If only CPU0 is normally connected to the switching device via the PCIe x16 uplink, then CPU0 can operate all devices connected to the downlink of the switching device through the PCIe Switch. If only CPU1 is normally connected to the switching device via the PCIe x16 uplink, then CPU1 can operate all devices connected to the downlink of the switching device through the PCIe Switch.

[0076] Specifically, in one embodiment, the management control module is also used to issue an uplink missing alarm if the routing allocation information indicates that any core processor is missing.

[0077] Among them, routing management control includes uplink missing alarms.

[0078] For example, if only CPU1 is normally connected to the switching device via the PCIe x16 uplink, an uplink missing alarm is generated for the uplink connected to CPU0. If only CPU0 is normally connected to the switching device via the PCIe x16 uplink, an uplink missing alarm is generated for the uplink connected to CPU1.

[0079] Specifically, in one embodiment, the management control module is also used to issue a system anomaly alarm when the routing allocation information indicates that all core processors are missing.

[0080] Specifically, if it is found that neither CPU0 nor CPU1 can connect to the switching device normally through the PCIe X16 uplink, that is, all core processors are missing, a system anomaly alarm will be issued.

[0081] The firmware design of the switching device provided in this application embodiment includes: designing PCIe links according to hardware specifications, allocating corresponding PCIe Lanes, supporting PCIe Fabric, enabling NTB functionality (non-transparent bridge: some PCIe switches support non-transparent bridge structures, allowing direct communication between different processor systems. CPU1 can directly access the device address space under CPU0 through NTB), supporting switching functionality when uplink PCIe links are abnormally lost, and supporting BMC to obtain PCIeSwitch status information and perform PCIe route allocation via I2C. The BMC firmware design in this application embodiment includes: the BMC can identify PCIe Switch boards (switching devices) with Multi-host functionality via I2C, and perform PCIeSwitch board status information reading, alarm information reading, and PCIe route switching based on the identified boards.

[0082] It should be noted that the switching device provided in this application embodiment has a multi-host function, supports PCIe 5.0, PCIe Fabric and 104 PICe lanes; all high-speed interfaces of the entire board adopt MCIO interfaces, the PCIeSwitch directly outputs PCIe high-speed signals to the MCIO connector, each MCIO interface carries PCIe X8 high-speed signals, and the MCIO connector is connected to different boards through cables; the board has an I2C interface to realize the interaction of PCIe Switch and BMC management information.

[0083] Based on the above embodiments, as one implementable approach, in one embodiment, the system further includes:

[0084] The address allocation module is used to assign access addresses to each extended device, so that each core processor can access the corresponding extended device according to the access address.

[0085] Specifically, the address allocation module can be implemented based on the Basic Input / Output System (BIOS).

[0086] Specifically, the address allocation module can scan and enumerate PCIe devices (extensions) using the PCIe depth-first search algorithm to complete the allocation of access addresses for PCIe extension devices.

[0087] Based on the above embodiments, as one implementable approach, in one embodiment, the system further includes:

[0088] The encoding allocation module is used to allocate non-overlapping bus encoding ranges to different processor cores, so that each core processor can allocate bus codes to multiple expansion devices in the corresponding expansion group within the allocated bus encoding range.

[0089] Each core processor accesses the corresponding extended device according to the bus code, which includes the bus number.

[0090] For example, the encoding allocation module assigns two different PCIe Bus ranges (bus encoding ranges) to CPU0 and CPU1. CPU0 is allocated a range of 0x00-0x7F, and CPU1 is allocated 0x80-0xFF. CPU0 assigns bus numbers 0x00 to 0x05 to the four NVMe hard drives and two PCIe slots connected to its PCIe switch. CPU10 assigns bus numbers 0x80 to 0x85 to the other four NVMe hard drives and two PCIe slots connected to its PCIe switch. In this dual-CPU device expansion system based on the PCIe bus, the encoding allocation module isolates and allocates bus codes to avoid device access conflicts.

[0091] Based on the above embodiments, as one possible implementation, in one embodiment, the normal core processor is further configured to:

[0092] Back up the running data of each extended device in the extended group of the abnormal core processor to the preset backup cache.

[0093] When the abnormal core processor recovers to normal, it retrieves the running data from the preset backup cache and restores the running data to each extended device, ensuring that the data of the extended devices is not lost when the core processor is abnormal and can be reused after recovery.

[0094] Specifically, when core processor CPU0 malfunctions, the management and control module identifies the anomaly through the status information of the switching device and sends a data takeover command to the normal core processor CPU1. Based on the non-transparent bridge function of the switching device, the normal core processor already has the ability to access the devices in the CPU0 expansion group, and therefore can directly read the real-time operating data of these devices, such as intermediate GPU computation results and cached data from NVMe hard drives. The normal core processor categorizes the read operating data according to device type and data type, and writes it to a preset backup cache. The preset backup cache can be an independent storage chip or a reserved partition in the normal processor's local memory. During the backup process, a data verification mechanism ensures that the written data is consistent with the original data, and records the backup timestamp and device identifier to provide an index for subsequent recovery. When the malfunctioning core processor CPU0 recovers, the management and control module detects that its uplink has been restored and sends a data recovery command to the normal core processor CPU1. The normal core processor reads the operating data of the corresponding device from the backup cache and writes the data back to the corresponding device in the CPU2 expansion group in its original format through the original routing link of the switching device. After recovery is complete, the corresponding data is released from the preset backup cache to avoid occupying storage space.

[0095] In order to achieve backup of the operating data of the extended device, the system firmware design of the core processor of the device extension system provided in this application embodiment includes: according to the PCIe hardware topology, after the BIOS completes the PCIe Bus allocation and address allocation, data operations can be performed on the PCIe device through the PCIe protocol. If there is a situation where only one CPU or one of the two CPUs is abnormal, the PCIe Switch Multi-host function can be used to realize data processing, backup and protection.

[0096] Based on the above embodiments, as one implementable approach, in one embodiment, the system further includes:

[0097] Cooling modules are used to provide targeted cooling for switching equipment and various expansion devices.

[0098] It should be noted that the main function of the heat dissipation module is to provide precise heat dissipation for the heat characteristics of switching and expansion devices, so as to avoid performance degradation or hardware failure caused by high temperature.

[0099] Specifically, in a device expansion system, switching devices and expansion devices are centrally deployed via connectors and links, which can easily create areas of heat accumulation. The cooling module optimizes the physical layout by designing independent cooling fans for each switching device and each expansion device, enabling targeted cooling. The cooling module includes multiple independent cooling fans, whose installation positions correspond to the locations of the switching devices and expansion devices within the chassis, thereby improving the cooling efficiency for both.

[0100] The device expansion system provided in this application includes: multiple core processors and a switching device; the switching device includes multiple uplinks and multiple downlinks; the multiple uplinks are used to connect the multiple core processors; the multiple downlinks are used to connect expansion groups of the multiple core processors, and the expansion groups include multiple expansion devices; the non-transparent bridge function of the switching device is enabled; any core processor accesses each expansion device in the expansion group of other core processors besides itself based on the non-transparent bridge function of the switching device; when any core processor among the multiple core processors malfunctions, the normal core processor among the multiple core processors accesses each expansion device in the expansion group of the malfunctioning core processor through the switching device. The system provided by the above solution, by configuring multiple uplinks and multiple downlinks on the switching device, connects multiple different core processors via multiple uplinks and multiple expansion groups of core processors via downlinks. Core processors can share access to all expansion devices connected to the downlinks of the switching device through the non-transparent bridge function of the switching device. When any core processor fails, other normal processor cores can still access the expansion devices corresponding to the failed core processor, thus preventing expansion devices from becoming inaccessible due to core processor failure and improving the security of the expansion devices. Furthermore, the new structural design provided in this application embodiment, while compatible with the MGX specification, can support 8×FHHL PCIe cards + 8×U.2 expansions, solving the problem of insufficient scalability in 4U MGX architecture servers.

[0101] Through the above description of the embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0102] This application provides a data processing method for protecting the operational data of extended devices of a core processor when any core processor malfunctions. The execution subject of this application is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, or other electronic devices that can be used to protect the operational data of extended devices.

[0103] like Figure 5 The diagram shown is a flowchart illustrating a data processing method provided in an embodiment of this application. The method includes:

[0104] Step 501: When any core processor in the device expansion system malfunctions, the normal core processor in the device expansion system accesses each expansion device in the expansion group of the malfunctioning core processor through the switching device.

[0105] Step 502: Back up the running data of each extended device in the extended group of the abnormal core processor to the preset backup cache;

[0106] Step 503: After the abnormal core processor recovers to normal, retrieve the running data from the preset backup cache;

[0107] Step 504: Restore the running data to each extended device.

[0108] The device expansion system includes multiple core processors and switching devices. The switching devices include multiple uplinks and multiple downlinks. The multiple uplinks are used to connect multiple core processors. The multiple downlinks are used to connect expansion groups of multiple core processors. The expansion groups include multiple expansion devices. The non-transparent bridge function of the switching devices is enabled. Any core processor can access each expansion device in the expansion group of other core processors (excluding the core processor itself) based on the non-transparent bridge function of the switching devices.

[0109] For a description of the features in the embodiment corresponding to the data processing method, please refer to the relevant description of the embodiment corresponding to the device expansion system, which will not be repeated here.

[0110] Embodiments of this application also provide a data processing apparatus for executing the data processing method provided in the above embodiments.

[0111] like Figure 6 The diagram shown is a structural schematic of a data processing apparatus provided in an embodiment of this application. The data processing apparatus 60 includes: an access module 601, a backup module 602, an acquisition module 603, and a recovery module 604.

[0112] The system includes: an access module for accessing various extended devices in the extended group of the abnormal core processor via a switching device when any core processor in the extended system malfunctions; a backup module for backing up the running data of each extended device in the extended group of the abnormal core processor to a preset backup cache; an acquisition module for acquiring the running data from the preset backup cache after the abnormal core processor recovers; and a recovery module for restoring the running data to each extended device.

[0113] The device expansion system includes multiple core processors and switching devices. The switching devices include multiple uplinks and multiple downlinks. The multiple uplinks are used to connect multiple core processors. The multiple downlinks are used to connect expansion groups of multiple core processors. The expansion groups include multiple expansion devices. The non-transparent bridge function of the switching devices is enabled. Any core processor can access each expansion device in the expansion group of other core processors (excluding the core processor itself) based on the non-transparent bridge function of the switching devices.

[0114] For a description of the features in the embodiment corresponding to the data processing device, please refer to the relevant description in the embodiment corresponding to the data processing method, which will not be repeated here.

[0115] Embodiments of this application also provide a computing device, such as Figure 7 The diagram shown is a structural schematic of a computing device provided in an embodiment of this application, including a chassis and a device expansion system provided in the above embodiment. The computing device may be a server or the like.

[0116] Embodiments of this application also provide an electronic device, such as... Figure 8 The diagram shown is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, including a processor 10 and a memory 20. The memory 20 stores a computer program, and the processor 10 is configured to run the computer program to perform the steps in any of the above-described data processing method embodiments.

[0117] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above data processing method embodiments when it is run.

[0118] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0119] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above data processing method embodiments.

[0120] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above data processing method embodiments.

[0121] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0122] The foregoing has provided a detailed description of a device expansion system, data processing method, apparatus, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A device expansion system, characterized in that, include: Multiple core processors and switching devices; The switching device includes multiple uplinks and multiple downlinks; The multiple uplinks are used to connect multiple core processors; The multiple downlinks are used to connect the multiple core processors to an expansion group, the expansion group including multiple expansion devices; The non-transparent bridge function of the switching device is enabled; Each of the core processors accesses various extension devices in the extension groups of the other core processors besides itself, based on the non-transparent bridge function of the switching device. When any one of the plurality of core processors malfunctions, the normal core processors among the plurality of core processors are used to access each of the extended devices in the extended group of the malfunctioning core processor through the switching device. The switching device has multiple mutually isolated logical domains; By configuring the hardware pins of the switching device, the multiple uplinks are divided into multiple logical domains, and address translation channels are established between the multiple isolated logical domains, thereby enabling the non-transparent bridge function of the switching device; wherein, the address translation channels are used to convert and map device addresses in different logical domains; The system also includes: The encoding allocation module is used to allocate non-overlapping bus encoding ranges to different core processors, so that each core processor can allocate bus codes to multiple expansion devices in the corresponding expansion group within the allocated bus encoding range, thereby achieving isolated allocation of bus codes for expansion devices in different expansion groups. Each of the core processors accesses the corresponding extended device according to the bus code; The normal core processor is also used for: The running data of each extended device in the extended group of the abnormal core processor is backed up to a preset backup cache; When the abnormal core processor recovers to normal, the running data is obtained from the preset backup cache and restored to each extended device; When the uplink of the abnormal core processor is detected to be restored, it is determined that the abnormal core processor has returned to normal. A data recovery command is sent to the normal core processor so that the normal core processor responds to the data recovery command, reads the corresponding running data from the preset backup buffer, and writes the data back to the extended device of the abnormal core processor in the original format through the original routing link of the switching device. The system also includes: The management and control module is used to acquire the current status information and routing allocation information of the switching device, and to perform routing management and control on the switching device based on the current status information and routing allocation information; wherein, the current status information includes link status information, device operating status information, and function activation status information; A bus link is provided between the management and control module and the switching device; The management and control module obtains the current status information and routing allocation information of the switching device through the bus link; The management and control module is specifically used for: Based on the current status information of the switching device, determine whether the switching device meets the preset routing allocation conditions; If the switching device meets the preset routing allocation conditions, the normal core processors connected to the uplink of the switching device are routed according to the routing allocation information, so that all normal core processors have the access conditions to each of the extended devices connected to the downlink of the switching device. The routing management control includes route allocation; The management and control module is also used for: If the routing allocation information indicates that any of the core processors is missing, an uplink missing alarm will be issued; The routing management control includes uplink missing alarms.

2. The device expansion system according to claim 1, characterized in that, The downlink includes a first connector interface on the switching device, a connector, and a second connector interface on the expansion device.

3. The device expansion system according to claim 2, characterized in that, The expansion device includes a slot expansion card; The slot expansion card is connected to the connector via the second connector interface; The downlink port of the slot expansion card includes multiple expansion slots, which conform to the expansion standard of the switching device.

4. The device expansion system according to claim 2, characterized in that, The expansion device includes a storage backplane; The storage backplane is equipped with multiple hard drives; The storage backplane is connected to the connector via the second connector interface.

5. The device expansion system according to claim 1, characterized in that, The management and control module is also used for: If the routing allocation information indicates that all core processors are missing, a system anomaly alarm will be issued.

6. The device expansion system according to claim 1, characterized in that, The system also includes: The address allocation module is used to allocate access addresses to each of the extended devices, so that each of the core processors can access the corresponding extended device according to the access address.

7. The device expansion system according to claim 1, characterized in that, The system also includes: A heat dissipation module is used to provide targeted heat dissipation for the switching device and each of the expansion devices.

8. A data processing method, applied to the device expansion system as described in any one of claims 1 to 7, characterized in that, The method includes: When any core processor in the device expansion system malfunctions, the normal core processors in the device expansion system access each expansion device in the expansion group of the malfunctioning core processor through the switching device. The running data of each extended device in the extended group of the abnormal core processor is backed up to a preset backup cache; Once the abnormal core processor returns to normal, the running data is retrieved from the preset backup cache. The operational data is then restored to each extended device. The device expansion system includes multiple core processors and switching devices. Each switching device includes multiple uplinks and multiple downlinks. The multiple uplinks connect the multiple core processors. The multiple downlinks connect expansion groups of the multiple core processors, each expansion group including multiple expansion devices. The non-transparent bridge function of the switching device is enabled. Any core processor can access each expansion device in the expansion groups of other core processors (excluding the core processor itself) based on the non-transparent bridge function of the switching device. The switching device has multiple mutually isolated logical domains; By configuring the hardware pins of the switching device, the multiple uplinks are divided into multiple logical domains, and address translation channels are established between the multiple isolated logical domains, thereby enabling the non-transparent bridge function of the switching device; wherein, the address translation channels are used to convert and map device addresses in different logical domains; The system also includes: The encoding allocation module is used to allocate non-overlapping bus encoding ranges to different core processors, so that each core processor can allocate bus codes to multiple expansion devices in the corresponding expansion group within the allocated bus encoding range, thereby achieving isolated allocation of bus codes for expansion devices in different expansion groups. Each of the core processors accesses the corresponding extended device according to the bus code; The normal core processor backs up the operating data of each extended device in the extended group of the abnormal core processor to a preset backup cache. When the abnormal core processor recovers to normal, the running data is obtained from the preset backup cache and restored to each extended device; When the uplink of the abnormal core processor is detected to be restored, it is determined that the abnormal core processor has returned to normal. A data recovery command is sent to the normal core processor so that the normal core processor responds to the data recovery command, reads the corresponding running data from the preset backup buffer, and writes the data back to the extended device of the abnormal core processor in the original format through the original routing link of the switching device. The system also includes: The management and control module is used to acquire the current status information and routing allocation information of the switching device, and to perform routing management and control on the switching device based on the current status information and routing allocation information; wherein, the current status information includes link status information, device operating status information, and function activation status information; A bus link is provided between the management and control module and the switching device; The management and control module obtains the current status information and routing allocation information of the switching device through the bus link; The management and control module is specifically used for: Based on the current status information of the switching device, determine whether the switching device meets the preset routing allocation conditions; If the switching device meets the preset routing allocation conditions, the normal core processors connected to the uplink of the switching device are routed according to the routing allocation information, so that all normal core processors have the access conditions to each of the extended devices connected to the downlink of the switching device. The routing management control includes route allocation; The management and control module is also used for: If the routing allocation information indicates that any of the core processors is missing, an uplink missing alarm will be issued; The routing management control includes uplink missing alarms.

9. A data processing apparatus, applied to the device expansion system as described in any one of claims 1 to 7, characterized in that, The device includes: The access module is used to access each expansion device in the expansion group of the abnormal core processor through the switching device when any core processor in the device expansion system malfunctions. The backup module is used to back up the operating data of each extended device in the extended group of the abnormal core processor to a preset backup cache. The acquisition module is used to acquire the running data from the preset backup cache after the abnormal core processor recovers to normal. The recovery module is used to restore the operating data to each extended device; The device expansion system includes multiple core processors and switching devices. Each switching device includes multiple uplinks and multiple downlinks. The multiple uplinks connect the multiple core processors. The multiple downlinks connect expansion groups of the multiple core processors, each expansion group including multiple expansion devices. The non-transparent bridge function of the switching device is enabled. Any core processor can access each expansion device in the expansion groups of other core processors (excluding the core processor itself) based on the non-transparent bridge function of the switching device. The switching device has multiple mutually isolated logical domains; By configuring the hardware pins of the switching device, the multiple uplinks are divided into multiple logical domains, and address translation channels are established between the multiple isolated logical domains, thereby enabling the non-transparent bridge function of the switching device; wherein, the address translation channels are used to convert and map device addresses in different logical domains; The system also includes: The encoding allocation module is used to allocate non-overlapping bus encoding ranges to different core processors, so that each core processor can allocate bus codes to multiple expansion devices in the corresponding expansion group within the allocated bus encoding range, thereby achieving isolated allocation of bus codes for expansion devices in different expansion groups. Each of the core processors accesses the corresponding extended device according to the bus code; The normal core processor backs up the running data of each extended device in the extended group of the abnormal core processor to a preset backup cache. When the abnormal core processor recovers, it retrieves the running data from the preset backup cache and restores the running data to each extended device. When the uplink of the abnormal core processor is detected to be reconnected, it determines that the abnormal core processor has recovered and sends a data recovery command to the normal core processor, so that the normal core processor responds to the data recovery command, reads the corresponding running data from the preset backup cache, and writes the data back to the extended device of the abnormal core processor in its original format through the original routing link of the switching device. The system also includes: The management and control module is used to acquire the current status information and routing allocation information of the switching device, and to perform routing management and control on the switching device based on the current status information and routing allocation information; wherein, the current status information includes link status information, device operating status information, and function activation status information; A bus link is provided between the management and control module and the switching device; The management and control module obtains the current status information and routing allocation information of the switching device through the bus link; The management and control module is specifically used for: Based on the current status information of the switching device, determine whether the switching device meets the preset routing allocation conditions; If the switching device meets the preset routing allocation conditions, the normal core processors connected to the uplink of the switching device are routed according to the routing allocation information, so that all normal core processors have the access conditions to each of the extended devices connected to the downlink of the switching device. The routing management control includes route allocation; The management and control module is also used for: If the routing allocation information indicates that any of the core processors is missing, an uplink missing alarm will be issued; The routing management control includes uplink missing alarms.

10. A computing device, characterized in that, include: The chassis and the device expansion system as described in any one of claims 1 to 7; The device expansion system is deployed within the chassis.

11. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the steps of the data processing method as described in claim 8 when executing the computer program.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data processing method as described in claim 8.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the data processing method as described in claim 8.

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