Charge pump circuit for phase-locked loop, charge pump module, phase-locked loop and communication chip

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a charge pump circuit for a phase-locked loop, a charge pump module, the phase-locked loop and a communication chip. The charge pump circuit adopts a source switch single-end topology, and a numerical control current source DAC with an adaptive compensation circuit and two rail-to-rail operational amplifiers are applied. According to the source electrode switch single-end topology, the switch time sequence is dynamically optimized through a three-state working mode, and the charge injection effect and clock feed-through interference are remarkably reduced; the numerical control current source realizes multi-stage high-precision programmable current output according to a control code, responds to the change of output voltage in real time by utilizing a self-adaptive compensation mechanism, and maintains the stability of charging and discharging current; the rail-to-rail operational amplifier eliminates the common-mode constraint in a full-swing input range by connecting an NMOS-PMOS differential pair structure in parallel. The charge pump circuit overcomes the defects of a charge pump circuit adopted in an existing phase-locked loop in the aspects of output swing, stability and the like, static power consumption can be reduced to the microampere level, and the advantages are obvious.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a charge pump circuit for a phase-locked loop, and a corresponding charge pump module, a phase-locked loop, and a communication chip. Background Art

[0002] As the core module for frequency synthesis and signal synchronization in modern electronic systems, the performance of the phase-locked loop is directly affected by the working accuracy and stability of the charge pump. However, traditional charge pump technology has many shortcomings: 1. In terms of switching topology, the drain switch topology is easily affected by the clock feedthrough effect, resulting in output voltage peak noise, while the gate switch topology is limited by the transconductance of the MOS tube, resulting in slow switching speed and high static power consumption. 2. In terms of current control, analog current sources are difficult to meet the needs of multi-level fine current regulation. The current mismatch caused by process deviations will significantly worsen the phase noise of the phase-locked loop, and there is a lack of effective digital calibration mechanism to compensate for the impact of environmental changes. 3. In terms of loop stability, the input common-mode range of traditional operational amplifiers cannot cover the full swing range. Insufficient gain leads to a decrease in current matching accuracy. At the same time, output voltage fluctuations will cause changes in charging and discharging currents, resulting in unstable phase-locked loop bandwidth.

[0003] To address these issues, technicians have developed several improved circuit solutions. However, these solutions often focus on optimizing only a single performance factor, failing to achieve the combined performance improvements of low power consumption, high precision, a wide input range, and strong stability. Therefore, designing a high-performance charge pump circuit that integrates digital calibration, wide-swing amplification, and dynamic compensation technologies has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0004] In order to overcome the deficiencies of the charge pump circuit used in the existing phase-locked loop in terms of output swing and stability, the present invention provides a charge pump circuit for a phase-locked loop, and its corresponding charge pump module, phase-locked loop and communication chip.

[0005] The technical solution provided by the present invention is:

[0006] A charge pump circuit for a phase-locked loop (PLL) consists of nine NMOS transistors (M1-M8, M15), six PMOS transistors (M9-M14), a digitally controlled current source (DAC), two capacitors (C1, C2), and two rail-to-rail operational amplifiers (AMP1 and AMP2). The circuit is connected as follows: the sources of M13 and M14, the gates of M1-M3, M11, and M15, and the DAC power supply are connected to VDD. The gates of M5 and M13 and the sources of M1, M2, and M15 are grounded. The drains of M11 and M13 are connected to the sources of M9 and M11. The drains of M7 and M9 are connected to the non-inverting input of AMP2. The drains of M8 and M10 are connected to the inverting input of AMP2 and serve as the output port (Vout) of the charge pump circuit. The output of AMP2 is connected to M9, M10, and one end of C1, while the other end of C2 is connected to the power supply. The drains of M12 and M14 are connected to the sources of M10 and M12. The DAC's current output is connected to the drain of M15 and the non-inverting input of AMP1. The drain of M1 and the source of M3 are connected to the inverting input of AMP1. The output of AMP1 is connected to the gates of M7 and M8 and one end of C2, the other end of which is connected to the power supply. The sources of M5 and M7 are connected to the drains of M3 and M7; the sources of M6 and M8 are connected to the drains of M4 and M6. The source of M3 is connected to the drain of M2. The gates of M14 and M4 are connected to the differential signals UP and DW, respectively. The gate of M12 is connected to the pull-up signal UPN; the gate of M6 is connected to the switch control signal DWN.

[0007] Among them, the digitally controlled current source DAC adopts a binary weighted MOS resistor array architecture including an adaptive compensation circuit, which is dynamically configured by an n-bit control code. n The programmable bias current Icp of the stage can be adaptively compensated for the bias current of its own output according to Vout.

[0008] As a further improvement of the present invention, the digitally controlled current source DAC includes a current bias circuit, a current proportional mirror array, a MOS-R switch array and an adaptive compensation circuit. The current proportional mirror array includes n branches, each branch contains a number of 1:2:...:2 n-1 Multiple PMOS transistors connected in parallel. The gates of all PMOS transistors in each branch are connected, and the sources are connected to VDD. The MOS-R switch array includes n switch units corresponding to the number of branches in the current proportional mirror array; each switch unit includes an NMOS transistor and a resistor. The drain of the NMOS transistor in each switch unit is connected to the drain of the PMOS transistor in the corresponding branch of the current proportional mirror array. The gate of the NMOS transistor in each switch unit is connected to the control signal D <0> ~D <n-1>, the source is connected to one end of the resistor, and the other end of the resistor is connected and serves as the output port A of the bias current Icp.

[0009] The current bias circuit includes two PMOS transistors M20 and M21, four NMOS transistors M18, M19, M22, and M23, and two resistors R1 and R2. The sources of M20 and M21, the drain of M19, and one end of R1 are connected to the power supply; the other end of R1 is connected to the gates of M18 and M19, and the drain of M18. The sources of M18 and M23 and one end of R2 are grounded; the other end of R2 is connected to the gate of M23 and the source of M22. The drains of M20 and M23 are connected to the source of M19 and the gate of M1; the drains of M21 and M22 are connected. The gates of M20 and M21 are connected to the gates of the PMOS transistors in each branch of the current proportional mirror array.

[0010] The adaptive compensation circuit is composed of PMOS tubes M16 and M17; the source of M17 is connected to the power supply; the drain and gate of M17 are connected to the source of M16; the drain of M16 is connected to port A; and the gate of M16 is connected to Vout.

[0011] As a further improvement of the present invention, the magnitude of the bias current Icp output by the digitally controlled current source DAC is controlled by an n-bit control code consisting of a control signal connected to the gate of the NMOS tube in the switching unit; the value of the n-bit control code is the multiple of the bias current Icp relative to the unit current.

[0012] As a further improvement of the present invention, PMOS tubes M9, M10, M13, and M14 constitute a pull-up network of the circuit, and NMOS tubes M3, M4, M7, and M8 constitute a pull-down network, and the two cooperate to realize the charging and discharging functions of the charge pump.

[0013] When the UP signal is valid, the charge pump circuit is in a charging state; when the DW signal is valid, the charge pump circuit is in a discharging state; when both UP and DW are invalid, the output port of the charge pump circuit is in a high-impedance state.

[0014] As a further improvement of the present invention, M1, M15 and AMP1 constitute a linear current mirror circuit, and AMP1 is used to monitor the drain voltage difference between M1 and M15 in real time, and then dynamically adjust it through a negative feedback mechanism to form an output impedance multiplication structure and suppress the channel length modulation effect, thereby improving the mirror accuracy of the current mirror circuit.

[0015] As a further improvement of the present invention, capacitors C1, C2, M5, M6, M11, M12 as Dummy tubes, and M7, M8, M9, M10 as isolation tubes together form a switching noise suppression structure. Among them, capacitors C1 and C2 serve as energy storage elements and constitute a low-pass filter network, thereby smoothing the voltage fluctuations during the charge pump circuit switching process by absorbing high-frequency components. The nodes at the two input ends of AMP2 are denoted as X and Y; AMP2 is used to detect the current difference between the output branch and the mirror branch in real time according to the input signal, and adjusts the gate voltage of M9 and M10 through its own output, forcing the potential of nodes X and Y to converge. The deviation of the output current and the reference current is then fed back to the control loop to achieve high-precision matching of the two currents.

[0016] As a further improvement of the present invention, the rail-to-rail operational amplifiers AMP1 and AMP2 are composed of three parts: a complementary input stage, a folded cascode structure, and an output stage. AMP1 and AMP2 adopt a parallel NMOS-PMOS differential pair structure.

[0017] The present invention also includes a charge pump module encapsulated from the aforementioned charge pump circuit for a phase-locked loop. The charge pump module's pins include a power supply terminal (VDD), a ground terminal (VSS), an output port (Vout), control ports (UP and DW), and control ports (UPN and DWN). The power supply terminal is used to connect to a power source, the ground terminal is used for grounding, and the output port is used to output a desired voltage signal. UP and DW are connected to differential control signals for adjusting the charge pump's operating state, respectively; UPN and DWN are connected to pull-up signals and switch control signals, respectively.

[0018] The present invention also includes a phase-locked loop (PLL) comprising a phase frequency detector (PFD), a charge pump circuit (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider. The charge pump circuit uses the aforementioned charge pump circuit for a phase-locked loop; the output of the CP is processed by the LPF and then used as the input of the VCO, and the output of the VCO is processed by the frequency divider to generate a feedback frequency f div ;PFD combined with reference frequency f REF and f div The control signals UP and DOWN are generated for regulating the charge pump circuit CP.

[0019] The present invention also provides a communication chip, which adopts the aforementioned phase-locked loop.

[0020] The technical solution provided by the present invention has the following beneficial effects: The charge pump circuit of the present invention adopts a source-switched single-ended topology, significantly reducing static power consumption under high-current conditions while improving switching response speed, suppressing output voltage ripple, and improving the dynamic performance and stability of the charge pump. The circuit employs a newly designed digitally controlled current source DAC to finely adjust the output bias current according to a control code. Combined with an adaptive compensation circuit, this effectively suppresses current fluctuations caused by process variations, temperature drift, or load transients, ensuring that the charge pump maintains stable output current characteristics over a wide voltage range, significantly improving the system's linearity and anti-interference capabilities. The two rail-to-rail operational amplifiers in the circuit utilize a parallel NMOS-PMOS differential pair input stage, covering the full input swing from 0 to VDD. Combined with a dynamic voltage clamping network, signal processing accuracy is enhanced. Furthermore, a linear current mirror can be adjusted through the MOS transistor current mirror structure and operational amplifier negative feedback, achieving high-precision mirroring of the reference current. Furthermore, the current matching control module dynamically adjusts the switch conduction state by real-time monitoring of the potential difference between the output branch and the mirror branch, suppressing output voltage fluctuations caused by clock feedthrough and charge injection.

[0021] Compared to existing solutions, the circuit solution provided by this invention offers advantages such as precise voltage control, rapid response, good stability, and efficient energy transmission. It can meet the needs of a variety of applications with stringent requirements for voltage accuracy, response speed, stability, and energy efficiency. Furthermore, this solution improves performance while controlling area overhead, avoiding excessive power consumption and meeting the requirements of highly integrated designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a circuit diagram of a charge pump circuit for a phase-locked loop provided in Example 1 of the present invention.

[0023] Figure 2 for Figure 1 Circuit diagram of the digitally controlled current source DAC used in.

[0024] Figure 3 Figure 1 Circuit diagram of the rail-to-rail operational amplifier used in.

[0025] Figure 4 This is a schematic diagram of the phase-locked loop provided in Example 2 of the present invention.

[0026] Figure 5 The gain and phase margin curves of the rail-to-rail operational amplifier in the performance test experiment.

[0027] Figure 6 The figure is a comparison diagram of the current matching between the present invention and the existing circuit in the performance test experiment.

[0028] Figure 7 Graph showing the charge and discharge characteristics of the charge pump circuit of the present invention in a performance test experiment.

[0029] Figure 8 This is the design layout of the charge pump circuit of the present invention used in the performance test experiment. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0031] Example 1

[0032] This embodiment provides a charge pump circuit for a phase-locked loop, such as Figure 1 As shown, it is composed of 9 NMOS transistors M1 to M8, M15, 6 PMOS transistors M9 to M14, a digitally controlled current source DAC, two capacitors C1 and C2, and two rail-to-rail operational amplifiers AMP1 and AMP2. Specifically, the circuit connection between the various components in the charge pump circuit provided by this embodiment is as follows:

[0033] The sources of M13 and M14, along with the gates of M1-M3, M11, and M15, and the DAC power supply, are connected to VDD. The gates of M5 and M13, along with the sources of M1, M2, and M15, are grounded. The drains of M11 and M13 are connected to the sources of M9 and M11. The drains of M7 and M9 are connected to the non-inverting input of AMP2. The drains of M8 and M10 are connected to the inverting input of AMP2 and serve as the output port Vout of the charge pump circuit. The output of AMP2 is connected to M9, M10, and one end of C1, with the other end of C2 connected to the power supply. The drains of M12 and M14 are connected to the sources of M10 and M12; the DAC current output is connected to the drain of M15 and the non-inverting input of AMP1. The drain of M1 and the source of M3 are connected to the inverting input of AMP1. The output of AMP1 is connected to the gates of M7 and M8 and one end of C2, with the other end of C2 connected to the power supply. The sources of M5 and M7 are connected to the drains of M3 and M7; the sources of M6 and M8 are connected to the drains of M4 and M6. The source of M3 is connected to the drain of M2; the gates of M14 and M4 are connected to differential signals UP and DW, respectively. The gate of M12 is connected to the pull-up signal UPN; and the gate of M6 is connected to the switch control signal DWN.

[0034] exist Figure 1 In the circuit shown, a digitally controlled current source DAC employs a binary-weighted MOS resistor array architecture with adaptive compensation circuitry. This current source can precisely configure a multi-level programmable bias current, Icp, based on a multi-bit control code. This digitally controlled current source DAC also adaptively compensates its output bias current based on Vout. This ensures output current stability over a wide temperature range and dynamically compensates for current drops caused by channel length modulation, meeting the precise current control requirements of a phase-locked loop (PLL).

[0035] Specifically, in practical applications, the digitally controlled current source DAC in the charge pump circuit can be used as follows Figure 2 The circuit shown includes a current bias circuit, a current proportional mirror array, a MOS-R switch array and an adaptive compensation circuit. The current proportional mirror array includes n branches, each branch contains a number of 1:2:...:2 n-1 Multiple PMOS transistors connected in parallel. The gates of all PMOS transistors in each branch are connected, and the sources are connected to VDD. The MOS-R switch array includes n switch units corresponding to the number of branches in the current proportional mirror array; each switch unit includes an NMOS transistor and a resistor. The drain of the NMOS transistor in each switch unit is connected to the drain of the PMOS transistor in the corresponding branch of the current proportional mirror array. The gate of the NMOS transistor in each switch unit is connected to the control signal D <0> ~D <n-1>, the source is connected to one end of the resistor, and the other end of the resistor is connected and serves as the output port A of the bias current Icp.

[0036] The current bias circuit includes two PMOS transistors M20 and M21, four NMOS transistors M18, M19, M22, and M23, and two resistors R1 and R2. The sources of M20 and M21, the drain of M19, and one end of R1 are connected to the power supply; the other end of R1 is connected to the gates of M18 and M19, as well as the drain of M18. The sources of M18 and M23 and one end of R2 are grounded; the other end of R2 is connected to the gate of M23 and the source of M22. The drains of M20 and M23 are connected to the source of M19 and the gate of M1; the drains of M21 and M22 are connected. The gates of M20 and M21 are connected to the gates of the PMOS transistors in each branch of the current proportional mirror array. The adaptive compensation circuit is composed of PMOS tubes M16 and M17; the source of M17 is connected to the power supply; the drain and gate of M17 are connected to the source of M16; the drain of M16 is connected to port A; and the gate of M16 is connected to Vout.

[0037] Specifically, in a digitally controlled current source DAC, a current bias circuit is used to generate a reference current. The current proportional mirror array, MOS-R switch array, and adaptive compensation circuit constitute the bias current output section. Each branch of the current proportional mirror array can utilize a different number of PMOS transistors as current sources to output the corresponding unit current; since the number of PMOS transistors in each branch is 1:2:…:2, the current proportional mirror array can generate a reference current. n-1 Therefore, the unit current output by each branch also increases at a corresponding rate; under this condition, the MOS-R switch connected under each branch constitutes a switch connected to the output node A. By switching the gate voltage of the NMOS tube in each switch unit (that is, D <0> ~D <n-1>) can switch the conduction state of the corresponding branch in the current proportional mirror array. For example, when D <0> ~D <n-1>When any one of the MOSFETs is high, the corresponding switch turns on, activating the current branch with the corresponding weight. Therefore, when different numbers of MOSFETs are turned on, the number of current branches activated and connected to the output node A varies. This allows the output bias current Icp to be adjusted based on the multi-bit control code.

[0038] For example, in Figure 2 In the circuit shown, both the current proportional mirror array and the MOS-R switch array employ a four-stage circuit structure. Therefore, a 4-bit control code (D3D2D1D0) can dynamically configure 16 levels of programmable bias current. For example, when the control code is 0011 (corresponding to the decimal number 3), the channels corresponding to the primary and secondary branches are turned on, the first branch outputs unit current, and the second branch outputs twice the unit current. The final bias current Icp output by the circuit is 3 times the unit current. When the control code is 0101 (corresponding to the decimal number 5), the channels corresponding to the primary and tertiary branches are turned on, the first branch outputs unit current, and the second branch outputs four times the unit current. The final bias current Icp output by the circuit is 5 times the unit current. In other words, the magnitude of the bias current Icp output by the digitally controlled current source DAC is controlled by an n-bit control code consisting of the control signal connected to the gate of the NMOS transistor in the switch unit. The value of the n-bit control code represents the ratio of the bias current Icp to the unit current.

[0039] On this basis, the digitally controlled current source DAC of this embodiment can also construct a closed-loop feedback mechanism through the PMOS transistors M16 and M17 in the adaptive compensation circuit. Among them, the source of M16 is directly connected to the power supply VDD, and the gate and drain are short-circuited to form a diode connection structure, so that the drain voltage is stable at VDD-|V thp ∣(V thp is the PMOS threshold voltage), providing a reference bias for subsequent circuits. The source of M17 is connected to the drain of M16. The gate monitors the voltage change of the output node Vout in real time. The drain is connected to the output end of the current source Icp to form a dynamic feedback path. When the load changes and causes the Vout voltage to drop, the gate-source voltage of M17 VGS=(VDD-|V thp ∣)-Vout increases accordingly, enhancing its conduction capability and injecting additional compensation current from the Icp terminal to offset the loss of charge and discharge current. Conversely, when Vout increases, the conduction degree of M17 decreases, and the compensation current automatically decreases until it is turned off. This structure can quickly adjust the compensation amount according to the real-time status of the output node Vout, effectively suppressing current fluctuations caused by process deviations, temperature drift or load transients, ensuring that the charge pump can maintain stable output current characteristics over a wide voltage range (such as as low as the deep subthreshold region or as high as near the power rail), significantly improving the system's linearity and anti-interference capabilities.

[0040] exist Figure 1 In the charge pump circuit shown, PMOS transistors M9, M10, M13, and M14 form the circuit's pull-up network, while NMOS transistors M3, M4, M7, and M8 form the pull-down network. These two transistors work together to achieve the charge and discharge functions of the charge pump. The charge pump circuit of this embodiment employs a single-ended source-switched topology. Compared to conventional drain-switched topologies, this circuit avoids output voltage peak interference caused by clock feedthrough and improves phase-locked loop stability. Compared to gate-switched topologies, the present invention also shortens transient response time due to its superior transconductance characteristics. In practical applications, this charge pump circuit employs a three-state operating mode. When the UP signal is valid, the PMOS transistor M14 (source connected to VDD, gate controlled by UP) is turned on, and current is injected into the output node through M12 and M10 to complete charging; when the DW signal is valid, the NMOS transistor M4 (source connected to ground, gate controlled by DW) is turned on, and current is extracted from the output node through M2 to complete discharging; when both UP / DW are invalid, M14 and the complementary switch transistor are turned off, and the output node Vout enters a high-impedance state, completely eliminating the shoot-through current, reducing the static power consumption to the microampere level, and at the same time improving the switching speed and shortening the response time.

[0041] In the charge pump circuit of this embodiment, one end of the digitally controlled current source DAC is connected to VDD, and the other end is connected to the drain of NMOS transistor M15. The gates of NMOS transistors M1, M2, and M15 are connected to VDD to maintain their on-state. The sources of M1 and M2 are connected to the drains of M3 and M4, respectively. Finally, the drains of M1, M2, and M15 are grounded, forming a classic current mirror structure. This structure accurately replicates the bias current Icp output by the digitally controlled current source DAC, providing a stable foundation for subsequent current matching and amplification. Furthermore, by properly selecting the width-to-length ratio of M1, M2, and M15, the reference current required for current matching and amplification can be flexibly adjusted.

[0042] Based on functional division, the charge pump circuit of this embodiment includes three parts, in addition to the digitally controlled current source DAC, a linear current mirror, a current matching control module, and a transient optimization module. This circuit can achieve low-noise output through precise current mirroring and noise suppression. The linear current mirror achieves high-precision mirroring of the reference current through the MOS tube current mirror structure and operational amplifier negative feedback regulation. The current matching control module dynamically adjusts the conduction state of the switch tube by real-time monitoring the potential difference between the output branch and the mirror branch, suppressing output voltage fluctuations caused by clock feedthrough and charge injection effects. The transient optimization module suppresses voltage spikes during the switching process through low-pass filter capacitors and switching noise suppression structures, and shortens transient recovery time to nanoseconds by optimizing switching timing and transconductance characteristics.

[0043] The linear current mirror consists of MOS transistors M1 and M15 operating in the linear region and an operational amplifier AMP1. The negative feedback of the operational amplifier forcibly clamps the drain voltage of the MOS transistors, creating an output impedance multiplication mechanism. This significantly improves the accuracy of the current mirror and reduces the impact of channel length modulation. Specifically, the source of NMOS transistor M1 is grounded, its gate is directly connected to the power supply voltage, and its drain is connected to the output of operational amplifier AMP1. The source of NMOS transistor M15 is grounded, its gate is also connected to the power supply voltage, and its drain is connected to the inverting input of AMP1. This connection allows AMP1 to monitor the drain voltage difference between M1 and M15 in real time and dynamically adjust it through negative feedback, forming an output impedance multiplication structure. Ideally, this structure can increase the output impedance of the current mirror several times, effectively suppressing the channel length modulation effect and improving the accuracy of the current mirror, significantly outperforming traditional single-stage current mirror structures.

[0044] The current matching control module connects nodes X and Y between the output branch and the mirror branch via a rail-to-rail operational amplifier AMP2. The operational amplifier's "virtual short" characteristic forces the potentials of nodes X and Y to be equal, achieving high-precision matching of the output current with the reference current and effectively suppressing the impact of current mismatch on the phase-locked loop's performance. Specifically, AMP2's non-inverting input is connected to node X (located between the drains of PMOS transistors M7 and M9), its inverting input is connected to node Y (located between the drains of PMOS transistors M8 and M10), and its output directly controls the gate voltages of PMOS transistors M9 and M10. M9's source is connected to the drain of PMOS transistor M13 via switch M11, and its drain is connected to the drain of M7. M10's source is connected to the drain of PMOS transistor M14 via switch M12, and its drain is connected to the drain of M8. This cross-connected differential input structure enables AMP2 to detect the current difference between the output branch (M7 / M8) and the mirror branch (M9 / M10) in real time, and force the potentials of nodes X and Y to be consistent by adjusting the gate voltages of M9 and M10.

[0045] The transient optimization module includes capacitors C1 and C2 connected in parallel at the output of the operational amplifier, as well as a switching noise suppression structure consisting of dummy transistors M5, M6, M11, and M12, and isolation transistors M7-M10. Capacitor C1's two sides are connected to the gates of M9 and M10 and VDD, respectively. Capacitor C2's two sides are connected to the gates of M7, M8, and M2. The source and drain of the dummy transistors are connected to each other, the gate of M5 is connected to VSS, the gate of M6 is connected to the DWN signal, the gate of M11 is connected to VDD, and the gate of M12 is connected to the UPN signal. The transient optimization module ensures stability and low-noise characteristics during switching through a multi-level noise suppression design. Its core consists of a filtering network and a charge compensation structure: capacitor C1 (connected between the gates of PMOS transistors M9 / M10 and the power supply VDD) and capacitor C2 (connected between the gates of PMOS transistors M7 / M8 and the gate of NMOS transistor M2) form a low-pass filtering network. By absorbing high-frequency components, it effectively suppresses transient gate voltage spikes (such as overshoot or undershoot) caused by switching. At the same time, the dummy transistors M5-M6 with shorted source and drain terminals (the gates are fixedly grounded to VSS and connected to the switch control signal DWN) work together with M11-M12 (the gates are connected to the power supply VDD and the pull-up signal UPN). When the main switch transistors M4 and M14 are switched on / off, the dummy transistors balance the parasitic capacitance charges of key nodes (such as the drain capacitance of M4 and the gate capacitance of M14) in advance through pre-charge and discharge actions, offsetting the transient errors caused by the charge injection effect and the clock feedthrough effect, and reducing the switching noise peak to below the millivolt level.

[0046] This combined design not only significantly reduces the interference of switching transients on the charging and discharging paths, but also shortens the stabilization time through smooth voltage transition, allowing the charge pump to maintain high-precision current output in high-speed switching scenarios, while improving the system's robustness to process fluctuations and temperature changes.

[0047] In the charge pump circuit designed in this embodiment, two rail-to-rail operational amplifiers AMP1 and AMP2 are used. Figure 3 As shown in Figure 1, rail-to-rail operational amplifiers AMP1 and AMP2 consist of three parts: a complementary input stage, a folded cascode structure, and an output stage. They employ a parallel NMOS-PMOS differential pair structure. The NMOS transistor processes input signals close to VSS, while the PMOS transistor processes input signals close to VDD. The complementary input stage design allows input signals to approach or even reach the power rails. Through optimized input stage topology, transconductance stability is maintained over a wide input range, preventing gain fluctuations caused by input voltage variations.

[0048] Specifically, in the complementary input stage, the source of NMOS transistor M32 is grounded, its gate is connected to bias voltage Vbn, and its drain is connected to the sources of M34 and M35. The source of PMOS transistor M33 is connected to the source of M36 and the drain of M37. Its gate receives input signal Vip, and its drain is connected to the source of M41. The gate of M34 receives input signal Vip, and its drain is connected to the drain of M47. The gate of M35 receives input signal Vin, and its drain is connected to the source of M34 and the drain of M32. The gate of M36 receives input signal Vin, and its drain is connected to the source of M40. The source of M37 is connected to the power supply, its gate is connected to bias voltage Vbp, and its drain is connected to the sources of M33 and M36. This section implements full coverage reception of input signals from the power rail to the ground rail.

[0049] In the folded cascode structure, the source of NMOS tube M38 is grounded, the gate is connected to the drain of M40, and the drain is connected to the source of M40; the source of M39 is grounded, the gate is connected to the gate of M38, and the drain is connected to the source of M41; the source of M40 is connected to the drain of M38, the gate is connected to the bias voltage Vb2, and the drain is connected to the source of M43 and the drain of M42; the gate of M41 is connected to the bias voltage Vb2, and the drain is connected to the source of M44 and the drain of M45; the source of M42 is connected to M43's drain and gate are connected to bias voltage Vb3, and its drain is connected to M43's source. M43's gate is connected to bias voltage Vb4, and its drain is connected to M42's source. M44's source is connected to M45's drain, its gate is connected to bias voltage Vb4, and its drain is connected to M45's source. M45's gate is connected to bias voltage Vb3, and its drain is connected to M44's source. M46's gate is connected to bias voltage Vb1, its source is connected to M48's drain, and its drain is connected to M45's source and M44's drain. M47's source is connected to the power supply, its gate is connected to M45's drain, and its drain is connected to M45's source. M48's source is connected to the power supply, its gate is connected to M47's gate, and its drain is connected to M46's source. This structure achieves high-gain signal amplification.

[0050] In the output stage, the source of the PMOS tube M50 is connected to the power supply, the gate is connected to the drain of M46, and the drain outputs the signal V1; the source of the NMOS tube M49 is grounded, the gate is connected to the drain of M41, and the drain outputs the signal V1; the network composed of resistors and capacitors is connected between the output end and the bias voltage to play a frequency compensation role and ensure stable output of the circuit.

[0051] AMP1 forms a linear current mirror with a PMOS transistor. Based on the circuit principles of a rail-to-rail operational amplifier, the parallel NMOS-PMOS structure in AMP1's input stage maintains a constant transconductance over a wide range, stably converting the input signal into output current. AMP1's output stage dynamically clamps a high-impedance current mirror, suppressing channel-length modulation effects and providing a stable output current. Combined, these two elements achieve high gain stability across the full power supply range, improving the flatness of the charge and discharge currents. AMP2, connected across nodes X and Y between the output branch and the mirror branch, leverages the operational amplifier's virtual short characteristic (VX = VY) to feed the deviation between the output current and the reference current back into the control loop, ultimately achieving high-precision matching of the two current paths (mismatch rate less than 0.2% over the entire operating range). This design not only eliminates static errors caused by process variations but also dynamically compensates for temperature changes and power supply fluctuations, laying a critical foundation for the charge pump's stable output.

[0052] To better manufacture and use the charge pump circuit of the present invention in practical applications, this embodiment also provides a charge pump module, which is encapsulated from the aforementioned charge pump circuit for a phase-locked loop. The charge pump module's pins include: a power supply terminal VDD, a ground terminal VSS, an output port Vout, control ports UP and DW, and control ports UPN and DWN. The power supply terminal is used to connect to a power source, the ground terminal is used for grounding, and the output port is used to output the desired voltage signal. UP and DW are respectively connected to differential control signals for adjusting the charge pump's operating state; UPN and DWN are respectively connected to pull-up signals and switch control signals.

[0053] Example 2

[0054] Based on the solution of embodiment 1, this embodiment provides a phase-locked loop, such as Figure 4 As shown in Figure 1, it consists of a phase frequency detector (PFD), a charge pump circuit (CP), a loop filter (LPF), a voltage controlled oscillator (VCO), and a frequency divider. The output of the CP is processed by the LPF and then used as the input of the VCO. The output of the VCO is processed by the frequency divider to generate the feedback frequency f div ;PFD combined with reference frequency f REF and f div The control signals UP and DOWN are generated for regulating the charge pump circuit CP.

[0055] As a core component of a phase-locked loop (PLL), the charge pump's performance directly determines the PLL's locking speed, phase noise level, and loop stability. This makes it crucial for electronic systems such as communications and radar that rely on high-precision frequency synthesis and signal synchronization. In this embodiment of the PLL, the charge pump circuit uses the PLL charge pump circuit of Example 1. Because the charge pump circuit of Example 1 can output multiple levels of bias current and achieve more stable output across the full swing range, it overcomes the effects of temperature drift and noise, significantly improving the PLL's performance.

[0056] In combination with the aforementioned phase-locked loop, this embodiment further provides a communication chip, which adopts the aforementioned phase-locked loop, thereby further improving the performance of the communication chip.

[0057] Performance Testing

[0058] In order to verify the Figure 1-Figure 3 To understand the performance of the charge pump circuit shown, technicians simulated and tested the circuit; the experimental items and test results of the test experiment are as follows:

[0059] 1. Stability test:

[0060] This experiment first measures the loop gain and phase margin of the input rail-to-rail operational amplifier in the circuit. The obtained loop gain curve and phase margin curve are as follows Figure 5 Analysis Figure 5 From the data in , we can see that the gain of this input rail-to-rail operational amplifier is 76.39dB and the phase margin is 83.4°.

[0061] Gain represents the operational amplifier's ability to amplify the input signal. A higher gain indicates a greater amplification factor. In a charge pump circuit, a higher gain effectively amplifies weak control signals, enabling precise control of the charge pump's charge and discharge currents and improving the charge pump's current control accuracy. For example, in a phase-locked loop (PLL) system, this allows for more precise output voltage regulation, enabling the PLL to lock onto the target frequency more quickly and reducing frequency error. Phase margin is a key indicator of the stability of a negative feedback system. It represents the amount of phase variation the system can tolerate before becoming unstable. A larger phase margin indicates a more stable system and is less likely to oscillate. In a charge pump circuit, a larger phase margin ensures stable operation of the operational amplifier at different frequencies, preventing instability in the charge pump circuit caused by phase issues, such as excessive output voltage fluctuations. This helps maintain PLL stability and ensures reliable operation of the entire system. Generally speaking, a phase margin of approximately 45° indicates system stability. The 83.4° phase margin of this operational amplifier demonstrates good stability and provides stable signal processing capabilities for the charge pump circuit.

[0062] 2. Charge and discharge current matching test:

[0063] In a charge pump circuit, the matching degree of charge and discharge current is a key factor in determining its performance. This implementation tests the current matching of the charge pump circuit provided by the present invention and compares it with the current matching of existing charge pump circuits.

[0064] After testing, the current matching of the traditional charge pump is as follows Figure 6 As shown in part (a) of the diagram, the curves of the charging current Iup and the discharging current Idn show a significant difference, with the maximum mismatch reaching 0.42μA. This large current deviation, under the action of different control voltages Vctrl, will seriously interfere with the normal charging and discharging process of the charge pump. Specifically, due to the imbalance of the charging and discharging currents, the output voltage will fluctuate significantly. For the phase-locked loop system that relies on the precise control of the charge pump, this fluctuation will directly translate into an increase in phase noise. The increase in phase noise not only deteriorates the signal quality, but also significantly prolongs the frequency locking time, making the entire system slow to respond to frequency adjustment requirements and difficult to quickly and accurately reach the target frequency, resulting in a significant decrease in system performance. This makes it impossible to meet the requirements of application scenarios such as communications and radar that have extremely high requirements for frequency stability and accuracy.

[0065] On the other hand, the current matching of the charge pump of the present invention is as follows: Figure 6 As shown in part (b), the curves of the charging current Iup and the discharging current Idn almost perfectly overlap, the maximum mismatch is controlled at an extremely low 0.21μA, and the charge and discharge matching reaches an extremely high level. This highly precise charge and discharge matching can ensure that the charge pump can stably and accurately perform charge and discharge operations under various working conditions. The stable charge and discharge process effectively suppresses the output voltage ripple and greatly reduces the phase noise. At the same time, due to the precise matching of the charge and discharge currents, the phase-locked loop system can lock the target frequency more quickly and accurately, greatly improving the response speed and stability of the system. This outstanding performance enables the charge pump of the present invention to play an important role in fields with strict requirements on zero frequency control accuracy, such as high-speed communications, high-precision radar detection, etc., and provide more reliable and stable frequency control guarantees for related electronic systems.

[0066] 3. Charge pump charge and discharge characteristics test:

[0067] This embodiment tests the charge and discharge characteristics of the charge pump circuit provided by the present invention, and obtains the following results: Figure 7 The charge and discharge waveforms are shown in Figure 2. Figure 7 In the waveform shown, the horizontal axis is time (Time), the unit is nanosecond (ns), and the range is from 0 to 20ns; the vertical axis is the charge pump output voltage (CP_OUT), the unit is volt (V), and the range is from 0.48V to 0.64V.

[0068] The curves in the figure show that both the charging waveform and the discharge waveform are in a step-like shape. During charging, the blue charging waveform gradually rises in a step-like shape, and each step represents a voltage jump at a specific time point, which reflects that the charge pump discretely increases the output voltage during the charging process; during discharging, the red discharge waveform also gradually decreases in a step-like shape, and each step corresponds to a voltage drop, indicating that the charge pump discretely reduces the output voltage during the discharge process. The charge pump circuit provided by the present invention has a step-like charging and discharging, and has the advantages of precise voltage control, fast response capability, good stability and efficient energy transmission, and can meet a variety of application scenarios with strict requirements on voltage accuracy, response speed, stability and energy efficiency.

[0069] 4. Power consumption and area test:

[0070] This experiment also designs the layout of the charge pump circuit diagram. Figure 8 As shown in the figure, the simulation results combined with the layout show that at a 1MHz frequency offset, the peak power consumption is 729.33μW and the phase noise is -136.63dBc / Hz. In addition, the design is implemented in a 28nm CMOS process and occupies an area of ​​0.0195mm 2 .

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A charge pump circuit for a phase-locked loop, characterized in that: It consists of 9 NMOS transistors M1 to M8, M15, 6 PMOS transistors M9 to M14, a digitally controlled current source DAC, two capacitors C1 and C2, and two rail-to-rail operational amplifiers AMP1 and AMP2; the circuit connection is: The sources of M13 and M14, the gates of M1 to M3, M11 and M15, and the power supply of DAC are connected to VDD; the gates of M5 and M13, and the sources of M1, M2 and M15 are grounded; the drains of M11 and M13 are connected to the sources of M9 and M11; the drains of M7 and M9 are connected to the non-inverting input of AMP2; the drains of M8 and M10 are connected to the inverting input of AMP2 and serve as the output port Vout of the charge pump circuit; the output of AMP2 is connected to M9, M10 and one end of C1, and the other end of C2 is connected to the power supply; the drains of M12 and M14 are connected to M1 The sources of M0 and M12 are connected; the current output of the DAC is connected to the drain of M15 and the non-inverting input of AMP1; the drain of M1 and the source of M3 are connected to the inverting input of AMP1; the output of AMP1 is connected to the gates of M7 and M8 and one end of C2, and the other end of C2 is connected to the power supply; the sources of M5 and M7 are connected to the drains of M3 and M7; the sources of M6 and M8 are connected to the drains of M4 and M6; the source of M3 is connected to the drain of M2; the gates of M14 and M4 are connected to the differential signals UP and DW respectively; the gate of M12 is connected to the pull-up signal UPN; the gate of M6 is connected to the switch control signal DWN; The digitally controlled current source DAC adopts a binary weighted MOS resistor array architecture including an adaptive compensation circuit, which is dynamically configured by an n-bit control code. n The programmable bias current Icp of the stage can be adaptively compensated for the bias current of its own output according to Vout.

2. The charge pump circuit for a phase-locked loop according to claim 1, wherein: The digitally controlled current source DAC includes a current bias circuit, a current proportional mirror array, a MOS-R switch array and an adaptive compensation circuit; wherein the current proportional mirror array includes n branches, each branch contains a number of 1:2:...:2 n-1 The MOS transistors in each branch are connected in parallel; the gates of the MOS transistors in each branch are connected, and the sources are connected to VDD; the MOS-R switch array includes n switch units corresponding to the number of branches in the current proportional mirror array, each switch unit includes an NMOS transistor and a resistor; the drain of the NMOS transistor in each switch unit is connected to the drain of the PMOS transistor in the corresponding branch in the current proportional mirror array; the gate of the NMOS transistor in each switch unit is connected to the control signal D <0> ~D <n-1> , the source is connected to one end of the resistor, and the other end of the resistor is connected and serves as the output port A of the bias current Icp; The current bias circuit includes two PMOS transistors M20 and M21, four NMOS transistors M18, M19, M22, and M23, and two resistors R1 and R2. The sources of M20 and M21, the drain of M19, and one end of R1 are connected to a power supply. The other end of R1 is connected to the gates of M18 and M19, and the drain of M18. The sources of M18 and M23 and one end of R2 are grounded. The other end of R2 is connected to the gate of M23 and the source of M22. The drains of M20 and M23 are connected to the source of M19 and the gate of M1. The drains of M21 and M22 are connected. The gates of M20 and M21 are connected to the gates of the PMOS transistors on each branch in the current proportional mirror array. The adaptive compensation circuit is composed of PMOS tubes M16 and M17; the source of M17 is connected to the power supply; the drain and gate of M17 are connected to the source of M16; the drain of M16 is connected to port A; and the gate of M16 is connected to Vout.

3. The charge pump circuit for a phase-locked loop according to claim 2, wherein: The magnitude of the bias current Icp output by the digitally controlled current source DAC is controlled by an n-bit control code consisting of a control signal connected to the gate of the NMOS tube in the switch unit; the value of the n-bit control code is the ratio of the bias current Icp to the unit current.

4. The charge pump circuit for a phase-locked loop according to claim 1, wherein: The PMOS tubes M9, M10, M13, and M14 form the pull-up network of the circuit, and the NMOS tubes M3, M4, M7, and M8 form the pull-down network. The two work together to realize the charging and discharging functions of the charge pump. When the UP signal is valid, the charge pump circuit is in a charging state; when the DW signal is valid, the charge pump circuit is in a discharging state; when both UP and DW are invalid, the output port of the charge pump circuit is in a high-impedance state.

5. The charge pump circuit for a phase-locked loop according to claim 4, wherein: M1, M15 and AMP1 form a linear current mirror circuit. AMP1 is used to monitor the drain voltage difference between M1 and M15 in real time, and then dynamically adjust it through a negative feedback mechanism to form an output impedance multiplication structure and suppress the channel length modulation effect, thereby improving the mirror accuracy of the current mirror circuit.

6. The charge pump circuit for a phase-locked loop according to claim 5, wherein: Capacitors C1 and C2, along with M5, M6, M11, and M12 (dummy transistors) and M7, M8, M9, and M10 (isolation transistors), form a switching noise suppression structure. Capacitors C1 and C2 act as energy storage elements and form a low-pass filter network, which absorbs high-frequency components to smooth voltage fluctuations during the charge pump circuit's switching process. The nodes at the two input ends of AMP2 are denoted as X and Y. AMP2 is used to detect the current difference between the output branch and the mirror branch in real time based on the input signal. It adjusts the gate voltage of M9 and M10 through its own output, forcing the potentials of nodes X and Y to be consistent. The deviation between the output current and the reference current is then fed back to the control loop to achieve high-precision matching of the two currents.

7. The charge pump circuit for a phase-locked loop according to claim 1, wherein: The rail-to-rail operational amplifiers AMP1 and AMP2 are composed of three parts: a complementary input stage, a folded cascode structure, and an output stage; AMP1 and AMP2 adopt a parallel NMOS-PMOS differential pair structure.

8. A charge pump module, comprising the charge pump circuit for a phase-locked loop according to any one of claims 1 to 7, wherein the pins of the charge pump module include: Power supply terminal VDD, Ground terminal VSS, Output port Vout, Control ports UP and DW, which are used to connect differential control signals respectively; Control ports UPN and DWN; they are used to connect pull-up signals and switch control signals respectively.

9. A phase-locked loop, characterized in that: The circuit is composed of a phase frequency detector (PFD), a charge pump circuit (CP), a loop filter (LPF), a voltage controlled oscillator (VCO), and a frequency divider; the charge pump circuit adopts the charge pump circuit for a phase-locked loop as described in any one of claims 1 to 7; wherein the output of the CP is processed by the LPF and then used as the input of the VCO, and the output of the VCO is processed by the frequency divider to generate a feedback frequency f div ;PFD combined with reference frequency f REF and f div The control signals UP and DOWN are generated for regulating the charge pump circuit CP.

10. A communication chip, characterized in that: It adopts the phase-locked loop as claimed in claim 9.

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