System and method for memory block allocation

Abstract

A system and method for memory block allocation. In some embodiments, a method includes receiving a memory allocation request from an application, the memory allocation request including: a number of blocks of memory and a first address; determining that the memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

Description

TECHNICAL FIELD

[0001] One or more aspects of embodiments according to the present disclosure relate to storage devices, and more particularly to block allocators. BACKGROUND

[0002] Computing systems can be used for a variety of tasks. A computing system can include processing circuitry (e.g., a central processing unit (CPU)), main memory, and a storage device. In operation, a computing system can read data from a storage device into main memory, perform data processing operations on the data in main memory, save the results of the data processing operations in main memory, and store the data saved in main memory (e.g., the results of the data processing operations) in the storage device.

[0003] Aspects of the present disclosure are relevant to the general technical field related thereto. SUMMARY

[0004] According to embodiments of the present disclosure, a method is provided that includes receiving a memory allocation request from an application, the memory allocation request including: a number of blocks of memory and a first address; determining that the memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

[0005] In some embodiments: the memory is non-volatile memory in a storage device, and the method further includes computing the first threshold based on the first address and an input-output size limit of the storage device.

[0006] In some embodiments: the memory is non-volatile memory in a storage device that is compatible with an interface protocol that provides reporting of an input-output size limit of the storage device, and the method further includes computing the first threshold based on the first address and the input-output size limit.

[0007] In some embodiments, determining that the memory at the first address is allocated includes searching an entry indexed by the first address in a data structure.

[0008] In some embodiments, determining that the memory at the first address is allocated includes searching an entry indexed by the first address in a data structure that is configured to be searched in logarithmic time.

[0009] In some embodiments: the memory allocation request further includes a second address; and the memory is non-volatile memory in a storage device, and the method further includes computing the first threshold based on: the first address, the second address, and an input-output size limit of the storage device.

[0010] In some embodiments: determining that the memory at the first address is allocated comprises searching a first data structure for an entry indexed by the first address; and the identification of the second address comprises searching a second data structure for an entry indexed by the number of blocks of memory.

[0011] In some embodiments: determining that the memory at the first address is allocated comprises searching a first data structure for an entry indexed by the first address; the identification of the second address comprises searching a second data structure for an entry indexed by the number of blocks of memory; and the second data structure stores one or more addresses of free regions of memory at indexed nodes.

[0012] According to an embodiment of the disclosure, there is provided a system comprising: processing circuitry; and a memory operatively connected to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the system to perform a method comprising: receiving, from an application, a memory allocation request, the memory allocation request comprising: a number of blocks of memory and a first address; determining that the memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

[0013] In some embodiments: the memory is non-volatile memory in a storage device, and the method further comprises calculating the first threshold based on the first address and an input-output size limit of the storage device.

[0014] In some embodiments: the memory is non-volatile memory in a storage device compatible with an interface protocol that provides reporting of an input-output size limit of the storage device, and the method further comprises calculating the first threshold based on the first address and the input-output size limit.

[0015] In some embodiments, determining that the memory at the first address is allocated comprises searching a data structure for an entry indexed by the first address.

[0016] In some embodiments, determining that the memory at the first address is allocated comprises searching a data structure for an entry indexed by the first address, the data structure being configured to be searched in logarithmic time.

[0017] In some embodiments: the memory allocation request further comprises a second address; and the memory is non-volatile memory in a storage device, and the method further comprises calculating the first threshold based on: the first address, the second address, and an input-output size limit of the storage device.

[0018] In some embodiments: determining that the memory at the first address is allocated comprises searching an entry indexed by the first address in a first data structure; and the identification of the second address comprises searching an entry indexed by the number of blocks of memory in a second data structure.

[0019] In some embodiments: determining that the memory at the first address is allocated comprises searching an entry indexed by the first address in a first data structure; the identification of the second address comprises searching an entry indexed by the number of blocks of memory in a second data structure; and the second data structure stores one or more addresses of free regions of memory at indexed nodes.

[0020] According to embodiments of the disclosure, there is provided a system comprising: a computer readable medium storing instructions that, when executed by one or more processing circuits, cause the one or more processing circuits to: execute an application configured to call an allocation request method of a block allocator, the allocation request method taking as arguments: a number of blocks of memory and a first address; the computer readable medium further storing instructions that, when executed by the one or more processing circuits, cause the one or more processing circuits to execute the allocation request method, the execution of the allocation request method comprising: determining that the memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

[0021] In some embodiments: the memory is non-volatile memory in a storage device, and the method further comprises computing the first threshold based on the first address and an input-output size limit of the storage device.

[0022] In some embodiments: the memory is non-volatile memory in a storage device compatible with an interface protocol that provides reporting of an input-output size limit of the storage device, and the method further comprises computing the first threshold based on the first address and the input-output size limit.

[0023] In some embodiments, determining that the memory at the first address is allocated comprises searching an entry indexed by the first address in a data structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] These and other features and advantages of the present disclosure will be recognized and understood by those skilled in the art upon reading this specification, claims, and attached drawings, in which:

[0025] Figure 1A is a block diagram of a host and storage device according to embodiments of the present disclosure;

[0026] Figure 1B is a system level block diagram according to embodiments of the present disclosure;

[0027] Figure 1C is a block diagram of a storage device according to embodiments of the present disclosure;

[0028] Figure 2A is a diagram of allocated and free memory in a storage device according to embodiments of the present disclosure;

[0029] Figure 2B is a diagram of a first data structure according to embodiments of the present disclosure;

[0030] Figure 2C is a diagram of a second data structure according to embodiments of the present disclosure;

[0031] Figure 3A is a flow diagram of an allocation according to embodiments of the present disclosure;

[0032] Figure 3B is a flow diagram of a deallocation according to embodiments of the present disclosure;

[0033] Figure 3C is a flow diagram of a split operation according to embodiments of the present disclosure;

[0034] Figure 3D is a flow diagram of a merge operation according to embodiments of the present disclosure; and

[0035] Figure 4 is a flow diagram of a method for allocation according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] The detailed description set forth below, in connection with the appended drawings, is intended as a description of exemplary embodiments of a block allocator provided in accordance with the present disclosure and is not intended to represent the only form in which the present disclosure can be constructed or utilized. The description sets forth the features of the present disclosure in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent features can be incorporated in different embodiments which are also intended to be encompassed within the scope of the present disclosure. Where the same or equivalent elements are shown in more than one figure, the same or equivalent elements are designated with the same reference numerals.

[0037] In computing systems, applications (e.g., software running in user space in a host device) can sometimes interact with storage systems to store or retrieve data. Storage systems can have characteristics that affect the performance of read and write operations in ways that depend on various circumstances. Storage devices can be connected to host devices through interfaces that exhibit better performance for input-output requests that meet certain input-output size limitations. For example, a read request to request data of the same capacity from a set of logical block addresses that span a range of logical block addresses that is greater than an input-output size limitation can be performed significantly faster by a storage device than a read request to request data from a set of logical block addresses where each logical block address falls within a range of logical block addresses that is less than or equal to the input-output size limitation. For a NonVolatile Memory Express (NVMe) solid state drive, for example, the optimal input-output (IO) boundary can be the input-output size limitation (e.g., the IO boundary can refer to a starting logical block address). As used herein, the input-output size limitation is a limitation on the size of IO operations for efficient operation (and it is not an absolute limitation). A storage device can report the input-output size limitation. For example, a storage device can have an interface that is compatible with an interface protocol (e.g., NVMe), and the interface protocol can provide for reporting the input-output size limitation of the storage device by the storage device in response to a query from a host. In some embodiments, a storage device has an interface that is compatible with different interface protocols, such as Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Ethernet remote direct memory access (RDMA), Serial Advanced Technology Attachment (SATA), Fiber Channel, Serial Attached SCSI (SAS), NVMe over Fabrics (NVMe-oF), etc.

[0038] As such, if data that would normally be retrieved or “read” in a single input-output operation (or “read operation”) is stored within a range of logical block addresses that is less than the input-output size limitation, the performance of the application can be improved. However, in some interfaces, when an allocation request is issued from a storage device, there is no mechanism available to the application to specify a preferred location for the allocation.

[0039] Systems in which the interface between applications and storage devices allows applications to specify a preferred location for storage space allocation can provide improved performance over systems that do not provide such a feature. For example, an application can manage a key-value store, storing identifiers (which can be referred to as “keys”), and for each key, storing zero or more values associated with the key. The system can use each key to identify the zero or more values associated with the key; for example, a host device can generate a key (e.g., using a hash function), and (i) store one or more values associated with the key, and (ii) retrieve one or more values associated with the key. The set of frequently performed operations can include (i) allocating storage space and storing a key at a first address (e.g., determined by hashing the key), (ii) in one or more additional separate operations, allocating additional storage space and storing a value or additional values associated with the key, and (iii) in a single operation, reading the key and one or more (e.g., all) values associated with the key. Alternatives to key-value stores can include other data structures, such as tables or heterogeneous structures (which can include groups of fields of different data types). If a key and all values associated with the key are stored within a range of logical block addresses that is less than an input-output size limit, then reading the key and one or more (e.g., all) values associated with the key can be performed more efficiently than if the key and all values associated with the key are not stored within a range of logical block addresses that is less than an input-output size limit.

[0040] Accordingly, in some embodiments, the block allocator exposes an allocation request method that an application can call for the purpose of arranging that certain memory (e.g., storage) allocations are proximate to one another, if possible. The allocation request method can take two arguments, (i) a size or “length,” and (ii) an address (which can be referred to as a “hint” or “requested allocation address”), and when the allocation request method is executed by the block allocator, the block allocator allocates memory proximate to the requested allocation address (e.g., within an input-output size limit of the requested allocation address).

[0041] The block allocator can use one or more suitable data structures stored in memory (e.g., in host memory) for storing a list of available address ranges to make identification of suitable address ranges available for allocation more efficient. In some embodiments, a first data structure (e.g., a first radix tree) is used to store available address ranges, where nodes are indexed by address, and where each node stores the size of the range available at that address. Such a tree can be searched for a requested allocation address in O(log n) time (or "log time"), and the tree can be searched for a next node or a previous node in O(l) time if there is no node at the requested allocation address or if the range available at the requested allocation address is too small. This can be repeated until (i) a node corresponding to an allocation is found, which, if made, would result in the entire allocated range being within the input-output size limit of the requested allocation address, or (ii) it is determined that there is no node that would allow an allocation to be made such that the entire allocated range is within the input-output size limit of the requested allocation address. As used herein, a "radix" tree can be a tree in which each node that is not a leaf node is connected to at least two child nodes. As used herein, a data structure that is "configured to be searched in log time," such as a radix tree, is a data structure that is capable of being searched using a number of operations that is proportional to the log of n, where n is the number of data storage elements (e.g., nodes) of the data structure.

[0042] In the latter case, i.e., if it is determined that there is no node that would allow an allocation to be made such that the entire allocated range is within the input-output size limit of the requested allocation address, the block allocator (e.g., the allocation request method of the block allocator) can perform a search of a second data structure to search for an address range, among the remaining available address ranges, that is large enough to accommodate the allocation request. The second data structure can be a second radix tree, where each node is indexed by size, and each node contains a data structure listing the addresses of all available ranges of that size. The data structure at a node can also be a radix tree. When performing a search of the second data structure, the block allocator can first search for the size specified in the call to the allocation request method (a search that can be performed in O(n) time for a radix tree), and if there is no node for that size, it can search for a next node (which can be performed in O(l) time for a radix tree). If there is a next node, it will identify at least one address at which there is an available address range of sufficient size, and the block allocator can then allocate a range at that address or within that available address range. If there is no next node, the allocation request method of the block allocator can return a value indicating that the allocation failed (e.g., "false" or "NULL").

[0043] Figure 1A A system, which can be referred to as "target" 100, in accordance with some embodiments of the present disclosure is shown. Referring to Figure 1A The target 100 can include a host device 102 and a storage device 104 (which can be a persistent storage device 104). In some embodiments, the host device 102 can be housed in the storage device 104, and in other embodiments, the host device 102 can be separate from the storage device 104. The host device 102 can include any suitable computing device that connects to the storage device 104, such as, for example, a personal computer (PC), a portable electronic device, a handheld device, a laptop computer, etc.

[0044] The host device 102 can connect to the storage device 104 through a host interface 106. The host device 102 can issue data request commands or input-output (IO) commands (e.g., read or write commands) to the storage device 104 through the host interface 106, and can receive responses from the storage device 104 through the host interface 106.

[0045] The host device 102 can include a host processor 108 and a host memory 110. The host processor 108 can be processing circuitry (discussed in further detail below), for example, such as a general purpose processor or a central processing unit (CPU) core of the host device 102. The host processor 108 can connect to other components via address buses, control buses, data buses, etc. The host memory 110 can be considered a high performance main memory (e.g., primary memory) of the host device 102. For example, in some embodiments, the host memory 110 can include (or can be) a volatile memory, such as, for example, dynamic random access memory (DRAM). However, the present disclosure is not so limited, and the host memory 110 can include (or can be) any suitable high performance main memory (e.g., primary memory) for the host device 102, as known to those skilled in the art. For example, in other embodiments, the host memory 110 can be a relatively high performance non-volatile memory, such as NAND flash memory, phase change memory (PCM) (a memory that uses a phase change of a material (e.g., chalcogenide) in a companion cell to store information by changing its resistance), resistive RAM (a memory in which information is stored by changing the resistance of a controllable resistor (or "memristor")), spin transfer torque RAM (STTRAM) (a memory in which a spin-polarized current can be used to change the magnetization of a magnetic layer of a memory cell), any suitable memory based on PCM technology, or resistive random access memory (ReRAM), etc.

[0046] The storage device 104 can operate as a secondary storage that can persistently store data that is accessible by the host device 102. In this context, the storage device 104 can include relatively slower storage when compared to the high-performance storage of the host memory 110. For example, in some embodiments, the storage device 104 can be a secondary storage of the host device 102, such as, for example, a solid-state drive (SSD). However, the present disclosure is not so limited, and in other embodiments, the storage device 104 can include (or can be) any suitable storage device, such as, for example, a magnetic storage device (e.g., a hard disk drive (HDD), etc.), an optical storage device (e.g., a Blu-ray disc drive, a compact disc (CD) drive, a digital versatile disc (DVD) drive, etc.), other kinds of flash memory storage devices (e.g., a USB flash drive, etc.), etc. In various embodiments, the storage device 104 can conform to a larger form factor standard (e.g., a 3.5-inch hard drive form factor), a smaller form factor standard (e.g., a 2.5-inch hard drive form factor), an M.2 form factor, an E1.S form factor, etc. In other embodiments, the storage device 104 can conform to any suitable or desirable derivative of these form factors. For convenience, the storage device 104 can be described hereinafter in the context of a solid-state drive, although the present disclosure is not so limited.

[0047] The storage device 104 can be communicatively connected to the host device 102 by a host interface 106. The host interface 106 can facilitate communication between the host device 102 and the storage device 104 (e.g., using a connector and a protocol). In some embodiments, the host interface 106 can facilitate the exchange of storage requests (or “commands”) and responses (e.g., command responses) between the host device 102 and the storage device 104. In some embodiments, the host interface 106 can facilitate data transfers to and from the host memory 110 of the host device 102 by the storage device 104. For example, in various embodiments, the host interface 106 (e.g., a connector and its protocol) can include (or can conform to) a small computer system interface (SCSI), a non-volatile memory express (NVMe), a peripheral component interconnect express (PCIe), an Ethernet remote direct memory access (RDMA), a serial advanced technology attachment (SATA), a Fibre Channel, a serial attached SCSI (SAS), NVMe over Fabrics (NVMe-oF), etc. In other embodiments, the host interface 106 (e.g., a connector and its protocol) can include (or can conform to) various general-purpose interfaces, such as, for example, Ethernet, universal serial bus (USB), etc.

[0048] In some embodiments, the storage device 104 can include a storage controller 112, a storage memory 114 (which can also be referred to as a buffer), a non-volatile memory (NVM) 116, and a storage interface 118. The storage memory 114 can be a high performance memory of the storage device 104 and can include (or can be) a volatile memory such as, for example, DRAM, although the present disclosure is not so limited, and the storage memory 114 can be any suitable kind of high performance volatile or non-volatile memory. The non-volatile memory 116 can persistently store data received, for example, from the host device 102. The non-volatile memory 116 can include, for example, NAND flash memory, although the present disclosure is not so limited, and the non-volatile memory 116 can include any suitable kind of memory (e.g., disk, tape, optical disk, etc.) for persistently storing data depending on the implementation of the storage device 104.

[0049] The storage controller 112 can be connected to the non-volatile memory 116 through the storage interface 118. In the context of an SSD, the storage interface 118 can be referred to as a flash channel, and can be an interface through which the non-volatile memory 116 (e.g., NAND flash memory) can communicate with a processing component (e.g., the storage controller 112) or other devices. Commands such as reset, write enable, control signals, clock signals, etc. can be sent through the storage interface 118. Further, a software interface can be used in conjunction with hardware elements that can be used to test or verify the operation of the storage interface 118. Software can be used to read data from and write data to the non-volatile memory 116 via the storage interface 118. Further, the software can include firmware that can be downloaded onto the hardware elements (e.g., for controlling write, erase, and read operations).

[0050] The storage controller 112, which can be processing circuitry (discussed in further detail below), can be connected to the host interface 106 and can manage signaling on the host interface 106. In some embodiments, the storage controller 112 can include an associated software layer (e.g., a host interface layer) to manage the physical connectors of the host interface 106. The storage controller 112 can respond to input or output requests received from the host device 102 over the host interface 106. The storage controller 112 can also manage the storage interface 118 to control the non-volatile memory 116 and provide access to and from the non-volatile memory 116. For example, the storage controller 112 can include at least one processing component embedded therein for interfacing with the host device 102 and the non-volatile memory 116. The processing component can include, for example, a general purpose digital circuit (e.g., a microcontroller, microprocessor, digital signal processor, or logic device (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.)) that is capable of executing data access instructions (e.g., via firmware or software) to provide access to data stored in the non-volatile memory 116 in accordance with the data access instructions. For example, the data access instructions can correspond to data request commands and can include any suitable data storage and retrieval algorithm (e.g., read, write, or erase) instructions, etc.

[0051] Figure 1B is a system level diagram in some embodiments. Within each target 100, the host device 102 is connected to a persistent storage device 104 (which can be, for example, a solid state drive (SSD)). The persistent storage device 104 can have a form factor (as discussed above) that is any one of a number of form factors suitable for the persistent storage device, including but not limited to 2.5", 1.8", MO-297, MO-300, M.2, and enterprise and data center SSD form factor (EDSFF), and it can have an electrical interface (which can be referred to as a "host interface") through which it can be connected to the host device 102, i.e., any one of a number of interfaces suitable for the persistent storage device, including peripheral component interconnect (PCI), PCI express (PCIe), Ethernet, small computer system interface (SCSI), serial AT attachment (SATA), and serial attached SCSI (SAS), or universal flash storage (UFS). The persistent storage device 104 can include interface circuitry that operates as an interface adapter between the host interface 106 and one or more internal interfaces in the persistent storage device 104.

[0052] The host interface can be used by the host device 102 to communicate with the persistent storage device 104, e.g., by sending write and read commands, which can be received by the persistent storage device 104 over the host interface. The host interface can also be used by the persistent storage device 104 to perform data transfers to and from the system memory of the host device 102.

[0053] Such data transfers can be performed using direct memory access (DMA). For example, when the host device 102 sends a write command to the persistent storage device 104, the persistent storage device 104 can use direct memory access to fetch data from the host memory 110 of the host device 102 to be written to the non-volatile memory 116, and the persistent storage device 104 can then save the fetched data to the non-volatile memory 116. Similarly, if the host device 102 sends a read command to the persistent storage device 104, the persistent storage device 104 can read the requested data (i.e., the data specified in the read command) from the non-volatile memory 116 and save it in the host memory 110 of the host device 102 using direct memory access. The persistent storage device 104 can store data in persistent storage, e.g., in a memory die containing memory cells, each of which can be, e.g., a Single-Level Cell (SLC), a Multi-Level Cell (MLC), or a Triple-Level Cell (TLC), in a NAND flash memory.

[0054] A flash translation layer (FTL) of the persistent storage device 104 (discussed in further detail below) can provide a mapping between logical addresses used by the host device 102 and physical addresses of data in the persistent storage. The persistent storage device 104 can also include (i) a buffer, which can include (e.g., consist of) a dynamic random access memory (DRAM), and (ii) a persistent storage controller (e.g., a flash controller) to provide appropriate signals to the persistent storage. Some or all of the host interface, the flash translation layer, the buffer, and the persistent storage controller can be implemented in processing circuitry, which can be referred to as a persistent storage device controller.

[0055] Figure 1Cis a block diagram of a persistent storage device 104 (e.g., a solid state drive) in some embodiments. A host interface 106 is used by the host device 102 to communicate with the persistent storage device 104. Data write and read input / output commands, as well as various media management commands such as a Non-Volatile Memory Express (NVMe) Identify command and an NVMe Get Log command, can be received by the persistent storage device 104 over the host interface 106. In some embodiments, the storage device has an interface compatible with different interface protocols such as Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Ethernet Remote Direct Memory Access (RDMA), Serial Advanced Technology Attachment (SATA), Fibre Channel, Serial Attached SCSI (SAS), NVMe over Fabrics (NVMe-oF), etc. In such embodiments, a command similar, identical, or analogous to an Identify command or a Get Log command can be received by the persistent storage device 104 over the host interface 106. The host interface 106 can also be used by the persistent storage device 104 to perform data transfers to and from the host system memory. The persistent storage device 104 can store data in non-volatile memory 116 (e.g., a non-volatile and (NAND) flash memory), e.g., in memory dies 117 containing memory cells, each of which can be, for example, a single-level cell (SLC), a multi-level cell (MLC), or a triple-level cell (TLC) as described above. A flash translation layer (FTL) (e.g., based on firmware stored in the non-volatile memory 116) that can be implemented in the storage controller 112 can provide a mapping between logical addresses used by the host and physical addresses of data in the non-volatile memory 116. The persistent storage device 104 can also include (i) a buffer (e.g., a storage memory 114) that can include (e.g., consist of) a dynamic random access memory (DRAM), and (ii) a flash interface (or “flash controller”) 125 to provide appropriate signals to the memory dies 117 of the non-volatile memory 116. Some or all of the host interface 106, the flash translation layer (as described above), the storage memory 114 (e.g., the buffer), and the flash interface 125 can be implemented in processing circuitry, which can be referred to as a persistent storage device controller 112 (or simply a storage controller 112).

[0056] NAND flash memory can be read or written at the granularity of a flash page, which can be between 8KB and 16KB. Before reprogramming a flash memory page with new data, the flash memory page can first be erased. The granularity of an erase operation can be one NAND block or “physical block,” which can include, for example, 128 to 256 pages. Because the granularity of erase and program operations is different, garbage collection (GC) can be used to free partially invalid physical blocks and make room for new data. A garbage collection operation can (i) identify fragmented flash blocks, where a majority (e.g., a large majority) of the pages are invalid, and (ii) erase each such physical block. When garbage collection is complete, the pages in the erased physical block can be recycled and added to a free list in the flash translation layer.

[0057] Non-volatile memory 116 (e.g., if it includes or is flash memory) can be able to be programmed and erased only a limited number of times. This can be referred to as the maximum number of program / erase cycles (P / E cycles) that non-volatile memory 116 can sustain. To maximize the lifetime of persistent storage device 104, persistent storage device controller 112 can strive to distribute write operations across all physical blocks of non-volatile memory 116; this process can be referred to as wear leveling.

[0058] Mechanisms that can be referred to as “read disturb” can degrade the reliability of persistent storage device 104. A read operation on a NAND flash cell can cause the threshold voltage of nearby, un-read flash cells in the same physical block to change. Such disturbance can change the logical state of the un-read cells, and can cause uncorrectable error correction code (ECC) read errors, degrading flash endurance. To avoid this result, the flash translation layer can have a counter of the total number of reads to a physical block since the last erase operation. When the counter exceeds a threshold (e.g., 50,000 reads for a multi-level cell), the contents of the physical block can be copied to a new physical block, and the physical block can be recycled to avoid unrecoverable read disturb errors. As an alternative, in some embodiments, test reads can be periodically performed within a physical block to check error correction code error rates; if the error rate approaches the error correction code capability, the data can be copied to a new physical block.

[0059] As described above, in some embodiments, the block allocator includes an allocation request method that can be called by an application to request a memory allocation (e.g., an allocation of non-volatile memory in a solid state drive (SSD), e.g., in an NVMe SSD). An application can make a memory allocation request (or “allocation request”) by calling the allocation request method, and the allocation request can include (i) a number of blocks of memory (i.e., a size of the requested allocation, in blocks of memory) and (ii) an address (which can be a “hint,” i.e., an address or vicinity thereof that the application requests to be allocated). In some embodiments, the storage device has an interface compatible with an interface protocol other than NVMe, such as small computer system interface (SCSI), peripheral component interconnect express (PCIe), compute express link (CXL), Ethernet remote direct memory access (RDMA), serial advanced technology attachment (SATA), Fibre Channel, serial attached SCSI (SAS), NVMe over Fabrics (NVMe-oF), etc. In such embodiments, a similar, identical, or analogous request to an NVMe allocation request can be made.

[0060] In performing the allocation request method, the block allocator can use two data structures. Figure 2A is a diagram of free and allocated memory in an example illustrating data structures used by the block allocator. Figure 2B A first data structure is shown for storing free ranges, where the free ranges are listed in order of address (e.g., logical block address (LBA)). Figure 2C A second data structure is shown for storing free ranges, where the free ranges are listed in order of size. For each size (e.g., 100 blocks, 200 blocks, or 2896 blocks), the second data structure contains a data structure storing a list of addresses (e.g., logical block addresses) at which a range of addresses of the given size is available. In some embodiments, each of the data structures (e.g., each of the first data structure, the second data structure, and the data structures at the nodes of the second data structure) is a data structure that can be searched in O(log n) time, e.g., a tree such as a radix tree. In some embodiments, one or more of the data structures is a different structure, e.g., a balanced binary search tree, or an unbalanced binary search tree, or a hash table.

[0061] Figure 3Ais a flowchart of an allocate request method in some embodiments. When the block allocator receives an allocation request at step 302 (e.g., when the allocate request method is invoked by an application), the block allocator can (i) search for the requested allocation address in a first data structure (e.g., a first radix tree) at step 304, and (ii) if the block allocator finds a node containing an available address range of sufficient size at the requested allocation address, the block allocator can allocate the available address range to the application and perform a split operation at step 306 (discussed in further detail below). If the block allocator does not find a node of sufficient size, the block allocator can repeat the search for the next node (e.g., in ascending order of address) in the first data structure until at step 308 (i) the block allocator finds an available address range of sufficient size or (ii) the difference between the address and the requested allocation address exceeds a first threshold.

[0062] The block allocator can also repeat the search for the previous node (e.g., in descending order of address) in the first data structure (before or after repeating the search for the next node) until (i) the block allocator finds an available address range of sufficient size or (ii) the difference between the requested allocation address and the address exceeds the first threshold. If the block allocator finds an available address range of sufficient size during any of the searches, the set of searches can terminate and the block allocator can allocate the available address range to the application and perform the split operation at step 306. If the block allocator does not find an available address range of sufficient size in (i) the search for one or more next nodes or (ii) the search for one or more previous nodes, it proceeds to a search of a second data structure at 310.

[0063] The search of the second data structure can include searching for the length specified in the allocation request at step 312 and, if the length specified in the allocation request is not found, searching for the next node at step 314. If the block allocator finds a free address range as a result of searching for the length specified in the allocation request at step 312 or searching for the next node at step 314, the block allocator can allocate the available address range to the application and perform the split operation at step 316.

[0064] The threshold can be selected to be equal to (i) the input-output size limit minus the number of blocks of memory requested by the application in the allocation request, or (ii) in embodiments in which the allocation request method takes an additional argument (discussed in further detail below), the input-output size limit minus the number of blocks of memory requested by the application in the allocation request, and minus half the size of the previous allocation made at the requested allocation address. For example, if the input-output size limit is "A", the number of blocks of memory requested by the application in the allocation request is "B", and the size of the previous allocation made at the requested allocation address is "C", and then the threshold can be selected to be equal to (i) "A-B" or (ii) "A-B-1 / 2C".

[0065] Figure 3B is a flowchart of the deallocation method, which can be called by the application when the previously allocated memory is no longer needed, where the first argument specifies the address (e.g., logical block address) and the second argument specifies the length. The method includes determining whether the request is valid (e.g., whether the address range specified by the address and length is actually allocated) at step 320; if the request is valid, the block allocator performs a merge operation (discussed in further detail below) at step 322 and returns a flag indicating success (e.g., "true"), and if the request is not valid, the block allocator returns a flag indicating failure (e.g., "false").

[0066] Figure 3C is a flowchart of the split operation, which can be an operation for updating the data structure when a new allocation is made, e.g., removing the allocated address range from the data structure at step 330. This can be performed as follows. At steps 332 and 334, it can be determined whether the allocated address range is left-justified or right-justified (with the free address range where the allocation is made), respectively. If it is left-justified or right-justified, then at steps 336 or 338, respectively, a new free address range is created (comprised of the remaining unallocated portion of the free address range where the allocation is made), and, if the allocation is neither left-justified nor right-justified, but rather splits the free address range where the allocation is made into two portions, then at step 340, new free address ranges corresponding to the two portions are added to the data structure. At step 342, the free address range where the allocation is made is removed from the data structure.

[0067] Figure 3Dis a flowchart of a merge operation, which can be an operation for updating the data structure when deallocations are made. The operation includes determining, at step 350, whether the previous address range or the next address range is empty, and if so, determining, at step 352, whether the deallocated address range can be merged (e.g., abutted) with the empty previous address range or the next address range. If so, removing, at step 354, the deallocated address range, and creating, at step 356, a new address range that consists of the deallocated address range and the adjacent address range.

[0068] If, at step 350, it is determined that the previous address range or the next address range is not empty, then determining, at step 358, whether the deallocated address range can be merged (e.g., abutted) with the free address ranges on both sides. If so, removing, at step 360, the free address ranges on both sides of the deallocated address range from the data structure, and creating, at step 362, a new address range that consists of the deallocated address range and the adjacent address ranges. If, at step 358, it is determined that the deallocated address range cannot be merged with the free address ranges on both sides, then creating, at step 364, a new address range that includes the deallocated address range. The new free address range is then stored in the data structure, at step 366.

[0069] In some embodiments, as noted above, the allocation request method can take more than two arguments, for example, it can be invoked with:

[0070] Allocate(hint_pref_1, hint_pref_2, num_blocks)

[0071] where hint pref 1 is the allocation address of the first request (first hint), hint pref 2 is the allocation address of the second request (second hint), and num blocks is the number of blocks of memory requested. All hints can be subject to priority. While the block allocator can attempt to allocate close to hint pref 1, it can use hint pref 2 in the allocation policy to reinforce the maximum effort of the input-output size limit. In some embodiments, the allocation request method can take additional hints (e.g., hint pref 1, hint pref 2, hint pref 3, etc.) ordered according to priority as arguments, and the block allocator can use these hints to allocate in priority order. In some embodiments, the allocation request method takes as arguments a list comprising an ordered set of pairs, each pair specifying an allocation already made (e.g., as {start LBA, end LBA} or as {start LBA, length}), and the allocation already made and the new requested allocation together are a set of allocations, which set of allocations (i) can be accessed as a group (as for keys and for each of their values), and (ii) should thus be stored, if possible, within an address range that is no larger than the input-output size limit.

[0072] Some embodiments include a software framework for block allocators that allows flexibility for modifying the underlying allocator type. Some embodiments use a bitmap allocator, where all logical blocks on a drive are represented as bits in a bitmap. The software framework can allow modification or interspersing of different types of allocators. As an example, for a 1 terabyte (TB) drive, the first 500 gigabytes (GB) can be represented as a bitmap-based allocator, and the next 500 GB can be managed by a doubly-linked list type allocator.

[0073] In some embodiments, the block allocator has a documented application programming interface (API) and is designed as a pluggable module that can be integrated with any application.

[0074] Some embodiments include a low disk input-output (IO) sensitive allocation policy. Upon an allocation request for "n" chunks and hint address, the chunk allocator can attempt to find "n" contiguous free chunks from the hint address on either side within the input-output size limit (or optimal IO boundary). This can result in only a single disk IO (and no transaction) being required. Upon failure of this policy, a fallback option can be to find "n" contiguous free chunks from anywhere in memory, where the number of free chunks is closest to and at least as large as the requested length ("n"). This approach can reduce fragmentation. From the chunk allocator's perspective, this approach can also only require a single disk IO, but, since it can not be able to get chunks within the input-output size limit of the hint LBA, the application can need to use a transaction to persist its metadata.

[0075] If "n" contiguous chunks are not available, the chunk allocator can split the length in the best way possible to build a minimum length scatter-gather list from the hint address within the same write granularity (if possible). If the length of the scatter-gather list exceeds a threshold, the chunk allocator can treat the IO as a failure and, if the drive is not too full, start garbage collection to defragment.

[0076] Some embodiments include scatter-gather and fragmentation management. The chunk allocator can utilize different configurable policies to address fragmentation issues. The chunk allocator can scatter a data request into multiple smaller chunks of equal length and honor the request only if each smaller data chunk can be allocated contiguously. The data can be scattered or split into smaller data chunks of equal size until a configurable threshold is reached; the request can be treated as a failure upon unsuccessful allocation of all split data chunks. If fragmentation is heavy, a background garbage collection module can re-shuffle the data based on a configurable threshold. Another approach is to allow the application to manage fragmentation outside of the chunk allocator and use the chunk allocator to allocate contiguous memory. This approach can facilitate chunk allocator expansion across different drives.

[0077] Some embodiments include persistence support for the chunk allocator. The chunk allocator can use an IO ordering policy based on disjoint memory ranges to allow parallel persistence to drives (e.g., to non-volatile storage). Each IO request can also persist chunk allocator metadata on the drive upon completion.

[0078] Some embodiments include multi-threading support for the chunk allocator. The "Allocate" and "Free" operations supported by the chunk allocator can not be thread-safe. The design of such cases mitigates the need for the design to build central processing unit (CPU) intensive synchronization primitives, improving performance. The application can be responsible for managing its concurrency and synchronization strategy. However, the application can have concurrent "read" or "write" operations after verifying that the race regions are disjoint. The chunk allocator can expose a "state" API to verify whether a region is being modified.

[0079] In some embodiments, power savings can be achieved on an SSD by using a chunk allocator as described herein.

[0080] Figure 4 A method for allocating is shown in some embodiments. Although Figure 4 Various operations in the method for allocating are shown, but embodiments according to the present disclosure are not limited thereto. For example, the method for allocating can include additional operations or fewer operations, or the order of the operations can be varied, according to some embodiments without departing from the spirit and scope of embodiments according to the present disclosure (unless otherwise explicitly or implicitly indicated).

[0081] Figure 4 The method of includes receiving a memory allocation request from an application at step 400, the memory allocation request including a number of chunks of memory and a first address. For example, as discussed above in the context of Figure 3A The application can call the allocate request method of the chunk allocator, passing the requested allocation address and the requested length as arguments, as discussed above in the context of

[0082] The method further includes determining that the memory at the first address is allocated at step 405. For example, as discussed above in the context of Figure 3A The chunk allocator can perform a search of the first data structure using the requested allocation address as an index of the search, and determine that there is no entry for the index in the first data structure, as discussed above in the context of

[0083] The method further includes identifying a second address that differs from the first address by less than a first threshold at step 410. As one example, if the second address is "D" and the first address is "E", the difference between the first address and the second address (i.e., "D-E") can be less than the first threshold. For example, as discussed above in the context of Figure 3AIn the context of the discussion above, the block allocator can perform one or more searches in the first data structure for a next node or for a previous node and determine that there is a node corresponding to a free address range having a size at least as large as the requested length, where the index of the node is an address that differs from the requested allocation address by less than the first threshold.

[0084] The method also includes, at step 415, allocating the number of blocks of memory at the second address. For example, as discussed above in the context of the discussion above, having found a node in the first data structure that has both (i) an address that is within the first threshold of the requested allocation address and (ii) a size that is at least equal to the requested length, the block allocator can allocate to the application memory spanning the address range, the memory having a size equal to the requested length and beginning at an address equal to the requested allocation address. Figure 3A

[0085] In some embodiments: the memory is non-volatile memory in a storage device, and the method further includes, at step 420, calculating the first threshold based on the first address and an input-output size limit. For example, the first threshold can be calculated by subtracting the requested length from the input-output size limit. In some embodiments: the memory is non-volatile memory in a storage device, and the method further includes calculating the first threshold based on the first address and an optimal input output (IO) boundary of the storage device. In some embodiments, determining that the memory at the first address is allocated includes searching an entry indexed by the first address in a data structure. In some embodiments, determining that the memory at the first address is allocated includes searching an entry indexed by the first address in a radix tree.

[0086] In some embodiments: the memory allocation request further includes a second address; and the memory is non-volatile memory in a storage device, and the method further includes calculating the first threshold based on the first address, the second address, and an optimal input output (IO) boundary. In some embodiments, determining that the memory at the first address is allocated includes searching an entry indexed by the first address in a first data structure; and the identification of the second address includes searching an entry indexed by the number of blocks of memory in a second data structure. In some embodiments, determining that the memory at the first address is allocated includes searching an entry indexed by the first address in a first data structure; the identification of the second address includes searching an entry indexed by the number of blocks of memory in a second data structure; and the second data structure stores one or more addresses of free regions of memory at indexed nodes.

[0087] ​Although some examples described herein relate to non-volatile memory express solid state drives, the present disclosure is not limited to such embodiments. The systems and methods described herein can be used with any storage interface, including small computer system interface (SCSI), peripheral component interconnect express (PCIe), compute express link (CXL), Ethernet remote direct memory access (RDMA), serial advanced technology attachment (SATA), Fibre Channel, serial attached SCSI (SAS), NVMe over Fabrics (NVMe-oF), etc. Moreover, the systems and methods described herein can be used with storage interfaces that can be developed and documented in the future. In some embodiments, the storage interface includes an input-output size limit or similar aspect that relies on input-output performance of data distribution.

[0088] As used herein, a “portion” of something means “at least some” of the thing, and thus can mean all of the thing or less than all of the thing. As such, a “portion” of something includes, as a special case, the entirety of the thing, i.e., the entirety of the thing is an example of a portion of the thing. As used herein, when a second quantity is “within Y of’ a first quantity X, it means that the second quantity is at least X-Y and the second quantity is at most X+Y. As used herein, when a second quantity is “within Y% of’ a first quantity, it means that the second quantity is at least (1-Y / 100) times the first quantity and the second quantity is at most (1+Y / 100) times the first quantity. As used herein, the term “or” should be interpreted as “and / or,” such that, for example, “A or B” means either “A” or “B” or “A and B.”

[0089] The background provided in the Background section of this disclosure is included solely for setting context and does not constitute admission that the background is prior art. Any component or combination of components described (e.g., in any system diagram included herein) can be used to perform one or more operations of any flow diagram included herein. Moreover, (i) the operations are example operations and can involve various additional steps not clearly mentioned, and (ii) the time order of the operations can vary.

[0090] Each of the terms “processing circuit” and “means for processing” is used herein to mean any combination of hardware, firmware, and software for processing data or digital signals. Processing circuit hardware can include, for example, an application specific integrated circuit (ASIC), a general purpose or special purpose central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), and a programmable logic device such as a field programmable gate array (FPGA). In processing circuit, as used herein, each function is performed by hardware (i.e., hardwired) configured to perform that function or by more general purpose hardware (such as a CPU) configured to execute instructions stored in a non-transitory storage medium. Processing circuit can be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. Processing circuit can contain other processing circuits; for example, processing circuit can include two processing circuits, an FPGA and a CPU, interconnected on a PCB.

[0091] As used herein, when a method (e.g., adjusting) or a first quantity (e.g., a first variable) is referred to as being “based on” a second quantity (e.g., a second variable), this means that the second quantity is an input to the method or influences the first quantity, e.g., the second quantity can be an input (e.g., the only input or one of several inputs) to a function that computes the first quantity, or the first quantity can equal the second quantity, or the first quantity can be identical to the second quantity (e.g., stored at the same location or locations in a memory).

[0092] It should be understood that although the terms “first,” “second,” “third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, elements, components, regions, layers or sections discussed herein as first elements, components, regions, layers or sections can be called second elements, components, regions, layers or sections without departing from the spirit and scope of the inventive concept.

[0093] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximation terms not to be limited to the exact matches described, but to allow a reasonable range of error for the measure or calculation values as would be recognized by those of ordinary skill in the art.

[0094] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding the list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, use of “can” in describing embodiments of the inventive concept means “one or more embodiments of the disclosure.” Also, the term “exemplary” is intended to mean an example or an illustration. As used herein, the terms “use,” “using,” and “used” can be taken in their broadest possible context as synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0095] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.

[0096] Any numerical range recited herein is intended to include all sub-ranges of the same entire number of increments within that range. For example, "1 to 10" or "between 1 and 10" is intended to include, for example, 2.4 to 7.6 or 5.5 to 9.9. Similarly, "at most 10" or "at least 10" is intended to include all individual numbers within the same entire number of increments, for example, 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

[0097] Some embodiments can include features of the numbered statements below.

[0098] Statement 1. A method comprising: receiving a memory allocation request from an application, the memory allocation request comprising: a number of blocks of memory and a first address; determining that memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

[0099] Statement 2. The method of statement 1, wherein: the memory is non-volatile memory in a storage device, and the method further comprises computing the first threshold based on the first address and an input-output size limit of the storage device.

[0100] Statement 3. The method of statement 1 or statement 2, wherein: the memory is non-volatile memory in a storage device compatible with an interface protocol, the interface protocol provides for reporting of an input-output size limit of the storage device, and the method further comprises computing the first threshold based on the first address and the input-output size limit.

[0101] Statement 4. The method of any of the preceding statements, wherein determining that memory at the first address is allocated comprises searching for an entry indexed by the first address in a data structure.

[0102] Statement 5. The method of any of the preceding statements, wherein determining that memory at the first address is allocated comprises searching for an entry indexed by the first address in a data structure configured to be searched in logarithmic time.

[0103] Statement 6. The method of any of the preceding Statements, wherein: the memory allocation request further comprises a second address; and the memory is non-volatile memory in a storage device, and the method further comprises computing the first threshold based on: the first address, the second address, and an input-output size limit of the storage device.

[0104] Statement 7. The method of any of the preceding Statements, wherein: determining that the memory at the first address is allocated comprises searching a first data structure for an entry indexed by the first address; and the identification of the second address comprises searching a second data structure for an entry indexed by the number of blocks of memory.

[0105] Statement 8. The method of any of the preceding Statements, wherein: determining that the memory at the first address is allocated comprises searching a first data structure for an entry indexed by the first address; the identification of the second address comprises searching a second data structure for an entry indexed by the number of blocks of memory; and the second data structure stores one or more addresses of free regions of memory at nodes of the index.

[0106] Statement 9. A system comprising: processing circuitry; and a memory operatively connected to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the system to perform a method comprising: receiving a memory allocation request from an application, the memory allocation request comprising: a number of blocks of memory and a first address; determining that the memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

[0107] Statement 10. The system of Statement 9, wherein: the memory is non-volatile memory in a storage device, and the method further comprises computing the first threshold based on the first address and an input-output size limit of the storage device.

[0108] Statement 11. The system of Statement 9 or Statement 10, wherein: the memory is non-volatile memory in a storage device that is compatible with an interface protocol, the interface protocol providing for reporting of an input-output size limit of the storage device, and the method further comprises computing the first threshold based on the first address and the input-output size limit.

[0109] Statement 12. The system of any of Statements 9 to 11, wherein determining that the memory at the first address is allocated comprises searching a data structure for an entry indexed by the first address.

[0110] Statement 13. The system of any of Statements 9 to 12, wherein determining that the memory at the first address is allocated comprises searching a data structure for an entry indexed by the first address, the data structure being configured to be searched in logarithmic time.

[0111] Statement 14. The system of any of statements 9 to 13, wherein: the memory allocation request further comprises a second address; and the memory is non-volatile memory in a storage device, and the method further comprises computing the first threshold based on: the first address, the second address, and an input-output size limit of the storage device.

[0112] Statement 15. The system of any of statements 9 to 14, wherein: determining that the memory at the first address is allocated comprises searching an entry indexed by the first address in a first data structure; and the identification of the second address comprises searching an entry indexed by the number of blocks of memory in a second data structure.

[0113] Statement 16. The system of any of statements 9 to 15, wherein: determining that the memory at the first address is allocated comprises searching an entry indexed by the first address in a first data structure; the identification of the second address comprises searching an entry indexed by the number of blocks of memory in a second data structure; and the second data structure stores one or more addresses of free regions of memory at indexed nodes.

[0114] Statement 17. A system comprising: a computer-readable medium storing instructions that, when executed by one or more processing circuits, cause the one or more processing circuits to: execute an application, the application configured to call an allocation request method of a block allocator, the allocation request method taking as arguments: a number of blocks of memory and a first address; the computer-readable medium further storing instructions that, when executed by the one or more processing circuits, cause the one or more processing circuits to execute the allocation request method, execution of the allocation request method comprising: determining that the memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

[0115] Statement 18. The system of statement 17, wherein: the memory is non-volatile memory in a storage device, and the method further comprises computing the first threshold based on the first address and an input-output size limit of the storage device.

[0116] Statement 19. The system of statement 17 or statement 18, wherein: the memory is non-volatile memory in a storage device compatible with an interface protocol, the interface protocol providing for reporting of an input-output size limit of the storage device, and the method further comprises computing the first threshold based on the first address and the input-output size limit.

[0117] Statement 20. The system of any of statements 17 to 19, wherein determining that the memory at the first address is allocated comprises searching an entry indexed by the first address in a data structure.

[0118] While example embodiments of the block dispenser have been specifically described and illustrated herein, numerous modifications and variations are possible, as will be clear to those skilled in the art. Accordingly, it is to be understood that block dispensers constructed in accordance with the principles of the present disclosure can be implemented in a different manner than specifically described herein. The present invention is also defined in the following claims, and their equivalents.

Claims

1. A method of memory allocation of a memory of a storage device, comprising: receiving a memory allocation request from an application, the memory allocation request comprising: a number of blocks of memory, and a first address; determining that memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

2. The method of claim 1, wherein: the memory is non-volatile memory in the storage device, and the method further comprises calculating the first threshold based on the first address and an input-output size limit of the storage device.

3. The method of claim 1, wherein: the memory is non-volatile memory in the storage device that is compatible with an interface protocol, the interface protocol provides for reporting of an input-output size limit of the storage device, and the method further comprises calculating the first threshold based on the first address and the input-output size limit.

4. The method of claim 1, wherein, the determining that memory at the first address is allocated comprises searching an entry indexed by the first address in a data structure.

5. The method of claim 1, wherein, the determining that memory at the first address is allocated comprises searching an entry indexed by the first address in a data structure, the data structure configured to be searched in logarithmic time.

6. The method of claim 1, wherein: the memory allocation request further comprises a second address; and the memory is non-volatile memory in the storage device, and the method further comprises calculating the first threshold based on: the first address, the second address, and an input-output size limit of the storage device.

7. The method of claim 1, wherein: the determining that memory at the first address is allocated comprises searching an entry indexed by the first address in a first data structure; and the identifying of the second address comprises searching an entry indexed by the number of blocks of memory in a second data structure.

8. The method of claim 1, wherein: the determining that memory at the first address is allocated comprises searching an entry indexed by the first address in a first data structure; the identifying of the second address comprises searching an entry indexed by the number of blocks of memory in a second data structure; and the second data structure stores one or more addresses of free regions of memory at indexed nodes.

9. A system, comprising: processing circuitry; and memory operably connected to the processing circuitry and storing instructions that, when executed by the processing circuitry, cause the system to perform a memory allocation method, the method comprising: receiving a memory allocation request from an application, the memory allocation request comprising: a number of blocks of memory, and a first address; determining that memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

10. The system of claim 9, wherein: ​ The memory is non-volatile memory in a storage device, and The method further includes computing the first threshold based on the first address and an input-output size limit of the storage device.

11. The system of claim 9, wherein: The memory is non-volatile memory in a storage device compatible with an interface protocol, The interface protocol provides reporting of an input-output size limit of the storage device, and The method further includes computing the first threshold based on the first address and the input-output size limit.

12. The system of claim 9, wherein, The determining that memory at the first address is allocated includes searching a data structure for an entry indexed by the first address.

13. The system of claim 9, wherein, The determining that memory at the first address is allocated includes searching a data structure for an entry indexed by the first address, the data structure configured to be searched in logarithmic time.

14. The system of claim 9, wherein: The memory allocation request further includes a second address; and The memory is non-volatile memory in a storage device, and The method further includes computing the first threshold based on: The first address, The second address, and An input-output size limit of the storage device.

15. The system of claim 9, wherein: The determining that memory at the first address is allocated includes searching a first data structure for an entry indexed by the first address; and The identifying of the second address includes searching a second data structure for an entry indexed by the number of blocks of memory.

16. The system of claim 9, wherein: The determining that memory at the first address is allocated includes searching a first data structure for an entry indexed by the first address; The identifying of the second address includes searching a second data structure for an entry indexed by the number of blocks of memory; and The second data structure stores one or more addresses of free regions of memory at indexed nodes.

17. A system comprising: a computer-readable medium storing first instructions that, when executed by one or more processing circuits, cause the one or more processing circuits to: execute an application configured to call an allocation request method of a block allocator, the allocation request method taking as arguments: a number of blocks of memory, and a first address; the computer-readable medium further storing second instructions that, when executed by the one or more processing circuits, cause the one or more processing circuits to execute the allocation request method, the execution of the allocation request method including: determining that memory at the first address is allocated; identifying a second address that differs from the first address by less than a first threshold; and allocating the number of blocks of memory at the second address.

18. The system of claim 17, wherein: The memory is non-volatile memory in a storage device, and The execution of the allocation request method further includes computing the first threshold based on the first address and an input-output size limit of the storage device.

19. The system of claim 17, wherein: the memory is a non-volatile memory in a storage device compatible with an interface protocol, the interface protocol provides for reporting of an input-output size limit of the storage device, and the execution of the allocation request method further comprises calculating the first threshold based on the first address and the input-output size limit.

20. The system of claim 17, wherein, the determining that the memory at the first address is allocated comprises searching a data structure for an entry indexed by the first address.

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