A cache allocation method, device and medium for a shared cache system
By introducing a mode switching detector and a state update mechanism into the shared cache system, the allocation of cache resources is dynamically adjusted, which solves the problem of uneven resource allocation in the existing technology, realizes load balancing and efficient resource utilization, and improves system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN TECH UNIV
- Filing Date
- 2025-06-17
- Publication Date
- 2026-05-15
AI Technical Summary
Existing shared caching systems lack the ability to dynamically assess and adjust the overall system load in dynamic cache management, leading to uneven resource allocation, affecting system performance and resource utilization. In particular, under high load conditions, there is a tendency for insufficient or excessive cache resources.
By combining a mode switching judge and a mode selection module with logical shifting and state update mechanisms, the cache resource allocation strategy is dynamically adjusted. The mode switching judge determines the target mode based on the saturation state value of the SRAM block and the total number of ports, selects an appropriate SRAM block for allocation, and updates the used space and saturation state value through an adder and a saturation comparator to achieve load balancing and efficient resource allocation.
It improves resource utilization, avoids local congestion, reduces cache resource allocation latency, enhances the adaptability and efficiency of resource allocation, and ensures stable system operation under different load conditions.
Smart Images
Figure CN120849313B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of cache allocation technology, and in particular to a cache allocation method, device and medium for a shared cache system. Background Technology
[0002] In modern high-speed data communication systems, especially network switches and routers, it is necessary to process large amounts of data in a very short time while ensuring low latency and high throughput. To effectively address these challenges, a shared cache architecture is typically used to manage high-speed SRAM (Static Random Access Memory) storage resources. The core idea of a shared cache architecture is to centrally manage limited SRAM storage resources by dynamically allocating and reclaiming cache space to adapt to the needs of different ports and data streams. This architecture can significantly improve resource utilization and avoid data packet loss and performance degradation caused by insufficient storage resources.
[0003] However, current dynamic cache management methods have significant shortcomings. When allocating cache resources to request ports, the allocation strategy is relatively simplistic, lacking the ability to dynamically assess and adjust the overall system load. This simplistic strategy can easily lead to insufficient cache resources on some ports while other ports have excess resources when facing sudden traffic surges, impacting system performance and resource utilization. Furthermore, under high load conditions, resource allocation efficiency is low, easily leading to contention and conflicts, increasing cache allocation latency, and reducing system throughput. Therefore, developing a dynamic cache management mechanism to achieve load balancing and efficient resource allocation under high load conditions is of great significance for improving the overall performance of high-speed data communication systems. Summary of the Invention
[0004] The main objective of this application is to propose a cache allocation method, device, and medium for a shared cache system, aiming to reduce cache management latency and achieve efficient resource allocation.
[0005] To achieve the above objectives, a first aspect of this application proposes a cache allocation method for a shared cache system, the method comprising:
[0006] The mode switching determiner uses the saturation state value of each SRAM block to determine the target mode corresponding to each SRAM block.
[0007] Using the mode selection module, the target allocation signal corresponding to each SRAM block is determined according to the mode, and the SRAM block to be allocated is determined according to the target allocation signal corresponding to each SRAM block;
[0008] Using the adder, the source SRAM block before the logical shift is determined according to the preset logical shift step size and the preset logical shift direction;
[0009] Read the number of used spaces in the source SRAM block to obtain the number of used spaces in the previous cycle;
[0010] Based on the target allocation signal and the used space of the previous cycle, update the used space and saturation state value of the SRAM block to be allocated to obtain a new SRAM block to be allocated.
[0011] An index is generated for the new SRAM block to be allocated so that it can be assigned to the corresponding port.
[0012] The method provided in the first aspect can distribute the load across different cache resources, improve resource utilization, avoid local congestion, and concurrently allocate all available SRAM resources to all ports with valid requests when resources are scarce, thereby improving resource utilization, increasing the adaptability of resource allocation, reducing the latency of cache resource allocation, and improving resource allocation efficiency.
[0013] In one possible implementation, selecting a target mode for the plurality of SRAM blocks using the mode switching determiner includes:
[0014] Obtain the saturation state value of each of the SRAM blocks;
[0015] Obtain the total number of ports in the shared cache system;
[0016] Using the mode switching determiner, multiple SRAM blocks are sorted based on the saturation state values to obtain a saturation state sequence;
[0017] The values of the saturation state sequence are read, and the continuous saturation detection result is obtained by detecting whether there are multiple consecutive SRAM blocks with a value of 1 in the saturation state sequence. The number of available resources is obtained based on the number of SRAM blocks with a value of 0 in the saturation state sequence.
[0018] The target mode is determined using the mode switching determiner based on the continuous saturation detection results, the number of available resources, and the total number of ports.
[0019] In one possible implementation, determining the target mode using the mode switching determiner based on the continuous saturation detection result, the number of available resources, and the total number of ports includes:
[0020] When the number of available resources is greater than or equal to the total number of ports, and the continuous saturation detection result is that there are multiple consecutive saturation state sequences with a value of 1, then the mode switching judge selects the first mode as the target mode.
[0021] When the number of available resources is greater than or equal to the total number of ports, and the continuous saturation detection result is 1 (meaning there are no consecutive sequences of saturated states), the mode switching determiner selects the second mode as the target mode.
[0022] In one possible implementation, the shared cache system further includes a first mode comparator and a second mode priority encoder; the step of using the mode selection module to determine the allocation signal corresponding to each SRAM block according to the mode, and determining the SRAM block to be allocated according to the allocation signal corresponding to each SRAM block, includes:
[0023] When the target mode is the first mode, the first mode comparator is used to determine the first target SRAM block based on the used space value of each SRAM block, and a first mode allocation signal is sent to the first target SRAM block.
[0024] When the target mode is the second mode, the second mode priority encoder is used to determine the second target SRAM block based on the saturation state value of each SRAM block, and a second mode allocation signal is sent to the second target SRAM block.
[0025] The mode selection module determines the target allocation signal from the first mode allocation signal and the second mode allocation signal;
[0026] The SRAM block with a target allocation signal value of 1 is identified as the SRAM block to be allocated.
[0027] In one possible implementation, selecting a first target SRAM block based on the used space value using the first mode comparator and sending a first mode allocation signal to the first target SRAM block includes:
[0028] Using the first mode comparator, when a write request is made to the port connected to the first mode comparator, the SRAM block with the smallest amount of used space is selected from multiple SRAM blocks corresponding to the first mode comparator to obtain the first target SRAM block, and a first mode allocation signal is sent to the first target SRAM block.
[0029] In one possible implementation, the step of using the second mode priority encoder to select a second target SRAM block based on the saturation state value and sending a second mode allocation signal to the second target SRAM block includes:
[0030] Using the second mode priority encoder, the index of the SRAM block with a saturation state value of 0 is found to obtain the index set;
[0031] Using the second mode priority encoder, find all ports for write requests to obtain the set of request port indices;
[0032] Based on the preset priority rules, the index set, and the request port index set, an available SRAM block is selected for each port of the write request to obtain a second target SRAM block, and a second mode allocation signal is sent to the second target SRAM block.
[0033] In one possible implementation, the shared cache system further includes a saturation comparator, wherein updating the used space and saturation state value of the SRAM block to be allocated based on the target allocation signal and the used space of the previous cycle to obtain a new SRAM block to be allocated includes:
[0034] Using the adder, a new used space is obtained based on the target allocation signal and the used space of the previous cycle;
[0035] Using the saturation comparator, a new saturation state value is obtained based on the new used space;
[0036] The used space and saturation state value of the SRAM block to be allocated are updated based on the new used space and the new saturation state value to obtain a new SRAM block to be allocated.
[0037] In one possible implementation, the shared cache system further includes a global bitmap management module, and before updating the used space and saturation state values of the SRAM block to be allocated based on the target allocation signal and the used space of the previous cycle to obtain a new SRAM block to be allocated, the system further includes:
[0038] Obtain the release signal from the global bitmap management module;
[0039] Read the value of the release signal. When the value of the release signal is 1, release the storage cell of the SRAM block to be allocated to obtain the released SRAM block.
[0040] The data in the storage cells of the released SRAM block is updated to the data in the storage cells of the source SRAM block.
[0041] In one possible implementation, using the adder to obtain new used space based on the target allocation signal and the used space of the previous cycle includes:
[0042] Using the adder, a new used space is determined based on the target allocation signal, the space used in the previous cycle, the release signal, a preset single allocation space amount, and a preset single release space amount.
[0043] In one possible implementation, obtaining a new saturation state value based on the new used space using the saturation comparator includes:
[0044] The saturation comparator is used to compare whether the new number of used spaces is equal to a preset storage capacity saturation threshold in order to determine the new saturation state value.
[0045] In a second aspect, an electronic device is provided, the electronic device including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement a cache allocation method for a shared cache system as described in any possible implementation of the first aspect.
[0046] Thirdly, a computer-readable storage medium is provided, the storage medium storing a computer program that, when executed by a processor, implements a cache allocation method for a shared cache system as described in any possible implementation of the first aspect. Attached Figure Description
[0047] To more clearly illustrate the technical solutions in one or more embodiments or prior art of this specification, the accompanying drawings used in the description of one or more embodiments or prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0048] Figure 1 This is a flowchart illustrating a cache allocation method for a shared cache system provided in an embodiment of this application.
[0049] Figure 2 This is a logical shift diagram of the cache allocation method for a shared cache system provided in the embodiments of this application;
[0050] Figure 3 This is a schematic block diagram of the mode switching detector provided in the embodiments of this application;
[0051] Figure 4 This is a schematic block diagram illustrating the selection of SRAM blocks to be allocated in the first mode provided in the embodiments of this application;
[0052] Figure 5 This is a schematic block diagram illustrating the selection of SRAM blocks to be allocated in the second mode provided in the embodiments of this application;
[0053] Figure 6 This is a structural block diagram of an electronic device according to an embodiment of this application. Detailed Implementation
[0054] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described one or more embodiments are merely some embodiments of this specification, and not all embodiments. All other embodiments obtained by those skilled in the art based on one or more embodiments of this specification without creative effort should fall within the protection scope of this document.
[0055] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0057] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The embodiments of the present invention will be further described below with reference to the accompanying drawings.
[0058] Figure 1 This is an optional flowchart of a cache allocation method for a shared cache system provided in an embodiment of this application. Figure 1 The method may include, but is not limited to, steps S100 to S700.
[0059] Firstly, such as Figure 1 As shown, to achieve the above objective, a cache allocation method for a shared cache system is provided, the method comprising:
[0060] S100. The mode switching detector determines the target mode corresponding to each SRAM block based on the saturation state value of each SRAM block.
[0061] It should be noted that in the cache allocation system, the mode switching determiner is a global combinational logic module used to determine which cache allocation mode to switch to based on the SRAM block saturation status value output by the SRAM logic unit's status register. This mechanism ensures that the system dynamically adjusts the cache resource allocation strategy according to the global resource scarcity under different workloads and performance requirements, including switching modes or requesting a halt, thereby improving resource utilization and system performance.
[0062] S200: Using the mode selection module, determine the target allocation signal corresponding to each SRAM block according to the mode, and determine the SRAM block to be allocated according to the target allocation signal corresponding to each SRAM block.
[0063] It should be noted that in the cache allocation system, the mode selection module is a combinational logic selector, such as a 2-to-1 multiplexer, used to determine the target allocation signal corresponding to each SRAM block according to the current mode, so as to select SRAM for allocation according to the target allocation signal corresponding to each SRAM block, that is, to determine the SRAM block to be allocated, which serves as the basis for status update.
[0064] S300: Using an adder, the source SRAM block before the logical shift is determined according to the preset logical shift step size and preset logical shift direction.
[0065] It should be noted that, based on the preset logical shift step size and preset logical shift direction, the source SRAM block before the logical shift of the SRAM block to be allocated is determined. This serves as the basis for merging the state update and logical shift operation into the same clock cycle, which helps to realize the flow of load information between different logic processing units, promotes load balancing, and shortens the core operation latency to a single cycle.
[0066] S400: Read the number of used spaces in the source SRAM block to obtain the number of used spaces in the previous cycle.
[0067] S500: Based on the target allocation signal and the used space of the previous cycle, update the used space and saturation state value of the SRAM block to be allocated to obtain a new SRAM block to be allocated.
[0068] It should be noted that by using the number of used spaces in the source SRAM block as the number of used spaces in the previous cycle, and updating the used space and saturation state value of the SRAM block to be allocated based on the target allocation signal and the used space in the previous cycle, and writing the updated used space and saturation state value into the SRAM block to be allocated, a new SRAM block to be allocated is obtained. This achieves the merging of state update and logic shift operation into the same clock cycle, making the register array logically like a ring shift register. The SRAM state information stored in each clock cycle is equivalent to moving according to the preset logic shift step size and preset logic shift direction, thereby realizing the flow of load information between different logic processing units, promoting load balancing, and shortening the core operation latency to a single cycle.
[0069] It should also be noted that in some embodiments, during each clock cycle, the circularly connected SRAM blocks undergo a logical shift. A logical shift represents storing data from one SRAM block into another SRAM block. For example, ... Figure 2 As shown, when the preset logical shift step size is 1 and the preset logical shift direction is to the right, the data in the storage cell of SRAM1 is stored back into SRAM2. Simultaneously, the value in the second status register of SRAM2 is updated according to the value in the first status register of SRAM1. For example, if the used space count in the first status register is 4, and data is written to one storage cell of SRAM2 in the current clock cycle, then the used space count in the second status register of SRAM2 is 5. Without shifting, since the comparator corresponding to each port is fixed, and the multiple SRAM blocks corresponding to each comparator are also fixed, it is equivalent to each port having a fixed SRAM block. Therefore, if a port is continuously written to, it will cause local congestion in the SRAM block corresponding to that port. To address this problem, this application embodiment proposes a logical cyclic shift, which can evenly distribute storage resources to a port evenly, achieving load balancing, even if a port is continuously written to.
[0070] S600: Generate an index for the new SRAM block to be allocated and assign it to the corresponding port.
[0071] The method provided in the first aspect integrates core management operations such as SRAM block selection, state update, and logical shifting into a single cycle. This enables the load to be distributed across different cache resources, improving resource utilization, avoiding local congestion, and concurrently allocating all available SRAM resources to all ports with valid requests when resources are scarce, thereby improving resource utilization, adaptability of resource allocation, reducing latency in cache resource allocation, and improving resource allocation efficiency.
[0072] In one possible implementation, selecting a target mode for the multiple SRAM blocks using the mode switching determiner includes: obtaining the saturation state value of each SRAM block; obtaining the total number of ports in the shared cache system; using the mode switching determiner to sort the multiple SRAM blocks based on the saturation state values to obtain a saturation state sequence; reading the values of the saturation state sequence, obtaining a continuous saturation detection result by detecting whether there are multiple consecutive SRAM blocks with a value of 1 in the saturation state sequence, and obtaining the number of available resources based on the number of SRAM blocks with a value of 0 in the saturation state sequence; and using the mode switching determiner to determine the target mode based on the continuous saturation detection result, the number of available resources, and the total number of ports.
[0073] It should be noted that, as Figure 3 As shown, Figure 3 This is a schematic diagram illustrating the working logic of the mode switching determiner provided in this application embodiment. The mode switching determiner is a global combinational logic module used to determine which cache allocation mode to switch based on the saturation state value of the SRAM block output by the status register of the SRAM logic unit. Specifically, to select a target mode for multiple SRAM blocks, it is necessary to obtain the saturation state value of each SRAM block and the total number of ports in the shared cache system. The multiple SRAM blocks are then sorted based on the obtained saturation state values to obtain a saturation state sequence. The values of the saturation state sequence are read, and a continuous saturation detection result is obtained by detecting whether there are multiple consecutive SRAM blocks with a value of 1 in the saturation state sequence. The number of SRAM blocks with a value of 0 in the saturation state sequence is counted to obtain the number of available resources. Using the mode switching determiner, the target mode is determined based on the obtained continuous saturation detection result, the number of available resources, and the total number of ports. The mode switching determiner will output a mode switching signal or a stop-work signal based on the continuous saturation result, the number of available resources, and the total number of ports. This mechanism ensures that the system dynamically adjusts the cache resource allocation strategy, including switching modes or requesting a stop, based on the global resource scarcity under different workloads and performance requirements, thereby improving resource utilization and system performance.
[0074] In one possible implementation, the step of using the mode switching determiner to determine the target mode based on the continuous saturation detection result, the number of available resources, and the total number of ports includes: when the number of available resources is greater than or equal to the total number of ports, and the continuous saturation detection result shows that there are multiple consecutive saturation state sequences with a value of 1, then the mode switching determiner selects a first mode as the target mode; when the number of available resources is greater than or equal to the total number of ports, and the continuous saturation detection result shows that there are no multiple consecutive saturation state sequences with a value of 1, then the mode switching determiner selects a second mode as the target mode.
[0075] It should be noted that in some embodiments, a mode switching determiner is proposed to determine the target mode based on the continuous saturation detection result, the number of available resources, and the total number of ports. Specifically, when the number of available resources is greater than or equal to the total number of ports, and the continuous saturation detection result shows a value of 1 indicating the existence of multiple consecutive saturation state sequences, the mode switching determiner selects a first mode as the target mode and sends a mode switching signal for selecting the first mode to the mode selection module. When the number of available resources is greater than or equal to the total number of ports, and the continuous saturation detection result shows a value of 1 indicating the absence of multiple consecutive saturation state sequences, the mode switching determiner selects a second mode as the target mode and sends a mode switching signal for selecting the second mode to the mode selection module. Furthermore, when the number of available resources is less than the total number of ports, the mode switching determiner sends a stop-operation signal to a higher-level controller in the system.
[0076] In one possible implementation, the shared cache system further includes a first mode comparator and a second mode priority encoder; the step of using the mode selection module to determine the allocation signal corresponding to each SRAM block according to the mode, and determining the SRAM block to be allocated according to the allocation signal corresponding to each SRAM block, includes: when the target mode is a first mode, using the first mode comparator to determine a first target SRAM block based on the used space value of each SRAM block, and sending a first mode allocation signal to the first target SRAM block; when the target mode is a second mode, using the second mode priority encoder to determine a second target SRAM block based on the saturation state value of each SRAM block, and sending a second mode allocation signal to the second target SRAM block; the mode selection module determines the target allocation signal from the first mode allocation signal and the second mode allocation signal; and the SRAM block with a target allocation signal value of 1 is determined as the SRAM block to be allocated.
[0077] It should be noted that the shared cache system also includes a first mode comparator and a second mode priority encoder. When the target mode is the first mode, the first mode comparator is used to determine the first target SRAM block based on the used space value of each SRAM block, and a first mode allocation signal with a value of 1 is sent to the first target SRAM block, indicating that the first target SRAM block is selected for allocation. When the target mode is the second mode, the second mode priority encoder is used to determine the second target SRAM block based on the saturation state value of each SRAM block, and a second mode allocation signal with a value of 1 is sent to the second target SRAM block, indicating that the second target SRAM block is selected for allocation. The first mode proposed in this application embodiment can achieve load balancing under normal load conditions to ensure uniform utilization of system resources, avoid local overload, and thus maintain stable system operation and high efficiency. The second mode proposed in this application embodiment can achieve rapid global resource allocation under high load conditions to quickly respond to the system's large demand for resources. By realizing adaptive switching between the two modes, system performance can be optimized in different scenarios.
[0078] In one possible implementation, the step of using the first mode comparator to select a first target SRAM block based on the used space value and sending a first mode allocation signal to the first target SRAM block includes: using the first mode comparator, when a write request is made to the port to which the first mode comparator is connected, selecting the SRAM block with the smallest used space from a plurality of SRAM blocks corresponding to the first mode comparator to obtain the first target SRAM block, and sending a first mode allocation signal to the first target SRAM block.
[0079] It should be noted that, as Figure 4 As shown, Figure 4This is a logical diagram illustrating the selection of an SRAM block to be allocated in a first mode according to an embodiment of this application. The system has multiple port logic units, each corresponding to an input port, and each unit is responsible for selecting a first target SRAM block for allocation to the corresponding port under a given mode. Specifically, using a first mode comparator, the port write request signal of the corresponding port is read. If the value of the port write request signal is 0, all allocation outputs are invalid; if the value of the port write request signal is 1, the used space count of a specific number of SRAM blocks is compared, and the SRAM block with the smallest used space count is selected as the first target SRAM block. A first mode allocation signal is then sent to the first target SRAM block. It should also be noted that when comparing the used space count of a specific number of SRAM blocks, the selection of the specific number of SRAM blocks can be based on port numbers or other predetermined rules, and the specific number can be three or more. It is understood that this application does not limit the specific number. A larger specific number allows for more even selection of SRAM resources, ensuring uniform utilization of system resources, avoiding local overload, and thus maintaining stable system operation and high performance.
[0080] It should also be noted that, such as Figure 4 As shown, the shared cache system also includes a first mode encoder, which calculates the index of the first target SRAM block to be allocated to the port based on the SRAM selection instruction sent by the first mode comparator, i.e., the instruction to select the first target SRAM block, the initial encoding offset of the port corresponding to the first target SRAM block, and a globally maintained, time-varying dynamic displacement.
[0081] In one possible implementation, the step of using the second mode priority encoder to select a second target SRAM block based on the saturation state value and sending a second mode allocation signal to the second target SRAM block includes: using the second mode priority encoder to find the index of the SRAM block with a saturation state value of 0, obtaining an index set; using the second mode priority encoder to find all ports of write requests, obtaining a request port index set; and based on a preset priority rule, the index set, and the request port index set, selecting an available SRAM block for each port of the write request, obtaining a second target SRAM block, and sending a second mode allocation signal to the second target SRAM block.
[0082] It should be noted that, as Figure 5 As shown, Figure 5This is a logical diagram illustrating the selection of SRAM blocks to be allocated in the second mode provided in this application embodiment. The second mode priority encoder is a global combinational logic module responsible for global resource allocation in the second mode. Specifically, using the second mode priority encoder, the indices of all SRAM blocks with a saturation state value of 0 are found to obtain an index set. Then, the indices of all ports with a write request signal value of 1 are found to obtain a request port index set. According to preset priority rules, the index set, and the request port index set, as many available SRAM blocks as possible are allocated to the request ports one-to-one. That is, an available SRAM block is selected for each port with a write request. This SRAM block is the second target SRAM block, and the second mode allocation signal and index are sent to the second target SRAM block. The second mode proposed in this application embodiment can achieve rapid global resource allocation under high load conditions to quickly respond to the system's large demand for resources. By realizing adaptive switching between the two modes, system performance can be optimized in different scenarios.
[0083] In one possible implementation, the shared cache system further includes a saturation comparator. The step of updating the used space and saturation state value of the SRAM block to be allocated based on the target allocation signal and the used space of the previous cycle to obtain a new SRAM block to be allocated comprises: using the adder to obtain new used space based on the target allocation signal and the used space of the previous cycle; using the saturation comparator to obtain a new saturation state value based on the new used space; and updating the used space and saturation state value of the SRAM block to be allocated based on the new used space and the new saturation state value to obtain a new SRAM block to be allocated.
[0084] It should be noted that the shared cache system also includes a saturation comparator. To update the used space and saturation state value of the SRAM block to be allocated, and obtain a new SRAM block to be allocated, an adder is used to calculate the new used space based on the target allocation signal and the used space of the previous cycle. Then, a saturation comparator is used to obtain a new saturation state value based on the new used space. The updated used space and saturation state value are written to the SRAM block to be allocated, resulting in a new SRAM block to be allocated. This allows the state update and logical shift operation to be completed within the same clock cycle, making the register array logically like a ring shift register. The SRAM state information stored in each clock cycle is equivalent to moving according to a preset logical shift step size and preset logical shift direction, thereby enabling the flow of load information between different logic processing units, promoting load balancing, and reducing core operation latency to a single cycle.
[0085] In one possible implementation, the shared cache system further includes a global bitmap management module. Before updating the used space and saturation state value of the SRAM block to be allocated based on the target allocation signal and the used space of the previous cycle to obtain a new SRAM block to be allocated, the system further includes: obtaining a release signal from the global bitmap management module; reading the value of the release signal; when the value of the release signal is 1, releasing the storage unit of the SRAM block to be allocated to obtain a released SRAM block; and updating the data in the storage unit of the released SRAM block to the data in the storage unit of the source SRAM block.
[0086] It should be noted that the release signal is used to indicate whether a memory cell in the SRAM block is freed in the current cycle. Specifically, the release signal is obtained from the global bitmap management module of the shared cache system. The value of this release signal is read; when the value is 1, the memory cell of the SRAM block to be allocated is released, and the data in the released SRAM block's memory cell is updated to the data in the source SRAM block's memory cell. This coordinates data consistency between different cache instances, ensures efficient operation and data consistency of the cache system, avoids data redundancy, and guarantees data accuracy. The obtained release signal is used by the adder to calculate the new used space.
[0087] In one possible implementation, obtaining new used space based on the target allocation signal and the space used in the previous cycle using the adder includes: determining new used space based on the target allocation signal, the space used in the previous cycle, the release signal, a preset single allocation space amount, and a preset single release space amount using the adder.
[0088] It should be noted that, in order to update the used space of the SRAM block to be allocated, an adder is needed to calculate the new used space based on the target allocation signal, the used space in the previous cycle, the release signal, the preset single allocation space amount, and the preset single release space amount. Specifically, the calculation method is as follows: add the used space in the previous cycle to the product of the preset single allocation space amount and the target allocation signal, and then subtract the product of the preset single release space amount and the release signal to obtain the new used space.
[0089] In one possible implementation, obtaining a new saturation state value based on the new used space using the saturation comparator includes: using the saturation comparator to compare whether the new number of used spaces is equal to a preset storage capacity saturation threshold, in order to determine the new saturation state value.
[0090] It should be noted that in order to update the saturation state value in the SRAM block to be updated, a new saturation state value needs to be determined. Specifically, a saturation comparator is used to compare whether the new number of used spaces is equal to the preset storage capacity saturation threshold in order to determine the new saturation state value.
[0091] In some embodiments, this application also provides another cache allocation method for a shared cache system, executed in multiple independent clock cycles. For example, the multiple independent clock cycles can be three independent clock cycles. The first cycle is used to determine the index of the target physical index register based on the system port request and the corresponding allocation logic. Specifically, it calculates the logical SRAM start number based on the current index and outputs it to the port. Simultaneously, it sends an "increment count" request to the physical register corresponding to the SRAM block to be allocated. The second cycle is used to update the used space count of the SRAM block to be allocated based on the request received in the first cycle. Simultaneously, some specified registers can perform asynchronous updates based on information provided by external modules to reflect space reclamation. The third cycle is used to update the global offset, changing the mapping relationship between the physical registers and physical SRAM blocks at the start of the next first cycle. This method achieves dynamic allocation and a certain degree of load balancing, but requires setting conservative thresholds such as the maximum memory usage capacity to handle the uncertainty introduced in the state update due to the asynchronous mechanism.
[0092] This application also provides an electronic device, such as... Figure 6 As shown, the electronic device 1400 includes:
[0093] One or more processors 1410;
[0094] The memory 1420 stores one or more programs, which, when executed by one or more processors 1410, enable the one or more processors 1410 to implement the cache allocation method for a shared cache system provided in any embodiment of this application.
[0095] Memory 1420, as a non-transitory network system, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory 1420 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 1420 may optionally include remotely located memories 1420 relative to processor 1410, which can be connected to processor 1410 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0096] The memory 1420 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1420 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1420 and is called and executed by the processor 1410.
[0097] The processor 1410 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.
[0098] In some embodiments, the electronic device further includes:
[0099] Input / output interfaces are used to implement information input and output;
[0100] The communication interface is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).
[0101] The bus transmits information between various components of the device (e.g., processor 1410, memory 1420, input / output interfaces, and communication interfaces);
[0102] The processor 1410, memory 1420, input / output interface, and communication interface can communicate with each other within the device via a bus.
[0103] An embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions for executing a cache allocation method for a shared cache system provided in any embodiment of this application.
[0104] An embodiment of this application also provides a computer program product, including a computer program or computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform a cache allocation method for a shared cache system provided in any embodiment of this application.
[0105] The system architecture and application scenarios described in this application are intended to more clearly illustrate the technical solutions of this application and do not constitute a limitation on the technical solutions provided in this application. Those skilled in the art will understand that as system architectures evolve and new application scenarios emerge, the technical solutions provided in this application are also applicable to similar technical problems.
[0106] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0107] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
[0108] The above description, with reference to the accompanying drawings, illustrates some embodiments of this application, but does not limit the scope of the invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of this invention should be considered within the scope of this application.
[0109] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.
[0110] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0111] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0112] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
[0113] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.
[0114] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.
Claims
1. A cache allocation method for a shared cache system, characterized in that, The shared cache system includes multiple SRAM blocks, a mode switching detector, a mode selection module, and an adder; the method includes: The mode switching determiner uses the saturation state value of each SRAM block to determine the target mode corresponding to each SRAM block. Using the mode selection module, the target allocation signal corresponding to each SRAM block is determined according to the mode, and the SRAM block to be allocated is determined according to the target allocation signal corresponding to each SRAM block; Using the adder, the source SRAM block before the logical shift is determined according to the preset logical shift step size and the preset logical shift direction; Read the number of used spaces in the source SRAM block to obtain the number of used spaces in the previous cycle; Based on the target allocation signal and the used space of the previous cycle, update the used space and saturation state value of the SRAM block to be allocated to obtain a new SRAM block to be allocated. An index is generated for the new SRAM block to be allocated so that it can be assigned to the corresponding port.
2. The method according to claim 1, characterized in that, The step of using the mode switching determiner to select a target mode for multiple SRAM blocks includes: Obtain the saturation state value of each of the SRAM blocks; Obtain the total number of ports in the shared cache system; Using the mode switching determiner, multiple SRAM blocks are sorted based on the saturation state values to obtain a saturation state sequence; The values of the saturation state sequence are read, and the continuous saturation detection result is obtained by detecting whether there are multiple consecutive SRAM blocks with a value of 1 in the saturation state sequence. The number of available resources is obtained based on the number of SRAM blocks with a value of 0 in the saturation state sequence. The target mode is determined using the mode switching determiner based on the continuous saturation detection results, the number of available resources, and the total number of ports.
3. The method according to claim 2, characterized in that, The step of using the mode switching determiner to determine the target mode based on the continuous saturation detection result, the number of available resources, and the total number of ports includes: When the number of available resources is greater than or equal to the total number of ports, and the continuous saturation detection result is that there are multiple consecutive saturation state sequences with a value of 1, then the mode switching judge selects the first mode as the target mode. When the number of available resources is greater than or equal to the total number of ports, and the continuous saturation detection result is 1 (meaning there are no consecutive sequences of saturated states), the mode switching determiner selects the second mode as the target mode.
4. The method according to claim 1, characterized in that, The shared cache system further includes a first mode comparator and a second mode priority encoder; the step of using the mode selection module to determine the allocation signal corresponding to each SRAM block according to the mode, and determining the SRAM block to be allocated according to the allocation signal corresponding to each SRAM block, includes: When the target mode is the first mode, the first mode comparator is used to determine the first target SRAM block based on the used space value of each SRAM block, and a first mode allocation signal is sent to the first target SRAM block. When the target mode is the second mode, the second mode priority encoder is used to determine the second target SRAM block based on the saturation state value of each SRAM block, and a second mode allocation signal is sent to the second target SRAM block. The mode selection module determines the target allocation signal from the first mode allocation signal and the second mode allocation signal; The SRAM block with a target allocation signal value of 1 is identified as the SRAM block to be allocated.
5. The method according to claim 4, characterized in that, The step of using the first mode comparator to select a first target SRAM block based on the used space value and sending a first mode allocation signal to the first target SRAM block includes: Using the first mode comparator, when a write request is made to the port connected to the first mode comparator, the SRAM block with the smallest amount of used space is selected from multiple SRAM blocks corresponding to the first mode comparator to obtain the first target SRAM block, and a first mode allocation signal is sent to the first target SRAM block.
6. The method according to claim 4, characterized in that, The step of using the second mode priority encoder to select a second target SRAM block based on the saturation state value and sending a second mode allocation signal to the second target SRAM block includes: Using the second mode priority encoder, the index of the SRAM block with a saturation state value of 0 is found to obtain the index set; Using the second mode priority encoder, find all ports for write requests to obtain the set of request port indices; Based on the preset priority rules, the index set, and the request port index set, an available SRAM block is selected for each port of the write request to obtain a second target SRAM block, and a second mode allocation signal is sent to the second target SRAM block.
7. The method according to claim 1, characterized in that, The shared cache system further includes a saturation comparator, and the step of updating the used space and saturation state value of the SRAM block to be allocated based on the target allocation signal and the used space of the previous cycle to obtain a new SRAM block to be allocated includes: Using the adder, a new used space is obtained based on the target allocation signal and the used space of the previous cycle; Using the saturation comparator, a new saturation state value is obtained based on the new used space; The used space and saturation state value of the SRAM block to be allocated are updated based on the new used space and the new saturation state value to obtain a new SRAM block to be allocated.
8. The method according to claim 7, characterized in that, The shared cache system further includes a global bitmap management module. Before updating the used space and saturation state value of the SRAM block to be allocated based on the target allocation signal and the used space of the previous cycle to obtain a new SRAM block to be allocated, the system further includes: Obtain the release signal from the global bitmap management module; Read the value of the release signal. When the value of the release signal is 1, release the storage cell of the SRAM block to be allocated to obtain the released SRAM block. The data in the storage cells of the released SRAM block is updated to the data in the storage cells of the source SRAM block.
9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the cache allocation method for a shared cache system as described in any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the cache allocation method for a shared cache system as described in any one of claims 1 to 7.