FPGA implementation of tdlas-wms gas signal enhancement method based on periodic average algorithm

Abstract

The application discloses a kind of FPGA implementation TDLAS-WMS gas signal enhancement method based on periodic average algorithm, belong to gas detection technical field.For trace gas detection, due to the target gas concentration is extremely low, the second harmonic signal obtained by demodulation is easy to be submerged by random noise, leading to signal identification difficulty, affect the accuracy and stability of detection system, the application provides a kind of signal enhancement method based on periodic average algorithm, by corresponding sampling point in multiple cycles is averaged, effectively suppress random noise, significantly improve the signal-to-noise ratio of weak signal, especially suitable for FPGA implementation TDLAS-WMS trace gas detection system.The method of the application utilizes the multiple relationship of read-write clock frequency, after BRAM stores complete cycle data, quickly completes cycle alignment, average operation and real-time output, improves system signal quality and processing efficiency.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of gas detection, and particularly relates to a TDLAS-WMS gas signal enhancement method based on a periodic average algorithm and implemented by FPGA. BACKGROUND

[0002] Tunable Diode Laser Absorption Spectroscopy (TDLAS) is a kind of gas detection technology with high sensitivity and high selectivity. The technology measures the absorption intensity of laser passing through a gas medium by scanning the characteristic absorption spectrum of the target gas with a tunable laser, and inversely calculates the gas concentration according to the Beer-Lambert law. TDLAS has the advantages of fast response, non-contact, high resolution, and suitability for online monitoring, and is widely used in environmental monitoring, industrial process control, and trace gas detection.

[0003] In order to further improve the detection sensitivity, TDLAS is usually combined with Wavelength Modulation Spectroscopy (WMS). The WMS technology superimposes a high-frequency sinusoidal modulation signal on the basis of laser sawtooth wave scanning, and extracts the second harmonic component of the modulation signal through a lock-in amplifier to inversely calculate the gas concentration, which significantly improves the signal-to-noise ratio and measurement accuracy of the system and enhances the ability of trace gas detection. However, when the gas concentration is further reduced, the signal-to-noise ratio of the demodulated second harmonic signal decreases significantly and is often submerged in random noise, and the conventional single-cycle filtering method cannot effectively extract the useful signal. The existing second harmonic signal enhancement methods include Kalman filtering, average filtering, and wavelet transform filtering. These filtering methods can suppress noise and improve signal-to-noise ratio to some extent; collecting multiple cycle signals and processing them through a computer is usually used for experimental data analysis. However, when the gas concentration is extremely low, the amplitude of the second harmonic signal is close to or lower than the noise level, and the traditional filter cannot further improve the signal-to-noise ratio, and even may cause further loss of useful signal. The method of collecting multiple cycle signals and using a computer for averaging has the problem of insufficient real-time performance. SUMMARY

[0004] In order to solve the problem that, in trace gas detection, the second harmonic signal obtained by demodulation is easily submerged in random noise due to extremely low concentration of the target gas, leading to difficulty in signal identification and affecting the accuracy and stability of the detection system, the application provides a signal enhancement method based on a periodic average algorithm, which effectively suppresses random noise by averaging corresponding sampling points in multiple cycles, significantly improves the signal-to-noise ratio of weak signals, and is particularly suitable for TDLAS-WMS trace gas detection systems implemented by FPGA.

[0005] To solve the above technical problems, the application adopts the following technical solutions:

[0006] A FPGA implementation TDLAS-WMS gas signal enhancement method based on periodic average algorithm, comprising the following steps:

[0007] Step 1, write the second harmonic signal of continuous period_cnt periods, each period containing point sampling points, into the block memory (BRAM) in the Field-Programmable Gate Array (FPGA) in sequence;

[0008] Step 2, control the write operation by the period synchronization trigger signal, so that the BRAM write address increases in sequence;

[0009] Step 3, when the write address accumulates to (period_cnt - 1) × point, start the read operation;

[0010] Step 4, the read address is generated by a double-layer counter, using the formula addrb = inner_cnt × point +outer_cnt;

[0011] Step 5, through the nonlinear address mapping mechanism, the data of the same sampling position in multiple periods are read in staggered manner, ensuring one-to-one correspondence of the cross-period sampling points;

[0012] Step 6, sum the period_cnt sampling point data of each group of the same position, and calculate the average through the right shift operation;

[0013] Step 7, finally output the period average signal containing point points.

[0014] The method utilizes the multiple relationship of read and write clock frequencies, and after storing the complete period data in the BRAM, quickly completes the period alignment, average operation and real-time output, improving the system signal quality and processing efficiency.

[0015] Further, the write clock frequency in step 1 is consistent with the signal sampling rate.

[0016] Further, the read operation of step 3 is that the read clock frequency is period_cnt times of the write clock, for realizing fast reading processing.

[0017] Further, the block memory (BRAM) is an asynchronous dual-port RAM structure.

[0018] A second harmonic detection system based on phase-locked amplification, comprising: a high-speed analog-to-digital converter, a periodic average module, a phase-locked amplification module, a cascaded integral comb filter (CIC filter), a processing module and a block memory module;

[0019] The high-speed analog-to-digital converter (ADC) is used for real-time sampling of the analog signal output by the photodetector;

[0020] The cycle average module is used for averaging a plurality of cycle signals to improve the signal-to-noise ratio of the signal;

[0021] The phase-locked amplification module is used for extracting a weak signal component of the same frequency as the reference signal to suppress noise;

[0022] The cascaded integral comb filter realizes downsampling of the sampled signal to reduce the operation complexity of the subsequent filter;

[0023] The processing module is used for cycle average processing of the second harmonic signal in gas detection to improve the signal-to-noise ratio and reduce the detection lower limit;

[0024] After signal acquisition by the high-speed analog-to-digital converter (ADC), the signal is demodulated by the phase-locked amplification module to extract the second harmonic signal (2f signal) containing the target gas absorption information, and then extracted by the cascaded integral comb filter (CIC filter) for processing, effectively reducing the data rate from 25 MSPS to 10 kSPS to adapt to the computing power and data bandwidth requirements of the processing module.

[0025] Further, the second harmonic detection system uses a sawtooth wave to modulate the laser, and the modulation period of the sawtooth wave is set to 10 Hz; at the beginning of each sawtooth wave period, the second harmonic detection system generates a synchronous high-level control signal with a duration of 100 microseconds, which is used to trigger the block memory (BRAM) module to start writing operation, ensuring cycle synchronization and data consistency.

[0026] Further, the cycle average module includes a reset signal interface, an input signal interface, a cycle signal point number interface, a BRAM read clock interface, a BRAM write clock interface, a cycle start signal interface, and an output signal interface, a BRAM read enable signal interface, a BRAM write enable signal interface, a BRAM read address interface, a BRAM write address interface, and an average completion signal interface.

[0027] Further, the sampling rate of the high-speed analog-to-digital converter (ADC) is 25 million samples per second (25 MSPS), which ensures sufficient sampling accuracy of high-frequency signals.

[0028] Further, the block memory (BRAM) module uses a 10 kHz clock for the write port and a 20 kHz clock for the read port to realize a data processing architecture of slow writing and fast reading.

[0029] Further, the mapping strategy of BRAM read address is: at each moment, the same position of the sampling points in two different periods is taken out, and a zero supplement period is taken out, so that the cross-period point-to-point data alignment and subsequent processing are realized; the calculation formula is represented as: addrb=N+k×1000; wherein, k=0, 1; N=0~999.

[0030] Compared with the prior art, the present application has the following advantages:

[0031] The present application improves the signal-to-noise ratio by introducing a multi-period average mechanism: compared with the traditional phase-locked amplification system which usually only collects a single period of harmonic signals, there is a problem that it is easy to be disturbed by noise, resulting in large fluctuations in the detection results, the present application writes the second harmonic signals of continuous multiple periods into the block memory (BRAM) in the FPGA, and in the readout stage, weighted average is carried out in units of period corresponding points (four period data accumulation right shift two bits), which significantly suppresses random noise, improves the stability of the signal and the repeatability of the system.

[0032] At the same time, the asynchronous dual-port BRAM design and the nonlinear address mapping strategy of the present application: the asynchronous dual-port BRAM is adopted, the write port is consistent with the 10kHz rate of the sample and hold, while the read port works at a higher 40kHz rate, realizing the separation and parallel operation of writing and reading. When reading, the address mapping formula addrb=N+k×1000 is used innovatively, realizing the data interleaving arrangement and reading of the same sampling points of multiple periods, which is convenient for subsequent period average processing. This "cross-period point-to-point pairing" reading method is an improvement over the existing average strategy. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows, obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0034] Figure 1 is a period average method flow chart.

[0035] Figure 2 is a period average module interface schematic diagram.

[0036] Figure 3 is a module timing diagram. DETAILED DESCRIPTION

[0037] For a more complete understanding of the present application, it will be described in detail with reference to the following description and drawings. However, the present application is not limited to the specific examples described herein. The presentation of these examples is intended to deepen the overall understanding of the disclosure of the present application.

[0038] Embodiment 1

[0039] A FPGA implementation of TDLAS-WMS gas signal enhancement method based on period average algorithm, as shown in Figure 1

[0040] Step 1, write the second harmonic signal of continuous period_cnt periods, each period containing point sampling points, into the block memory BRAM inside the field programmable gate array FPGA in turn; the write clock frequency is consistent with the signal sampling rate;

[0041] Step 2, control the write operation by period synchronization trigger signal, so that the BRAM write address increases in order;

[0042] Step 3, when the write address accumulates to (period_cnt - 1) × point, start the read operation; the read clock frequency is period_cnt times of the write clock, so as to realize fast read processing;

[0043] Step 4, the read address is generated by a double-layer counter, and the formula addrb = inner_cnt × point + outer_cnt is used;

[0044] Step 5, through the nonlinear address mapping mechanism, the data of the same sampling position in multiple periods are read in staggered manner, so as to ensure one-to-one correspondence of the cross-period sampling points;

[0045] Step 6, sum the period_cnt sampling point data of each group of the same position, and calculate the average through right shift operation;

[0046] Step 7, finally output the period average signal containing point points.

[0047] By using the multiple relationship of read and write clock frequencies, after storing the complete period data in BRAM, the period alignment, average operation and real-time output are quickly completed, which improves the system signal quality and processing efficiency.

[0048] Embodiment 2

[0049] A second harmonic detection system based on phase-locked amplification, comprising: a high-speed analog-to-digital converter, a period average module, a phase-locked amplification module, a cascaded integral comb filter (CIC filter), and a processing module;

[0050] ​The high-speed analog-to-digital converter (ADC) is used for real-time sampling of the analog signal output by the photodetector;

[0051] The cycle averaging module is used for averaging a plurality of cycle signals to improve the signal-to-noise ratio of the signal;

[0052] The phase-locked amplification module is used for extracting a weak signal component of the same frequency as the reference signal to suppress noise;

[0053] The cascaded integral comb filter realizes downsampling of the sampled signal to reduce the operation complexity of the subsequent filter;

[0054] The processing module is used for cycle averaging processing of the second harmonic signal in gas detection to improve the signal-to-noise ratio and reduce the detection lower limit;

[0055] After signal acquisition by the high-speed analog-to-digital converter (ADC), the signal is demodulated by the phase-locked amplification module to extract the second harmonic signal (2f signal) containing the target gas absorption information, and then is extracted by the cascaded integral comb filter (CIC filter) for processing, so that the data rate is effectively downsampled from 25 MSPS to 10 kSPS to adapt to the computing power and data bandwidth requirements of the processing module. Figure 2 The input and output interfaces of the cycle averaging module.

[0056] Since the system uses a sawtooth wave to modulate the laser, the modulation period of the sawtooth wave is set to 10 Hz, so each cycle contains a time length of 100 ms. Corresponding to the 10 kSPS sampling rate, 1000 points of second harmonic data will be collected in each cycle. To ensure cycle synchronization and data consistency, the system generates a synchronization high-level control signal with a duration of 100 microseconds at the beginning of each sawtooth cycle update, which is used to trigger the block memory (BRAM) module to start writing operation.

[0057] The BRAM is configured as an asynchronous dual-port RAM structure, the number of averaged cycles is set to 2, the write port uses a 10 kHz clock, and the read port uses a 20 kHz clock to realize the data processing architecture of "slow writing and fast reading". After receiving the write trigger signal, the write address of the BRAM is initialized to 0 and is incremented by 1 at each rising edge of the write clock until the write address reaches 1999. During this process, a total of two complete cycles (i.e. 2000 points) of second harmonic signals are written, which are stored in the address intervals [0, 999], [1000, 1999] respectively.

[0058] When the two cycle data are completely written, the system automatically switches to the reading mode, and the reading operation of the BRAM is started. In order to realize the fast average calculation of the corresponding points of the cycle, the reading address is generated by using a special mapping strategy. Specifically, the reading address is sequentially accessed according to the following sequence: 0, 1000, 1, 1001, 2, 1002,..., that is, the reading address is generated by using the following calculation formula:

[0059] addrb = N + k * 1000 (k = 0, 1; N = 0 ~ 999)

[0060] The address generation mode ensures that the same position sampling points (for example, the Nth sampling point) are taken out from two different cycles at each moment, and a zero complementary cycle (address 1000 + N) is taken out, so that the data alignment and subsequent processing of the cross-cycle point-to-point are realized.

[0061] Subsequently, the data of the four adjacent cycle corresponding sampling points read are accumulated, and the average value is calculated by shifting the logic to the right by one bit (equivalent to dividing by 2), so that a cycle average result is output. The module timing diagram is as shown in Figure 3 .

[0062] This processing method not only significantly reduces the influence of random fluctuations in the cycle on the signal stability, but also effectively improves the signal-to-noise ratio and data repeatability, and helps to improve the stability of the gas concentration inversion.

[0063] In addition, the design realizes the accumulation and average logic of the corresponding points of multiple cycles in the FPGA, cooperates with the efficient clock control and address mapping mechanism, and can complete the complex data fusion processing without relying on an external processor, has high integration and real-time performance, and is especially suitable for application in high-precision gas detection and laser absorption spectrum systems.

[0064] The contents not described in detail in the specification of the present application belong to the prior art known to those skilled in the art. Although the above describes the specific embodiments of the present application in order to facilitate those skilled in the art to understand the present application, it should be clear that the present application is not limited to the scope of the specific embodiments, and for those skilled in the art, it is obvious that various changes are within the spirit and scope of the present application defined and limited by the appended claims, and all the application and creation utilizing the concept of the present application are within the scope of protection.

Claims

1. A method for enhancing TDLAS-WMS gas signals using an FPGA based on a periodic averaging algorithm, characterized in that: Includes the following steps: Step 1: Write the second harmonic signal with consecutive period_cnt cycles and each cycle containing point sampling points into the block memory (BRAM) inside the field programmable gate array (FPGA) in sequence. Step 2: Control the write operation through the periodic synchronous trigger signal to make the BRAM write address increment sequentially; Step 3: When the accumulated write address reaches (period_cnt - 1) × point, initiate the read operation; Step 4: The read address is generated by a two-level counter, using the formula addrb = inner_cnt × point + outer_cnt; Step 5: Through a non-linear address mapping mechanism, data at the same sampling position in multiple cycles are read in an interleaved manner to ensure that the sampling points across cycles correspond one-to-one. Step 6: Sum the data from period_cnt sampling points at the same position in each group, and then calculate the average by right shifting. Step 7: The final output is a periodic average signal containing points.

2. The method for enhancing TDLAS-WMS gas signals using an FPGA based on a periodic averaging algorithm according to claim 1, characterized in that: In step 1, the clock frequency is written to be consistent with the signal sampling rate.

3. The method for enhancing TDLAS-WMS gas signals using an FPGA based on a periodic averaging algorithm according to claim 1, characterized in that: The read operation in step 3 uses a read clock frequency that is period_cnt times the write clock frequency to achieve fast read processing.

4. The FPGA-based TDLAS-WMS gas signal enhancement method based on a periodic averaging algorithm according to claim 1, characterized in that: The block memory (BRAM) is an asynchronous dual-port RAM structure.

5. A second harmonic detection system based on lock-in amplification, characterized in that, The method for implementing any one of claims 1 to 4 specifically includes: a high-speed analog-to-digital converter, a periodic averaging module, a phase-locked amplifier module, a cascaded integrator-comb filter, a processing module, and a block memory module. The high-speed analog-to-digital converter is used to sample the analog signal output by the photodetector in real time. The periodic averaging module is used to average multiple periodic signals to improve the signal-to-noise ratio of the signal; The lock-in amplifier module is used to extract weak signal components with the same frequency as the reference signal to suppress noise; The cascaded integrator comb filter achieves downsampling of the sampled signal to reduce the computational complexity of subsequent filters; The processing module is used to perform periodic averaging of the second harmonic signal in gas detection to improve the signal-to-noise ratio and reduce the detection limit. After the signal is acquired by the high-speed analog-to-digital converter, the signal is demodulated by the lock-in amplifier module to extract the second harmonic signal containing the absorption information of the target gas. Then, it is processed by the cascaded integrator comb filter to effectively downsample the data rate from 25 MSPS to 10 kSPS to match the computing power and data bandwidth requirements of the processing module.

6. The second harmonic detection system based on lock-in amplification according to claim 5, characterized in that: The second harmonic detection system uses a sawtooth wave to modulate the laser frequency, with the modulation period of the sawtooth wave set to 10 Hz. At the start of each sawtooth wave cycle update, the second harmonic detection system generates a 100-microsecond synchronous high-level control signal to trigger the block memory module to begin write operations, ensuring cycle synchronization and data consistency.

7. The second harmonic detection system based on lock-in amplification according to claim 5, characterized in that: The period averaging module includes a reset signal interface, an input signal interface, a period signal point count interface, a BRAM read clock interface, a BRAM write clock interface, a period start signal interface, an output signal interface, a BRAM read enable signal interface, a BRAM write enable signal interface, a BRAM read address interface, a BRAM write address interface, and an averaging completion signal interface.

8. The second harmonic detection system based on lock-in amplification according to claim 5, characterized in that: The high-speed analog-to-digital converter has a sampling rate of 25 megasamples per second.

9. A second harmonic detection system based on lock-in amplification according to claim 5, characterized in that: The block memory module uses a 10 kHz clock for the write port and a 20 kHz clock for the read port to implement a slow write and fast read data processing architecture.

10. A second harmonic detection system based on lock-in amplification according to claim 7, characterized in that: The mapping strategy adopted by BRAM read address is as follows: at each time step, the sampling point at the same position is taken from two different cycles, and a zero-padding cycle is added to realize cross-cycle point-to-point data alignment and subsequent processing; the calculation formula is expressed as: addrb =N+k×1000; where k=0,1; N=0~999.

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