Methods, systems, and electronic devices for preparing graph-based stable substates

Abstract

This invention discloses a method, system, and electronic device for preparing stable substates based on graph states. The method includes: acquiring and preprocessing stable substate generators to obtain complete stable substate generators; generating an initial parity-check matrix based on the complete stable substate generators; converting the initial parity-check matrix into a graph state parity-check matrix and recording the conversion operations performed during the conversion; constructing a graph state preparation circuit based on the graph state parity-check matrix; constructing a stable substate reduction circuit based on the conversion operations; merging the graph state preparation circuit and the stable substate reduction circuit into a total circuit; acquiring an initial quantum state and executing the total circuit with the initial quantum state to obtain a stable substate. This invention uses graph states as an intermediary, reducing the complexity of circuit design and improving computational efficiency, making it suitable for large-scale quantum systems. Furthermore, the precise mapping relationship between stable substates and graph states avoids approximation errors.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of quantum technology, in particular to a preparation method of stabilizer states based on graph states, a preparation system of stabilizer states based on graph states and an electronic device. BACKGROUND

[0002] Stabilizer states are one of the core resources in quantum information science, playing an irreplaceable role in multiple key fields. For example, in the field of quantum error correction, many important quantum error-correcting codes, such as [[n, k, d]] quantum error-correcting codes, are mostly constructed based on stabilizer states. Stabilizer states can effectively resist quantum noise and decoherence effects. By measuring the stabilizer generators, errors in quantum bits can be detected and corrected, ensuring the accuracy of quantum information during transmission and storage, which is crucial for reliable quantum communication and large-scale quantum computation. In the field of quantum simulation, stabilizer states also have important significance. For example, in the field of quantum chemistry, the ground state energy of a molecular system can be obtained by solving the minimum expectation value of the Hamiltonian, and stabilizer states are ideal candidate solutions for this problem. By preparing and manipulating stabilizer states, complex quantum systems can be accurately simulated, providing powerful tools for new material research and drug design. In quantum computing, stabilizer state encoding can improve the reliability and fault tolerance of computation, enabling quantum algorithms to run correctly in noisy environments.

[0003] However, the stabilizer state preparation method in the related art has some limitations. The current method relies on a variational quantum-classical hybrid algorithm to approximate the target state through a quantum circuit with parameters. This method has significant shortcomings: 1. The complete quantum state needs to be trained and optimized through a classical simulator, and the computational complexity increases exponentially with the number of quantum bits, making it difficult to adapt to large-scale systems, resulting in high computational complexity. 2. The approximation nature of the variational algorithm leads to cumulative preparation errors, especially in many-body systems, where the fidelity significantly decreases as the system size increases. SUMMARY

[0004] The present application is proposed to solve at least one of the above problems. According to a first aspect of the present application, a preparation method of stabilizer states based on graph states is provided, which comprises:

[0005] Obtaining and preprocessing stabilizer generators to obtain complete stabilizer generators.

[0006] Generating an initial check matrix according to the complete stabilizer generators.

[0007] Converting the initial check matrix into a check matrix of graph states, and recording the conversion operations performed during the conversion.

[0008] Based on the verification matrix of the pattern, construct the pattern preparation circuit.

[0009] Based on the aforementioned conversion operation, a stable substate restoration circuit is constructed.

[0010] The pattern preparation circuit and the stable substate restoration circuit are combined into a total circuit.

[0011] An initial quantum state is obtained, and the initial quantum state is made to execute the overall circuit to obtain a stable substate.

[0012] The initial parity-check matrix consists of a Z matrix, an X matrix, and a phase index. The parity-check matrix of the graphical state is characterized by the X matrix being an identity matrix, and all qubits in the initialized quantum state are in a state where... state.

[0013] In one embodiment of the present invention, the step of converting the initial parity-check matrix into a graph-state parity-check matrix includes:

[0014] The X matrix is ​​converted into an upper triangular matrix or a lower triangular matrix, and the upper triangular matrix or the lower triangular matrix is ​​converted into the identity matrix.

[0015] Set the diagonal of the Z matrix to zero.

[0016] Set all phase indices to zero.

[0017] In one embodiment of the present invention, the step of converting the X matrix into an upper triangular matrix includes:

[0018] Traverse the X matrix row by row and determine Is it equal to 1?

[0019] like and Then through ,make .

[0020] like and Then through ,make 1, and return the judgment. The steps to determine if it equals 1.

[0021] like And none Then execute The door is opened, and the judgment is returned. The steps to determine if it equals 1.

[0022] The step of converting the upper triangular matrix into the identity matrix includes:

[0023] traversing the upper triangular matrix by row, judging whether is equal to 1.

[0024] If , then by , set to 0.

[0025] The step of setting the diagonal of the Z matrix to zero comprises:

[0026] traversing the Z matrix by row, judging whether is equal to 1.

[0027] If , then execute gate, set to 0.

[0028] The step of setting all the phase indices to zero comprises:

[0029] traversing the phase indices by row, judging whether is equal to 1.

[0030] If , then execute gate, set to 0.

[0031] In an embodiment of the present application, the comprises:

[0032] The phase index of the jth row is determined by the following formula:

[0033]

[0034] XOR the first row to the first row.

[0035] The comprises:

[0036] Swap the first row and the first row of the exchange matrix.

[0037] The step of executing gate comprises:

[0038] The phase index of the ith row is updated in turn by the following formula:

[0039]

[0040] Swap the ath column of the Z matrix and the ath column of the X matrix.

[0041] The executing The step of performing a gate includes:

[0042] The phase index of the i-th row is updated in sequence by the following formula:

[0043]

[0044] The matrix element is updated in sequence by the following formula:

[0045]

[0046] The step of performing a gate includes: The step of performing a gate includes:

[0047] The phase index of the i-th row is updated in sequence by the following formula:

[0048]

[0049] wherein, represents an H gate on the a-th qubit, represents an S gate on the a-th qubit, represents a Z gate on the a-th qubit, represents an element in the i-th row and the j-th column of the X matrix, represents an element in the i-th row and the j-th column of the Z matrix, represents the i-th phase index, , , , , and n represents the number of qubits.

[0050] In an embodiment of the present application, the step of constructing a graph state preparation circuit according to the check matrix of the graph state includes:

[0051] An H gate is independently applied to each qubit.

[0052] A CZ gate is applied according to an adjacency matrix in the check matrix of the graph state, to obtain the graph state preparation circuit.

[0053] In an embodiment of the present application, the conversion operation includes: , , an H gate, an S gate and a Z gate; the step of constructing a stabilizer state reduction circuit according to the conversion operation includes:

[0054] The H gate, the S gate and the Z gate in the conversion operation are combined in reverse order to generate the stabilizer state reduction circuit.

[0055] ​In one embodiment of the present application, the step of combining the graph state preparation circuit and the stabilizer state reduction circuit into a total circuit comprises:

[0056] An inverse circuit of the graph state preparation circuit is constructed to obtain a first inverse circuit.

[0057] An inverse circuit of the stabilizer state reduction circuit is constructed to obtain a second inverse circuit.

[0058] The first inverse circuit and the second inverse circuit are connected in sequence to obtain the total circuit.

[0059] In one embodiment of the present application, the step of obtaining and preprocessing the stabilizer generating elements comprises:

[0060] It is judged whether the number of the stabilizer generating elements is equal to the number of qubits in the stabilizer state to be prepared.

[0061] If yes, the stabilizer generating elements are taken as the complete stabilizer generating elements.

[0062] If no, the stabilizer generating elements are padded to obtain the complete stabilizer generating elements.

[0063] According to the second aspect of the present application, a preparation system of a stabilizer state based on a graph state is provided, which comprises a preprocessing module, an initialization module, a transformation module, a graph state preparation circuit construction module, a stabilizer state reduction circuit construction module, a total circuit construction module and a stabilizer state preparation module.

[0064] The preprocessing module is used to obtain and preprocess stabilizer generating elements to obtain complete stabilizer generating elements.

[0065] The initialization module is used to generate an initial check matrix according to the complete stabilizer generating elements.

[0066] The transformation module is used to convert the initial check matrix into a check matrix of a graph state and record conversion operations performed in the conversion process.

[0067] The graph state preparation circuit construction module is used to construct a graph state preparation circuit according to the check matrix of the graph state.

[0068] The stabilizer state reduction circuit construction module is used to construct a stabilizer state reduction circuit according to the conversion operations.

[0069] The total circuit construction module is used to combine the graph state preparation circuit and the stabilizer state reduction circuit into a total circuit.

[0070] The stable state preparation module is configured to obtain an initial quantum state, and make the initial quantum state execute the total circuit to obtain the stable state.

[0071] The initial check matrix is composed of a Z matrix, an X matrix and a phase pointer array, the check matrix of the graph state is characterized in that the X matrix is a unit matrix, and each quantum bit in the initial quantum state is in a state.

[0072] According to a third aspect of the present application, an electronic device is provided, which comprises a memory, a processor and a computer program stored in the memory, and the computer program, when executed by the processor, implements any of the above-mentioned preparation methods of a stable state based on a graph state.

[0073] According to the preparation method, system and electronic device of a stable state based on a graph state provided by the embodiments of the present application, the preparation method of a stable state based on a graph state of the present application uses a graph state as an intermediary, reduces the complexity of circuit design, thereby reducing the complexity of calculation, improving the efficiency of quantum information processing, and making the present application adapt to a large-scale quantum system. And through the accurate mapping relationship between the stable state and the graph state, the occurrence of approximation error is avoided, so that the theoretical fidelity reaches 100%. At the same time, by preprocessing the stable state generator, the accuracy and reliability of the stable state preparation are improved. BRIEF DESCRIPTION OF DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0075] Figure 1 The flowchart of the preparation method of a stable state based on a graph state provided by an embodiment of the present application is shown in the figure.

[0076] Figure 2 The circuit diagram of the quantum circuit provided by an embodiment of the present application is shown in the figure.

[0077] Figure 3 The circuit diagram of the quantum circuit provided by another embodiment of the present application is shown in the figure.

[0078] Figure 4 The structure diagram of the preparation system of a stable state based on a graph state provided by an embodiment of the present application is shown in the figure.

[0079] Figure 5 The hardware structure block diagram of the computer terminal of the preparation method of a stable state based on a graph state provided by an embodiment of the present application is shown in the figure. ​Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of the present invention.

[0081] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0082] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0083] To fully understand this invention, a detailed structure will be presented in the following description to illustrate the technical solution proposed by this invention. Optional embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0084] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0085] To improve the efficiency of quantum information processing, the first aspect of this invention provides a method for preparing stable substates based on graph states, such as... Figure 1 As shown, the method for preparing stable substates based on graph states includes:

[0086] S1: Obtain and preprocess stable sub-generators to obtain complete stable sub-generators.

[0087] It should be noted that a stable substate can be defined by a set of stable sub-generators. A stable sub-generator can be represented as a single... binary matrix:

[0088]

[0089] in, row representation One generator, Indicates the first the phase index of the th generating element, corresponding to the phase , and for the th generating element:

[0090] If the th bit is , then is 1, otherwise 0.

[0091] If the th bit is , then is 1, otherwise 0.

[0092] If the th bit is , then are both 1, otherwise both 0.

[0093] S2, generating an initial parity-check matrix according to the complete stabilizer generating elements.

[0094] S3, converting the initial parity-check matrix into a parity-check matrix of a graph state, and recording the conversion operations performed in the conversion process.

[0095] It should be noted that a graph state is a kind of quantum state closely related to graph theory, and the entanglement structure between its quantum bits is described by an undirected graph, which plays a key role in distributed quantum computing. Taking the measurement-based quantum computing (MBQC) model as an example, the graph state serves as the initial state, and through a series of carefully designed single-bit measurement operations, it can implement any quantum computing task. This computing mode has high parallelism and scalability, providing a highly potential approach for building large-scale quantum computing systems. In addition, the preparation and operation of the graph state are relatively simple, only H gates and CZ gates are needed, which is highly compatible with current superconducting, ion trap and other mainstream quantum hardware platforms, and has good hardware implementability.

[0096] Exemplarily, a graph state is composed of a vertex set V and an undirected, non-weighted edge set E, each vertex in the vertex set V corresponds to a quantum bit, and the edge set E determines the interaction relationship between the quantum bits. After the initial parity-check matrix is converted into a parity-check matrix of a graph state, each generating element can be represented as: wherein, is a vertex, represents the edge neighborhood of vertex . The parity-check matrix of the graph state can be represented as: wherein, is an adjacency matrix, is an identity matrix, is a column vector of phases, usually​​​​ .

[0097] S4, constructing a graph state preparation circuit according to the check matrix of the graph state.

[0098] As an example, the generation process of the graph state preparation circuit can include: initialization and entanglement generation.

[0099] S5, constructing a stabilizer state reduction circuit according to the conversion operation.

[0100] As an example, the stabilizer state reduction circuit can be constructed according to the column operation of the conversion operation.

[0101] S6, merging the graph state preparation circuit and the stabilizer state reduction circuit into a total circuit.

[0102] S7, obtaining an initial quantum state and making the initial quantum state execute the total circuit to obtain a stabilizer state.

[0103] The initial check matrix is composed of a Z matrix, an X matrix and a phase index array, and the feature of the check matrix of the graph state is that the X matrix is a unit matrix, and all the quantum bits in the initial quantum state are in the state.

[0104] The preparation method of the stabilizer state based on the graph state of the embodiment reduces the complexity of the circuit design, thereby reducing the complexity of the calculation, improving the efficiency of the quantum information processing, and making the application adapt to large-scale quantum systems. And through the accurate mapping relationship between the stabilizer state and the graph state, the appearance of the approximate error is avoided, so that the theoretical fidelity reaches 100%. At the same time, by preprocessing the stabilizer generator, the accuracy and reliability of the stabilizer state preparation are improved.

[0105] In some embodiments, the step of converting the initial check matrix into the check matrix of the graph state includes:

[0106] S31, converting the X matrix into an upper triangular matrix or a lower triangular matrix, and converting the upper triangular matrix or the lower triangular matrix into a unit matrix.

[0107] S32, setting the diagonal line of the Z matrix to zero.

[0108] S33, setting all the phase indexes to zero.

[0109] Specifically, the step of converting the X matrix into an upper triangular matrix includes:

[0110] S3111, traversing the X matrix by row, and judging whether is equal to 1.

[0111] S3112, if and Then through ,make .

[0112] S3113, if and Then through ,make 1, and return the judgment. The steps to determine if it equals 1.

[0113] S3114, if And none Then execute The door is opened, and the judgment is returned. The steps to determine if it equals 1.

[0114] The steps to convert an upper triangular matrix into an identity matrix include:

[0115] S3121, traverse the upper triangular matrix row by row and determine... Is it equal to 1?

[0116] S3122, if Then through ,Will Set to 0.

[0117] The steps to set the diagonal of the Z matrix to zero include:

[0118] S321, Traverse the Z matrix row by row and determine... Is it equal to 1?

[0119] S322, if Then execute The door will Set to 0.

[0120] The steps to set all phase indices to zero include:

[0121] S331, traverse the phase index row by row to determine Is it 1?

[0122] S332, if Then execute The door will Set to 0.

[0123] More specifically, include:

[0124] The phase index of the j-th row is determined using the following formula:

[0125]

[0126] The first XOR to the first row.

[0127] comprises the step of swapping the first row of the exchange matrix with the first row.

[0128] performing the step of applying a gate, comprising:

[0129] the phase index of the i-th row is updated in turn by the following formula:

[0130]

[0131] swapping the a-th column of the Z matrix with the a-th column of the X matrix.

[0132] performing the step of applying a gate, comprising:

[0133] the phase index of the i-th row is updated in turn by the following formula:

[0134]

[0135] updating the matrix element in turn by the following formula:

[0136]

[0137] performing the step of applying a gate, comprising:

[0138] the phase index of the i-th row is updated in turn by the following formula:

[0139]

[0140] wherein, denotes an H gate on the a-th qubit, denotes an S gate on the a-th qubit, denotes a Z gate on the a-th qubit, denotes the element in the i-th row and j-th column of the X matrix, denotes the element in the i-th row and j-th column of the Z matrix, denotes the i-th phase index, , , , , and n denotes the number of qubits.

[0141] It should be noted that the initial parity check matrix is finally processed into the form of .

[0142] In this embodiment, through a series of transformation operations, the initial parity check matrix is ​​converted into a graph state parity check matrix, and the subsequent graph state preparation circuit and stable substate restoration circuit design are connected, which greatly reduces the complexity and operational error of stable substate preparation.

[0143] In some embodiments, the step of constructing a pattern fabrication circuit based on the pattern parity matrix includes:

[0144] S41, apply the H gate independently to each qubit.

[0145] Accordingly, this step can be denoted as initialization.

[0146] As an example, apply to all qubits Gate, preparation This state is the basis for the subsequent generation of entangled states. The matrix representation of the gate is as follows Apply to all qubits Gate operations can be represented by tensor products, i.e. ,in It is the number of qubits.

[0147] S42, based on the adjacency matrix in the parity check matrix of the pattern, apply the CZ gate to obtain the pattern preparation circuit.

[0148] Accordingly, this step can be denoted as entanglement generation.

[0149] As an example, based on the adjacency matrix Apply a pass to each edge (i,j) A gate can introduce entanglement between two qubits; specifically, when the control bit is in a certain state... When the target bit is in phase flip, the control bit will be in phase flip. At that time, the target bit remains unchanged. In this invention, based on the adjacency matrix... The element value determines whether to apply to the first element. The and the first Applying one quantum bit Door, if Then it means the first The and the first Entanglement exists between individual qubits, requiring the application of... Door; if This indicates that there is no entanglement between them, and no action is required. Door. The matrix representation of the gate is as follows The entanglement generation operation can be represented as ,in It is the edge set of a graph. This means that an application is performed on the two qubits corresponding to each edge in the graph. This introduces entanglement between these qubits by creating a gate.

[0150] It should be noted that by combining the initialization and entanglement generation steps, the pattern state preparation circuit is obtained. Specifically, the operation sequence is as follows: first, initialization is performed, placing all qubits in... The graph state is then generated, and entanglement is introduced between the qubits. Therefore, the graph state generation circuit can be represented as follows: (The evolution of a quantum state is mathematically described by the action of a unitary matrix; that is, when a quantum state...) Apply first Operation, then apply During the operation, matrix multiplication can be represented as follows: ).

[0151] In this embodiment, the circuit design described above enables efficient fabrication of the desired graph state, providing a foundation for subsequent quantum computing operations. Compared to traditional graph state fabrication methods, the method of this invention reduces the number of quantum gates used by optimizing operational steps and utilizing information from the adjacency matrix, thereby reducing circuit complexity and noise impact, and improving the efficiency and fidelity of graph state fabrication.

[0152] In some embodiments, the conversion operation includes: , The steps for constructing a stable substate restoration circuit based on the conversion operation include: combining the H gate, S gate, and Z gate in the conversion operation in reverse order to generate a stable substate restoration circuit.

[0153] It should be noted that after the pattern is prepared by the pattern preparation circuit, it needs to be restored to a stable sub-state in order to perform subsequent measurements or other operations.

[0154] As an example, the process of converting the initial parity-check matrix into a graphical parity-check matrix is ​​documented, including each conversion operation, such as row swapping. Seeking a balance and single-bit gate operations ( To restore a graph state to a stable substate, the inverse operations of these operations need to be performed in reverse order, and only column operations need to be performed. The inverse operation of the gate is obtained, while the inverse of the row operation (row swap, row summation) is achieved through a linear transformation, without the need to add extra gate operations to the physical circuit, finally resulting in a stable substate restoration circuit. The specific mechanism is as follows:

[0155] Seeking a balance The inverse of the XOR operation is itself, achieved through a linear combination of row operation matrices, without the need for quantum gates.

[0156] Line swap Its inverse operation is itself, which is achieved by swapping row indices and does not require quantum gates.

[0157] H-gate: The inverse operation is itself. .

[0158] The S-gate, its inverse operation is transpose-conjugate. .

[0159] Z-gate: The inverse operation is itself. .

[0160] In this embodiment, the circuit design described above enables the efficient fabrication of the required stable substate reduction circuit, providing a foundation for subsequent quantum computing operations.

[0161] In some embodiments, the step of merging the pattern preparation circuit and the stable substate restoration circuit into a total circuit includes:

[0162] S61, construct the inverse circuit of the pattern preparation circuit to obtain the first inverse circuit.

[0163] S62, construct the inverse circuit of the stable substate reduction circuit to obtain the second inverse circuit.

[0164] S63, connect the first inverse circuit and the second inverse circuit in series to obtain the total circuit.

[0165] Specifically, in quantum circuits, combinations of different operations can be represented using matrix multiplication. When attempting to convert a stable substate into a graphical state and then back to a stable substate from the graphical state, these two processes occur sequentially. First, using a circuit... Will Convert to a graphical state; then, use a circuit. The graph state is manipulated to reduce it to a stable substate. These two operations act sequentially on the quantum state, mathematically equivalent to a matrix. and Multiply in sequence, that is And the total circuit It is the whole from The inverse operation of the process from the graph state to the stable substate, i.e. .

[0166] Through such a circuit design, the graph state can be accurately restored to the stabilizer state, and since the operation of each step is recorded during the conversion process, the accuracy and repeatability of the restoration process can be guaranteed. This is very important for error correction and measurement operations in quantum computing, because only accurate restoration of the stabilizer state can correctly proceed with subsequent measurements and analysis, thereby obtaining reliable calculation results.

[0167] In this embodiment, the quantum circuit design of the present application realizes efficient conversion between the stabilizer state and the graph state through the graph state preparation circuit and the stabilizer state restoration circuit, providing important technical support for the practical application of quantum computing. This circuit design not only reduces the number of quantum gates used and reduces the complexity of the circuit, but also improves the fidelity and efficiency of quantum state conversion, which has significant technical advantages compared to the prior art.

[0168] In some embodiments, the step of obtaining and preprocessing the stabilizer generator includes:

[0169] S11, determining whether the number of stabilizer generators is equal to the number of quantum bits in the stabilizer state to be prepared.

[0170] S12, if equal, the stabilizer generator is used as a complete stabilizer generator.

[0171] S13, if not equal, the stabilizer generator is padded to obtain a complete stabilizer generator.

[0172] As an example, when the number of quantum bits is n and the number of stabilizer generators is less than n, the existing generator padding technology can be applied to expand it to n, thereby forming a standard check matrix form.

[0173] In this embodiment, by padding the stabilizer generator, the preprocessed stabilizer generator can form a standard check matrix form, ensuring the full rank of the check matrix.

[0174] Next, the present application takes a set of generators as an example to illustrate the conversion process and circuit construction of the present application from a three-qubit stabilizer state to a graph state:

[0175] A1, the conversion process from the stabilizer state to the graph state:

[0176] The initial form of the check matrix is:

[0177] The check matrix of the converted graph state is obtained by operating The check matrix of the converted graph state is: , the conversion operation In order, rowsum(0,1), rowuswap(1,2), H(2), rowsum(2,1), rowsum(2,0), S(0), Z(0), Z(1), Z(2).

[0178] B1, the conversion process from stabilizer state to graph state:

[0179] Graph state preparation circuit : apply H gate to all qubits, prepare state; according to the adjacency matrix Add CZ(0,1), CZ(0,2).

[0180] Stabilizer state reduction circuit : according to the column operation H(2), S(0), Z(0), Z(1), Z(2) in , add its inverse circuit, that is .

[0181] Total circuit: , see Figure 2 .

[0182] Next, the present application takes a set of generators as an example to illustrate the conversion process and circuit construction of the present application from four-qubit stabilizer state to graph state:

[0183] B1, the conversion process from stabilizer state to graph state:

[0184] The initial form of the check matrix is:

[0185] The check matrix converted to graph state: through the operation The check matrix converted to graph state: , the conversion operation In order, rowsum(0,1), rowuswap(1,2), rowusum(1,3), H(2), H(3), rowsum(3,1), rowsum(2,1), rowsum(2,0), S(0), Z(0), S(1), Z(1), Z(3).

[0186] B2, the construction of the total circuit:

[0187] Graph state preparation circuit : apply H gate to all qubits, prepare state; according to the adjacency matrix Add CZ(0,1), CZ(0,2), CZ(1,3).

[0188] Stabilizer state reduction circuit : according to The column operations H(2), H(3), S(0), Z(0), S(1), Z(1), and Z(3) in the above formula are added with inverse circuits, that is, .

[0189] The total circuit is: , see Figure 3 .

[0190] In addition, the application also provides a preparation system of a graph-based stabilizer state, as shown in Figure 4 The preparation system of the graph-based stabilizer state comprises a preprocessing module 10, an initialization module 20, a transformation module 30, a graph state preparation circuit construction module 40, a stabilizer state reduction circuit construction module 50, a total circuit construction module 60, and a stabilizer state preparation module 70.

[0191] The preprocessing module 10 is used to acquire and preprocess a stabilizer generator to obtain a complete stabilizer generator.

[0192] The initialization module 20 is used to generate an initial check matrix according to the complete stabilizer generator.

[0193] The transformation module 30 is used to convert the initial check matrix into a check matrix of a graph state and record a conversion operation performed in the conversion process.

[0194] The graph state preparation circuit construction module 40 is used to construct a graph state preparation circuit according to the check matrix of the graph state.

[0195] The stabilizer state reduction circuit construction module 50 is used to construct a stabilizer state reduction circuit according to the conversion operation.

[0196] The total circuit construction module 60 is used to combine the graph state preparation circuit and the stabilizer state reduction circuit into a total circuit.

[0197] The stabilizer state preparation module 70 is used to acquire an initial quantum state and make the initial quantum state execute the total circuit to obtain a stabilizer state.

[0198] The initial check matrix is composed of a Z matrix, an X matrix, and a phase pointer array, the check matrix of the graph state is characterized in that the X matrix is a unit matrix, and the quantum bits in the initial quantum state are all in state.

[0199] Other specific embodiments of the preparation system of the graph-based stabilizer state of the application can refer to the specific embodiments of the preparation method of the graph-based stabilizer state of the application described above.

[0200] The preparation system of the stable substate based on the graph state of the embodiment of the application takes the graph state as an intermediary, reduces the complexity of circuit design, thereby reducing the complexity of calculation, improving the efficiency of quantum information processing, and making the application adapt to a large-scale quantum system. And through the accurate mapping relationship between the stable substate and the graph state, the appearance of approximate error is avoided, so that the theoretical fidelity reaches 100%. At the same time, through the preprocessing of the stable substate generating element, the accuracy and reliability of the stable substate preparation are improved.

[0201] The following will be described in detail taking a computer terminal as an example. Figure 5 A hardware structure block diagram of a computer terminal of a preparation method of a stable substate based on a graph state provided by the embodiment of the application is shown in the figure. Figure 5 As shown in the figure, the computer terminal can include one or more (only one is shown in the figure) processors 501 (the processor 501 can include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 502 for storing data. Optionally, the above computer terminal can also include a transmission device 503 for communication function and an input and output device 504. Those skilled in the art can understand that the structure shown in the figure is only schematic, which does not limit the structure of the above computer terminal. For example, the computer terminal can also include more or fewer components than those shown in the figure, or have a different configuration from that shown in the figure. Figure 5 Figure 5 Figure 5 Figure 5

[0202] The memory 502 can be used to store software programs and modules of application software, such as program instructions / modules corresponding to the preparation method of the stable substate based on the graph state in the embodiment of the application. The processor 501 performs various functional applications and data processing by running the software programs and modules stored in the memory 502, that is, implements the above method. The memory 502 can include a high-speed random access memory, and can also include a non-volatile memory such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 502 can further include a memory remotely arranged with respect to the processor 501, which can be connected to the computer terminal through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0203] ​​​​The transmission device 503 is configured to receive or send data via a network. The network can include a wireless network provided by a communication provider of a computer terminal. In an example, the transmission device 503 includes a network interface controller (NIC) that can be connected to other network devices through a base station to communicate with the Internet. In an example, the transmission device 503 can be a radio frequency (RF) module configured to communicate with the Internet in a wireless manner. Embodiments of the present disclosure also provide a computer readable storage medium storing a computer program for electronic data exchange, where the computer program is configured to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments, and the computer includes an electronic device.

[0204] Embodiments of the present disclosure also provide a computer program product including a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. The computer program product can be a software installation package, and the computer includes an electronic device.

[0205] Although the example embodiments have been described with reference to the accompanying drawings, it is to be understood that the example embodiments are only exemplary and are not intended to limit the scope of the present disclosure. Those of ordinary skill in the art can make various changes and modifications without departing from the scope and spirit of the present disclosure. All such changes and modifications are intended to be included within the scope of the present disclosure as claimed in the appended claims.

[0206] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be realized by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0207] In several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another device, or some features can be omitted or not executed.

[0208] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0209] Similarly, it is to be understood that the various features of the application can sometimes be used to advantage together, while at other times they can not be used to advantage together. It is therefore contemplated that the application can be practiced or carried out in other ways than is explicitly shown and described herein.

[0210] One skilled in the art will appreciate that, aside from specific features being mutually exclusive, all of the features disclosed in this specification (including the claims, abstract, and drawings) and all of the processes or steps (or equivalents thereof) of any method or of any device disclosed in this specification can be combined in any combination, except where such combinations are mutually exclusive. Each of the features disclosed in this specification (including the claims, abstract, and drawings) can be replaced by alternative features serving the same, equivalent, or similar purpose, unless otherwise expressly stated.

[0211] Furthermore, those skilled in the art will recognize that references in the specification to "one embodiment", "an embodiment", "an example embodiment", etc., mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, where a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the purview of one skilled in the art to effect such particular feature, structure, or characteristic in connection with other embodiments whether or not explicit reference is made to that particular feature, structure, or characteristic. Additionally, it is within the purview of one skilled in the art to make major or minor changes or alterations with respect to the application described herein, and changes in the order of steps or stages described herein. Where compositions are described as having, including, or comprising, various components, it is intended that the compositions can also consist exactly of, or consist essentially of, unless otherwise explicitly provided.

[0212] Embodiments of various components of the application can be implemented in hardware, software, or a combination thereof. Those skilled in the art will appreciate that some or all of the functionality of some of the modules according to embodiments of the application can be implemented using a microprocessor or a digital signal processor (DSP) in practice. The application can also be implemented as a program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. A program embodying the application can be stored on a computer-readable medium, or can have one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier medium, or in any other form.

[0213] It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that one skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of both hardware and software, and any combination thereof. In a unitary claim, several devices or sub-claims can be joined by means of the expression "and / or". The use of the term "at least" followed by a list of one or more items should be interpreted as including at least one of the items but it does not exclude the presence of others not listed. The use of the term "one" followed by a list of one or more items should be interpreted as including at least one of the items but it does not exclude the presence of others not listed. It is emphasized that the terms "comprises / comprising" when used in this specification are taken to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0214] The above description is only specific embodiments of the present application or specific explanations of specific embodiments, and the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, and all of them should be covered in the protection scope of the present application. The protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for preparing a graph state based stabilizer state, characterized by, The preparation method comprises: obtaining and preprocessing stabilizer generators to obtain complete stabilizer generators; generating an initial check matrix according to the complete stabilizer generators; converting the initial check matrix into a check matrix of a graph state and recording conversion operations performed in the conversion process; constructing a graph state preparation circuit according to the check matrix of the graph state; constructing a stabilizer state reduction circuit according to the conversion operations; combining the graph state preparation circuit and the stabilizer state reduction circuit into a total circuit; obtaining an initial quantum state and making the initial quantum state execute the total circuit to obtain a stabilizer state; the step of combining the graph state preparation circuit and the stabilizer state reduction circuit into a total circuit comprises: constructing an inverse circuit of the graph state preparation circuit to obtain a first inverse circuit; constructing an inverse circuit of the stabilizer state reduction circuit to obtain a second inverse circuit; serially connecting the first inverse circuit and the second inverse circuit in sequence to obtain the total circuit; the step of obtaining and preprocessing stabilizer generators comprises: determining whether the number of the stabilizer generators is equal to the number of quantum bits in the stabilizer state to be prepared; if yes, taking the stabilizer generators as the complete stabilizer generators; if no, padding the stabilizer generators to obtain the complete stabilizer generators; The initial check matrix is composed of a Z matrix, an X matrix and a phase pointer array, the feature of the check matrix of the graph state is that the X matrix is a unit matrix, and the quantum bits in the initialized quantum state are all in state.

2. The method of claim 1, wherein the graph state is a 4x4 graph state. the step of converting the initial check matrix into a check matrix of a graph state comprises: converting the X matrix into an upper triangular matrix or a lower triangular matrix, and converting the upper triangular matrix or the lower triangular matrix into the unit matrix; setting the diagonal line of the Z matrix to zero; setting all the phase exponents to zero.

3. The method of claim 2, wherein the graph state is a Dicke state. the step of converting the X matrix into an upper triangular matrix comprises: traversing the X matrix by row, determining whether equal to 1; If and then by making ; If and then by making 1 and returning to the step of determining whether the value is equal to 1. If and not then execute the gate, and return to the step of determining whether it is equal to 1; the step of converting the upper triangular matrix into the unit matrix comprises: traversing the upper triangular matrix by row, determining whether it is equal to 1; like Then through ,Will Set to 0; the step of setting the diagonal line of the Z matrix to zero comprises: traversing the Z matrix by row, determining whether equal to 1; If then execute the AND gate to set the output to 0; the step of setting all the phase exponents to zero comprises: traversing the phase index by row, determining whether it is 1; If then execute the gate, setting the output to 0; comprising: determining the phase exponent of the jth row through the following formula: ； The first XOR to the first Line up; The comprising: the first column of the exchange matrix the first row of the exchange matrix the second row of the exchange matrix The execution The steps of the door include: updating the phase exponent of the ith row in sequence through the following formula: ； swapping the a th column of the Z matrix with the a th column of the X matrix; The execution The steps of the door include: updating the phase exponent of the ith row in sequence through the following formula: ； The matrix elements are updated in turn by the following equation : ； The execution The steps of the door include: updating the phase exponent of the ith row in sequence through the following formula: ； wherein, represents an H gate on the a-th qubit, represents an S gate on the a-th qubit, represents a Z gate on the a-th qubit, represents the a-th phase index, represents the i-th row, j-th column element of the X matrix, represents the i-th row, j-th column element of the Z matrix, represents the i-th phase index, , , , , n represents the number of qubits.

4. The method of claim 1, wherein the graph state is a 4x4 graph state. the step of constructing a graph state preparation circuit according to the check matrix of the graph state comprises: independently applying an H gate to each quantum bit; applying a CZ gate according to an adjacency matrix in the check matrix of the graph state to obtain the graph state preparation circuit.

5. The method of claim 3, wherein the graph state is a 4x4 graph state. The conversion operations include: , , H gates, S gates, and Z gates; the step of constructing a stabilizer state reduction circuit according to the conversion operations comprises: performing inverse operation combination of H gates, S gates and Z gates in the conversion operations in reverse order to generate the stabilizer state reduction circuit.

6. A system for preparing a graph-based stabilizer state, the system comprising: the system comprises: a preprocessing module configured to obtain and preprocess stabilizer generators to obtain complete stabilizer generators; an initialization module configured to generate an initial check matrix according to the complete stabilizer generators; a transformation module configured to convert the initial check matrix into a check matrix of a graph state and record conversion operations performed in the conversion process; a graph state preparation circuit construction module configured to construct a graph state preparation circuit according to the check matrix of the graph state; The stable subspace reduction circuit construction module is configured to construct a stable subspace reduction circuit according to the conversion operation; The total circuit construction module is configured to combine the graph state preparation circuit and the stable subspace reduction circuit into a total circuit; The stable subspace preparation module is configured to obtain an initial quantum state, and make the initial quantum state execute the total circuit to obtain a stable subspace; The total circuit construction module is configured to, when combining the graph state preparation circuit and the stable subspace reduction circuit into a total circuit: construct an inverse circuit of the graph state preparation circuit to obtain a first inverse circuit; construct an inverse circuit of the stable subspace reduction circuit to obtain a second inverse circuit; serially connect the first inverse circuit and the second inverse circuit in sequence to obtain the total circuit; The preprocessing module is configured to, when obtaining and preprocessing the stable subspace generator: determine whether the number of the stable subspace generators is equal to the number of quantum bits in the stable subspace to be prepared; if yes, take the stable subspace generators as the complete stable subspace generators; if no, pad the stable subspace generators to obtain the complete stable subspace generators; The initial check matrix is composed of a Z matrix, an X matrix and a phase pointer array, the feature of the check matrix of the graph state is that the X matrix is a unit matrix, and the quantum bits in the initialized quantum state are all in state.

7. An electronic device comprising a memory, a processor, and a computer program stored on the memory, characterized in that, The computer program, when executed by the processor, implements the preparation method of a stable subspace based on a graph state according to any one of claims 1-5.

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