Driving chip and display panel

Abstract

The invention provides a driving chip and a display panel. The driving chip comprises a first output end, a second output end, a third output end, a control module (comprising a time sequence control unit or a source electrode driving unit), a level conversion module used for generating a second signal, and a signal processing module used for processing the second signal at least according to the first signal to generate a third signal (comprising a first sub-signal and a second sub-signal), in at least one frame, the first output end is used for outputting a first sub-signal, the second output end is used for outputting a second sub-signal, in at least another frame, the first output end is used for outputting the second sub-signal, the second output end is used for outputting the first sub-signal, and / or the signal processing module is used for generating a fourth signal according to the first signal; and the third output end is used for outputting a fourth signal, so that lower cost and higher flexibility are both considered.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to driver chips and display panels. Background Technology

[0002] Due to the high integration requirements of laptop products, timing controllers, level shifters and source controllers are usually integrated on a single chip. However, this limits the types of devices the chip can be used in. If a separate design is adopted, although the chip is more flexible, the manufacturing cost is higher. Summary of the Invention

[0003] This invention provides a driver chip and a display panel to solve the technical problem that existing notebook products cannot simultaneously achieve low cost and high flexibility.

[0004] This invention provides a driver chip for use in a display panel, including a first output terminal, a second output terminal, and a third output terminal, comprising:

[0005] The control module includes a timing control unit or a source drive unit;

[0006] Level conversion module, used to generate a second signal;

[0007] A signal processing module is configured to process the second signal based on at least a first signal to generate a third signal, the third signal including a first sub-signal and a second sub-signal;

[0008] In at least one frame, the first output terminal is used to output the first sub-signal, and the second output terminal is used to output the second sub-signal; in at least another frame, the first output terminal is used to output the second sub-signal, and the second output terminal is used to output the first sub-signal.

[0009] And / or, the signal processing module is used to generate a fourth signal based on the first signal, and the third output terminal is used to output the fourth signal.

[0010] In some embodiments, the control module includes the timing control unit, which is used to generate a fifth signal, and the level conversion module is used to generate the second signal based on the fifth signal.

[0011] In some embodiments, the control module further includes a microcontroller unit for generating the first signal.

[0012] In some embodiments, the first signal includes:

[0013] A control signal, wherein the signal processing module is configured to process the second signal according to at least the control signal to generate the third signal;

[0014] And / or, an information signal, wherein the signal processing module is used to generate the fourth signal based on the information signal.

[0015] In some embodiments, within at least one frame, the first output terminal is used to output the first sub-signal, and the second output terminal is used to output the second sub-signal; within at least one frame, the first output terminal is used to output the second sub-signal, and the second output terminal is used to output the first sub-signal.

[0016] The signal processing module includes:

[0017] A signal transmission unit is configured to receive the second signal and transmit the second signal.

[0018] A signal output unit is configured to receive the control signal and the second signal output by the signal transmission unit, and process the second signal according to the control signal to generate the third signal.

[0019] In some embodiments, the second signal includes a first sub-transmitted signal corresponding to the first sub-signal and a second sub-transmitted signal corresponding to the second sub-signal;

[0020] The signal output unit includes a first data selection subunit and a second data selection subunit;

[0021] The first input terminal of the first data selection subunit and the first input terminal of the second data selection subunit are both used to load the first sub-transmitted signal;

[0022] Both the second input terminal of the first data selection subunit and the second input terminal of the second data selection subunit are used to load the second sub-transmitted signal.

[0023] Both the control terminal of the first data selection subunit and the control terminal of the second data selection subunit are used to load the control signal.

[0024] The output terminal of the first data selection subunit is electrically connected to the first output terminal, and the output terminal of the second data selection subunit is electrically connected to the second output terminal;

[0025] Within each frame, both the first data selection subunit and the second data selection subunit are used to output the first sub-signal or the second sub-signal according to the control signal.

[0026] In some embodiments, the signal processing module is further configured to generate the fourth signal based on the first signal;

[0027] The signal processing module includes:

[0028] A signal transmission unit is used to receive the information signal and output the information signal as the fourth signal.

[0029] In some embodiments, the second signal includes a first clock signal corresponding to the first sub-signal and a second clock signal corresponding to the second sub-signal, wherein the first clock signal includes a first clock pulse and the second clock signal includes a second clock pulse;

[0030] There is a time interval between the first pulse in the first sub-signal corresponding to the first clock pulse and the second pulse in the second sub-signal corresponding to the second clock pulse.

[0031] This invention provides a display panel, including:

[0032] The main panel consists of multiple sub-pixels;

[0033] The driving chip described above is used to drive the plurality of sub-pixels to emit light.

[0034] In some embodiments, the control module includes the source driving unit, and the timing control unit is set independently of the control module. The timing control unit is used to drive the source driving unit so that the source driving unit transmits a corresponding data voltage to each sub-pixel to control the corresponding sub-pixel to emit light.

[0035] This invention provides a driver chip and a display panel. By integrating the control module and the level conversion module, the cost of the driver chip is reduced. A signal processing module is added to process a second signal based on a first signal to generate a third signal that can be output with different content replacement in different frames. And / or, the signal processing module is also used to generate a fourth signal based on the first signal for output, thereby improving the flexibility of the types and order of output signals of the driver chip. Attached Figure Description

[0036] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for illustrating some embodiments of the present invention. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0037] Figure 1 This is an internal architecture diagram of the driver chip provided in an embodiment of the present invention.

[0038] Figure 2 and Figure 3 A module diagram of a driver chip provided in an embodiment of the present invention.

[0039] Figure 4The waveform diagram shows some signals of the driver chip provided in the embodiment of the present invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0041] The terms "first," "second," etc., used in this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or apparatuses.

[0042] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0043] This invention provides a driver chip for use in a display panel. The driver chip includes, but is not limited to, the following embodiments and combinations thereof.

[0044] In some embodiments, such as Figures 1 to 3 As shown, the driver chip 100 includes a first output terminal out1, a second output terminal out2, and a third output terminal out3, and includes: a control module 10, including a timing control unit 101 (reference). Figure 1 and Figure 2 ) or source drive unit 102 (reference) Figure 3The signal processing module 20 is configured to generate a second signal S2; the signal processing module 30 is configured to process the second signal S2 according to at least the first signal S1 to generate a third signal S3, wherein the third signal S3 includes a first sub-signal S31 and a second sub-signal S32; wherein, in at least one frame, the first output terminal out1 is configured to output the first sub-signal S31 and the second output terminal out2 is configured to output the second sub-signal S32, and in at least another frame, the first output terminal out1 is configured to output the second sub-signal S32 and the second output terminal out2 is configured to output the first sub-signal S31; and / or, the signal processing module 30 is configured to generate a fourth signal S4 according to the first signal S1, and the third output terminal out3 is configured to output the fourth signal S4.

[0045] In this embodiment, the type of display panel used for the driver chip 100 is not limited, and can be, but is not limited to, an organic self-emissive display panel, an inorganic self-emissive direct-view display panel, or a liquid crystal display panel. In this embodiment, the signal processing module 30 is used to receive the first signal S1 and the second signal S2 generated by the level conversion module 20, and to process the second signal S2 according to the first signal S1 to generate a third signal S3. The generated third signal S3 includes a first sub-signal S31 and a second sub-signal S32, and / or, the signal processing module 30 is also used to generate a fourth signal S4 according to the first signal S1, meaning that the generation of the fourth signal S4 can be independent of the second signal S2.

[0046] Specifically, when the signal processing module 30 is used to generate the third signal S3, the first sub-signal S31 can be output through the first output terminal out1 and the second output terminal out2 of the driver chip 100 in at least two different frames. Correspondingly, the second sub-signal S32 can be output through the second output terminal out2 and the first output terminal out1 of the driver chip 100 in at least two different frames. That is, the first output terminal out1 and the second output terminal out2 can be used to output different signals in different frames to improve the flexibility of the signals output by the output terminal of the driver chip 100. When the signal processing module 30 is used to generate the fourth signal S4, it can be considered that it can also output signals that are not generated according to the second signal S2 to increase the variety of signals output by the output terminal of the driver chip 100.

[0047] Understandably, in this embodiment, the control module 10 and the level conversion module 20 are integrated, which can reduce the cost of the driver chip 100 while having more output terminals and increasing the capacity to accommodate different types of output signals. At the same time, a signal processing module 30 is added to generate a third signal S3 with multiple sub-signals based on the second signal S2 generated by the level conversion module 20, and / or to generate a fourth signal S4 based on the first signal S1, thereby improving the flexibility of the driver chip 100.

[0048] In some embodiments, combined with Figure 1 and Figure 4 As shown, the second signal S2 includes a first clock signal CK1 corresponding to the first sub-signal S31 and a second clock signal CK2 corresponding to the second sub-signal S32. The first clock signal CK1 includes a first clock pulse p1, and the second clock signal CK2 includes a second clock pulse p2. There is a time interval between the first pulse in the first sub-signal S31 corresponding to the first clock pulse p1 and the second pulse in the second sub-signal S32 corresponding to the second clock pulse p2.

[0049] Specifically, the level conversion module 20 in the driver chip 100 can be used to generate multiple clock signals (at least including a first clock signal CK1 and a second clock signal CK2) acting on the gate drivers in the corresponding display panel. Each clock signal includes multiple clock pulses (e.g., p1, p9 in CK1, p2, p10 in CK2, etc.). Each clock pulse in each clock signal (e.g., each of p1, p9 in CK1, p2, p10 in CK2, etc.) is used to control the corresponding row of sub-pixels to turn on. The multiple clock pulses in each clock signal can be used to drive the corresponding multiple gate driving units to generate multiple gate pulses. The start signal STV is used to control the multiple gate driving units in the gate driver to send gate pulses to sequentially turn on multiple rows of sub-pixels. Figure 4 The following example illustrates the concept of 8 clock signals CK1 to CK8, with 2160 rows of sub-pixels:

[0050] Within a frame, such as Figure 4As shown in (a), the first clock pulses p1 to p8 of CK1 to CK8 are used to drive the first to eighth level gate driving units to generate their respective gate pulses in sequence, thereby turning on the first to eighth rows of sub-pixels in sequence. The second clock pulses p9 to p16 of CK1 to CK8 are used to drive the ninth to 16th level gate driving units to generate their respective gate pulses in sequence, thereby turning on the ninth to 16th rows of sub-pixels in sequence, and so on. The 270th clock pulses p2153 to p2160 of CK1 to CK8 are used to drive the 2153rd to 2160th level gate driving units to generate their respective gate pulses in sequence, thereby turning on the 2153rd to 2160th rows of sub-pixels in sequence. When each row of sub-pixels is turned on, the source driver in the display panel outputs multiple data voltages corresponding to that row of sub-pixels to drive the row of sub-pixels to emit light. It can be considered that during the period from the first row of sub-pixels to the last row of sub-pixels being turned on, the data line connected between the source driver and the corresponding column of sub-pixels sequentially outputs multiple data voltages corresponding to that column of sub-pixels (included in the same data signal Data). That is, the starting point of the effective data pulse pd of the data signal Data needs to be within p1, and the ending point needs to be beyond p2160, so as to ensure that each data voltage can be fully written to the corresponding sub-pixel after each row of sub-pixels is turned on.

[0051] In addition, the 271st clock pulses p2161 to p216i (all virtual clock pulses DUM) in CK1 to CTi (2≤i≤8) are used to drive the gate driving units of the 2161 to 216i levels (these i-level gate driving units are all virtual gate driving units) to generate their respective gate pulses in sequence (not output to the sub-pixels in the plane) to affect the gate driving units of the previous levels.

[0052] Among them, the two clock pulses that overlap in two adjacent clock signals CKj (1≤j≤7) and CK(j+1) (e.g., the first clock pulse p1 in the first clock signal CK1 and the second clock pulse p2 in the second clock signal CK2) have a time interval. Specifically, each pair of adjacent signals from p1 to p8, each pair of adjacent signals from p9 to p16, and each pair of adjacent signals from p2153 to p2160 are overlapped, and the pulse widths are equal and there is a time delay.

[0053] Among them, combined Figure 1 and Figure 4As shown in (a), the second signal S2 generated by the level conversion module 20 may include CK1 to CK8 here. The signal processing module 30 is used to process the second signal S2 (CK1 to CK8) according to at least the first signal S1 to generate a third signal S3. The third signal S3 includes the first sub-signal S31 (obtained by processing CK1), the second sub-signal S32 (obtained by processing CK2), the third sub-signal S33 (obtained by processing CK3) up to the eighth sub-signal S38 (not shown in the figure, obtained by processing CK8), which causes a time interval between the first pulse in S31 (which may also be the same as CK1) corresponding to the first clock pulse p1 and the second pulse in S32 (which may also be the same as CK2) corresponding to the second clock pulse p2. Similarly, it can be considered that S33 to S38 in this frame are sequentially the same as CK3 to CK8.

[0054] Based on the previous discussion, in another frame, such as Figure 4 As shown in (b), with Figure 4 The difference in (a) is that in the third signal S3 generated by the signal processing module 30 after processing the second signal S2 (CK1 to CK8) according to the first signal S1, D S3m (m = 1, 3, 5 or 7) and S3(m+1) can be obtained by exchanging the content of the aforementioned "frame". That is, in this frame, S31 and S32 have been exchanged to CK2 and CK1 respectively, S33 and S34 have been exchanged to CK4 and CK3 respectively, S35 and S36 have been exchanged to CK6 and CK5 respectively, and S37 and S38 have been exchanged to CK8 and CK7 respectively. Correspondingly, taking the first 8 rows of sub-pixels in this frame as an example, the order in which the sub-pixels are turned on is the 2nd, 1st, 4th, 3rd, 6th, 5th, 8th and 7th rows of sub-pixels, which are turned on by p1 to p8 respectively. Similarly, the order in which the sub-pixels are turned on in subsequent rows and the working order of some multi-level gate driving units that require the action of the virtual clock pulse DUM will also be changed according to the content transformation of multiple sub-signals in the third signal S3.

[0055] In some embodiments, such as Figure 1 and Figure 2As shown, the control module 10 includes a timing control unit 101, which generates a fifth signal S5. The level conversion module 20 generates a second signal S2 based on the fifth signal S5. The number of sub-signals in the fifth signal S5 can be less than or equal to the number of sub-signals in the second signal S2. For example, the fifth signal S5 may include two sub-signals, both of which are clock signals. The level conversion module 20 can generate multiple second signals S2, each including multiple sub-signals (e.g., CK1 to CK8), based on the two sub-signals in the fifth signal S5. When the number of sub-signals in the fifth signal S5 is the same as the number of sub-signals in the second signal S2, it can be considered that the pulse distribution in each sub-signal of the fifth signal S5 is the same as the pulse distribution of the corresponding sub-signal in the second signal S2, the difference being the amplitude. That is, the level conversion module 20 can change the amplitude of the pulses.

[0056] In some embodiments, such as Figures 1 to 4 As shown, in addition to the timing control unit 101, the control module 10 also includes a microcontroller 103, which generates the first signal S1. The microcontroller 103 can be a single-chip microcomputer or a microcontroller, which integrates peripheral interfaces such as memory, counters, USB, A / D converter, UART, PLC, and DMA onto a single chip, forming a chip-level computer. The microcontroller 103 can also communicate with the timing control unit 101 of the display panel and generate the first signal S1, transmitting it to the signal processing module 30.

[0057] Specifically, such as Figure 1 As shown, the first signal S1 includes: a control signal Sc, which the signal processing module 30 processes at least the control signal Sc to generate the second signal S2 to generate the third signal S3; and / or an information signal Si, which the signal processing module 30 generates the fourth signal S4 (different from the fifth signal S5) based on the information signal Si. That is, the first signal S1 generated by the microcontroller unit 103 may include at least one of the control signal Sc and the information signal Si to generate at least one of the third signal S3, which can have different outputs in different frames, and the fourth signal S4, which is independent of the fifth signal S5.

[0058] Specifically, when, within at least one frame, the first output terminal out1 is used to output the first sub-signal S31, and the second output terminal out2 is used to output the second sub-signal S32; and within at least one frame, the first output terminal out1 is used to output the second sub-signal S32, and the second output terminal out2 is used to output the first sub-signal S31; the signal processing module 30 includes: a signal transmission unit 308, used to receive and transmit the second signal S2; and a signal output unit 309, used to receive the control signal Sc and the second signal S2 output by the signal transmission unit 308, and to process the second signal S2 according to the control signal Sc to generate the third signal S3. As discussed above, the signal transmission unit 308 can function as a transmitter of the second signal S2, and the signal output unit 309 processes the second signal S2 according to the control signal Sc to generate the third signal S3. Here, the control signal Sc can be used to achieve "outputting a third signal S3 with different outputs in different frames".

[0059] Specifically, such as Figure 1 As shown, the second signal S2 includes a first sub-transmitted signal corresponding to the first sub-signal S31 (e.g., CK1 as described above) and a second sub-transmitted signal corresponding to the second sub-signal S32 (e.g., CK2 as described above); the signal output unit 309 includes a first data selection subunit 301 and a second data selection subunit 302; the first input terminal of the first data selection subunit 301 and the first input terminal of the second data selection subunit 302 are both used to load the first sub-transmitted signal; the second input terminal of the first data selection subunit 301 and the second input terminal of the second data selection subunit 302 are both used to load the first sub-transmitted signal; The input terminals are both used to load the second sub-transmitted signal; the control terminals of the first data selection subunit 301 and the second data selection subunit 302 are both used to load the control signal Sc; the output terminal of the first data selection subunit 301 is electrically connected to the first output terminal out1, and the output terminal of the second data selection subunit 302 is electrically connected to the second output terminal out2; wherein, in each frame, the first data selection subunit 301 and the second data selection subunit 302 are both used to output the first sub-signal S31 or the second sub-signal S32 according to the control signal Sc.

[0060] Understandably, in this embodiment, by setting at least a first data selection subunit 301 and a second data selection subunit 302, both of which are loaded with a first sub-transmitted signal (e.g., CK1 as mentioned above) and a second sub-transmitted signal (e.g., CK2 as mentioned above) generated by the level conversion module 20, and are controlled by the control signal Sc in the first signal S1 generated by the microcontroller unit 103, so as to control one of them to output one of the first sub-signal S31 and the second sub-signal S32 in each frame, and the other to output the other of the first sub-signal S31 and the second sub-signal S32, and at least in two frames, the contents output by the first data selection subunit 301 and the second data selection subunit 302 are exchanged.

[0061] Similarly, CK3 and CK4 can also be loaded into both data selection subunits to achieve alternating output of the corresponding two outputs within two frames. CK5, CK6, CK7, and CK8 can all be set in the same way. Of course, it can also be done as follows: Figure 1 As shown, the four input terminals of each of the first data selection subunit 301, the second data selection subunit 302, the third data selection subunit 303, and the fourth data selection subunit (not shown) can be loaded with CK1 to CK4 respectively. In each frame, the four can be controlled by the control signal Sc, and each outputs one of CK1 to CK4 as the corresponding sub-signal in the third signal S3. The output signal of each is different, and the output of the four data selection subunits is different in the four frames, thereby realizing the exchange of output of CK1 to CK4 in different frames to form a third signal S3 with different content in different frames.

[0062] Furthermore, a data buffer can be set between each data selection subunit (e.g., one of the first data selection subunit 301, the second data selection subunit 302, the third data selection subunit 303, etc.) and the corresponding output terminal in the driver chip 100 (e.g., one of the first output terminal out1, the second output terminal out2, the third output terminal out3, etc.) to perform processing such as amplification on the signal output by the data selection subunit. In this case, the amplitude of each sub-signal (belonging to the third signal S3) output by the output terminal of the driver chip 100 may differ from the amplitude of the sub-signal in the corresponding second signal S2.

[0063] Among them, such as Figure 1As shown, when the signal processing module 30 is further configured to generate the fourth signal S4 based on the first signal S1, the signal processing module 30 includes: the aforementioned signal transmission unit 308, configured to receive the information signal Si and output the information signal Si to generate the fourth signal S4. As discussed above, the signal transmission unit 308 can also function as a transmitter of the information signal Si. In this case, the information signal Si can be directly output as the corresponding fourth signal S4, or the signal output unit 309 can be configured to process the information signal Si based on the control signal Sc to generate the fourth signal S4 (refer to the discussion above regarding the generation of the third signal S3 based on the control signal Sc).

[0064] In this embodiment, it can be considered that... Figure 4 The frame start signal STV is set to include a first frame start signal STV1 and a second frame start signal STV2. The information signal Si may include the first frame start signal STV1, the second frame start signal STV2, a first oscillation signal LS1, and a second oscillation signal LS2. One of the first frame start signal STV1 and the second frame start signal STV2 can be understood as a newly added signal compared to the other. Similarly, one of the first oscillation signal LS1 and the second oscillation signal LS2 can be understood as a newly added signal compared to the other.

[0065] Understandably, depending on the design requirements of the gate drivers of different display panels, the driver chip 100 has a large number of output terminals. Therefore, the driver chip 100 can be set to output at least one of the first frame start signal STV1 and the second frame start signal STV2, as well as at least one of the first oscillation signal LS1 and the second oscillation signal LS2, thereby improving the flexibility of the application scenarios of the driver chip 100.

[0066] Furthermore, such as Figure 1 As shown, the level conversion module 20 may include a signal generation module 201 and a power-saving module 202. The signal generation module 201 is used to generate multiple clock signals (e.g., CK1 to CK8 mentioned above). The power-saving module 202 is used to control the multiple clock signals not to be output during the frame blanking of each frame, thereby preventing the multi-level gate driving unit from working and reducing the power consumption of the display panel. During the frame blanking of each frame, the microcontroller unit 103 may be used to output a control signal Sc to be transmitted to the signal processing module 30, so as to control the signal processing module 30 to output the corresponding third signal S3 in the next frame to drive the gate driver of the display panel to work.

[0067] This invention also provides a display panel, comprising: a panel body including a plurality of sub-pixels (refer to the relevant discussion above); and a driving chip as described in any of the above descriptions, for driving the plurality of sub-pixels to emit light. The driving chip can be referenced in the relevant discussion above.

[0068] Specifically, such as Figure 1 and Figure 2 As shown, the control module 10 includes the timing control unit 101, which is used to generate a fifth signal S5, and the level conversion module 20 is used to generate a second signal S2 based on the fifth signal S5; or, as shown... Figure 3 As shown, the control module 10 includes the source drive unit 102, and the timing control unit 101 is set independently of the control module 10. The timing control unit 101 is used to drive the source drive unit 102 so that the source drive unit 102 transmits the corresponding data voltage to each sub-pixel to control the corresponding sub-pixel to emit light.

[0069] In the case where the control module 10 includes a timing control unit 101, please refer to the relevant description above. In this case, the timing control unit 101 in the driver chip 100 can control the source driving unit 102 and the gate driver in the display panel to operate, so as to control the activation and light emission of the sub-pixels. In the case where the control module 10 includes a source driving unit 102, compare... Figure 1 and Figure 3 As shown, the microcontroller unit 103 is not integrated into the control module 10 at this time. It can be assumed that the microcontroller unit 103 is generally integrated with the timing control unit 101. Therefore, in this embodiment, the timing control unit 101 and the microcontroller unit 103 in the display panel can provide the driver chip 100 with the required fifth signal S5 and first signal S1 to assist the driver chip 100 in realizing the above functions. Of course, at this time, the source driving unit 102 in the driver chip 100 can also be controlled by the timing control unit 101 in the display panel to drive the sub-pixels in the surface to emit light.

[0070] In this context, regardless of whether the control module 10 includes a timing control unit 101 or a source drive unit 102, the number of level conversion modules 20 and signal processing modules 30 in the drive chip 100 are not limited, and the two can be the same or different.

[0071] This invention provides a driver chip and a display panel. By integrating the control module and the level conversion module, the cost of the driver chip is reduced. A signal processing module is added to process a second signal based on a first signal to generate a third signal that can be output with different content replacement in different frames. And / or, the signal processing module is also used to generate a fourth signal based on the first signal for output, thereby improving the flexibility of the types and order of output signals of the driver chip.

[0072] The driving chip and display panel provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A driver chip, used in a display panel, characterized in that, Including a first output terminal, a second output terminal, and a third output terminal, including: The control module includes a timing control unit or a source drive unit; Level conversion module, used to generate a second signal; A signal processing module is configured to process the second signal based on at least a first signal to generate a third signal, the third signal including a first sub-signal and a second sub-signal; In at least one frame, the first output terminal is used to output the first sub-signal, and the second output terminal is used to output the second sub-signal; in at least another frame, the first output terminal is used to output the second sub-signal, and the second output terminal is used to output the first sub-signal. And / or, the signal processing module is used to generate a fourth signal based on the first signal, and the third output terminal is used to output the fourth signal.

2. The driver chip according to claim 1, characterized in that, The control module includes the timing control unit, which is used to generate a fifth signal, and the level conversion module is used to generate a second signal based on the fifth signal.

3. The driver chip according to claim 2, characterized in that, The control module further includes a microcontroller unit, which is used to generate the first signal.

4. The driver chip according to claim 1, characterized in that, The first signal includes: A control signal, wherein the signal processing module is configured to process the second signal according to at least the control signal to generate the third signal; And / or, an information signal, wherein the signal processing module is used to generate the fourth signal based on the information signal.

5. The driver chip according to claim 4, characterized in that, Within at least one frame, the first output terminal is used to output the first sub-signal, and the second output terminal is used to output the second sub-signal. Within at least one frame, the first output terminal is used to output the second sub-signal, and the second output terminal is used to output the first sub-signal. The signal processing module includes: A signal transmission unit is configured to receive the second signal and transmit the second signal. A signal output unit is configured to receive the control signal and the second signal output by the signal transmission unit, and process the second signal according to the control signal to generate the third signal.

6. The driver chip according to claim 5, characterized in that, The second signal includes a first sub-transmitted signal corresponding to the first sub-signal and a second sub-transmitted signal corresponding to the second sub-signal; The signal output unit includes a first data selection subunit and a second data selection subunit; The first input terminal of the first data selection subunit and the first input terminal of the second data selection subunit are both used to load the first sub-transmitted signal; Both the second input terminal of the first data selection subunit and the second input terminal of the second data selection subunit are used to load the second sub-transmitted signal. Both the control terminal of the first data selection subunit and the control terminal of the second data selection subunit are used to load the control signal. The output terminal of the first data selection subunit is electrically connected to the first output terminal, and the output terminal of the second data selection subunit is electrically connected to the second output terminal; Within each frame, both the first data selection subunit and the second data selection subunit are used to output the first sub-signal or the second sub-signal according to the control signal.

7. The driver chip according to claim 4, characterized in that, The signal processing module is further configured to generate the fourth signal based on the first signal; The signal processing module includes: A signal transmission unit is used to receive the information signal and output the information signal as the fourth signal.

8. The driver chip according to any one of claims 1 to 6, characterized in that, The second signal includes a first clock signal corresponding to the first sub-signal and a second clock signal corresponding to the second sub-signal. The first clock signal includes a first clock pulse, and the second clock signal includes a second clock pulse. There is a time interval between the first pulse in the first sub-signal corresponding to the first clock pulse and the second pulse in the second sub-signal corresponding to the second clock pulse.

9. A display panel, characterized in that, include: The main panel consists of multiple sub-pixels; The driving chip as described in any one of claims 1 to 8 is used to drive the plurality of said sub-pixels to emit light.

10. The display panel according to claim 9, characterized in that, The control module includes the source drive unit, and the timing control unit is set independently of the control module. The timing control unit is used to drive the source drive unit so that the source drive unit can transmit a corresponding data voltage to each sub-pixel to control the corresponding sub-pixel to emit light.

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