Display panel and display device

Abstract

The invention discloses a pixel circuit, a display panel and a display device, and relates to the technical field of display. The pixel circuit includes a driving transistor (T3), a tank circuit (RU), a write circuit (DU), and a first light emission control circuit (EU1). The grid electrode of the driving transistor (T3) is connected with the first electrode of the driving transistor (T3) through the energy storage circuit (RU), the first electrode of the driving transistor (T3) is used for being connected with a light-emitting device (LD), the second electrode of the driving transistor (T3) is connected with the first light-emitting control circuit (EU1), and the first light-emitting control circuit (EU1) is used for receiving a first power supply signal (VDD); the write circuit is connected with the grid electrode of the driving transistor (T3); the write-in circuit (DU) is connected with the first pole of the driving transistor (T3) through the energy storage circuit (RU); the write-in circuit (DU) is used for writing a data signal (Data) into the energy storage circuit (RU); the tank circuit (RU) is used for storing a data signal (Data) and the voltage of the first pole of the driving transistor (T3).

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (organic light-emitting diode) display panels offer a wide range of applications thanks to their advantages, including self-luminescence, wide color gamut, high contrast, flexibility, and high responsiveness. However, the brightness uniformity of current display panels still needs to be improved, and display anomalies are prone to occur.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device.

[0006] According to one aspect of the present disclosure, there is provided a pixel circuit including a driving transistor, a storage circuit, a writing circuit, and a first light emitting control circuit;

[0007] The gate of the driving transistor is connected to the first electrode of the driving transistor through the energy storage circuit, and the first electrode of the driving transistor is used to be connected to the light-emitting device, and the second electrode of the driving transistor is connected to the first light-emitting control circuit, and the first light-emitting control circuit is used to receive a first power supply signal;

[0008] The write circuit is connected to the gate of the driving transistor; the write circuit is connected to the first electrode of the driving transistor through the energy storage circuit; the write circuit is used to write a data signal to the energy storage circuit; the energy storage circuit is used to store the data signal and the voltage of the first electrode of the driving transistor.

[0009] In an exemplary embodiment of the present disclosure, the energy storage circuit includes a first capacitor and a second capacitor; the write circuit includes a write transistor; the first light emission control circuit includes a first light emission control transistor;

[0010] The first electrode of the write transistor is used to input the data signal, and the second electrode of the write transistor is connected to the gate of the driving transistor and the first plate of the first capacitor; the second plate of the first capacitor is connected to the first plate of the second capacitor, and the second plate of the second capacitor is connected to the first electrode of the driving transistor; the first electrode of the first light-emitting control transistor is used to input the first power supply signal, and the second electrode of the first light-emitting control transistor is connected to the second electrode of the driving transistor.

[0011] In an exemplary embodiment of the present disclosure, the pixel circuit further includes:

[0012] a first reset transistor, wherein a first electrode of the first reset transistor is used to receive a reference signal, and a second electrode of the first reset transistor is connected to the gate of the driving transistor;

[0013] A second reset transistor, wherein a first electrode of the second reset transistor is used to receive the reference signal, and a second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor.

[0014] In an exemplary embodiment of the present disclosure, the pixel circuit further includes:

[0015] A third reset transistor, wherein a first electrode of the third reset transistor is used to receive a reset signal, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the second electrode plate of the second capacitor.

[0016] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a second light emitting control circuit, and the first electrode of the driving transistor is connected to the light emitting device through the second light emitting control circuit.

[0017] In an exemplary embodiment of the present disclosure, the second light emitting control circuit includes a second light emitting control transistor; a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor, and a second electrode of the second light emitting control transistor is connected to the light emitting device;

[0018] The pixel circuit further includes:

[0019] A third reset transistor, wherein a first electrode of the third reset transistor is used to receive a reset signal, and a second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor.

[0020] In an exemplary embodiment of the present disclosure, at least one of the driving transistor, the writing transistor, the first reset transistor, the second reset transistor, the third reset transistor, the first emission control transistor, and the second emission control transistor is a metal oxide transistor.

[0021] According to one aspect of the present disclosure, a display panel is provided, comprising a plurality of pixel circuits arranged in an array along row and column directions, the pixel circuits comprising a plurality of transistors, a first capacitor and a second capacitor, each of the transistors comprising a drive transistor, a write transistor, a first emission control transistor, a second emission control transistor, a first reset transistor, a second reset transistor, and a third reset transistor;

[0022] The first electrode of the first light-emitting control transistor is used to receive a first power supply signal, and the second electrode of the first light-emitting control transistor is connected to the second electrode of the driving transistor; the first electrode of the write transistor is used to receive a data signal, the second electrode of the write transistor is connected to the first plate of the first capacitor and the gate of the driving transistor, the second plate of the first capacitor is connected to the first plate of the second capacitor, and the second plate of the second capacitor is connected to the first electrode of the driving transistor; the first electrode of the second light-emitting control transistor is connected to the first electrode of the driving transistor;

[0023] The first electrode of the first reset transistor and the first electrode of the second reset transistor are used to receive a reference signal, the second electrode of the first reset transistor is connected to the gate of the driving transistor, and the second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor; the first electrode of the third reset transistor is used to receive a reset signal, and the second electrode of the third reset transistor is connected to the first electrode of the driving transistor or the second electrode of the second light-emitting control transistor;

[0024] The display panel includes:

[0025] substrate;

[0026] a semiconductor layer, provided on one side of the substrate and including an active portion of each of the transistors;

[0027] A plurality of light-emitting devices are provided on a side of the semiconductor layer away from the substrate, and one of the light-emitting devices is connected to the second electrode of the second light-emitting control transistor of the pixel circuit;

[0028] One of the first plate and the second plate of the first capacitor is arranged in the same layer as one of the first plate and the second plate of the second capacitor; and one of the first capacitor and the second capacitor overlaps with the active portion of the driving transistor.

[0029] In an exemplary embodiment of the present disclosure, the semiconductor layer includes first semiconductor portions and second semiconductor portions spaced apart along the row direction;

[0030] The active parts of the write transistor, the first reset transistor and the second reset transistor are all located in the first semiconductor part and are connected in sequence; the active parts of the first light-emitting control transistor, the drive transistor, the second light-emitting control transistor and the third reset transistor are located in the second semiconductor part and are connected in sequence.

[0031] In an exemplary embodiment of the present disclosure, the first plate of the first capacitor and the first plate of the second capacitor are arranged in the same layer and are spaced apart along the column direction; the second plate of the first capacitor and the second plate of the second capacitor are arranged in the same layer and are spaced apart along the column direction; the first plate and the second plate of the second capacitor overlap with the active portion of the driving transistor.

[0032] In an exemplary embodiment of the present disclosure, the first plate of the first capacitor and the second plate of the second capacitor are arranged in the same layer and are spaced apart along the column direction; the second plate of the first capacitor and the first plate of the second capacitor are arranged in the same layer and are connected into an integrated structure; the first plate and the second plate of the second capacitor overlap with the active portion of the driving transistor.

[0033] In an exemplary embodiment of the present disclosure, an active portion of the first light emission control transistor overlaps with a first plate and a second plate of the first capacitor.

[0034] In an exemplary embodiment of the present disclosure, the first semiconductor portion includes a first semiconductor segment, a second semiconductor segment, and a third semiconductor segment; the first semiconductor segment and the third semiconductor segment extend along the column direction and are spaced apart along the row direction; the second semiconductor segment connects the first semiconductor segment and the third semiconductor segment; the active portions of the write transistor and the first reset transistor are located in the first semiconductor segment, and the active portion of the second reset transistor is located in the second semiconductor segment; the third semiconductor segment is connected to the first plate of the second capacitor.

[0035] In an exemplary embodiment of the present disclosure, the second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the first electrode of the second light emission control transistor;

[0036] The second semiconductor portion includes a fourth semiconductor segment and a fifth semiconductor segment. The fourth semiconductor segment extends along the column direction and is located on a side of the third semiconductor segment away from the first semiconductor segment. The active portions of the first emission control transistor, the drive transistor, and the second emission control transistor are sequentially distributed in the fourth semiconductor segment along the column direction. The fifth semiconductor segment is connected to a region of the fourth semiconductor segment located between the active portion of the drive transistor and the active portion of the second emission control transistor. The active portion of the third reset transistor is located in the fifth semiconductor segment.

[0037] In an exemplary embodiment of the present disclosure, the second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor and the light emitting device;

[0038] The second semiconductor portion includes a fourth semiconductor segment and a fifth semiconductor segment. The fourth semiconductor segment extends along the column direction and is located on a side of the third semiconductor segment away from the first semiconductor segment. The active portions of the first light-emitting control transistor, the driving transistor, and the second light-emitting control transistor are sequentially distributed in the fourth semiconductor segment along the column direction. The fifth semiconductor segment is connected to a region of the fourth semiconductor segment located on a side of the active portion of the second light-emitting control transistor away from the active portion of the driving transistor. The active portion of the third reset transistor is located in the fifth semiconductor segment.

[0039] In an exemplary embodiment of the present disclosure, the display panel further includes a first light emitting control line, a scan line, a first reset control line, a first reset line, a second reset control line, a second light emitting control line, a third reset control line, and a second reset line, which are sequentially spaced apart along the column direction;

[0040] The first light emitting control line extends along the row direction and is connected to the gate of the first light emitting control transistor for transmitting a first light emitting control signal; the first light emitting control line overlaps with the first capacitor;

[0041] The scan line extends along the row direction and is connected to the gate of the write transistor for transmitting a scan signal; the scan line overlaps with the first capacitor;

[0042] The first reset control line extends along the row direction and is connected to the gate of the first reset transistor for transmitting a first reference control signal; the first reset control line overlaps with the second capacitor;

[0043] The first reset line extends along the row direction and is connected to the first electrodes of the first reset transistor and the second reset transistor, and is used to transmit the reference signal; the first reset line overlaps with the second capacitor;

[0044] The second reset control line extends along the row direction and is connected to the gate of the second reset transistor, and is used for transmitting a second reference control signal;

[0045] The second light emitting control line extends along the row direction and is connected to the gate of the second light emitting control transistor, and is used for transmitting a second light emitting control signal;

[0046] The third reset control line extends along the row direction and is connected to the gate of the third reset transistor, and is used for transmitting a reset control signal;

[0047] The second reset line extends along the row direction and is connected to the first electrode of the third reset transistor, and is used for transmitting the reset signal;

[0048] The orthographic projection of the active portion of the driving transistor on the substrate is located between the scan line and the orthographic projection of the first reset control line on the substrate; the orthographic projection of the active portion of the first reset transistor on the substrate is located between the scan line and the orthographic projection of the first reset line on the substrate; the orthographic projection of the active portion of the second reset transistor on the substrate is located between the orthographic projection of the first reset line and the second light-emitting control line on the substrate; the orthographic projection of the active portion of the third reset transistor on the substrate is located between the orthographic projections of the second light-emitting control and the second reset lines on the substrate.

[0049] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0050] a plurality of first auxiliary power lines extending along the row direction and distributed along the column direction; a first auxiliary power line is provided between two adjacent rows of pixel circuits; the first auxiliary power line is connected to the first electrode of the first light emission control transistor of the pixel circuit on one side thereof;

[0051] a plurality of first power lines, disposed on a side of the first auxiliary power line away from the substrate, each of the first power lines extending in the column direction and spaced apart in the row direction; a first power line connected to each of the first auxiliary power lines and overlapping with a column of the pixel circuits; the first power lines and the first auxiliary power lines being configured to transmit the first power signal;

[0052] A plurality of data lines are arranged on a side of the first auxiliary power line away from the substrate, each of the data lines extends along the column direction and is spaced apart along the row direction; one of the data lines is connected to the first electrode of the write transistor of a column of the pixel circuit for transmitting the data signal.

[0053] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0054] A second auxiliary power line extends along the row direction and is distributed along the column direction for transmitting a second power signal; the orthographic projection of the second auxiliary power line on the substrate is located between the orthographic projections of the second light-emitting control line and the third reset control line on the substrate.

[0055] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0056] a plurality of second power lines, a first auxiliary reset line, and a second auxiliary reset line extending along the column direction and distributed along the row direction, and arranged on a side of the first auxiliary power line away from the substrate; the second power line is connected to the second auxiliary power line, the first auxiliary reset line is connected to the first reset line, and the second auxiliary reset line is connected to the second reset line;

[0057] The first power line and the data line connected to the pixel circuits in the same column are defined as a column line group, and the first power line and the data line of the column line group are provided with one of the second power line, the first auxiliary reset line and the second auxiliary reset line;

[0058] The light emitting device has a first electrode and a second electrode distributed in a direction away from the substrate, the first electrode is connected to the second electrode of the second light emitting control transistor, and the second electrode is connected to the second power line and the second auxiliary power line.

[0059] In an exemplary embodiment of the present disclosure, the semiconductor layer further includes a first auxiliary transition portion and a second auxiliary transition portion;

[0060] The first auxiliary switching portion is connected to a region of the first semiconductor portion of the pixel circuit that is located between the active portion of the first reset transistor and the active portion of the second reset transistor; the first auxiliary reset line is connected to the first auxiliary switching portion;

[0061] The second auxiliary switching portion is connected to a region of the second semiconductor portion of the pixel circuit where the active portion of the third reset transistor is away from the active portion of the second light emission control transistor; the second auxiliary reset line is connected to the second auxiliary switching portion.

[0062] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0063] a light shielding layer, provided on one side of the substrate, and comprising a first electrode plate of the first capacitor and a first electrode plate of the second capacitor;

[0064] a first gate layer, provided on a side of the light shielding layer away from the substrate, and comprising a second plate of the first capacitor, a second plate of the second capacitor, and the second auxiliary power line; and the semiconductor layer is provided on a side of the first gate layer away from the substrate;

[0065] a second gate layer, disposed on a side of the semiconductor layer away from the substrate and overlapping the active portion of each of the transistors;

[0066] a first source / drain layer, provided on a side of the second gate layer away from the substrate, and comprising the first auxiliary power line, the first light-emitting control line, the scan line, the first reset control line, the first reset line, the second reset control line, the second light-emitting control line, the third reset control line, and the second reset line;

[0067] The second source-drain layer is provided on a side of the first source-drain layer away from the substrate, and includes the data line, the first power line, the second power line, the first auxiliary reset line and the second auxiliary reset line.

[0068] In an exemplary embodiment of the present disclosure, the second gate layer further includes:

[0069] a first gate portion overlapping the active portion of the first light emission control transistor to form a gate of the first light emission control transistor; the first gate portion being connected to the first light emission control line;

[0070] a second gate portion overlapping the active portion of the write transistor to form a gate of the write transistor; the second gate portion being connected to the scan line;

[0071] a third gate portion overlapping the active portion of the driving transistor and connected to the third gate portion to form a gate of the driving transistor;

[0072] a fourth gate portion overlapping the active portion of the first reset transistor to form a gate of the first reset transistor; the fourth gate portion being connected to the first reset control line;

[0073] a fifth gate portion overlapping the active portion of the second reset transistor to form a gate of the second reset transistor; the fifth gate portion being connected to the second reset control line;

[0074] a sixth gate portion overlapping the active portion of the second light emission control transistor to form a gate of the second light emission control transistor; the sixth gate portion being connected to the second light emission control line;

[0075] A seventh gate portion overlaps with the active portion of the third reset transistor to form a gate of the third reset transistor; the seventh gate portion is connected to the third reset control line.

[0076] In an exemplary embodiment of the present disclosure, the first source-drain layer further includes:

[0077] a first connecting portion located between the first light emitting control line and the scan line and connected to the data line and a region of the first semiconductor portion located on a side of the active portion of the write transistor away from the active portion of the first reset transistor;

[0078] a second connecting portion, located between the scan line and the first reset control line, and connected to the first plate of the first capacitor, the third gate portion, and a region of the first semiconductor portion between the active portion of the write transistor and the active portion of the first reset transistor;

[0079] a third connecting portion, located between the scan line and the first reset control line, and connected to the second plate of the first capacitor, the first plate of the second capacitor, and the second electrode of the second reset transistor;

[0080] a fourth connecting portion, located between the second connecting portion and the first reset control line, and connected to the second plate of the second capacitor and a region of the second semiconductor portion located between the active portion of the drive transistor and the active portion of the second light emission control transistor;

[0081] The fifth connection portion is located between the second light emission control line and the third reset control line and is connected to a region of the second semiconductor portion located at an active portion of the second light emission control transistor away from an active portion of the driving transistor.

[0082] In an exemplary embodiment of the present disclosure, the first source-drain layer further includes:

[0083] The sixth connection portion overlaps the third gate portion and the active portion of the driving transistor and is connected to the first power line.

[0084] In an exemplary embodiment of the present disclosure, the first source-drain layer further includes:

[0085] a seventh connecting portion, located between the second light emitting control line and the third reset control line, and connected to the second auxiliary power line and the second power line;

[0086] an eighth connecting portion, located between the second light-emitting control line and the third reset control line, and connected to the first auxiliary switching portion and the first auxiliary reset line;

[0087] The ninth connecting portion is located between the second light emitting control line and the third reset control line, and is connected to the second auxiliary switching portion and the second auxiliary reset line.

[0088] In an exemplary embodiment of the present disclosure, the first power line overlaps with the second connection portion.

[0089] In an exemplary embodiment of the present disclosure, one of the second power line, the first auxiliary reset line, and the second auxiliary reset line overlaps at least a portion of the active portion of the write transistor, the active portion of the first reset transistor, and the third connection portion.

[0090] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer includes metal oxide.

[0091] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0092] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0094] FIG1 is a top view of an embodiment of a display panel disclosed herein.

[0095] FIG2 is a partial cross-sectional schematic diagram of an embodiment of a display panel disclosed herein.

[0096] FIG3 is a schematic diagram of an embodiment of the first type of pixel circuit disclosed herein.

[0097] FIG4 is a timing diagram of a driving method for the pixel circuit in FIG3 .

[0098] FIG5 is a schematic diagram of a first embodiment of the second type of pixel circuit disclosed herein.

[0099] FIG6 is a timing diagram of a driving method for the pixel circuit in FIG5 .

[0100] FIG7 is a schematic diagram of a second embodiment of the second type of pixel circuit disclosed herein.

[0101] FIG8 is a timing diagram of a driving method for the pixel circuit in FIG7 .

[0102] FIG9 is a schematic diagram of an embodiment of the third type of pixel circuit disclosed herein.

[0103] FIG10 is a partial top view of the light shielding layer to the second source and drain layer of a single pixel circuit in one embodiment of the first display panel of the present disclosure.

[0104] FIG11 is a partial top view of the light shielding layer to the first source and drain layer of a single pixel circuit in one embodiment of the first display panel of the present disclosure.

[0105] FIG12 is a partial top view of the light shielding layer to the second gate layer of a single pixel circuit in one embodiment of the first display panel of the present disclosure.

[0106] FIG13 is a partial top view of the light shielding layer to the semiconductor layer of a single pixel circuit in one embodiment of the first display panel of the present disclosure.

[0107] FIG14 is a partial top view of the light shielding layer to the first gate layer of a single pixel circuit in one embodiment of the first display panel of the present disclosure.

[0108] 15 to 20 are partial top views of each layer from the light shielding layer to the second source and drain layer of a single pixel circuit in one embodiment of the first display panel of the present disclosure.

[0109] FIG21 is a partial top view of the light shielding layer to the second source and drain layer of a single pixel circuit in another embodiment of the first display panel of the present disclosure.

[0110] FIG22 is a partial top view of the light shielding layer to the first source and drain layer of a single pixel circuit in another embodiment of the first display panel of the present disclosure.

[0111] FIG23 is a partial top view of the light shielding layer to the second gate layer of a single pixel circuit in another embodiment of the first display panel of the present disclosure.

[0112] FIG24 is a partial top view of the light shielding layer to the semiconductor layer of a single pixel circuit in another embodiment of the first display panel of the present disclosure.

[0113] FIG25 is a partial top view of the semiconductor layer of a single pixel circuit in another embodiment of the first display panel of the present disclosure.

[0114] FIG26 is a partial top view of the region from the light shielding layer to the first electrode of a plurality of pixel circuits in one embodiment of the first display panel of the present disclosure.

[0115] FIG27 is a partial top view of the light shielding layer to the second source and drain layer of multiple pixel circuits in one embodiment of the first display panel of the present disclosure.

[0116] FIG28 is a partial top view of a light shielding layer to a first source and drain layer of a plurality of pixel circuits in one embodiment of the first display panel of the present disclosure.

[0117] FIG29 is a partial top view of a light shielding layer to a second gate layer of a plurality of pixel circuits in one embodiment of the first display panel of the present disclosure.

[0118] FIG30 is a partial top view of a light shielding layer to a semiconductor layer of a plurality of pixel circuits in one embodiment of the first display panel of the present disclosure.

[0119] FIG31 is a partial top view of a light shielding layer to a first gate layer of a plurality of pixel circuits in one embodiment of the first display panel of the present disclosure.

[0120] 32 to 35 are partial top views of a portion of film layers from the light shielding layer to the second source and drain layer of multiple pixel circuits in one embodiment of the first display panel of the present disclosure.

[0121] FIG36 is a partial top view of the light shielding layer to the second source and drain layer of a single pixel circuit in one embodiment of the second display panel disclosed herein.

[0122] FIG37 is a partial top view of the light shielding layer to the first source and drain layer of a single pixel circuit in one embodiment of the second display panel disclosed herein.

[0123] FIG38 is a partial top view of the light shielding layer to the second gate layer of a single pixel circuit in one embodiment of the second display panel disclosed herein.

[0124] FIG39 is a partial top view of the light shielding layer to the semiconductor layer of a single pixel circuit in one embodiment of the second display panel of the present disclosure.

[0125] FIG40 is a partial top view of the light shielding layer to the first gate layer of a single pixel circuit in one embodiment of the second display panel disclosed herein.

[0126] FIG41 is a partial top view of the first gate layer of a single pixel circuit in one embodiment of the second display panel disclosed herein.

[0127] FIG42 is a partial top view of the semiconductor layer of a single pixel circuit in one embodiment of the second display panel of the present disclosure. DETAILED DESCRIPTION

[0128] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0129] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0130] The row direction X and column direction Y herein are two intersecting directions. In the drawings of this disclosure, the row direction X may be horizontal and the column direction Y may be vertical, with the two directions being perpendicular to each other. However, this is not limiting. The row direction X and the column direction Y may also be non-perpendicular. Furthermore, those skilled in the art will appreciate that, as the display panel rotates, the actual orientations of the row direction X and the column direction Y may change, but their relative positions remain unchanged.

[0131] In this article, "overlap" of feature A and feature B means that the orthographic projection of feature A on a plane and the orthographic projection of feature B on the same plane at least partially overlap; the plane can be the surface of the substrate or other plane parallel to the substrate.

[0132] In this article, A and B are "set in the same layer" means that A and B belong to different continuous or disconnected regions in the same film layer, and the film layer can be a single-layer structure; or, the film layer can be a multi-layer structure including multiple sub-layers. In this case, A and B can be located in the same sub-layer or different sub-layers in the multi-layer structure.

[0133] As shown in FIG1 , the present disclosure provides a display panel, which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA. Of course, the peripheral area WA may also be a discontinuous area surrounding the area outside the display area AA.

[0134] As shown in FIG2 , the display panel may include a driving backplane BP and a plurality of light-emitting devices LD arranged on one side of the driving backplane BP. The light-emitting devices LD are arrayed along the row direction X and the column direction Y. The driving circuit in the driving backplane BP can drive the light-emitting devices LD to emit light to display images.

[0135] As shown in Figure 2, the light-emitting device LD can be located in the display area AA. It can be an OLED (organic light-emitting diode) using organic light-emitting materials; it can also be an LED (light-emitting diode) using inorganic light-emitting materials, such as Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also be a device such as QLED (quantum dot diode). There is no special limitation on the specific structure of the light-emitting device LD here, as long as it can display images.

[0136] As shown in Figure 2, taking the light-emitting device LD using OLED as an example, it may include a first electrode ANO, a light-emitting layer EL and a second electrode CAT stacked in sequence in a direction away from the driving backplane BP. By applying an electrical signal to the first electrode ANO and the second electrode CAT, the light-emitting layer EL can be stimulated to emit light. The specific light-emitting principle will not be described in detail here.

[0137] The driving circuit may include pixel circuits located within the display area AA and peripheral circuits located in the peripheral area WA. The pixel circuits may be arranged in an array along the row direction X and the column direction Y. One pixel circuit may be connected to the first electrode ANO of one light-emitting device LD, and a row of pixel circuits may be connected to the first electrode ANO of each light-emitting device LD in the row. Of course, the same pixel circuit may also be connected to the first electrodes ANO of multiple light-emitting devices LD. Furthermore, some pixel circuits may be located in the peripheral area WA.

[0138] The peripheral circuit can be connected to the light-emitting device LD via a pixel circuit, and a first power signal VDD can be applied to a first electrode ANO of the light-emitting device LD via the pixel circuit. Furthermore, the peripheral circuit can be connected to a second electrode CAT of the light-emitting device LD and a second power signal VSS can be applied to the second electrode CAT. The pixel circuit can control the current flowing through the light-emitting device LD, thereby controlling the brightness of the light-emitting device LD. The peripheral circuit can include at least one gate drive circuit and a light-emitting control circuit, wherein each gate drive circuit and light-emitting control circuit includes a plurality of cascaded shift register units, and a signal output by one shift register unit can control at least one row of pixel circuits.

[0139] The following is an exemplary description of the pixel circuit:

[0140] Type I pixel circuit

[0141] As shown in FIG3 , the pixel circuit may include a driving transistor T3, a data control circuit CU, a storage circuit RU, a writing circuit DU and a first light emitting control circuit EU1, wherein:

[0142] The gate of the driving transistor T3 is connected to the first electrode of the driving transistor T3 through the data control circuit CU and the energy storage circuit RU in sequence, and the first electrode of the driving transistor T3 is used to be connected to the light-emitting device LD. The second electrode of the driving transistor T3 is connected to the first light-emitting control circuit EU1, and the first light-emitting control circuit EU1 is used to receive the first power supply signal VDD;

[0143] The write circuit DU is connected to the gate of the driving transistor T3 through the data control circuit CU; the write circuit DU is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU;

[0144] The write circuit DU is used to write the data signal Data into the tank circuit RU; the tank circuit RU is used to store the data signal Data and the voltage of the first electrode of the driving transistor T3.

[0145] The data signal Data and the voltage of the first electrode of the driving transistor T3 can be stored separately by the energy storage circuit RU, so as to stabilize the voltage difference between the first electrode and the gate of the driving transistor T3. The data control circuit CU can control the conduction and disconnection between the gate and the first electrode of the driving transistor T3, thereby preventing the data signal Data from being directly written into the gate of the driving transistor T3 and interfering with the voltage of its first electrode. This can prevent the actual brightness of the light-emitting device LD from being significantly different from the designed brightness due to different levels of interference from different data signals Data, thereby improving picture quality.

[0146] The energy storage circuit RU is used to store the data signal Data and the threshold voltage of the driving transistor T3, respectively, and can prevent the two from interfering with each other. The write circuit DU can control the writing and shutting down of the data signal Data. The data control circuit CU can turn on and off the gate of the driving transistor T3 and the write circuit DU, and can also turn on and off the gate of the driving transistor T3 and the energy storage circuit RU. The energy storage circuit RU can be implemented by multiple capacitors, while the write circuit DU and the data control circuit CU can be implemented by transistors; for example:

[0147] As shown in FIG3 , in some embodiments of the present disclosure, the energy storage circuit RU may include a first capacitor C1 and a second capacitor C2 connected in series; the data control circuit CU includes a data control transistor T6 ; and the write circuit DU may include a write transistor T4 .

[0148] The first electrode of the write transistor T4 is used to input the data signal Data, the second electrode of the write transistor T4 is connected to the first electrode of the data control transistor T6 and the first plate C11 of the first capacitor C1, and can be connected to the N5 node; the second electrode of the data control transistor T6 is connected to the gate of the drive transistor T3, and can be connected to the N1 node; the second plate C12 of the first capacitor C1 is connected to the first plate C21 of the second capacitor C2, and can be connected to the N4 node; the second plate C22 of the second capacitor C2 is connected to the first electrode of the drive transistor T3, and can be connected to the N3 node.

[0149] The gate of the write transistor T4 can receive a scan signal Gate and be turned on or off under the control of the scan signal Gate. The gate of the data control transistor T6 can receive a data control signal DC and be turned on or off under the control of the data control signal DC.

[0150] In addition, the first light emitting control circuit EU1 can control the first power signal VDD to be turned on and off, which can also be achieved by transistors. For example:

[0151] As shown in Figure 3, in some embodiments of the present disclosure, the first light-emitting control circuit EU1 may include a first light-emitting control transistor T5, whose first electrode is used to receive the first power supply signal VDD, and the second electrode can be connected to the second electrode of the driving transistor T3, and the second electrode can be connected to the second electrode of the driving transistor T3 at the N2 node.

[0152] A gate of the first light emitting control transistor T5 may receive a light emitting control signal EM and be turned on or off under the control of the light emitting control signal EM.

[0153] In order to eliminate the influence of the signal of the previous frame image, before displaying the signal input of the current frame, the gate and the first electrode of the driving transistor T3 may be reset. At the same time, the energy storage circuit RU may also be reset. As shown in FIG3 , in some embodiments of the present disclosure, the pixel circuit may further include a first reset transistor T1 and a second reset transistor T2, wherein:

[0154] The first electrode of the first reset transistor T1 is used to receive the reference signal Vref, and the second electrode is connected to the gate of the driving transistor T3 and the second electrode of the data control transistor T6. As shown in Figure 3, the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3 and the second electrode of the data control transistor T6 at the N1 node.

[0155] A first electrode of the second reset transistor T2 is used to receive a reference signal Vref, and a second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2. As shown in FIG2 , the second electrode of the second reset transistor T2 and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are connected to the N4 node.

[0156] The gates of the first reset transistor T1 and the second reset transistor T2 can receive a reference control signal RE1 and be turned on or off under the control of the reference control signal RE1. In other words, the first reset transistor T1 and the second reset transistor T2 can be turned on or off synchronously and can be controlled by the same signal. Of course, the gates of the first reset transistor T1 and the second reset transistor T2 can receive the reference control signal RE1 via the same or different signal lines.

[0157] The reference signal Vref can be input to the N1 and N4 nodes through the first reset transistor T1 and the second reset transistor T2 to eliminate the influence of the signal when displaying the previous frame image.

[0158] The reference control signal RE1 received by the gates of the first reset transistor T1 and the second reset transistor T2 can be provided by a shift register of a gate drive circuit. In some embodiments, the gate of the first reset transistor T1 can receive the first reference control signal, and the gate of the second reset transistor T2 can receive the second reference control signal; the first reference control signal for the gate of the first reset transistor T1 of the pixel circuit in the n+1th row and the second reference control signal for the gate of the second reset transistor T2 of the pixel circuit in the nth row can be the same signal, where n is a positive integer. Thus, the first reset transistor T1 of the pixel circuit in the n+1th row and the second reset transistor T2 of the pixel circuit in the nth row are simultaneously controlled by the same shift register, that is, one shift register is used to simultaneously control multiple rows of pixel circuits, which helps reduce the number of shift registers and simplify the structure.

[0159] Furthermore, as shown in FIG3 , the pixel circuit further includes a third reset transistor T7, a first electrode of which is used to receive a reset signal Vinit, and a second electrode is connected to the first electrode of the driving transistor T3 and the second electrode plate C22 of the second capacitor C2. As shown in FIG3 , the second electrode of the third reset transistor T7 is connected to the first electrode of the driving transistor T3 and the second electrode plate C22 of the second capacitor C2 at the N3 node. The gate of the third reset transistor T7 can receive a reset control signal RE2 and be turned on or off under the control of the reset control signal RE2. The reset signal Vinit can be input to the N3 node through the third reset transistor T7, resetting the first electrode of the driving transistor T3, the second electrode plate C22 of the second capacitor C2, and the first electrode ANO of the light-emitting device LD, thereby eliminating the influence of the signal of the previous frame image.

[0160] At least one of the transistors in the pixel circuit described above may be a metal oxide transistor, i.e., the material of the active portion of the transistor may be a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the material of the active portion of the transistor may be an oxide of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti); or a mixture of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and an oxide of at least one metal selected from the group consisting of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). Within the spirit and scope of the disclosure, oxide semiconductors may include metal oxides such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc gallium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), and zinc tin oxide (ZTO). Accordingly, the transistor may be an N-type transistor. As shown in FIG3 , if each transistor is an N-type transistor, the first electrode of each transistor is a source electrode, the second electrode is a drain electrode, and the transistor is turned on when the gate electrode receives a high voltage level and is turned off when the gate electrode receives a low voltage level. For example, as shown in FIG3 , the drive transistor T3, the data control transistor T6, the write transistor T4, the first reset transistor T1, the second reset transistor T2, the third reset transistor T7, and the first light emission control transistor T5 are all metal oxide transistors. That is, the transistors in the pixel circuit are all metal oxide transistors to reduce leakage current. Of course, only some of the transistors can also be metal oxide transistors.

[0161] As shown in FIG4 , the driving method of the pixel circuit is exemplarily described below by taking the first type of pixel circuit in FIG3 (each transistor is an N-type metal oxide transistor) as an example:

[0162] During reset phase t1, the reference control signal RE1 received by the gates of the first and second reset transistors T1 and T2 is at a high level, turning on the first and second reset transistors T1 and T2. The reference signal Vref, which can be 2.5V, resets nodes N1 and N4. The reset control signal RE2 received by the gate of the third reset transistor T7 is at a high level, turning on the third reset transistor T7. The reset signal Vinit, which can be 1.5V, resets node N3. At this point, a voltage difference exists between the gate and the first electrode of the driving transistor T3, turning it on.

[0163] At the same time, the light-emitting control signal EM received by the gate of the first light-emitting control transistor T5 is at a low level, so that the light-emitting control transistor T5 is turned off; the scanning signal Gate received by the gate of the write transistor T4 is at a low level, so that the write transistor T4 is turned off; the data control signal DC received by the gate of the data control transistor T6 is at a low level, so that the data control transistor T6 is turned off.

[0164] The reset of nodes N1 and N4 and the reset of node N3 can be performed in stages. For example, the reset control signal RE2 first changes from a low level to a high level, and then the reference control signal RE1 changes from a low level to a high level. Of course, the two can also be performed simultaneously.

[0165] During compensation phase t2, the light control signal EM received by the gate of the light control transistor T5 is at a high level, turning on the first light control transistor T5. The voltage at the N2 node is equal to the voltage of the first power signal VDD. Since the driving transistor T3 is turned on, the voltage at the N3 node gradually increases. The voltage of the first power signal VDD can be 11.5V.

[0166] At the same time, the reference control signal RE1 is at a high level, the first reset transistor T1 and the second reset transistor T2 are turned on; the reset control signal RE2 is at a low level, the third reset transistor T7 is turned off; the data control signal DC is at a low level, the data control transistor T6 is turned off; the scan signal Gate is at a low level, and the write transistor T4 is turned off.

[0167] In the writing phase t3, the scanning signal Gate is high, the writing transistor T4 is turned on, and the data signal Data is written to the N5 node through the writing transistor T4, that is, stored in the first capacitor C1; the data control signal DC is low, and the data control transistor T6 is turned off.

[0168] At the same time, the emission control signal EM can remain high, turning on the first emission control transistor T5. The voltage at node N3 gradually increases until it reaches Vref-Vth, causing the voltage difference between the gate and the first electrode of the driving transistor T3 to equal the threshold voltage, i.e., gate-source voltage difference Vgs=Vth. At this point, the driving transistor T3 is turned off, and Vth is the threshold voltage of the driving transistor T3. Consequently, the threshold voltage Vth is written to node N3 and stored in the second capacitor C2. That is, the writing of the threshold voltage begins in compensation phase t2 and is completed in writing phase t3. The writing of the threshold voltage continues from compensation phase t2 to writing phase t3, meaning that the writing of the threshold voltage and the writing of the data signal Data are independent of each other. The emission control signal EM can continue until the driving transistor T3 is turned off, i.e., until the writing of the threshold voltage is completed. For example, the emission control signal EM can continue until the writing transistor T4 is turned off, i.e., after the writing of the data signal Data is completed.

[0169] In addition, the reference control signal RE1 is low, the first reset transistor T1 and the second reset transistor T2 are turned off; the reset control signal RE2 is low, the third reset transistor T7 is turned off; the data control signal DC is low, the data control transistor T6 is turned off.

[0170] During light-emitting phase t4, the light-emitting control signal EM is high, turning on the first light-emitting control transistor T5; the data control signal DC is high, turning on the data control transistor T6; the reference control signal RE1 is low, turning off the first and second reset transistors T1 and T2; the reset control signal RE2 is low, turning off the third reset transistor T7; the scan signal Gate is low, turning off the write transistor T4; and under the action of the first capacitor C1, the data signal Data begins to be written to point N1. At this time, the voltage at node N1, i.e., the gate voltage of the driving transistor T3, Vg = Vdata + Vld + VSS - (Vref - Vth); the voltage at node N3, i.e., the voltage at the first electrode of the driving transistor T3, Vs = Vld + VSS; and the gate-source voltage difference Vgs of the driving transistor T3 = Vdata - Vref + Vth. Vld is the voltage of the light-emitting device LD, i.e., the voltage of the capacitor Co of the light-emitting device LD; VSS is the voltage of the second power supply signal VSS input to the second electrode CAT of the light-emitting device LD; and Vdata is the voltage of the data signal Data.

[0171] The output current of the driving transistor T3 satisfies the following formula: I=(μWCox / 2L)(Vgs-Vth) 2 ;

[0172] I is the output current of the driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0173] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current of the driving transistor T3 I = (μWCox / 2L)(Vdata-Vref) 2 It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light-emitting device LD.

[0174] In the aforementioned pixel circuit driving method, a data control circuit CU is provided between the gate and the first electrode of the driving transistor T3. The writing of the data signal Data can be divided into two phases. The first phase is the writing phase t3, during which the data signal Data is stored separately via the energy storage circuit RU while the data control circuit CU is turned off, thereby preventing the data signal Data from being directly written to the gate of the driving transistor T3. The second phase is the light-emitting phase t4, during which the data control circuit CU is turned on and the data signal Data is applied to the gate of the driving transistor T3 via the energy storage circuit RU. During the compensation phase t2, the threshold voltage of the driving transistor T3 can also be written into the energy storage circuit RU (independent of the storage of the data signal Data).

[0175] The energy storage circuit RU does not interfere with the storage of the threshold voltage when storing the data signal Data. In the light-emitting stage t4, the energy storage circuit RU can ensure that the differential voltage between the data signal Data and the first electrode of the driving transistor T3 is stable, thereby preventing a large difference between the actual brightness of the light-emitting device LD and the designed brightness due to different levels of interference of different data signals Data, thereby improving picture quality.

[0176] The second type of pixel circuit

[0177] As shown in FIG5 and FIG7, the pixel circuit may include a driving transistor T3, a storage circuit RU, a writing circuit DU, a first light emitting control circuit EU1 and a second light emitting control circuit EU2, wherein:

[0178] The gate of the driving transistor T3 is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU, and the first electrode of the driving transistor T3 is connected to the light-emitting device LD. The second electrode of the driving transistor T3 is connected to the first light-emitting control circuit EU1, and the first light-emitting control circuit EU1 is used to receive the first power supply signal VDD;

[0179] The write circuit DU is connected to the gate of the driving transistor T3; the write circuit DU is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU; the first electrode of the driving transistor is connected to the light emitting device LD through the second light emitting control circuit EU2.

[0180] The write circuit DU is used to write the data signal Data into the tank circuit RU; the tank circuit RU is used to store the data signal Data and the voltage of the first electrode of the driving transistor T3.

[0181] The energy storage circuit RU can store the data signal Data and the voltage of the first electrode of the driving transistor T3 respectively, so as to stabilize the voltage difference between the first electrode and the gate of the driving transistor T3, which is beneficial to ensure that the light emitting device LD emits light stably, thereby improving the picture quality.

[0182] As shown in Figures 5 and 7, in some embodiments of the present disclosure, the energy storage circuit RU may include a first capacitor C1 and a second capacitor C2 connected in series; the write circuit DU may include a write transistor T4; the first light-emitting control circuit EU1 includes a first light-emitting control transistor T5; and the second light-emitting control circuit EU2 includes a second light-emitting control transistor T6.

[0183] The first electrode of the write transistor T4 is used to input the data signal Data. The second electrode of the write transistor T4 is connected to the gate of the drive transistor T3 and the first plate C11 of the first capacitor C1, and can be connected to the N5 node. The second plate C12 of the first capacitor C1 is connected to the first plate C21 of the second capacitor C2, and can be connected to the N4 node. The second plate C22 of the second capacitor C2 is connected to the first electrode of the drive transistor T3, and can be connected to the N3 node. The first electrode of the first light-emitting control transistor T5 is used to receive the first power supply signal VDD. The second electrode can be connected to the second electrode of the drive transistor T3, and can be connected to the N2 node. The first electrode of the second light-emitting control transistor T6 is connected to the first electrode of the drive transistor T3 and the second plate C22 of the second capacitor C2, and can be connected to the N3 node. The second electrode of the second light-emitting control transistor T6 can be connected to the first electrode ANO of the light-emitting device LD.

[0184] The gate of the write transistor T4 can receive a scan signal Gate and be turned on or off under the control of the scan signal Gate. The gate of the first emission control transistor T5 can receive a first emission control signal EM1 and be turned on or off under the control of the first emission control signal EM1. The gate of the second emission control transistor T6 can receive a second emission control signal EM2 and be turned on or off under the control of the second emission control signal EM2.

[0185] In order to eliminate the influence of the signal of the previous frame image, before displaying the signal input of the current frame, the gate and the first electrode of the driving transistor T3 may be reset. At the same time, the energy storage circuit RU may also be reset. As shown in FIG5 and FIG7, in some embodiments of the present disclosure, the pixel circuit may further include a first reset transistor T1 and a second reset transistor T2, wherein:

[0186] The first electrode of the first reset transistor T1 is used to receive the reference signal Vref, and the second electrode is connected to the gate of the driving transistor T3. As shown in FIG5 and FIG7, the second electrode of the first reset transistor T1 and the gate of the driving transistor T3 are connected to the N1 node.

[0187] A first electrode of the second reset transistor T2 is used to receive a reference signal Vref, and a second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2. As shown in Figures 5 and 7, the second electrode of the second reset transistor T2 and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are connected to the N4 node.

[0188] The gate of the first reset transistor T1 can receive a first reference control signal RE1 and be turned on or off under the control of the first reference control signal RE1. The gate of the second reset transistor T2 can receive a second reference control signal RE2 and be turned on or off under the control of the second reference control signal RE2. The first reference control signal RE1 and the second reference control signal RE2 can be synchronous signals, so that the first reset transistor T1 and the second reset transistor T2 can be turned on or off synchronously. Of course, the first reference control signal RE1 and the second reference control signal RE2 can also be asynchronous.

[0189] The reference signal Vref can be input to the N1 and N4 nodes through the first reset transistor T1 and the second reset transistor T2 to eliminate the influence of the signal when displaying the previous frame image.

[0190] Furthermore, in some embodiments, the first reference control signal RE1 for the gate of the first reset transistor T1 of the pixel circuit in the n+1th row and the second reference control signal RE2 for the gate of the second reset transistor T2 of the pixel circuit in the nth row can be the same signal, where n is a positive integer. Thus, the first reset transistor T1 of the pixel circuit in the n+1th row and the second reset transistor T2 of the pixel circuit in the nth row can be simultaneously controlled by the same shift register, i.e., one shift register can simultaneously control multiple rows of pixel circuits, which helps reduce the number of shift registers and simplify the structure.

[0191] As shown in FIG5 and FIG7, the pixel circuit further includes a third reset transistor T7, a first electrode of which is used to receive a reset signal Vinit, and a second electrode of which is used to reset the N3 node. For example:

[0192] In a first embodiment of the second type of pixel circuit, as shown in FIG5 , the second electrode of the third reset transistor T7 can be connected to the first electrode of the drive transistor T3, the second electrode plate C22 of the second capacitor C2, and the first electrode of the second light-emitting control transistor T6, and can be connected to the N3 node. The gate of the third reset transistor T7 can receive a reset control signal RE3 and be turned on or off under the control of the reset control signal RE3. A reset signal Vinit can be input to the N3 node via the third reset transistor T7, resetting the first electrode of the drive transistor T3 and the second electrode plate C22 of the second capacitor C2, thereby eliminating the influence of the signal of the previous frame image.

[0193] In a second embodiment of the second type of pixel circuit, as shown in FIG7 , the second electrode of the third reset transistor T7 can be connected to the second electrode of the second light-emitting control transistor T6 and the first electrode ANO of the light-emitting device LD, and can be connected to the N6 node. The gate of the third reset transistor T7 can receive a reset control signal RE3 and be turned on or off under the control of the reset control signal RE3. A reset signal Vinit can be input to the N6 node via the third reset transistor T7, resetting the first electrode of the drive transistor T3 and the second plate C22 of the second capacitor C2, thereby eliminating the influence of the signal of the previous frame.

[0194] At least one of the transistors in the pixel circuit described above may be a metal oxide transistor, i.e., the material of the active portion of the transistor may be a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the material of the active portion of the transistor may be an oxide of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti); or a mixture of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and an oxide of at least one metal selected from the group consisting of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). Within the spirit and scope of the disclosure, oxide semiconductors may include metal oxides such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc gallium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), and zinc tin oxide (ZTO). Accordingly, the transistor may be an N-type transistor, as shown in FIG5 and FIG7 . If each transistor is an N-type transistor, the first electrode of each transistor is a source electrode, the second electrode is a drain electrode, and the transistor is turned on when the gate electrode receives a high voltage level and is turned off when the gate electrode receives a low voltage level. For example, as shown in Figures 5 and 7, the drive transistor T3, the write transistor T4, the first reset transistor T1, the second reset transistor T2, the third reset transistor T7, the first emission control transistor T5, and the second emission control transistor T6 are all metal oxide transistors. That is, the transistors in the pixel circuit are all metal oxide transistors to reduce leakage current. Of course, only some of the transistors can also be metal oxide transistors.

[0195] The following describes the structure of the pixel circuit based on the first embodiment of the second type of pixel circuit and its driving method:

[0196] As shown in FIG5 and FIG6 , the driving method may include:

[0197] In the compensation phase t2 , the first light emitting control circuit EU1 is turned on and the second light emitting control circuit EU2 is turned off, so as to write the threshold voltage of the driving transistor T3 into the energy storage circuit RU.

[0198] Different voltages can be input to the gate and first electrode of the driving transistor T3 to turn on the driving transistor T3 and turn off the second light-emission control circuit EU2. When the first light-emission control circuit EU1 is turned on, the voltage at the first electrode of the driving transistor T3 gradually increases, and the threshold voltage of the driving transistor T3 begins to be written into the energy storage circuit RU. The compensation phase begins to write the threshold voltage into the energy storage circuit RU, but is not limited to the completion of the threshold voltage writing.

[0199] In the writing phase t3, the writing circuit DU and the first light-emitting control circuit EU1 are turned on, and the second light-emitting control circuit EU2 is turned off. The data signal Data is written into the energy storage circuit RU through the writing circuit DU, and the threshold voltage of the driving transistor T3 is written into the energy storage circuit RU.

[0200] The data signal Data is written to the tank circuit RU and the gate of the driving transistor T3 via the write circuit DU. Simultaneously, when the voltage at the first electrode of the driving transistor T3 reaches a value equal to the difference between the voltage at its gate and the threshold voltage, the driving transistor T3 is turned off, thereby writing the threshold voltage of the driving transistor T3 into the tank circuit RU. In other words, the writing of the threshold voltage and the writing of the data signal Data are independent of each other.

[0201] In the light emitting stage t4, the first light emitting control circuit EU1 and the second light emitting control circuit EU2 are turned on, the writing circuit DU is turned off, and the voltage difference between the gate and the first electrode of the driving transistor T3 is controlled by the energy storage circuit RU to make the light emitting device LD emit light.

[0202] Furthermore, as shown in FIG5 and FIG6 , in some embodiments of the present disclosure, the driving method may further include:

[0203] In the reset phase t1, the first reset transistor T1, the second reset transistor T2 and the third reset transistor T7 are turned on, and the write circuit DU, the first light-emitting control circuit EU1 and the second light-emitting control circuit EU2 are turned off; the gate of the driving transistor T3 is reset by the reference signal Vref, and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are reset, and the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2 are reset by the reset signal Vinit; at the same time, the driving transistor T3 can be turned on by the voltage difference between the reset signal Vinit and the reference signal Vref.

[0204] In the aforementioned pixel circuit driving method, the data signal Data and the threshold voltage of the driving transistor T3 can be stored separately via the energy storage circuit RU. Storage of the data signal Data by the energy storage circuit RU does not interfere with the storage of the threshold voltage. This ensures that the voltage differential between the data signal Data and the first electrode of the driving transistor T3 remains stable during the light-emitting phase, preventing significant differences between the actual brightness and the designed brightness of the light-emitting device LD due to varying degrees of interference from different data signals Data, thereby improving image quality. Furthermore, the gate of the driving transistor T3 can be directly connected to the write circuit DU, rather than through the data control circuit CU. This prevents coupling effects caused by the on / off state of the data control circuit CU from affecting the voltage at the gate of the driving transistor T3.

[0205] As shown in FIG6 , the driving method of the pixel circuit is exemplarily described below by taking the first embodiment of the second type of pixel circuit as an example:

[0206] Each transistor in the pixel circuit is an N-type metal oxide transistor.

[0207] During reset phase t1, the first and second reference control signals RE1 and RE2 are high, turning on the first and second reset transistors T1 and T2. Reference signal Vref resets nodes N1 and N4, and the voltage of reference signal Vref can be 2.5V. Reset control signal RE3 is high, turning on the third reset transistor T7, and resetting node N3 with reset signal Vinit, which can be 1.5V. At this point, a voltage difference exists between the gate and the first electrode of driver transistor T3, and the driver transistor is conducting.

[0208] At the same time, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at low levels, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off; the scan signal Gate is at a low level, and the write transistor T4 is turned off.

[0209] The N1 node, the N3 node, and the N4 node can be reset sequentially. For example, the first reference control signal RE1 and the second reference control signal RE2 are first changed from a low level to a high level, and then the reset control signal RE3 is changed from a low level to a high level; the first reset transistor T1 and the second reset transistor T2 are turned on first, and then the third reset transistor T7 is turned on.

[0210] During compensation phase t2, the first emission control signal EM1 is high, the first emission control transistor T5 is turned on, and the voltage at node N2 is equal to the voltage of the first power supply signal VDD. Due to the conduction of the driving transistor T3, the voltage at node N3 gradually increases until it reaches Vref-Vth, causing the voltage difference between the gate and the first electrode of the driving transistor T3 to equal the threshold voltage, i.e., gate-source voltage difference Vgs=Vth. At this point, the driving transistor T3 is turned off; Vth is the threshold voltage of the driving transistor T3. Consequently, the threshold voltage Vth is written to node N3 and stored in the second capacitor C2. The first emission control signal EM1 continues until the driving transistor T3 is turned off, i.e., until the threshold voltage is written. The voltage of the first power supply signal VDD can be 11.5V.

[0211] At the same time, the second light-emitting control signal EM2 is at a low level, so that the second light-emitting control transistor T6 is turned off; the first reference control signal RE1 and the second reference control signal RE2 are at a high level, and the first reset transistor T1 and the second reset transistor T2 are turned on; the reset control signal RE3 is at a low level, and the third reset transistor T7 is turned off; the scanning signal Gate is at a low level, and the write transistor T4 is turned off.

[0212] During write phase t3, the scan signal Gate is high, the write transistor T4 is turned on, the first reference control signal RE1 is low, and the first reset transistor T1 is turned off. The data signal Data is written to node N5 via the write transistor T4 and stored in the first capacitor C1. The second reference control signal RE2 continues to maintain a high level, causing the second reset transistor T2 to continue to conduct and remain on until the write transistor T4 turns off. This stabilizes the voltage at node N4 and prevents interference between the data signal Data stored in the first and second capacitors C1 and C2 and the threshold voltage. Simultaneously, the reset control signal RE3 is low, and the third reset transistor T7 is turned off. The low level of the second emission control signal EM2 persists until the write transistor T4 turns off, completing the writing of the data signal Data.

[0213] In light-emitting phase t4, the first and second light-emitting control signals EM1 and EM2 are high, turning on the first and second light-emitting control transistors T5 and T6. The first and second reference control signals RE1 and RE2 are low, turning off the first and second reset transistors T1 and T2. The reset control signal RE3 is low, turning off the third reset transistor T7. The scan signal Gate is low, turning off the write transistor T4. Under the action of the first capacitor C1, the data signal Data begins to be written to point N1. At this time, the voltage at node N1, i.e., the gate voltage of the driving transistor T3, Vg, is Vdata + Vld + VSS - (Vref - Vth). The voltage at node N3, i.e., the voltage at the first electrode of the driving transistor T3, Vs, is Vld + VSS. Therefore, the gate-source voltage difference Vgs of the driving transistor T3 is Vdata - Vref + Vth. Vld is the voltage of the light-emitting device LD, VSS is the voltage of the second power supply signal VSS input to the second electrode CAT of the light-emitting device LD, and Vdata is the voltage of the data signal Data.

[0214] The output current of the pixel circuit is I = (μWCox / 2L)(Vgs-Vth) 2 ; I is also the output current of the driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0215] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current of the driving transistor T3 I = (μWCox / 2L)(Vdata-Vref) 2 It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light-emitting device LD. The specific principle can be referred to the description of the current formula in the embodiment of the first type of pixel circuit above, and will not be repeated here.

[0216] The following describes the structure of the pixel circuit according to the second embodiment of the second type of pixel circuit and its driving method:

[0217] As shown in FIG7 and FIG8 , the driving method may include:

[0218] In the compensation phase t2 , the first light emitting control circuit EU1 is turned on and the second light emitting control circuit EU2 is turned off, so as to write the threshold voltage of the driving transistor T3 into the energy storage circuit RU.

[0219] When the first light emitting control circuit EU1 is turned on, the voltage of the first electrode of the driving transistor T3 gradually increases, and the threshold voltage of the driving transistor T3 is written into the energy storage circuit RU.

[0220] In the writing phase t3 , the writing circuit DU and the first light emitting control circuit EU1 are turned on, the second light emitting control circuit EU2 is turned off, and the data signal Data is written into the energy storage circuit RU through the writing circuit DU.

[0221] When the voltage of the first electrode of the driving transistor T3 reaches the difference between the voltage of its gate and the threshold voltage, the driving transistor T3 is turned off, so that the threshold voltage of the driving transistor T3 can be written into the energy storage circuit RU. In other words, the writing of the threshold voltage and the writing of the data signal Data can be performed independently.

[0222] In the light emitting stage t4, the first light emitting control circuit EU1 and the second light emitting control circuit EU2 are turned on, the writing circuit DU is turned off, and the voltage difference between the gate and the first electrode of the driving transistor T3 is controlled by the energy storage circuit RU to make the light emitting device LD emit light.

[0223] Furthermore, as shown in FIG7 and FIG8 , in some embodiments of the present disclosure, the driving method may further include:

[0224] In the reset stage t1, the first reset transistor T1, the second reset transistor T2 and the third reset transistor T7 and the second light-emitting control circuit EU2 are turned on, and the write circuit DU and the first light-emitting control circuit EU1 are turned off; the gate of the driving transistor T3 is reset by the reference signal Vref, and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are reset, and the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2 are reset by the reset signal Vinit; at the same time, the driving transistor T3 can be turned on by the voltage difference between the reset signal Vinit and the reference signal Vref.

[0225] In the aforementioned pixel circuit driving method, the data signal Data and the threshold voltage of the driving transistor T3 can be stored separately via the energy storage circuit RU. Storage of the data signal Data by the energy storage circuit RU does not interfere with the storage of the threshold voltage. This ensures that the voltage differential between the data signal Data and the first electrode of the driving transistor T3 remains stable during the light-emitting phase, preventing significant differences between the actual brightness and the designed brightness of the light-emitting device LD due to varying degrees of interference from different data signals Data, thereby improving image quality. Furthermore, the gate of the driving transistor T3 can be directly connected to the write circuit DU, rather than through the data control circuit CU. This prevents coupling effects caused by the on / off state of the data control circuit CU from affecting the voltage at the gate of the driving transistor T3.

[0226] As shown in FIG7 and FIG8 , the second embodiment of the second type of pixel circuit is taken as an example to exemplify the driving method of the pixel circuit.

[0227] Each transistor in the pixel circuit is an N-type metal oxide transistor.

[0228] During reset phase t1, the first and second reference control signals RE1 and RE2 are high, turning on the first and second reset transistors T1 and T2. The reference signal Vref resets nodes N1 and N4, and the voltage of the reference signal Vref can be 2.5V. The second emission control signal EM2 is high, turning on the second emission control transistor T6. The reset control signal RE3 is high, turning on the third reset transistor T7, and resetting the N3 node with a reset signal Vinit, which can be 1.5V. At this point, a voltage difference exists between the gate and the first electrode of the driving transistor T3, and the driving transistor T3 is turned on.

[0229] At the same time, the first light emitting control signal EM1 is at a low level, and the first light emitting control transistor T5 is turned off; the scanning signal Gate is at a low level, and the writing transistor T4 is turned off.

[0230] The N1 node, the N3 node, and the N4 node can be reset sequentially. For example, the first reference control signal RE1 and the second reference control signal RE2 are first changed from a low level to a high level, and then the reset control signal RE3 is changed from a low level to a high level; the first reset transistor T1 and the second reset transistor T2 are turned on first, and then the third reset transistor T7 is turned on.

[0231] During compensation phase t2, the first emission control signal EM1 is high, the first emission control transistor T5 is turned on, and the voltage at node N2 is equal to the voltage of the first power supply signal VDD. Due to the conduction of the driving transistor T3, the voltage at node N3 gradually increases until it reaches Vref-Vth, causing the voltage difference between the gate and the first electrode of the driving transistor T3 to equal the threshold voltage, i.e., gate-source voltage difference Vgs=Vth. At this point, the driving transistor T3 is turned off; Vth is the threshold voltage of the driving transistor T3. Consequently, the threshold voltage Vth is written to node N3 and stored in the second capacitor C2. The first emission control signal EM1 continues until the driving transistor T3 is turned off, i.e., until the threshold voltage is written. The voltage of the first power supply signal VDD can be 11.5V.

[0232] At the same time, the second light-emitting control signal EM2 is at a low level, so that the second light-emitting control transistor T6 is turned off; the first reference control signal RE1 and the second reference control signal RE2 are at a high level, and the first reset transistor T1 and the second reset transistor T2 are turned on; the reset control signal RE3 is at a low level, and the third reset transistor T7 is turned off; the scanning signal Gate is at a low level, and the write transistor T4 is turned off.

[0233] In the write phase t3, the scan signal Gate is at a high level, the write transistor T4 is turned on, the first reference control signal RE1 is at a low level, and the first reset transistor T1 is turned off; the data signal Data is written to the N5 node through the write transistor T4, that is, stored in the first capacitor C1, and the low level of the second light-emitting control signal EM2 can continue until the write transistor T4 is turned off, that is, after the writing of the data signal Data is completed.

[0234] The second reference control signal RE2 remains high, keeping the second reset transistor T2 on until the write transistor T4 turns off. This stabilizes the voltage at node N4 and prevents interference between the data signal Data stored in the first capacitor C1 and the second capacitor C2 and the threshold voltage. Simultaneously, the reset control signal RE3 is low, turning off the third reset transistor T7.

[0235] In light-emitting phase t4, the first and second light-emitting control signals EM1 and EM2 are high, turning on the first and second light-emitting control transistors T5 and T6. The first and second reference control signals RE1 and RE2 are low, turning off the first and second reset transistors T1 and T2. The reset control signal RE3 is low, turning off the third reset transistor T7. The scan signal Gate is low, turning off the write transistor T4. Under the action of the first capacitor C1, the data signal Data begins to be written to point N1. At this time, the voltage at node N1, i.e., the gate voltage of the driving transistor T3, Vg, is Vdata + Vld + VSS - (Vref - Vth). The voltage at node N3, i.e., the voltage at the first electrode of the driving transistor T3, Vs, is Vld + VSS. Therefore, the gate-source voltage difference Vgs of the driving transistor T3 is Vdata - Vref + Vth. Vld is the voltage of the light-emitting device LD, VSS is the voltage of the second power supply signal VSS input to the second electrode CAT of the light-emitting device LD, and Vdata is the voltage of the data signal Data.

[0236] The output current of the pixel circuit is I = (μWCox / 2L)(Vgs-Vth) 2 ; I is also the output current of the driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0237] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current of the driving transistor T3 I = (μWCox / 2L)(Vdata-Vref) 2 It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light-emitting device LD. The specific principle can be referred to the description of the current formula in the first embodiment above, and will not be repeated here.

[0238] The third type of pixel circuit

[0239] As shown in FIG9 , the pixel circuit may include a driving transistor T3, a storage circuit RU, a writing circuit DU, and a first light emitting control circuit EU1, but does not include the second light emitting control circuit EU2 mentioned above, wherein:

[0240] The gate of the driving transistor T3 is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU, and the first electrode of the driving transistor T3 is used to be connected to the light-emitting device LD. The second electrode of the driving transistor T3 is connected to the first light-emitting control circuit EU1, and the first light-emitting control circuit EU1 is used to receive the first power supply signal VDD;

[0241] The write circuit DU is connected to the gate of the driving transistor T3; the write circuit DU is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU; the first electrode of the driving transistor T3 can be directly connected to the light emitting device LD without being indirectly connected through the second light emitting control circuit EU2.

[0242] The write circuit DU is used to write the data signal Data into the tank circuit RU; the tank circuit RU is used to store the data signal Data and the voltage of the first electrode of the driving transistor T3.

[0243] The energy storage circuit RU can store the data signal Data and the voltage of the first electrode of the driving transistor T3 respectively, so as to stabilize the voltage difference between the first electrode and the gate of the driving transistor T3, which is beneficial to ensure that the light emitting device LD emits light stably, thereby improving the picture quality.

[0244] As shown in FIG9 , in some embodiments of the present disclosure, the energy storage circuit RU may include a first capacitor C1 and a second capacitor C2 connected in series; the write circuit DU may include a write transistor T4 ; and the first light emission control circuit EU1 may include a first light emission control transistor T5 .

[0245] The first electrode of the write transistor T4 is used to input the data signal Data. The second electrode of the write transistor T4 is connected to the gate of the drive transistor T3 and the first plate C11 of the first capacitor C1, and can be connected to the N5 node. The second plate C12 of the first capacitor C1 is connected to the first plate C21 of the second capacitor C2, and can be connected to the N4 node. The second plate C22 of the second capacitor C2 is connected to the first electrode of the drive transistor T3, and can be connected to the N3 node. The first electrode of the first light-emitting control transistor T5 is used to receive the first power supply signal VDD. The second electrode can be connected to the second electrode of the drive transistor T3, and the second electrode can be connected to the N2 node. The first electrode of the drive transistor T3 and the second plate C22 of the second capacitor C2 can be connected to the N3 node. The first electrode ANO of the light-emitting device LD is also connected to the N3 node.

[0246] The gate of the write transistor T4 receives a scan signal Gate and is turned on or off under the control of the scan signal Gate. The gate of the first emission control transistor T5 receives a first emission control signal EM1 and is turned on or off under the control of the first emission control signal EM1.

[0247] In order to eliminate the influence of the signal of the previous frame image, before displaying the signal input of the current frame, the gate and the first electrode of the driving transistor T3 may be reset. At the same time, the energy storage circuit RU may also be reset. As shown in FIG2 , in some embodiments of the present disclosure, the pixel circuit may further include a first reset transistor T1 and a second reset transistor T2, wherein:

[0248] The first electrode of the first reset transistor T1 is used to receive the reference signal Vref, and the second electrode is connected to the gate of the driving transistor T3. As shown in FIG2 , the second electrode of the first reset transistor T1 and the gate of the driving transistor T3 are connected to the N1 node.

[0249] A first electrode of the second reset transistor T2 is used to receive a reference signal Vref, and a second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2. As shown in FIG2 , the second electrode of the second reset transistor T2 and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are connected to the N4 node.

[0250] The gate of the first reset transistor T1 can receive a first reference control signal RE1 and be turned on or off under the control of the first reference control signal RE1. The gate of the second reset transistor T2 can receive a second reference control signal RE2 and be turned on or off under the control of the second reference control signal RE2. The first reference control signal RE1 and the second reference control signal RE2 can be synchronous signals, so that the first reset transistor T1 and the second reset transistor T2 can be turned on or off synchronously. Of course, the first reference control signal RE1 and the second reference control signal RE2 can also be asynchronous.

[0251] The reference signal Vref can be input to the N1 and N4 nodes through the first reset transistor T1 and the second reset transistor T2 to eliminate the influence of the signal when displaying the previous frame image.

[0252] Furthermore, in some embodiments, the first reference control signal RE1 for the gate of the first reset transistor T1 of the pixel circuit in the n+1th row and the second reference control signal RE2 for the gate of the second reset transistor T2 of the pixel circuit in the nth row can be the same signal, where n is a positive integer. Thus, the first reset transistor T1 of the pixel circuit in the n+1th row and the second reset transistor T2 of the pixel circuit in the nth row can be simultaneously controlled by the same shift register, i.e., one shift register can simultaneously control multiple rows of pixel circuits, which helps reduce the number of shift registers and simplify the structure.

[0253] The pixel circuit also includes a third reset transistor T7, whose second electrode can be connected to the first electrode of the drive transistor T3 and the second plate C22 of the second capacitor C2, and can be connected to the N3 node. The gate of the third reset transistor T7 can receive a reset control signal RE3 and be turned on or off under the control of the reset control signal RE3. The third reset transistor T7 can input a reset signal Vinit to the N3 node, thereby resetting the first electrode of the drive transistor T3, the second plate C22 of the second capacitor C2, and the first electrode ANO of the light-emitting device LD, thereby eliminating the influence of the signal of the previous frame.

[0254] At least one of the transistors in the above-mentioned pixel circuit can be a metal oxide transistor, that is, the material of the active portion of the transistor includes a metal oxide such as IGZO (indium gallium zinc oxide). Accordingly, the transistor can be an N-type transistor. As shown in Figure 9, if each transistor can be an N-type transistor, the first electrode of each transistor is the source electrode, and the second electrode is the drain electrode. The transistor is turned on when the gate electrode receives a high level and turned off when the gate electrode receives a low level. For example, as shown in Figure 9, the drive transistor T3, the write transistor T4, the first reset transistor T1, the second reset transistor T2, the third reset transistor T7, and the first light-emitting control transistor T5 are all metal oxide transistors, that is, the transistors of the pixel circuit are all metal oxide transistors to reduce leakage current. Of course, only some of the transistors can be metal oxide transistors.

[0255] The following uses the third type of pixel circuit as an example to illustrate the driving method of the pixel circuit:

[0256] Each transistor in the pixel circuit is an N-type metal oxide transistor.

[0257] During the reset phase, the first and second reference control signals RE1 and RE2 are high, turning on the first and second reset transistors T1 and T2. The reference signal Vref resets nodes N1 and N4, and the voltage of the reference signal Vref can be 2.5V. The reset control signal RE3 is high, turning on the third reset transistor T7, and resetting the node N3 with the reset signal Vinit, which can be 1.5V. At this point, a voltage difference exists between the gate and the first electrode of the driving transistor T3, and the transistor is turned on.

[0258] At the same time, the first light emitting control signal EM1 is at a low level, and the first light emitting control transistor T5 is turned off; the scanning signal Gate is at a low level, and the writing transistor T4 is turned off.

[0259] The N1 node, the N3 node, and the N4 node can be reset sequentially. For example, the first reference control signal RE1 and the second reference control signal RE2 are first changed from a low level to a high level, and then the reset control signal RE3 is changed from a low level to a high level; the first reset transistor T1 and the second reset transistor T2 are turned on first, and then the third reset transistor T7 is turned on.

[0260] During the compensation phase, the first emission control signal EM1 is high, the first emission control transistor T5 is turned on, and the voltage at node N2 is equal to the voltage of the first power supply signal VDD. As the driver transistor T3 is turned on, the voltage at node N3 gradually increases until it reaches Vref-Vth, causing the voltage difference between the gate and the first electrode of the driver transistor T3 to equal the threshold voltage, i.e., gate-source voltage difference Vgs=Vth. At this point, the driver transistor T3 is turned off; Vth is the threshold voltage of the driver transistor T3. Consequently, the threshold voltage Vth is written to node N3 and stored in the second capacitor C2. The first emission control signal EM1 can continue until the driver transistor T3 is turned off, i.e., until the threshold voltage is written. The voltage of the first power supply signal VDD can be 11.5V.

[0261] At the same time, the first reference control signal RE1 and the second reference control signal RE2 are high, the first reset transistor T1 and the second reset transistor T2 are turned on; the reset control signal RE3 is low, the third reset transistor T7 is turned off; the scan signal Gate is low, and the write transistor T4 is turned off.

[0262] In the writing phase t3 , the scanning signal Gate is high, the writing transistor T4 is turned on, the first reference control signal RE1 is low, and the first reset transistor T1 is turned off; the data signal Data is written to the N5 node through the writing transistor T4 , that is, stored in the first capacitor C1 .

[0263] The second reference control signal RE2 remains high, keeping the second reset transistor T2 on until the write transistor T4 turns off. This stabilizes the voltage at node N4 and prevents interference between the data signal Data stored in the first capacitor C1 and the second capacitor C2 and the threshold voltage. Simultaneously, the reset control signal RE3 is low, turning off the third reset transistor T7.

[0264] During light-emitting phase t4, the first light-emitting control signal EM1 is high, turning on the first light-emitting control transistor T5. The first reference control signal RE1 and the second reference control signal RE2 are low, turning off the first reset transistor T1 and the second reset transistor T2. The reset control signal RE3 is low, turning off the third reset transistor T7. The scan signal Gate is low, turning off the write transistor T4. Under the action of the first capacitor C1, the data signal Data begins to be written to point N1. The voltage at node N1, i.e., the gate voltage of the driving transistor T3, is Vg = Vdata + Vld + VSS - (Vref - Vth). The voltage at node N3, i.e., the voltage at the first electrode of the driving transistor T3, is Vs = Vld + VSS. The gate-source voltage difference Vgs of the driving transistor T3 is Vdata - Vref + Vth. Vld is the voltage of the light-emitting device LD, VSS is the voltage of the second power supply signal VSS input to the second electrode CAT of the light-emitting device LD, and Vdata is the voltage of the data signal Data.

[0265] The output current of the pixel circuit is I = (μWCox / 2L)(Vgs-Vth) 2 ; I is also the output current of the driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0266] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current of the driving transistor T3 I = (μWCox / 2L)(Vdata-Vref) 2 It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light-emitting device LD. The specific principle can be referred to the description of the current formula in the first embodiment above, and will not be repeated here.

[0267] The main difference between the driving method of the third type of pixel circuit and the driving method of the second type of pixel circuit mentioned above is that the third type of pixel circuit does not have a second light-emitting control circuit EU2 and a second light-emitting control transistor T6, and there is no second light-emitting control signal EM2, which will not be described in detail here.

[0268] It should be noted that although the steps of the driving method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0269] The structure of the display panel is described below based on the second type of pixel circuit described above:

[0270] As shown in FIG2 , the driving backplane BP may include a substrate SU and a driving circuit provided on one side of the substrate SU. The driving circuit includes a pixel circuit and a peripheral circuit. The pixel circuit may be a structure of any of the above embodiments.

[0271] As shown in Figure 2 , the driving backplane BP may further include a semiconductor layer SE, which is disposed on one side of the substrate SU. The active portions of the transistors in the pixel circuit are located in the semiconductor layer SE, i.e., the active portions of the transistors are arranged in the same layer. Light-emitting devices LD are disposed on a side of the semiconductor layer SE away from the substrate SU, and a first electrode ANO of a light-emitting device LD can be connected to the first electrode of a driving transistor T3 in a pixel circuit.

[0272] As shown in FIG10 to FIG12 , FIG19 , FIG21 and FIG22 , to facilitate signal transmission, in some embodiments of the present disclosure, the display panel may further include a first light emitting control line EML1, a second light emitting control line EML2, a first reset control line REL1, a second reset control line REL2, a third reset control line REL3, a scan line GL, a first reset line VRL and a second reset line VIL, wherein:

[0273] The first emission control line EML1 can extend along the row direction X and overlap with and be connected to the gate of the first emission control transistor T5 to transmit a first emission control signal EM1. Multiple first emission control lines EML1 are provided and spaced apart along the column direction Y. Pixel circuits in the same row are connected to a first emission control line EML1.

[0274] The scan line GL may extend along the row direction X and overlap and connect with the gate of the write transistor T4 for transmitting the scan signal Gate. There are multiple scan lines GL and they are spaced apart along the column direction Y. Each pixel circuit in the same row is connected to a scan line GL.

[0275] The first reset control line REL1 can extend along the row direction X and overlap with and be connected to the gate of the first reset transistor T1 for transmitting a first reference control signal RE1. There are multiple first reset control lines REL1, spaced apart along the column direction Y. Each pixel circuit in a row is connected to a first reset control line REL1.

[0276] A first reset line VRL can extend along the row direction X and be connected to the first electrode of the first reset transistor T1 and the first electrode of the second reset transistor T2 for transmitting a reference signal Vref. Multiple first reset lines VRL are provided and spaced apart along the column direction Y. Pixel circuits in the same row are connected to a first reset line VRL.

[0277] The second reset control line REL2 can extend along the row direction X and overlap with and be connected to the gate of the second reset transistor T2 for transmitting a second reference control signal RE2. A plurality of second reset control lines REL2 are provided and spaced apart along the column direction Y, with two rows of pixel circuits connected to the second reset control lines REL2.

[0278] The second emission control line EML2 extends along the row direction X and overlaps and is connected to the gate of the second emission control transistor T6. It is used to transmit a second emission control signal EM2. There are multiple second emission control lines EML2, which are spaced apart along the column direction Y. Pixel circuits in the same row are connected to a second emission control line EML2.

[0279] The third reset control line REL3 extends along the row direction X and overlaps and is connected to the gate of the third reset transistor T7. It is used to transmit a reset control signal RE3. There are multiple third reset control lines REL3, which are spaced apart along the column direction Y. Each pixel circuit in a row is connected to a third reset control line REL3.

[0280] The second reset line VIL can extend along the row direction X and be connected to the first electrode of the third reset transistor T7 for transmitting the reset signal Vinit. There are multiple second reset lines VIL, which are spaced apart along the column direction Y. Pixel circuits in the same row are connected to a second reset line VIL.

[0281] Furthermore, as shown in Figures 10 to 12, 19, 21 and 22, in some embodiments of the present disclosure, for the wiring connected to a pixel circuit, its first light-emitting control line EML1, the scanning line GL, the first reset control line REL1, the first reset line VRL, the second reset control line REL2, the second light-emitting control line EML2, the third reset control line REL3 and the second reset line VIL can be distributed in sequence along the column direction Y, that is, the orthographic projections of the aforementioned wirings on the substrate SU can be distributed in sequence along the column direction Y.

[0282] As shown in Figures 10-13, 19, and 21-24, the orthographic projection of the active portion ACT3 of the drive transistor T3 on the substrate SU is located between the orthographic projection of the scan line GL and the first reset control line REL1 on the substrate SU. The orthographic projection of the active portion ACT1 of the first reset transistor T1 on the substrate SU is located between the orthographic projection of the scan line GL and the first reset line VRL on the substrate SU; the orthographic projection of the active portion ACT2 of the second reset transistor T2 on the substrate SU is located between the orthographic projection of the first reset line VRL and the second emission control line EML2 on the substrate SU; and the orthographic projection of the active portion ACT7 of the third reset transistor T7 on the substrate SU is located between the orthographic projection of the second emission control line EML2 and the second reset line VIL on the substrate SU.

[0283] As shown in Figures 10, 20, and 21, to provide a first power signal VDD to the pixel circuits, in some embodiments of the present disclosure, the display panel further includes a plurality of first power lines VDL, which may be disposed on a side of the pixel circuits away from the substrate SU. The first power lines VDL may extend along the column direction Y, and the first power lines VDL may be spaced apart along the row direction X. A first power line VDL overlaps a column of pixel circuits and is connected to the first electrode of the first emission control transistor T5 of the pixel circuit in that column, thereby providing the first power signal VDD to the pixel circuits.

[0284] As shown in Figures 10, 11, 19, 21, and 22, to reduce resistance, multiple first auxiliary power lines VDLs can be provided on the side of the pixel circuits facing away from the substrate SU. The first power lines VDL are located on the side of the first auxiliary power lines VDLs facing away from the substrate SU. Each first auxiliary power line VDLs can extend in the row direction X and be distributed in the column direction Y. A first auxiliary power line VDLs can be provided between two adjacent rows of pixel circuits. A first auxiliary power line VDLs is connected to the first electrode of the first emission control transistor T5 of the pixel circuit in the row to which it is attached. A first power line VDL is located on a different layer from each of the first auxiliary power lines VDLs and is connected via contact holes. The first power line VDL can be connected to the pixel circuits via the first auxiliary power lines VDLs. The first power line VDL and the first auxiliary power lines VDLs can form a network within the space to transmit the first power signal VDD, which helps reduce resistance. Of course, in some embodiments of the present disclosure, the first power line VDL or the first auxiliary power line VDLs may not be provided, as long as the first power signal VDD can be transmitted to the first electrode of the first light emitting control transistor T5.

[0285] As shown in Figures 10, 11, 19, 21, and 22, in order to provide data signals Data to the pixel circuits, the display panel may further include a plurality of data lines DAL, which may be provided on a side of the first auxiliary power line VDLs away from the substrate SU and may be provided on the same layer as the first power line VDL. Each data line DAL may extend along the column direction Y and be spaced apart along the row direction X. A data line DAL overlaps with a column of pixel circuits and is connected to the first electrode of the write transistor T4 of the column of pixel circuits for transmitting the data signal Data. However, the pixel circuits overlapped by the data line DAL may be adjacent to the pixel circuits connected thereto. Of course, if space permits, the data line DAL may also be arranged to overlap with the pixel circuits connected thereto, for example, in the second embodiment of the display panel described below (see Figure 36), as described below for details.

[0286] As shown in Figures 10, 11, 19, 21, and 22, in some embodiments of the present disclosure, the display panel further includes a plurality of second power lines VSL, which may be disposed on a side of the first auxiliary power line VDLs away from the substrate SU. Each second power line VSL extends along the column direction Y and is spaced apart along the row direction X. A second power line VSL may overlap with a column of pixel circuits, but the number of second power lines VSL may be less than the number of pixel circuit columns, i.e., only some columns of pixel circuits may overlap with a second power line VSL. The second power lines VSL are used to transmit a second power signal VSS.

[0287] As shown in Figures 10-14, 16, 21, and 24, in some embodiments of the present disclosure, the display panel further includes second auxiliary power lines VSLs, which may be disposed on a side of the substrate SU near the semiconductor layer SE. The second auxiliary power lines VSLs extend in the row direction X and are distributed in the column direction Y. The second auxiliary power lines VSLs can transmit a second power signal VSS. The orthographic projection of the second auxiliary power lines VSLs on the substrate SU is located between the orthographic projections of the second emission control line EML2 and the third reset control line REL3 on the substrate SU. Furthermore, a second power line VSL and each of the second auxiliary power lines VSLs are located on different layers and connected via contact holes. The second power line VSL can be connected to the pixel circuits via the second auxiliary power lines VSLs, and the second power lines VSL and the second auxiliary power lines VSLs can form a network within the space that transmits the second power signal VSS, thereby reducing resistance. Of course, in some embodiments of the present disclosure, the second power line VSL or the second auxiliary power lines VSLs may not be provided, as long as they can transmit the second power signal VSS.

[0288] In addition, the peripheral area WA of the display panel may also be provided with a first power bus and a second power bus. Part or all of the first power line VDL and the first auxiliary power line VDLs may extend into the peripheral area WA and be connected to the first power bus. A first power signal VDD may be input to the first power line VDL via the first power bus. Part or all of the second power line VSL and the second auxiliary power line VSLs may extend into the peripheral area WA and be connected to the second power bus. A second power signal VSS may be input to the second power line VSL via the second power bus. Each light-emitting device LD may share the same second electrode CAT. That is, the second electrode CAT may be a continuous, single-layer structure and may be connected to the second power bus in the peripheral area WA to receive the second power signal VSS. The second power line VSL reduces resistance and thus reduces the voltage drop of the second power signal VSS.

[0289] As shown in FIG10 , FIG11 , FIG19 , and FIG20 - FIG22 , in some embodiments of the present disclosure, the display panel further includes a plurality of first auxiliary reset lines VRLs and second auxiliary reset lines VILs, wherein:

[0290] The first auxiliary reset lines VRLs and the second auxiliary reset lines VILs can be arranged on a side of the first auxiliary power line VDLs away from the substrate SU. The first auxiliary reset lines VRLs and the second auxiliary reset lines VILs can be arranged on the same layer, or alternatively, on different layers. Each first auxiliary reset line VRLs and second auxiliary reset line VILs extends in the column direction Y and is spaced apart in the row direction X.

[0291] The first auxiliary reset line VRLs can be located on a different layer from the first reset line VRL and can be connected via a contact hole. The first auxiliary reset line VRLs and the first reset line VRL can form a network within the space for transmitting the reference signal Vref, which helps reduce resistance. The second auxiliary reset line VILs can be located on a different layer from the second reset line VIL and can be connected via a contact hole. The second auxiliary reset line VILs and the second reset line VIL can form a network within the space for transmitting the reset signal Vinit, which helps reduce resistance.

[0292] A first auxiliary reset line VRLs may overlap with a column of pixel circuits, and a second auxiliary reset line VILs may overlap with a column of pixel circuits; however, the number of first auxiliary reset lines VRLs and second auxiliary reset lines VILs is less than the number of columns of pixel circuits, that is, only some columns of pixel circuits may overlap with the first auxiliary reset lines VRLs and the second auxiliary reset lines VILs.

[0293] In some embodiments of the present disclosure, as shown in Figures 10, 21, 26, 27, and 35, the data lines DAL and first power lines VDL connected to the same column of pixel circuits PC can be defined as a column line group YG. That is, each column of pixel circuits PC can be connected to a column line group YG. Furthermore, one of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs can be provided between the data line DAL and the first power line VDL of the same column line group YG. In other words, the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs are distributed in the space between the data line DAL and the first power line VDL of the column line group YG. This allows for efficient space utilization.

[0294] As shown in Figures 10, 11, 19, 21, 22, 26-28, and 34, in some embodiments of the present disclosure, the first emission control line EML1, scan line GL, first reset control line REL1, first reset line VRL, second reset control line REL2, second emission control line EML2, second auxiliary power line VSLs, and third reset control line REL3 connected to the same row of pixel circuits can be defined as a row line group, that is, each row of pixel circuits is connected to a row line group. At the same time, a first auxiliary power line VDLs and a second reset line VIL can be provided between two adjacent row line groups. A row line group is located between a first auxiliary power line VDLs and a second reset line VIL.

[0295] In some embodiments of the present disclosure, the first light-emitting control line EML1, the second light-emitting control line EML2, the first reset control line REL1, etc. can adopt a single-layer or multi-layer structure, and if a multi-layer structure is adopted, it may include two or more sub-layers, and adjacent sub-layers can be connected through contact holes, so that the resistance can be reduced through multiple sub-layers.

[0296] To simplify the structure and process, one of the first plate C11 and the second plate C12 of the first capacitor C1 can be placed on the same layer as one of the first plate C21 and the second plate C22 of the second capacitor C2. The co-located films can be formed simultaneously through the same patterning process, which helps simplify the structure and process. Furthermore, one of the first capacitor C1 and the second capacitor C2 can overlap with the active portion ACT3 of the drive transistor T3, allowing the capacitor plate to serve as the gate of the drive transistor T3, which also helps save space.

[0297] As shown in Figures 10 to 14 and Figures 21 to 25, in the first display panel, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are arranged in the same layer and are spaced apart along the column direction Y; the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are arranged in the same layer and are spaced apart along the column direction Y.

[0298] As shown in Figures 36 to 41, in the second display panel, the first plate C11 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are arranged in the same layer and are spaced apart along the column direction Y; the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are arranged in the same layer and are an integrated structure.

[0299] In some embodiments of the present disclosure, the orthographic projections of the first capacitor C1 and the second capacitor C2 on the substrate SU are located on a side of the second reset control line REL2 that is close to the first auxiliary power line VDLs, and the first capacitor C1 at most partially overlaps with the first auxiliary power line VDLs. The first emission control line EML1 overlaps with the first capacitor C1, the scan line GL overlaps with the first capacitor C1, the first reset control line REL1 overlaps with the second capacitor C2, and the first reset line VRL overlaps with the second capacitor C2.

[0300] In some embodiments of the present disclosure, for a pixel circuit, the active portion ACT5 of the first light-emitting control transistor T5 overlaps with the first plate C11 and second plate C12 of the first capacitor C1. The first plate C21 and second plate C22 of the second capacitor C2 overlap with the active portion ACT3 of the driving transistor T3. The active portions of other transistors may not overlap with the first capacitor C1 and second capacitor C2.

[0301] The following is an example of the pattern of the semiconductor layer corresponding to a pixel circuit:

[0302] As shown in FIG. 12 , FIG. 13 , FIG. 17 , FIG. 23 - FIG. 25 , and FIG. 40 - FIG. 42 , in some embodiments of the present disclosure, the semiconductor layer SE may include a first semiconductor portion SE1 and a second semiconductor portion SE2 spaced apart along a row direction X, wherein:

[0303] The active portion ACT4 of the write transistor T4, the active portion ACT1 of the first reset transistor T1, and the active portion ACT2 of the second reset transistor T2 are all located in the first semiconductor portion SE1 and are connected in sequence. The active portion ACT5 of the first emission control transistor T5, the active portion ACT3 of the drive transistor T3, the active portion ACT6 of the second emission control transistor T6, and the active portion ACT7 of the third reset transistor T7 are located in the second semiconductor portion SE2 and are connected in sequence.

[0304] In some embodiments of the present disclosure, the first semiconductor portion SE1 includes a first semiconductor segment SE11 , a second semiconductor segment SE12 , and a third semiconductor segment SE13 , wherein:

[0305] The first semiconductor segment SE11 and the third semiconductor segment SE13 may extend along the column direction Y and be spaced apart along the row direction X. The third semiconductor segment SE13 is located between the first semiconductor segment SE11 and the second semiconductor portion SE2. The second semiconductor segment SE12 may extend along the row direction X, with one end connected to the first semiconductor segment SE11 and the other end connected to the third semiconductor segment SE13.

[0306] The active portion ACT4 of the write transistor T4 and the active portion ACT1 of the first reset transistor T1 are located in the first semiconductor segment SE11, and the active portion ACT2 of the second reset transistor T2 is located in the second semiconductor segment SE12. The third semiconductor segment SE13 is connected to the first plate C21 of the second capacitor C2.

[0307] Furthermore, as shown in Figures 12, 13, and 17, for the first embodiment of the second type of pixel circuit described above, the second electrode of the third reset transistor T7 is connected to the first electrode of the driving transistor T3 and the first electrode of the second light-emitting control transistor T6. The second semiconductor portion SE2 may include a fourth semiconductor segment SE21 and a fifth semiconductor segment SE22, wherein:

[0308] The fourth semiconductor segment SE21 extends along the column direction Y and is located on a side of the third semiconductor segment SE13 away from the first semiconductor segment SE11. The active portion ACT5 of the first emission control transistor T5, the active portion ACT3 of the driver transistor T3, and the active portion ACT6 of the second emission control transistor T6 are sequentially distributed within the fourth semiconductor segment SE21 along the column direction Y. The active portion ACT3 of the driver transistor T3 can be formed by a protrusion of the fourth semiconductor segment SE21 along the row direction X. This allows the active portion ACT3 of the driver transistor T3 to be wider than that of the other transistors, thereby increasing the width-to-length ratio of the driver transistor T3 and thereby boosting current.

[0309] The fifth semiconductor segment SE22 is connected to the region of the fourth semiconductor segment SE21 between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second light emission control transistor T6; the active portion ACT7 of the third reset transistor T7 is located in the fifth semiconductor segment SE22. For example:

[0310] As shown in Figures 13 and 17, the fifth semiconductor segment SE22 may include a first sub-segment SE221, a second sub-segment SE222, a third sub-segment SE223, and a fourth sub-segment SE224, which are connected in sequence. The first sub-segment SE221 and the third sub-segment SE223 are located on a side of the fourth semiconductor segment SE21 away from the first semiconductor portion SE1 and may extend in the row direction X. The second sub-segment SE222 and the fourth sub-segment SE224 may extend in the column direction Y. The first sub-segment SE221 is connected to a region between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second emission control transistor T6. The second sub-segment SE222 connects the first sub-segment SE221 and the third sub-segment SE223. The third sub-segment SE223 connects the fourth sub-segment SE224 and the second sub-segment SE222. The first sub-segment SE221 overlaps the second reset control line REL2, and the fourth sub-segment SE224 overlaps the third reset control line REL3.

[0311] As shown in Figures 23-25 ​​, for the second embodiment of the second type of pixel circuit described above, the second electrode of the third reset transistor T7 is connected to the second electrode of the second light-emission control transistor T6 and the light-emitting device LD. The second semiconductor portion SE2 may include a fourth semiconductor segment SE21 and a fifth semiconductor segment SE22, wherein:

[0312] The fourth semiconductor segment SE21 extends along the column direction Y and is located on a side of the third semiconductor segment SE13 away from the first semiconductor segment SE11. The active portion ACT5 of the first emission control transistor T5, the active portion ACT3 of the driving transistor T3, and the active portion ACT6 of the second emission control transistor T6 are sequentially distributed in the fourth semiconductor segment SE21 along the column direction Y. The pattern of the fourth semiconductor segment SE21 can be the same as that of the fourth semiconductor segment SE21 in the first embodiment described above and will not be described in detail here.

[0313] The fifth semiconductor segment SE22 is connected to a region of the fourth semiconductor segment SE21 that is located on a side of the active portion ACT6 of the second light-emitting control transistor T6 away from the active portion ACT3 of the driving transistor T3. At the same time, the fifth semiconductor segment SE22 can be bent toward the first semiconductor portion SE1, and the active portion ACT7 of the third reset transistor T7 is located in the fifth semiconductor segment SE22.

[0314] As shown in FIG. 28 , FIG. 29 and FIG. 33 , in some embodiments of the present disclosure, the semiconductor layer SE further includes a first auxiliary transfer portion SE3 and a second auxiliary transfer portion SE4 , wherein:

[0315] The first auxiliary transfer portion SE3 is connected to a region of the first semiconductor portion SE1 of a pixel circuit, located between the active portion ACT1 of the first reset transistor T1 and the active portion ACT2 of the second reset transistor T2. For example, the first auxiliary transfer portion SE3 is connected to the junction of the first semiconductor segment SE11 and the second semiconductor segment SE12, and extends along the column direction Y toward the next row of pixel circuits. The first auxiliary reset line VRLs can be connected to the first auxiliary transfer portion SE3 through a contact hole, thereby connecting to the first reset line VRL. Thus, the connection between the first reset line VRL and the first auxiliary reset line VRLs is achieved through the first auxiliary transfer portion SE3 of the semiconductor layer SE.

[0316] The second auxiliary transfer portion SE4 is connected to an end of the active portion ACT3 of the third reset transistor T7 in the second semiconductor portion SE2 of a pixel circuit, distal from the active portion ACT3 of the drive transistor T3. For example, the second auxiliary transfer portion SE4 is connected to an end of the fifth semiconductor segment SE22 distal from the fourth semiconductor segment SE21 and extends along the column direction Y. The second auxiliary reset line VILs can be connected to the second reset line VIL via the second auxiliary transfer portion SE4. Thus, the second reset line VIL and the second auxiliary reset line VILs can be connected via the second auxiliary transfer portion SE4 of the semiconductor layer SE.

[0317] Of course, in other embodiments of the present disclosure, the first auxiliary transfer portion SE3 and the second auxiliary transfer portion SE4 mentioned above can be replaced by means of patterns of other film layers, as long as the connection between the first reset line VRL and the first auxiliary reset line VRLs and the connection between the second reset line VIL and the second auxiliary reset line VILs can be achieved, which will not be described in detail here.

[0318] The following is an exemplary description of the film layers and patterns of the driving backplane BP:

[0319] As shown in FIG3 , in some embodiments of the present disclosure, the display panel includes a light shielding layer BSM, a first gate layer GA1, a second gate layer GA2, a first source and drain layer SD1, and a second source and drain layer SD2, wherein:

[0320] As shown in Figures 12-15, 23, 24, 30-31, and 38-40, a light shielding layer (BSM) is provided on one side of the substrate SU. The material of the light shielding layer (BSM) can be metal or other conductive and light-shielding materials. The light shielding layer (BSM) can include portions of the plates of the first capacitor (C1) and the second capacitor (C2).

[0321] As shown in Figures 12 to 18, 23, 30 to 32, and 38 to 41, the first gate layer GA1 may be disposed on a side of the light shielding layer BSM away from the substrate SU, and the first gate layer GA1 may include partial plates of the first capacitor C1 and the second capacitor C2.

[0322] As shown in FIG. 12 , FIG. 18 , FIG. 23 , FIG. 30 - FIG. 32 , and FIG. 38 , the second gate layer GA2 may be disposed on a side of the semiconductor layer SE away from the substrate SU, and include at least a gate of a portion of the transistor.

[0323] As shown in Figures 11, 19, 18, 22, 28, 34 and 37, the first source and drain layer SD1 can be arranged on the side of the second gate layer GA2 away from the substrate SU, and include a first auxiliary power line VDLs, a first light-emitting control line EML1, a scan line GL, a first reset control line REL1, a first reset line VRL, a second reset control line REL2, a second light-emitting control line EML2, a third reset control line REL3 and a second reset line VIL.

[0324] As shown in Figures 10, 20, 21, 26, 27, 35, and 36, the second source and drain layer SD2 can be arranged on the side of the first source and drain layer SD1 away from the substrate SU, and include a data line DAL, a first power line VDL, a second power line VSL, a first auxiliary reset line VRLs, and a second auxiliary reset line VILs.

[0325] Furthermore, as shown in FIG3 , in some embodiments of the present disclosure, the display panel may further include insulating film layers, including a buffer layer BUF, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a passivation layer, a first planar layer PLN1, and a second planar layer PLN2, wherein:

[0326] The buffer layer BUF can cover the light-shielding layer BSM; the first gate layer GA1 is arranged on the surface of the buffer layer BUF away from the substrate SU; the first gate insulation layer GI1 covers the first gate layer GA1; the semiconductor layer SE is arranged on the surface of the first gate insulation layer GI1 away from the substrate SU; the second gate insulation layer GI2 covers the semiconductor layer SE; the second gate layer GA2 is arranged on the surface of the second gate insulation layer GI2 away from the substrate SU; the interlayer dielectric layer ILD covers the second gate layer GA2; the first source and drain layer SD1 is arranged on the surface of the interlayer dielectric layer ILD away from the substrate SU; the passivation layer covers the first source and drain layer SD1, and the first flat layer PLN1 covers the passivation layer. Of course, the passivation layer may not be provided, and the first flat layer PLN1 directly covers the first source and drain layer SD1; the second source and drain layer SD2 is arranged on the surface of the first flat layer PLN1 away from the substrate SU; the second flat layer PLN2 covers the second source and drain layer SD2.

[0327] The first electrode ANO of the light-emitting device LD is arranged on the surface of the second flat layer PLN2 away from the substrate SU, and can be defined by the pixel definition layer PDL. Specifically, the pixel definition layer PDL and the first electrode ANO are arranged on the surface of the second flat layer PLN2 away from the substrate SU, and the pixel definition layer PDL is provided with a pixel opening exposing the first electrode ANO, and the light-emitting layer EL is at least partially arranged in the pixel opening, and the range of a pixel opening is the range of a light-emitting device LD.

[0328] The light-emitting device LD can be divided into multiple light-emitting units. A light-emitting unit includes multiple light-emitting devices with different light-emitting colors. For example, a light-emitting unit may include a first light-emitting device that emits blue light, a second light-emitting device that emits red light, and a third light-emitting device that emits green light. The sizes of the first light-emitting device, the second light-emitting device, and the third light-emitting device can be different and can be distributed in a triangular shape. Of course, other distribution methods can also be used.

[0329] In some embodiments of the present disclosure, as shown in Figure 26, the area of ​​the orthographic projection of the first light-emitting device on the substrate SU is larger than the area of ​​the orthographic projection of the second light-emitting device and the third light-emitting device on the substrate SU; accordingly, the area of ​​the orthographic projection of the first electrode ANO1 of the first light-emitting device on the substrate SU is larger than the area of ​​the orthographic projection of the first electrode ANO2 of the second light-emitting device and the first electrode ANO3 of the third light-emitting device on the substrate SU; further, the area of ​​the orthographic projection of the second light-emitting device on the substrate SU is larger than the area of ​​the orthographic projection of the third light-emitting device on the substrate SU, and accordingly, the area of ​​the orthographic projection of the first electrode ANO2 of the second light-emitting device on the substrate SU is larger than the area of ​​the orthographic projection of the first electrode ANO3 of the third light-emitting device on the substrate SU.

[0330] The following is a further explanation of the patterns of some film layers using the first display panel as an example:

[0331] Light-shielding layer BSM

[0332] As shown in Figures 12-15, 23, 24, 30-31, and 38-40, the light shielding layer BSM includes a first plate C11 of a first capacitor C1 and a first plate C21 of a second capacitor C2, which may be spaced apart along the column direction Y. The orthographic projections of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate SU may be rectangular, or other shapes. The widths of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 in the row direction X may be the same.

[0333] First gate layer GA1

[0334] As shown in Figures 12-18, 23, 30-32, and 38-41, the first gate layer GA1 includes the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2, which can be spaced apart along the column direction Y. The orthographic projections of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate SU can be rectangular, or of course, other shapes. At the same time, the widths of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 in the row direction X can be the same, and the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate SU is located within the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate SU; and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate SU is located within the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate SU.

[0335] In addition, the first gate layer GA1 may further include a second auxiliary power line VSLs. The second auxiliary power line VSLs is located on a side of the second capacitor C2 away from the first capacitor C1 and extends along the row direction X.

[0336] Semiconductor layer SE

[0337] The semiconductor layer SE may include first semiconductor portions SE1 and second semiconductor portions SE2 spaced apart along the row direction X, and may also include first auxiliary transfer portions SE3 and second auxiliary transfer portions SE4 . The specific patterns have been described above and will not be described in detail here.

[0338] The second gate layer GA2

[0339] As shown in Figures 12, 18, 23, 30-32, and 38, the second gate layer GA2 further includes a first gate portion GA21, a second gate portion GA22, a third gate portion GA23, a fourth gate portion GA24, a fifth gate portion GA25, a sixth gate portion GA26, and a seventh gate portion GA27, wherein:

[0340] The first gate portion GA21 overlaps the active portion ACT5 of the first emission control transistor T5 to form the gate of the first emission control transistor T5. The orthographic projection of the first gate portion GA21 on the substrate SU can be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT5 in the row direction X.

[0341] The second gate portion GA22 overlaps the active portion ACT4 of the write transistor T4 to form the gate of the write transistor T4. The orthographic projection of the second gate portion GA22 on the substrate SU can be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT4 in the row direction X.

[0342] The third gate portion GA23 overlaps with the active portion ACT3 of the driving transistor T3 and is connected to the third gate portion GA23 to form the gate of the driving transistor T3. The orthographic projection of the third gate portion GA23 on the substrate SU can be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT3 in the row direction X. The orthographic projections of the third gate portion GA23 and the active portion ACT3 on the substrate SU are located within the orthographic projection of the second capacitor C2 on the substrate SU. The third gate portion GA23 and the one of the two plates of the second capacitor C2 that is closer to the active portion ACT3 can both serve as the gate of the driving transistor T3, thereby forming a dual-gate structure, which is beneficial for improving the stability of the gate signal. Of course, the driving transistor T3 can also adopt a single-gate structure, and only the one of the two plates of the third gate portion GA23 or the second capacitor C2 that is closer to the active portion ACT3 can be used as the gate to simplify the structure and reduce parasitic capacitance.

[0343] The fourth gate portion GA24 overlaps the active portion ACT1 of the first reset transistor T1 to form the gate of the first reset transistor T1. The orthographic projection of the fourth gate portion GA24 on the substrate SU may be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT1 in the row direction X.

[0344] The fifth gate portion GA25 overlaps the active portion ACT2 of the second reset transistor T2 to form the gate of the second reset transistor T2. The orthographic projection of the fifth gate portion GA25 on the substrate SU may be rectangular, with a width in the column direction Y greater than or equal to the width of the active portion ACT2 in the column direction Y, and a length in the row direction X less than the length of the second semiconductor segment SE12.

[0345] The sixth gate portion GA26 overlaps the active portion ACT6 of the second emission control transistor T6 to form the gate of the second emission control transistor T6. The orthographic projection of the sixth gate portion GA26 on the substrate SU can be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT6 in the row direction X.

[0346] The seventh gate portion GA27 overlaps the active portion ACT3 of the third reset transistor T7 to form the gate of the third reset transistor T7. The orthographic projection of the seventh gate portion GA27 on the substrate SU may be rectangular, and its width in the column direction Y is greater than or equal to the width of the active portion ACT3 in the column direction Y.

[0347] The first gate portion GA21, the second gate portion GA22, the third gate portion GA23, the fourth gate portion GA24, the fifth gate portion GA25, the sixth gate portion GA26 and the seventh gate portion GA27 can be distributed in sequence in the column direction Y, and the second gate portion GA22 and the fourth gate portion GA4 can be distributed along the first semiconductor segment SE11; the fifth gate portion GA25 and the sixth gate portion GA26 are located between the second capacitor C2 and the second auxiliary power line VSLs; the first gate portion GA21, the third gate portion GA23 and the sixth gate portion GA26 can be distributed along the fourth semiconductor segment SE21; the seventh gate portion GA27 is located on the side of the second auxiliary power line VSLs away from the second capacitor C2.

[0348] First source and drain layer SD1

[0349] As shown in Figures 11, 19, 18, 22, 28, 34 and 37, the first source and drain layer SD1 may include a first auxiliary power line VDLs, a first light-emitting control line EML1, a scan line GL, a first reset control line REL1, a first reset line VRL, a second reset control line REL2, a second light-emitting control line EML2, a third reset control line REL3 and a second reset line VIL, which are sequentially distributed along the column direction Y, and the orthographic projection of the second auxiliary power line VSLs on the substrate SU is located between the orthographic projections of the second light-emitting control line EML2 and the third reset control line REL3 on the substrate SU.

[0350] The first light-emitting control line EML1 and the scan line GL may overlap with the first capacitor C1; the first reset control line REL1 and the first reset line VRL may overlap with the second capacitor C2; the second reset control line REL2, the second light-emitting control line EML2 and the third reset control line REL3 are located on the side of the second capacitor C2 away from the first capacitor C1.

[0351] The first source-drain layer SD1 may further include a first connection portion SL1, a second connection portion SL2, a third connection portion SL3, a fourth connection portion SL4, and a fifth connection portion SL5, wherein:

[0352] The first connection portion SL1 is located between the first emission control line EML1 and the scan line GL, and is connected to the data line DAL and the first electrode of the write transistor T4 through a contact hole. The data line DAL can transmit the data signal Data to the first electrode of the write transistor T4 through the first connection portion SL1.

[0353] The orthographic projection of the second connection portion SL2 on the substrate SU is located between the orthographic projection of the scan line GL and the first reset control line REL1 on the substrate SU, and is located between the orthographic projections of the first semiconductor segment SE11 and the fourth semiconductor segment SE21 on the substrate SU. The second connection portion SL2 is connected to the first plate C11 of the first capacitor C1, the third gate portion GA23, and the region of the first semiconductor portion SE1 between the active portion ACT4 of the write transistor T4 and the active portion ACT1 of the first reset transistor T1. Thus, the second connection portion SL2 can serve as part of the N1 node, connecting the first plate C11 of the first capacitor C1, the gate (top gate) of the drive transistor T3, the second electrode of the write transistor T4, and the second electrode of the first reset transistor T1. For example:

[0354] The second connecting portion SL2 may include a first connecting segment SL21 and a second connecting segment SL22. The first connecting segment SL21 has a first end that overlaps with the second plate C12 of the first capacitor C1, a second end that overlaps with the second plate C22 of the second capacitor C2, and is connected to the first end of the second connecting segment SL22. The second connecting segment SL22 overlaps with the second plate C22 of the second capacitor C2, and the second end of the second connecting segment SL22 extends toward the first semiconductor segment SE11. The second end of the first connecting segment SL21 extends in a direction away from the fourth semiconductor segment SE21, such that the first connecting segment SL21 is tilted away from the active portion ACT3 of the driving transistor T3 and does not overlap with the active portion ACT3. The second connecting segment SL22 may extend along the row direction X.

[0355] The second plate C12 of the first capacitor C1 is provided with a first capacitor hole C121. The first end of the second connection portion SL2 can be connected to the first plate C11 of the first capacitor C1 via a contact hole passing through the first capacitor hole C121. The second end of the first connection segment SL21 and the first end of the second connection portion SL2 can be connected to the third gate portion GA23 via a contact hole. The first semiconductor segment SE11 includes a semiconductor connection portion SEL located between the active portion ACT4 of the write transistor T4 and the active portion ACT1 of the first reset transistor T1. The semiconductor connection portion SEL can extend along the row direction X to a position overlapping with the second plate C12 of the second capacitor C2 and the second end of the second connection portion SL2, and can be connected to the second end of the second connection portion SL2 via a contact hole.

[0356] The third connection portion SL3 is located, as an orthographic projection on the substrate SU, between the scan line GL and the orthographic projection of the first reset control line REL1, and between the orthographic projection of the first semiconductor segment SE11 and the second connection portion SL2. The third connection portion SL3 is connected to the second electrode of the second reset transistor T2, the second plate C12 of the first capacitor C1, and the first plate C21 of the second capacitor C2. Thus, the third connection portion SL3 functions as part of the N4 node, connecting the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2.

[0357] In some embodiments, the third connection portion SL3 overlaps with a region of the first semiconductor portion SE1 between the active portion ACT4 of the write transistor and the active portion ACT1 of the first reset transistor T1. For example, the third connection portion SL3 may include a third connection segment SL31, a fourth connection segment SL32, and a fifth connection segment SL33 connected in sequence, wherein:

[0358] The third connection segment SL31 is connected to the second plate C12 of the first capacitor C1 through a contact hole; the fourth connection segment SL32 can extend along the column direction Y and overlap with the area in the first semiconductor segment SE11 located between the active part ACT4 of the write transistor and the active part ACT1 of the first reset transistor T1; the second plate C22 of the second capacitor C2 is provided with a second capacitor hole C221, and the fifth connection segment SL33 can be connected to the first plate C21 of the second capacitor C2 through a contact hole passing through the second capacitor hole C221, thereby connecting the first capacitor C1 and the second capacitor C2 in series. At the same time, the fifth connection segment SL33 can also be connected to one end of the third semiconductor segment SE13 away from the active part ACT2 of the second reset transistor T2 through the contact hole, thereby connecting to the second electrode of the second reset transistor T2 to transmit the reference signal Vref.

[0359] The fourth connection portion SL4 is located between the second connection portion SL2 and the first reset control line REL1, and is connected to the second plate C22 of the second capacitor C2 and a region of the second semiconductor portion SE2 located between the active portion ACT3 of the drive transistor T3 and the active portion ACT6 of the second emission control transistor T6. Thus, the fourth connection portion SL4 can serve as at least a portion of the N3 node, connecting the second plate C22 of the second capacitor C2, the first electrode of the drive transistor T3, and the first electrode of the second emission control transistor T6.

[0360] The fifth connection portion SL5 is located between the second emission control line EML2 and the third reset control line REL3 and is connected to a region of the second semiconductor portion SE2 located away from the active portion ACT3 of the driving transistor T3 and located on the active portion ACT6 of the second emission control transistor 6. In other words, it is connected to the second electrode of the second emission control transistor 6. The fifth connection portion SL5 can also be connected to the first electrode ANO of the light-emitting device LD via a contact hole. The fifth connection portion SL5 can function as a connection for at least a portion of the N6 node.

[0361] In some embodiments of the present disclosure, the first source-drain layer SD1 may further include a sixth connection portion SL6. The sixth connection portion SL6 overlaps with the third gate portion GA23 and the active portion ACT3 of the driving transistor T3. The orthographic projection of the active portion ACT3 of the driving transistor T3 on the substrate SU is located within the orthographic projection of the sixth connection portion SL6 on the substrate SU, thereby shielding the gate of the driving transistor T3 through the sixth connection portion SL6. However, the sixth connection portion SL6 is spaced apart from the second connection portion SL2. Simultaneously, the sixth connection portion SL6 can be connected to the first power line VDL through a contact hole, thereby inputting a constant first power signal VDD to the sixth connection portion SL6, shielding the signal at the N1 node from interference from other signals. Of course, the sixth connection portion SL6 can also be connected to the second power signal VSS or other constant signal, which is not specifically limited here.

[0362] As shown in FIG. 28 and FIG. 29 , in some embodiments of the present disclosure, the first source / drain layer SD1 may further include a seventh connection portion SL7 , an eighth connection portion SL8 , and a ninth connection portion SL9 , wherein:

[0363] The seventh connection portion SL7 is located between the second light emitting control line EML2 and the third reset control line REL3 and is connected to the second auxiliary power line VSLs and the second power line VSL through a contact hole.

[0364] The eighth connection portion SL8 is located between the second light emitting control line EML2 and the third reset control line REL3, and is connected to the first auxiliary switching portion SE3 and the first auxiliary reset line VRLs through a contact hole;

[0365] The ninth connection portion SL9 is located between the second light emitting control line EML2 and the third reset control line REL3 , and is connected to the second auxiliary switching portion SE4 and the second auxiliary reset line VILs through a contact hole.

[0366] The first auxiliary power line VDLs can be connected to an end of the second semiconductor portion SE2 located at the active portion ACT5 of the first emission control transistor T5, away from the active portion ACT3 of the driving transistor T3, through a contact hole. This connects the first auxiliary power line VDLs to the first electrode of the first emission control transistor T5 to transmit the first power signal VDD. Simultaneously, a first auxiliary power line VDLs is simultaneously connected to the first electrode of the first emission control transistor T5 in the same row of pixel circuits.

[0367] The first emission control line EML1 can be connected to the first gate portion GA21 through a contact hole to transmit the first emission control signal EM1 to the gate of the first emission control transistor T5. A first emission control line EML1 is simultaneously connected to the first gate portion GA21 of the pixel circuits in the same row, that is, connected to the gates of the first emission control transistors T5 in the same row.

[0368] The scan line GL can be connected to the second gate portion GA22 through the contact hole and can transmit the scan signal Gate to the gate of the write transistor T4. A scan line GL is simultaneously connected to the second gate portion GA22 of the same row of pixel circuits, that is, to the gate of the same row of write transistors T3.

[0369] The first reset control line REL1 can be simultaneously connected to the fourth gate portion GA24 through a contact hole and can transmit the first reference control signal RE1 to the gate of the first reset transistor T1. The first reset control line REL1 is simultaneously connected to the fourth gate portion GA24 of the pixel circuits in the same row, that is, connected to the gates of the first reset transistors T1 in the same row.

[0370] The second reset control line REL2 can be simultaneously connected to the fifth gate portion GA25 through a contact hole and can transmit the second reference control signal RE2 to the gate of the second reset transistor T2. The second reset control line REL2 is simultaneously connected to the fifth gate portion GA25 of the pixel circuits in the same row, that is, connected to the gates of the second reset transistors T2 in the pixel circuits in the same row.

[0371] The second emission control line EML2 can be connected to the sixth gate portion GA26 through a contact hole to transmit the second emission control signal EM2 to the gate of the second emission control transistor T6. A second emission control line EML2 is also connected to the sixth gate portion GA26 of the pixel circuits in the same row, that is, connected to the gates of the second emission control transistors T6 in the same row.

[0372] The third reset control line REL3 is connected to the seventh gate portion GA27 through a contact hole to transmit a reset control signal RE3 to the gate of the third reset transistor T7. The third reset control line REL3 is also connected to the seventh gate portion GA27 of all pixel circuits in the same row, that is, to the gates of the third reset transistors T7 in the same row.

[0373] As shown in Figures 27 and 28, the first reset line VRL can be connected to the area of ​​the first semiconductor segment SE11 located at the active portion ACT1 of the first reset transistor T1 near the second semiconductor segment SE12 through the contact hole, thereby being connected to the first electrodes of the first reset transistor T1 and the second reset transistor T2 at the same time. The reference signal Vref can be transmitted to the first reset transistor T1 and the second reset transistor T2 at the same time through the first reset line VRL.

[0374] The second reset line VIL may be connected to an end of the fifth semiconductor segment SE22 away from the driving transistor T3 through a contact hole, thereby being connected to the first electrode of the third reset transistor T7 to transmit the reset signal Vinit.

[0375] Second source and drain layer SD2

[0376] As shown in Figures 10, 20, 21, 26, 27, 35, and 36, the second source and drain layer SD2 may include a first power line VDL, a second power line VSL, a first auxiliary reset line VRLs, and a second auxiliary reset line VILs. The specific patterns have been described in detail above and will not be described in detail here.

[0377] In addition, the second source / drain layer SD2 may further include an electrode transition portion S1 located between the two column line groups YG and connected to the fifth connection portion SL through a contact hole. The first electrode ANO of the light emitting device LD may be connected to the electrode transition portion S1 through a contact hole.

[0378] As shown in FIG26 , the first electrode ANO of the light emitting device LD may block the active portion of a portion of the transistor. For example:

[0379] In the pixel circuits from the i-th column to the i+2-th column and the j-th row to the j+1-th row, for the same light-emitting unit, the first electrode ANO1 of the first light-emitting device is connected to the second electrode of the second light-emitting control transistor T6 of the pixel circuit in the i+2-th column and the j-th row through the electrode adapter S1, and the first electrode ANO1 overlaps with the active part ACT3 of the driving transistor T3 of the pixel circuit in the i-th and i+1-th columns of the j-th row, which can play a light-shielding role, but does not overlap with the active part ACT3 of the driving transistor T3 of the pixel circuit in the i+2-th column.

[0380] A first electrode ANO2 of the second light-emitting device is connected to the second electrode of the second light-emitting control transistor T6 of the pixel circuit in the i-th column and j-th row via an electrode transition portion S1. The first electrode ANO2 overlaps with the active portion ACT5 of the first light-emitting control transistor T5 of the pixel circuit in the i-th column and j-th row, thereby providing light shielding. A first electrode ANO3 of the third light-emitting device is connected to the second electrode of the second light-emitting control transistor T6 of the pixel circuit in the i+1-th column and j-th row via an electrode transition portion S1. The first electrode ANO3 overlaps with the active portion ACT5 of the first light-emitting control transistor T5 of the pixel circuit in the i+1-th column and j-th row, thereby providing light shielding.

[0381] The following is an exemplary description of some film layers of the second display panel:

[0382] As shown in Figures 36 to 40, the light-shielding layer BSM may include the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2, and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 may be connected as an integrated structure, that is, there is no interruption between the two, which can reduce the connection structure and simplify the preparation process. The shape of the integrated structure on the substrate SU can be rectangular, of course, it can also be other shapes.

[0383] As shown in Figures 38 to 41, the first gate layer GA1 may include a first plate C11 of the first capacitor C1 and a second plate C22 of the second capacitor C2, which may be spaced apart along the column direction Y. The orthographic projections of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate SU may be rectangular, or of course, may be other shapes. At the same time, the widths of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 in the row direction X may be the same, and the orthographic projections of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate SU may be within the orthographic projections of the integrated structure of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate SU.

[0384] The first gate layer GA1 may further include a second auxiliary power line VSLs, which may be disposed on a side of the second capacitor C2 away from the first capacitor C1.

[0385] As shown in Figures 38, 39 and 42, the semiconductor layer SE may include a first semiconductor portion SE1 and a second semiconductor portion SE2 spaced apart along the row direction X. The second semiconductor portion SE2 may include a fourth semiconductor segment SE21 and a fifth semiconductor segment SE22. The specific diagrams of the first semiconductor portion SE1 and the fourth semiconductor segment SE21 can refer to the patterns of the first semiconductor portion SE1 and the fourth semiconductor segment SE21 of the first display panel above, and will not be described in detail here.

[0386] The fifth semiconductor segment SE22 may extend toward the first semiconductor portion SE1 and be connected to a region of the fourth semiconductor segment SE21 between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second emission control transistor T6. For example:

[0387] The fifth semiconductor segment SE22 may include a first subsegment and a second subsegment connected in sequence. The first subsegment is located on a side of the fourth semiconductor segment SE21 close to the first semiconductor portion SE1 and may extend along the row direction X. The first subsegment is connected to a region of the fourth semiconductor segment SE21 between the active portion ACT3 of the drive transistor T3 and the active portion ACT6 of the second light emission control transistor T6. The first subsegment overlaps with the third reset control line REL3. The second subsegment may extend along the column direction Y and be connected to the first subsegment. The active portion ACT3 of the third reset transistor T7 is located in the second subsegment.

[0388] As shown in FIG37 and FIG38 , the second gate layer GA2 may include a first gate portion GA21 , a second gate portion GA22 , a third gate portion GA23 , a fourth gate portion GA24 , a fifth gate portion GA25 , a sixth gate portion GA26 and a seventh gate portion GA27 , wherein:

[0389] The first gate portion GA21 overlaps the active portion ACT5 of the first emission control transistor T5 to form the gate of the first emission control transistor T5. The orthographic projection of the first gate portion GA21 on the substrate SU can be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT5 in the row direction X.

[0390] The second gate portion GA22 overlaps the active portion ACT4 of the write transistor T4 to form the gate of the write transistor T4. The orthographic projection of the second gate portion GA22 on the substrate SU can be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT4 in the row direction X.

[0391] The third gate portion GA23 overlaps with the active portion ACT3 of the driving transistor T3 and is connected to the third gate portion GA23 to form the gate of the driving transistor T3. For example, the third gate portion GA23 may include a gate portion GA231 and a gate extension portion GA232. The gate portion GA231 may extend in the row direction X and overlap with the active portion ACT3, and may serve as the gate of the driving transistor T3. The gate extension portion GA232 may extend in the column direction Y and overlap with the first plate C11 of the first capacitor. It may be connected to the first plate C11 of the first capacitor C1 through a contact hole, which can reduce the number of connections and simplify the manufacturing process. The orthographic projections of the gate portion GA231 and the active portion ACT3 on the substrate SU are located within the orthographic projection of the second capacitor C2 on the substrate SU. The third gate portion GA23 and one of the two plates of the second capacitor C2 that is close to the active portion ACT3 can both serve as the gate of the driving transistor T3, thereby forming a dual-gate structure, which is beneficial to improving the stability of the gate signal. For example, the third gate portion GA23 serves as the top gate of the driving transistor T3, and the second plate C22 of the second capacitor C2 serves as the bottom gate of the driving transistor T3, thereby forming a dual-gate structure, and when the second plate C22 serves as the bottom gate, it can be connected to the source (first pole) of the driving transistor T3 to ensure the stability of the saturation region of the driving transistor T3. Of course, the driving transistor T3 can also adopt a single-gate structure, and only the third gate portion GA23 or one of the two plates of the second capacitor C2 that is close to the active portion ACT3 can be used as the gate to simplify the structure and reduce parasitic capacitance.

[0392] The fourth gate portion GA24 overlaps the active portion ACT1 of the first reset transistor T1 to form the gate of the first reset transistor T1. The orthographic projection of the fourth gate portion GA24 on the substrate SU may be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT1 in the row direction X.

[0393] The fifth gate portion GA25 overlaps the active portion ACT2 of the second reset transistor T2 to form the gate of the second reset transistor T2. The orthographic projection of the fifth gate portion GA25 on the substrate SU may be rectangular, with a width in the column direction Y greater than or equal to the width of the active portion ACT2 in the column direction Y, and a length in the row direction X less than the length of the second semiconductor segment SE12.

[0394] The sixth gate portion GA26 overlaps the active portion ACT6 of the second emission control transistor T6 to form the gate of the second emission control transistor T6. The orthographic projection of the sixth gate portion GA26 on the substrate SU can be rectangular, and its width in the row direction X is greater than or equal to the width of the active portion ACT6 in the row direction X.

[0395] The seventh gate portion GA27 overlaps the active portion ACT3 of the third reset transistor T7 to form the gate of the third reset transistor T7. The orthographic projection of the seventh gate portion GA27 on the substrate SU may be rectangular, and its width in the column direction Y is greater than or equal to the width of the active portion ACT3 in the column direction Y.

[0396] As shown in Figures 36 and 37, the first source and drain layer SD1 may include a first auxiliary power line VDLs, a first light emitting control line EML1, a scan line GL, a first reset control line REL1, a first reset line VRL, a second reset control line REL2, a second light emitting control line EML2, a third reset control line REL3 and a second reset line VIL, which extend along the row direction X and are sequentially distributed along the column direction Y. The orthographic projection of the second auxiliary power line VSLs on the substrate SU is located between the orthographic projections of the second light emitting control line EML2 and the third reset control line REL3 on the substrate SU.

[0397] The first source and drain layer SD1 may further include a first connection portion SL1, a second connection portion SL2, a third connection portion SL3, a fourth connection portion SL4, a fifth connection portion SL5, a sixth connection portion SL6, and a seventh connection portion SL7, wherein:

[0398] The first connection portion SL1 is located between the first emission control line EML1 and the scan line GL, and is connected to the data line DAL and the first electrode of the write transistor T4 through a contact hole. The data line DAL can transmit the data signal Data to the first electrode of the write transistor T4 through the first connection portion SL1.

[0399] The second connection portion SL2 is positioned between the scan line GL and the first reset control line REL1 in its orthographic projection on the substrate SU, and overlaps with the first plate C11 of the first capacitor C1. The second connection portion SL2 can be connected to the gate extension GA232 of the third gate portion GA23 and the first plate C11 of the first capacitor C1 through a contact hole, thereby connecting the first plate C11 to the gate of the drive transistor T3.

[0400] The third connection portion SL3 can be connected to the gate extension portion GA232 of the third gate portion GA23 and the area between the active portion ACT4 of the write transistor T4 and the active portion ACT1 of the first reset transistor T1 in the first semiconductor portion SE1 through a contact hole; thus, the third connection portion SL3 and the second connection portion SL2 can serve as at least a part of the N1 node, connecting the first electrode C11 of the first capacitor C1, the gate (top gate) of the driving transistor T3, and the second electrode of the write transistor T4 and the second electrode of the first reset transistor T1.

[0401] The orthographic projection of the fourth connection portion SL4 on the substrate SU is located between the orthographic projection of the scan line GL and the first reset control line REL1 on the substrate SU. The fourth connection portion SL4 can be connected to the second electrode of the second reset transistor T2 and the first plate C21 of the second capacitor C2 through a contact hole. To facilitate connection with the first plate C21, the first plate C21 can be provided with a capacitor hole or a notch, so that the fourth connection portion SL4 can be connected to the first plate C21 of the second capacitor C2 through a contact hole passing through the capacitor hole or the notch. Thus, the fourth connection portion SL4 can serve as at least a portion of the N4 node, connecting the first plate C21 of the second capacitor C2. The second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are an integral structure, and therefore do not require a special connection.

[0402] The fifth connection portion SL5 is located between the second connection portion SL2 and the first reset control line REL1, and is connected to the second plate C22 of the second capacitor C2 and the region of the second semiconductor portion SE2 located between the active portion ACT3 of the drive transistor T3 and the active portion ACT6 of the second emission control transistor T6. Thus, the fifth connection portion SL5 can serve as at least a portion of the N3 node, connecting the second plate C22 of the second capacitor C2, the first electrode of the drive transistor T3, and the first electrode of the second emission control transistor T6. Furthermore, the second plate C22, as part of the bottom gate of the drive transistor T3, can be connected to the first electrode (source) of the drive transistor T3, thereby ensuring stability in the saturation region of the drive transistor T3.

[0403] The sixth connection portion SL6 is located between the second emission control line EML2 and the second reset line VIL and is connected to a region of the second semiconductor portion SE2 located at the active portion ACT6 of the second emission control transistor T6, away from the active portion ACT3 of the drive transistor T3. In other words, it is connected to the second electrode of the second emission control transistor T6. The sixth connection portion SL6 can also be connected to the first electrode ANO of the light-emitting device LD via a contact hole.

[0404] The seventh connection portion SL7 is located between the second emission control line EML2 and the second reset line VIL and is connected to the second auxiliary power line VSLs through a contact hole.

[0405] As shown in FIG36 , the second source-drain layer SD2 may include a data line DAL and a second power line VSL, and may further include:

[0406] The data line DAL overlaps with the first connection portion SL1 and can be connected to the first connection portion SL1 through a contact hole, thereby transmitting the data signal Data to the first electrode of the write transistor T4 through the first connection portion SL1. The data line DAL is located on the side of the first semiconductor portion SE1 away from the second semiconductor portion SE2. The data line DAL does not overlap with the write transistor T4 and the first reset transistor T1 of the pixel circuit connected to it, but can overlap with the active portion ACT3 of the drive transistor T3 of the adjacent pixel circuit. This allows the data line DAL to be distanced from the N3 node (the fifth connection portion SL5), further stabilizing the voltage at the N3 node.

[0407] The second power line VSL can extend along the column direction Y and overlap with the second connection portion SL2, the third connection portion SL3, and the fourth connection portion SL4. The second power line VSL can provide a shielding effect through the constant second power signal VSS, which helps to ensure that the voltages of nodes N1 and N4 are not disturbed. The second power line VSL is connected to the second auxiliary power line VSLs through a contact hole. The second power line VSL and the second auxiliary power line VSLs can form a network within the space to transmit the second power signal VSS, which helps to reduce resistance. Of course, in some embodiments of the present disclosure, the second power line VSL or the second auxiliary power line VSLs can also be omitted, as long as they can transmit the second power signal VSS.

[0408] In some embodiments of the present disclosure, multiple first auxiliary reset lines VRLs and second auxiliary reset lines VILs may also be included. The first auxiliary reset lines VRLs and the first reset lines VRL are connected to form a mesh structure through contact holes, and the second auxiliary reset lines VILs and the second reset lines VIL are connected to form a mesh structure through contact holes; this is beneficial to reducing resistance.

[0409] Furthermore, the second source and drain layer SD2 may also include an electrode transition portion S1, which can be connected to the sixth connection portion SL6 through a contact hole, and the first electrode ANO of the light-emitting device LD can be connected to the electrode transition portion S1 through the contact hole, thereby connecting the first electrode ANO to the second electrode of the second light-emitting control transistor T6.

[0410] In addition, in some embodiments of the present disclosure, the above embodiments may also be adopted to divide the display panel into multiple column line groups YG and row line groups, and arrange the data line DAL, the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs in a manner similar to the above embodiments, which will not be repeated here.

[0411] The present disclosure further provides a display device, which may include a display panel. The display panel may be any of the above-described embodiments. The specific structure and beneficial effects of the display panel may be referenced above with respect to the embodiments of the display panel and will not be described in detail here. The display device of the present disclosure may be a mobile phone, tablet computer, television, or other electronic device with a display function, such as a smartwatch, smart glasses, or an in-vehicle display, which will not be enumerated here.

[0412] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A pixel circuit, comprising a driving transistor, a storage circuit, a writing circuit, and a first light-emitting control circuit; A gate of the driving transistor is connected to a first pole of the driving transistor through the storage circuit, and the first pole of the driving transistor is configured to be connected to a light-emitting device. A second pole of the driving transistor is connected to the first light-emitting control circuit, and the first light-emitting control circuit is configured to receive a first power signal; The writing circuit is connected to the gate of the driving transistor; the writing circuit is connected to the first pole of the driving transistor through the storage circuit; the writing circuit is configured to write a data signal into the storage circuit; the storage circuit is configured to store the data signal and a voltage of the first pole of the driving transistor.

2. The pixel circuit according to claim 1, wherein, The storage circuit includes a first capacitor and a second capacitor; the writing circuit includes a writing transistor; the first light-emitting control circuit includes a first light-emitting control transistor; A first pole of the writing transistor is configured to input the data signal, a second pole of the writing transistor is connected to the gate of the driving transistor and a first plate of the first capacitor; a second plate of the first capacitor is connected to a first plate of the second capacitor, a second plate of the second capacitor is connected to the first pole of the driving transistor; a first pole of the first light-emitting control transistor is configured to input the first power signal, a second pole of the first light-emitting control transistor is connected to the second pole of the driving transistor.

3. The pixel circuit according to claim 2, wherein, The pixel circuit further includes: A first reset transistor, a first pole of the first reset transistor is configured to receive a reference signal, a second pole of the first reset transistor is connected to the gate of the driving transistor; A second reset transistor, a first pole of the second reset transistor is configured to receive the reference signal, a second pole of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor.

4. The pixel circuit according to claim 3, wherein, The pixel circuit further includes: A third reset transistor, a first pole of the third reset transistor is configured to receive a reset signal, a second pole of the third reset transistor is connected to the first pole of the driving transistor and the second plate of the second capacitor.

5. The pixel circuit according to claim 3, wherein The pixel circuit further includes a second light-emitting control circuit, and the first pole of the driving transistor is connected to the light-emitting device through the second light-emitting control circuit.

6. The pixel circuit according to claim 5, wherein, The second light-emitting control circuit includes a second light-emitting control transistor; a first pole of the second light-emitting control transistor is connected to the first pole of the driving transistor, a second pole of the second light-emitting control transistor is connected to the light-emitting device; The pixel circuit further includes: A third reset transistor, a first pole of the third reset transistor is configured to receive a reset signal, a second pole of the third reset transistor is connected to the second pole of the second light-emitting control transistor.

7. The pixel circuit according to claim 6, wherein, At least one of the driving transistor, the writing transistor, the first reset transistor, the second reset transistor, the third reset transistor, the first light-emitting control transistor, and the second light-emitting control transistor is a metal-oxide transistor.

8. A display panel, wherein, It includes a plurality of pixel circuits arranged in an array along the row direction and the column direction. Each pixel circuit includes a plurality of transistors, a first capacitor, and a second capacitor. Each of the transistors includes a driving transistor, a writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, and a third reset transistor; The first pole of the first light-emitting control transistor is used to receive a first power signal, and the second pole of the first light-emitting control transistor is connected to the second pole of the driving transistor; the first pole of the writing transistor is used to receive a data signal, the second pole of the writing transistor is connected to the first plate of the first capacitor and the gate of the driving transistor, the second plate of the first capacitor is connected to the first plate of the second capacitor, and the second plate of the second capacitor is connected to the first pole of the driving transistor; the first pole of the second light-emitting control transistor is connected to the first pole of the driving transistor; The first poles of the first reset transistor and the second reset transistor are used to receive a reference signal, the second pole of the first reset transistor is connected to the gate of the driving transistor, and the second pole of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor; the first pole of the third reset transistor is used to receive a reset signal, and the second pole of the third reset transistor is connected to the first pole of the driving transistor or the second pole of the second light-emitting control transistor; The display panel includes: A substrate; A semiconductor layer provided on one side of the substrate and including the active portions of each of the transistors; A plurality of light-emitting devices provided on the side of the semiconductor layer away from the substrate, and one light-emitting device is connected to the second pole of the second light-emitting control transistor of one pixel circuit; One of the first plate and the second plate of the first capacitor is provided on the same layer as one of the first plate and the second plate of the second capacitor; One of the first capacitor and the second capacitor overlaps with the active portion of the driving transistor.

9. The display panel according to claim 8, wherein, The semiconductor layer includes a first semiconductor portion and a second semiconductor portion spaced apart along the row direction; The active portions of the writing transistor, the first reset transistor, and the second reset transistor are all located in the first semiconductor portion and are connected in sequence; the active portions of the first light-emitting control transistor, the driving transistor, the second light-emitting control transistor, and the third reset transistor are located in the second semiconductor portion and are connected in sequence along.

10. The display panel according to claim 9, wherein, The first plates of the first capacitor and the second capacitor are provided on the same layer and are spaced apart along the column direction; the second plates of the first capacitor and the second capacitor are provided on the same layer and are spaced apart along the column direction; the first plate and the second plate of the second capacitor overlap with the active portion of the driving transistor.

11. The display panel according to claim 9, wherein, The first electrode plate of the first capacitor and the second electrode plate of the second capacitor are arranged on the same layer and are spaced apart along the column direction; the second electrode plate of the first capacitor and the first electrode plate of the second capacitor are arranged on the same layer and are connected into an integral structure; the first electrode plate and the second electrode plate of the second capacitor overlap with the active part of the driving transistor.

12. The display panel according to claim 8, wherein, The active part of the first light-emitting control transistor overlaps with the first electrode plate and the second electrode plate of the first capacitor.

13. The display panel according to claim 10, wherein, The first semiconductor part includes a first semiconductor segment, a second semiconductor segment, and a third semiconductor segment; the first semiconductor segment and the third semiconductor segment extend along the column direction and are spaced apart along the row direction; the second semiconductor segment connects the first semiconductor segment and the third semiconductor segment; the active parts of the writing transistor and the first reset transistor are located in the first semiconductor segment, and the active part of the second reset transistor is located in the second semiconductor segment; the third semiconductor segment is connected to the first electrode plate of the second capacitor.

14. The display panel according to claim 13, wherein, The second pole of the third reset transistor is connected to the first pole of the driving transistor and the first pole of the second light-emitting control transistor; The second semiconductor part includes a fourth semiconductor segment and a fifth semiconductor segment, the fourth semiconductor segment extends along the column direction and is located on the side of the third semiconductor segment away from the first semiconductor segment; the active parts of the first light-emitting control transistor, the driving transistor, and the second light-emitting control transistor are sequentially distributed along the column direction in the fourth semiconductor segment; the fifth semiconductor segment is connected to the region between the active parts of the driving transistor and the second light-emitting control transistor in the fourth semiconductor segment; the active part of the third reset transistor is located in the fifth semiconductor segment.

15. The display panel according to claim 13, wherein, The second pole of the third reset transistor is connected to the second pole of the second light-emitting control transistor and the light-emitting device; The second semiconductor part includes a fourth semiconductor segment and a fifth semiconductor segment, the fourth semiconductor segment extends along the column direction and is located on the side of the third semiconductor segment away from the first semiconductor segment; the active parts of the first light-emitting control transistor, the driving transistor, and the second light-emitting control transistor are sequentially distributed along the column direction in the fourth semiconductor segment; the fifth semiconductor segment is connected to the region on the side of the fourth semiconductor segment where the active part of the second light-emitting control transistor is away from the active part of the driving transistor; the active part of the third reset transistor is located in the fifth semiconductor segment.

16. The display panel according to claim 10, wherein, The display panel further includes a first light-emitting control line, a scanning line, a first reset control line, a first reset line, a second reset control line, a second light-emitting control line, a third reset control line, and a second reset line that are sequentially spaced apart along the column direction; The first light-emitting control line extends along the row direction and is connected to the gate of the first light-emitting control transistor for transmitting a first light-emitting control signal; the first light-emitting control line overlaps with the first capacitor. The scan line extends along the row direction and is connected to the gate of the writing transistor for transmitting a scan signal; the scan line overlaps with the first capacitor; The first reset control line extends along the row direction and is connected to the gate of the first reset transistor for transmitting a first reference control signal; the first reset control line overlaps with the second capacitor; The first reset line extends along the row direction and is connected to the first poles of the first reset transistor and the second reset transistor for transmitting the reference signal; the first reset line overlaps with the second capacitor; The second reset control line extends along the row direction and is connected to the gate of the second reset transistor for transmitting a second reference control signal; The second light emission control line extends along the row direction and is connected to the gate of the second light emission control transistor for transmitting a second light emission control signal; The third reset control line extends along the row direction and is connected to the gate of the third reset transistor for transmitting a reset control signal; The second reset line extends along the row direction and is connected to the first pole of the third reset transistor for transmitting the reset signal; The positive projection of the active part of the driving transistor on the substrate is located between the positive projections of the scan line and the first reset control line on the substrate; The positive projection of the active part of the first reset transistor on the substrate is located between the positive projections of the scan line and the first reset line on the substrate; The positive projection of the active part of the second reset transistor on the substrate is located between the positive projections of the first reset line and the second light emission control line on the substrate; The positive projection of the active part of the third reset transistor on the substrate is located between the positive projections of the second light emission control and the second reset line on the substrate.

17. The display panel according to claim 16, wherein, The display panel further includes: A plurality of first auxiliary power supply lines extend along the row direction and are distributed along the column direction; one of the first auxiliary power supply lines is provided between adjacent two rows of the pixel circuits; the first auxiliary power supply line is connected to the first pole of the first light emission control transistor of the pixel circuit on one side thereof; A plurality of first power supply lines are provided on the side of the first auxiliary power supply line away from the substrate, each of the first power supply lines extends along the column direction and is spaced apart along the row direction; one of the first power supply lines is connected to each of the first auxiliary power supply lines and overlaps with a column of the pixel circuits; The first power supply line and the first auxiliary power supply line are used for transmitting the first power signal; A plurality of data lines are provided on the side of the first auxiliary power supply line away from the substrate, each of the data lines extends along the column direction and is spaced apart along the row direction; one of the data lines is connected to the first pole of the writing transistor of a column of the pixel circuits for transmitting the data signal.

18. The display panel according to claim 17, wherein, The display panel further includes: A second auxiliary power supply line extends along the row direction and is distributed along the column direction for transmitting a second power signal; a positive projection of the second auxiliary power supply line on the substrate is located between positive projections of the second light-emitting control line and the third reset control line on the substrate.

19. The display panel according to claim 18, wherein, The display panel further includes: A plurality of second power supply lines, a first auxiliary reset line, and a second auxiliary reset line that extend along the column direction and are distributed along the row direction are provided on a side of the first auxiliary power supply line away from the substrate; the second power supply line is connected to the second auxiliary power supply line, the first auxiliary reset line is connected to the first reset line, and the second auxiliary reset line is connected to the second reset line; The first power supply line and the data line connected to the pixel circuits in the same column are defined as a column line group, and one of the second power supply line, the first auxiliary reset line, and the second auxiliary reset line is provided on the first power supply line and the data line of the column line group; The light-emitting device has a first electrode and a second electrode distributed in a direction away from the substrate, the first electrode is connected to a second pole of the second light-emitting control transistor, and the second electrode is connected to the second power supply line and the second auxiliary power supply line.

20. The display panel according to claim 19, wherein, The semiconductor layer further includes a first auxiliary transfer portion and a second auxiliary transfer portion; The first auxiliary transfer portion is connected to a region between the active portions of the first reset transistor and the second reset transistor in the first semiconductor portion of a pixel circuit; the first auxiliary reset line is connected to the first auxiliary transfer portion; The second auxiliary transfer portion is connected to a region of the second semiconductor portion of a pixel circuit where the active portion of the third reset transistor is away from the active portion of the second light-emitting control transistor; the second auxiliary reset line is connected to the second auxiliary transfer portion.

21. The display panel according to claim 20, wherein, The display panel further includes: A light-shielding layer is provided on one side of the substrate and includes a first electrode plate of the first capacitor and the first electrode plate of the second capacitor; A first gate layer is provided on a side of the light-shielding layer away from the substrate and includes a second electrode plate of the first capacitor, a second electrode plate of the second capacitor, and the second auxiliary power supply line; the semiconductor layer is provided on a side of the first gate layer away from the substrate; A second gate layer is provided on a side of the semiconductor layer away from the substrate and overlaps with the active portions of the transistors; A first source-drain layer is provided on a side of the second gate layer away from the substrate and includes the first auxiliary power supply line, the first light-emitting control line, the scanning line, the first reset control line, the first reset line, the second reset control line, the second light-emitting control line, the third reset control line, and the second reset line; A second source-drain layer is provided on a side of the first source-drain layer away from the substrate and includes the data line, the first power supply line, the second power supply line, the first auxiliary reset line, and the second auxiliary reset line.

22. The display panel according to claim 21, wherein, The second gate layer further includes: The first gate portion overlaps with the active portion of the first light-emitting control transistor to form the gate of the first light-emitting control transistor; the first gate portion is connected to the first light-emitting control line; The second gate portion overlaps with the active portion of the writing transistor to form the gate of the writing transistor; the second gate portion is connected to the scan line; The third gate portion overlaps with the active portion of the driving transistor and is connected to the third gate portion to form the gate of the driving transistor; The fourth gate portion overlaps with the active portion of the first reset transistor to form the gate of the first reset transistor; the fourth gate portion is connected to the first reset control line; The fifth gate portion overlaps with the active portion of the second reset transistor to form the gate of the second reset transistor; the fifth gate portion is connected to the second reset control line; The sixth gate portion overlaps with the active portion of the second light-emitting control transistor to form the gate of the second light-emitting control transistor; the sixth gate portion is connected to the second light-emitting control line; The seventh gate portion overlaps with the active portion of the third reset transistor to form the gate of the third reset transistor; the seventh gate portion is connected to the third reset control line.

23. The display panel according to claim 22, wherein, The first source-drain layer further includes: The first connection portion is located between the first light-emitting control line and the scan line and is connected to the data line and the region of the first semiconductor portion on the side of the active portion of the writing transistor away from the active portion of the first reset transistor; The second connection portion is located between the scan line and the first reset control line and is connected to the first electrode plate of the first capacitor, the third gate portion, and the region of the first semiconductor portion between the active portion of the writing transistor and the active portion of the first reset transistor; The third connection portion is located between the scan line and the first reset control line and is connected to the second electrode plate of the first capacitor, the first electrode plate of the second capacitor, and the second pole of the second reset transistor; The fourth connection portion is located between the second connection portion and the first reset control line and is connected to the second electrode plate of the second capacitor and the region of the second semiconductor portion between the active portion of the driving transistor and the active portion of the second light-emitting control transistor; The fifth connection portion is located between the second light-emitting control line and the third reset control line and is connected to the region of the second semiconductor portion on the side of the active portion of the second light-emitting control transistor away from the active portion of the driving transistor.

24. The display panel according to claim 23, wherein, The first source-drain layer further includes: The sixth connection portion overlaps with the third gate portion and the active portion of the driving transistor and is connected to the first power supply line.

25. The display panel according to claim 23, wherein, The first source-drain layer further includes: The seventh connection portion is located between the second light-emitting control line and the third reset control line and is connected to the second auxiliary power supply line and the second power supply line; The eighth connection portion is located between the second light-emitting control line and the third reset control line and is connected to the first auxiliary transfer portion and the first auxiliary reset line; The ninth connection part is located between the second light-emitting control line and the third reset control line, and is connected to the second auxiliary transfer part and the second auxiliary reset line.

26. The display panel according to claim 23, wherein, The first power supply line overlaps with one of the second connection parts.

27. The display panel according to claim 23, wherein, One of the second power supply line, the first auxiliary reset line, and the second auxiliary reset line overlaps at least a partial area of the active part of the writing transistor, the active part of the first reset transistor, and the third connection part.

28. The display panel according to any one of claims 8-27, wherein, The material of the semiconductor layer includes metal oxide.

29. A display device, comprising the display panel according to any one of claims 8-28.

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