Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises a display area and a non-display area, the display area comprises a light emitting device, a pixel circuit, a data signal line, a connection signal line, a virtual wire and a first power supply signal line, the connection signal line is electrically connected with the data signal line of the edge area, and the virtual wire is electrically connected with the first power supply signal line. The same connecting signal line comprises a first section and a second section which are electrically connected, the first section extends in the second direction, and the second section extends in the first direction; the plurality of virtual wires comprise a first virtual wire extending along the second direction and a second virtual wire extending along the first direction; the first power supply signal lines extend along a first direction, the plurality of first power supply signal lines are arranged along a second direction, and the first power supply signal lines are electrically connected with the pixel circuit; and at least part of the first virtual wires are electrically connected with the first power supply signal wire. The first power signal lines and the first virtual wires which are electrically connected can be of a latticed structure, and the uniformity of the first power voltage of the display area is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] In a display panel, pixel circuits are typically used to drive light-emitting devices to emit light. The pixel circuits are electrically connected to a first power signal line, and the light-emitting devices are electrically connected to a second power signal line. The voltage on both the first and second power signal lines affects the brightness of the light-emitting devices.

[0003] In existing technologies, the voltage drop on the first power signal line is relatively large in the display area. This results in poor voltage uniformity received by pixel circuits at different locations within the display area, affecting the brightness uniformity of the display panel. Therefore, a solution is urgently needed. Summary of the Invention

[0004] In view of this, embodiments of this application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, embodiments of this application provide a display panel, including a substrate and a display area and a non-display area located on one side of the substrate, wherein the non-display area surrounds at least a portion of the display area, and the display area includes:

[0006] The light-emitting device and the pixel circuit are electrically connected;

[0007] Multiple data signal lines, the data signal lines extend along a first direction, the multiple data signal lines are arranged along a second direction, and the first direction intersects with the second direction;

[0008] Multiple connection signal lines, each connection signal line including an electrically connected first segment and a second segment, the first segment extending along a second direction and the second segment extending along a first direction; the connection signal lines are electrically connected to data signal lines in the edge region;

[0009] Multiple virtual routing lines, including a first virtual routing line extending along a second direction and a second virtual routing line extending along a first direction, the first virtual routing line being on the same layer as the first segment and the second virtual routing line being on the same layer as the second segment;

[0010] Multiple first power signal lines extend along a first direction, and multiple first power signal lines are arranged along a second direction. The first power signal lines are electrically connected to the pixel circuit.

[0011] At least a portion of the first virtual trace is electrically connected to the first power signal line.

[0012] Secondly, based on the same inventive concept, embodiments of this application provide a display device, including the display panel as provided in the first aspect.

[0013] In this embodiment, a first power signal line extending along a first direction is provided and electrically connected to a first virtual trace extending along a second direction. In the display panel, the first power signal line and the first virtual trace can form a grid structure and transmit the same first power voltage PVDD. This helps to reduce the voltage drop of the first power voltage PVDD in the display area and improve the uniformity of the first power voltage PVDD at different positions in the display area AA, thereby improving the brightness uniformity of the display panel.

[0014] Meanwhile, since the first virtual trace is on the same layer as the first segment of the connecting signal line, the first virtual trace can be made of the same material as the connecting signal line. The sheet resistance of the material of the connecting signal line that is electrically connected to the data signal line is usually small. Therefore, making the first virtual trace and the first power signal line electrically connected to form a mesh structure is also beneficial to reduce the impedance of the mesh structure to a large extent, further reducing the voltage drop of the first power supply voltage PVDD in the display area, thereby further improving the uniformity of the first power supply voltage PVDD at different locations in the display area. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a plan view of a display panel provided in an embodiment of this application;

[0017] Figure 2 A plan view of yet another display panel provided in an embodiment of this application;

[0018] Figure 3 A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0019] Figure 4 A plan view of yet another display panel provided in an embodiment of this application;

[0020] Figure 5 A plan view of yet another display panel provided in an embodiment of this application;

[0021] Figure 6 This is a partially enlarged schematic diagram of a display panel provided in an embodiment of this application;

[0022] Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0023] Figure 8 A plan view of yet another display panel provided in an embodiment of this application;

[0024] Figure 9 A schematic diagram of yet another pixel circuit provided in an embodiment of this application;

[0025] Figure 10 A plan view of yet another display panel provided in an embodiment of this application;

[0026] Figure 11 A plan view of yet another display panel provided in an embodiment of this application;

[0027] Figure 12 A plan view of yet another display panel provided in an embodiment of this application;

[0028] Figure 13 for Figure 12 A schematic diagram of the structure of the first part;

[0029] Figure 14 for Figure 12 Another structural diagram of the first division;

[0030] Figure 15 A plan view of yet another display panel provided in an embodiment of this application;

[0031] Figure 16 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0032] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0033] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0034] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0035] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this article generally indicates that the related objects before and after it have an "or" relationship.

[0036] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0037] Figure 1 This is a plan view of a display panel provided in an embodiment of this application.

[0038] This application embodiment provides a display panel 01, such as Figure 1 As shown, the display panel 01 includes a substrate PI and a display area AA and a non-display area NA located on one side of the substrate PI. The non-display area NA surrounds at least a portion of the display area AA. The display area AA includes a pixel circuit 10 and a light-emitting device 20. The pixel circuit 10 and the light-emitting device 20 are electrically connected, and the pixel circuit 10 is used to drive the light-emitting device 20 to emit light. For example, the light-emitting device 20 is an organic light-emitting diode, which is not specifically limited in this application.

[0039] Combination Figure 2 As shown, Figure 2 This is a plan view of another display panel provided in an embodiment of this application. The display area AA also includes multiple data signal lines 30, multiple connection signal lines 40, multiple virtual traces 50, and multiple first power signal lines 60. The data signal lines 30 extend along the first direction Y, and the multiple data signal lines 30 are arranged along the second direction X. The data signal lines 30 are electrically connected to the pixel circuit 10 and can be used to transmit data voltage Vdata to the pixel circuit 10.

[0040] Wherein, the first direction Y intersects with the second direction X. For example, the first direction Y is the column direction of the display panel 01, and the second direction X is the row direction of the display panel 01.

[0041] The same connection signal line 40 includes a first segment 41 and a second segment 42 that are electrically connected. The first segment 41 extends along a second direction X, and the second segment 42 extends along a first direction Y. The first segment 41 and the second segment 42 may be located in different film layers. The connection signal line 40 is electrically connected to the data signal line 30 in the edge region. The data signal line 30 in the edge region can be led out from the middle area of ​​the display area AA to the fan-out area through the connection signal line 40 to reduce the width of the bezel where the fan-out area is located. The connection signal line 40 may adopt a titanium-aluminum-titanium structure.

[0042] For example, such as Figure 2 As shown, the non-display area NA includes a first non-display area NA1 located on one side of the display area AA. The first non-display area NA1 and the display area AA are arranged along the first direction Y. The fan-out area is located in the first non-display area NA1. The first non-display area NA1 can be the "bottom" border of the display panel 01.

[0043] The multiple virtual traces 50 include a first virtual trace 51 extending along the second direction X and a second virtual trace 52 extending along the first direction Y. The first virtual trace 51 is on the same layer as the first segment 41, and the second virtual trace 52 is on the same layer as the second segment 42. That is, the virtual traces 50 and the connecting signal lines 40 can be set on the same layer.

[0044] Optionally, the virtual traces 50 and the connecting signal lines 40 are evenly distributed in the display area AA. This helps to improve the structural uniformity of the display panel 01 and reduces the difficulty of manufacturing.

[0045] The first power signal line 60 extends along the first direction Y, and multiple first power signal lines 60 are arranged along the second direction X. The first power signal lines 60 are electrically connected to the pixel circuit 10, and the first power signal lines 60 can be used to transmit the first power supply voltage PVDD to the pixel circuit 10.

[0046] For example, such as Figure 3 As shown, Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. The pixel circuit 10 includes a driving transistor Td, a data writing transistor T1, a gate reset transistor T2, a threshold compensation transistor T3, a power supply voltage writing transistor T4, a light emission control transistor T5, an anode reset transistor T6, and a storage capacitor Cst.

[0047] The data signal line 30 is electrically connected to the data writing transistor T1 in the pixel circuit 10, and the first power signal line 60 is electrically connected to the power supply voltage writing transistor T4 in the pixel circuit 10.

[0048] Specifically, in the pixel circuit 10, the first terminal of the data writing transistor T1 is electrically connected to the data signal line 30, the second terminal is electrically connected to the first terminal of the driving transistor Td, and the gate is electrically connected to the first scan line S1. The first terminal of the gate reset transistor T2 is connected to the receiving first reset voltage Vref1, the second terminal is electrically connected to the gate of the driving transistor Td, and the gate is electrically connected to the second scan line S2.

[0049] The first terminal of the threshold compensation transistor T3 is electrically connected to the second terminal of the driving transistor Td, the second terminal is electrically connected to the gate of the driving transistor Td, and the gate is electrically connected to the third scan line S3. Both the gate reset transistor T2 and the threshold compensation transistor T3 may comprise metal oxides, such as indium gallium zinc oxide (IGZO).

[0050] The first terminal of the power supply voltage writing transistor T4 is electrically connected to the first power supply signal line 60, the second terminal is electrically connected to the first terminal of the driving transistor Td, and the gate is electrically connected to the light-emitting control signal line EM. The first terminal of the light-emitting control transistor T5 is electrically connected to the second terminal of the driving transistor Td, the second terminal is electrically connected to the first terminal of the light-emitting device 20, and the gate is electrically connected to the light-emitting control signal line EM. The first terminal of the light-emitting device 20 can be its anode, and the second terminal of the light-emitting device 20 can be its cathode. The second terminal of the light-emitting device 20 receives the second power supply voltage PVEE.

[0051] The first terminal of the anode reset transistor T6 receives the second reset voltage Vref2, the second terminal is electrically connected to the first terminal of the light-emitting device 20, and the gate is electrically connected to the first scan line S1. One plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor Td, and the other plate is electrically connected to the first power signal line 60.

[0052] like Figure 2 As shown, at least a portion of the first virtual trace 51 is electrically connected to the first power signal line 60.

[0053] Optional, such as Figure 2 As shown, the first virtual traces 51 in the display panel 01 are all electrically connected to the first power signal line 60.

[0054] In this embodiment, a first power signal line 60 extending along the first direction Y is electrically connected to a first virtual trace 51 extending along the second direction X. In the display panel 01, the first power signal line 60 and the first virtual trace 51 can form a grid structure and transmit the same first power supply voltage PVDD. This helps to reduce the voltage drop of the first power supply voltage PVDD in the display area AA and improve the uniformity of the first power supply voltage PVDD at different positions in the display area AA, thereby improving the brightness uniformity of the display panel 01.

[0055] Meanwhile, since the first virtual trace 51 is on the same layer as the first segment 41 of the connecting signal line 40, the first virtual trace 51 can be made of the same material as the connecting signal line 40. The sheet resistance of the material of the connecting signal line 40, which is electrically connected to the data signal line 30, is usually small. Therefore, making the first virtual trace 51 and the first power signal line 60 electrically connected to form a mesh structure is also beneficial to reduce the impedance of the mesh structure to a large extent, further reducing the voltage drop of the first power supply voltage PVDD in the display area AA, thereby further improving the uniformity of the first power supply voltage PVDD at different locations in the display area AA.

[0056] Figure 4 This is a plan view of another display panel provided in an embodiment of this application.

[0057] In one embodiment of this application, such as Figure 4 As shown, multiple first virtual traces 51 are arranged along the first direction Y, and the multiple first virtual traces 51 include first sub-virtual traces 511 and second sub-virtual traces 512.

[0058] At least a portion of the second virtual trace 52 serves as the second power signal line 70, that is, at least a portion of the second virtual trace 52 is electrically connected to the light-emitting device 20 to transmit the second power supply voltage PVEE to the light-emitting device 20.

[0059] The first sub-virtual trace 511 is electrically connected to the first power signal line 60, and the second sub-virtual trace 512 is electrically connected to the second power signal line 70. The first sub-virtual trace 511 and the second sub-virtual trace 512 are arranged at intervals.

[0060] In other words, among the multiple first virtual traces 51 extending along the second direction X, some of the first virtual traces 51 are first sub-virtual traces 511, which are electrically connected to the first power signal line 60 to form a mesh structure for transmitting the first power supply voltage PVDD. Some of the first virtual traces 51 are second sub-virtual traces 512, which are electrically connected to the second power signal line 70 extending along the first direction Y to form a mesh structure for transmitting the second power supply voltage PVEE.

[0061] In this embodiment, the first sub-virtual trace 511 is electrically connected to the first power signal line 60, and the second sub-virtual trace 512 is electrically connected to the second power signal line 70. This allows the first sub-virtual trace 511 and the first power signal line 60 to form a mesh structure, while the second sub-virtual trace 512 and the second power signal line 70 also form a mesh structure. This reduces both the voltage drop of the first power supply voltage PVDD and the voltage drop of the second power supply voltage PVEE. This not only improves the uniformity of the first power supply voltage PVDD at different locations in the display area AA, but also improves the uniformity of the second power supply voltage PVEE at different locations in the display area AA, thereby further improving the brightness uniformity of the display panel 01.

[0062] Meanwhile, by arranging the first sub-virtual trace 511 and the second sub-virtual trace 512 at intervals, it is beneficial to make the first power supply voltage PVDD and the second power supply voltage PVEE distributed more evenly in the first direction Y, thereby further improving the uniformity of the first power supply voltage PVDD and the second power supply voltage PVEE at different positions in the display area AA.

[0063] Optional, such as Figure 4 As shown, in the first direction Y, the first sub-virtual trace 511 and the second sub-virtual trace 512 are arranged alternately in alternating rows. This is to significantly improve the uniformity of the first power supply voltage PVDD and the second power supply voltage PVEE in the display area AA.

[0064] Figure 5 This is a plan view of another display panel provided in an embodiment of this application.

[0065] In one embodiment of this application, such as Figure 5 As shown, at least a portion of the second virtual traces 52 are electrically connected to the first sub-virtual traces 511. That is, among the multiple second virtual traces 52, a portion of the second virtual traces 52 can be electrically connected to the first sub-virtual traces 511 for transmitting the first power supply voltage PVDD.

[0066] Through research, the inventors discovered that the second electrode of the light-emitting device 20 is usually a solid layer structure. Since the second electrode of the light-emitting device 20 is electrically connected to the second power signal line 70, the uniformity of the second power supply voltage PVEE in the display area AA is relatively high. The uniformity of the first power supply voltage PVDD in the display area AA has a significant impact on the brightness uniformity of the display screen.

[0067] In this embodiment of the application, by setting a portion of the second virtual trace 52 to be electrically connected to the first sub-virtual trace 511, the grid density of the grid structure transmitting the first power supply voltage PVDD can be increased, which is beneficial to further reduce the voltage drop of the first power supply voltage PVDD, thereby further improving the uniformity of the first power supply voltage PVDD at different positions in the display area AA, and further improving the brightness uniformity of the display panel 01.

[0068] Optional, such as Figure 5 As shown, multiple second virtual traces 52 are arranged along the second direction X, and the multiple second virtual traces 52 include a third sub-virtual trace 521 and a fourth sub-virtual trace 522.

[0069] The third sub-virtual trace 521 is electrically connected to the first sub-virtual trace 511, and the fourth sub-virtual trace 522 is electrically connected to the second sub-virtual trace 512. The fourth sub-virtual trace 522 can be the second power signal line 70.

[0070] In the second direction X, the third sub-virtual trace 521 and the fourth sub-virtual trace 522 are arranged alternately.

[0071] For example, such as Figure 5 As shown, in the second direction X, the third sub-virtual route 521 and the fourth sub-virtual route 522 are arranged alternately in alternating columns.

[0072] In this embodiment, the third sub-virtual trace 521 and the fourth sub-virtual trace 522 are arranged at intervals. In the second direction X, this helps to make the first power supply voltage PVDD more uniformly distributed, thereby further improving the uniformity of the first power supply voltage PVDD at different positions in the display area AA.

[0073] In one embodiment of this application, please continue to refer to Figure 5 The first sub-virtual route 511 intersects with the third sub-virtual route 521, and the first sub-virtual route 511 intersects with the fourth sub-virtual route 522.

[0074] Among them, the first sub-virtual trace 511 and the third sub-virtual trace 521 include a via K1, and there is no via between the first sub-virtual trace 511 and the fourth sub-virtual trace 522.

[0075] As can be seen from the foregoing analysis, the first sub-virtual trace 511, the third sub-virtual trace 521, and the fourth sub-virtual trace 522 are located in different film layers. In this embodiment of the application, a via K1 is included between the first sub-virtual trace 511 and the third sub-virtual trace 521. The first sub-virtual trace 511 and the third sub-virtual trace 521 can be electrically connected through the via K1 to form a mesh structure and transmit the first power supply voltage PVDD.

[0076] By eliminating vias between the first sub-virtual trace 511 and the fourth sub-virtual trace 522, a short circuit between them can be avoided.

[0077] In addition, such as Figure 5 As shown, a via K2 can be provided between the second sub-virtual trace 512 and the fourth sub-virtual trace 522. The two are electrically connected through the via K2, which can form a mesh structure and transmit the second power supply voltage PVEE. There is no via between the second sub-virtual trace 512 and the third sub-virtual trace 521 to avoid short circuits between them.

[0078] Figure 6 This is a partially enlarged schematic diagram of a display panel provided in an embodiment of this application.

[0079] In one embodiment of this application, such as Figure 6 As shown, the first power signal line 60 includes a first sub-power signal line 61 and a second sub-power signal line 62 disposed in different layers. Both the first sub-power signal line 61 and the second sub-power signal line 62 extend along the first direction Y. Along a direction perpendicular to the plane where the substrate PI is located, the first sub-power signal line 61 and the second sub-power signal line 62 overlap, and the first sub-power signal line 61 and the second sub-power signal line 62 can be connected by vias.

[0080] The first sub-power signal line 61 is located on the side of the second sub-power signal line 62 away from the substrate PI.

[0081] The second sub-power signal line 62 is connected to the first virtual trace 51. That is, the first virtual trace 51 can achieve electrical connection with the first power signal line 60 by connecting to the second sub-power signal line 62.

[0082] In this embodiment, the first power signal line 60 is configured as a double-layer structure, which helps to further reduce the impedance of the first power signal line 60, thereby helping to further reduce the voltage drop of the first power supply voltage PVDD and improve the uniformity of the first power supply voltage PVDD at different positions in the display area AA.

[0083] Optionally, the second sub-power signal line 62 is on the same layer as the first virtual trace 51. In this way, the second sub-power signal line 62 and the first virtual trace 51 can be electrically connected without drilling, which helps to save drilling process and reduce the manufacturing cost of display panel 01.

[0084] In one embodiment of this application, such as Figure 6 As shown, the first sub-power signal line 61 is a continuous structure, while the second sub-power signal line 62 is a discontinuous structure. That is, there is a break DK in the second sub-power signal line 62 extending along the first direction Y.

[0085] As can be seen from the foregoing analysis, when the first virtual trace 51 includes a first sub-virtual trace 511 and a second sub-virtual trace 512, the first sub-virtual trace 511 is electrically connected to the first power signal line 60, and the second sub-virtual trace 512 is electrically insulated from the first power signal line 60. The first sub-virtual trace 511 and the second sub-virtual trace 512 are arranged at intervals.

[0086] In this embodiment, the second sub-power signal line 62 is configured as a discontinuous structure. When the second sub-power signal line 62 is on the same layer as the first virtual trace 51, the first sub-virtual trace 511 can be connected to the second sub-power signal line 62 to achieve electrical connection between the first sub-virtual trace 511 and the first power signal line 60. The second sub-virtual trace 512 extends through the break DK region of the second sub-power signal line 62 to avoid short circuit between the second sub-virtual trace 512 and the first power signal line 60.

[0087] Meanwhile, in this embodiment, the first sub-power signal line 61 is set to a continuous structure. Therefore, the unconnected parts of the second sub-power signal line 62 can be electrically connected to the same first sub-power signal line 61 through vias, which helps to reduce the difficulty of the peripheral signal lines providing the first power supply voltage PVDD to the first sub-power signal line 61 and the second sub-power signal line 62.

[0088] Optionally, the first virtual trace 51 is located on the side of the second virtual trace 52 close to the substrate PI, and the second virtual trace 52 is on the same layer as the data signal line 30.

[0089] For example, such as Figure 7 As shown, Figure 7 This is a schematic diagram of a display panel structure provided in an embodiment of this application. The light-emitting device 20 includes a first electrode 21, a light-emitting layer 22, and a second electrode 23. The light-emitting layer 22 is located between the first electrode 21 and the second electrode 23. The first electrode 21 is located on the side of the light-emitting layer 22 closer to the substrate PI. The first electrode 21 can be the first electrode (anode) of the light-emitting device 20, and the second electrode 23 can be the second electrode (cathode) of the light-emitting device 20.

[0090] The pixel circuit 10 is located between the substrate PI and the first electrode 21 of the light-emitting device 20. The pixel circuit 10 includes a plurality of transistors T (only one transistor is shown in the figure). The transistor T includes a semiconductor layer TF, a gate G, a source S and a drain D. The gate G is located on the side of the semiconductor layer TF away from the substrate PI. The source S and the drain D are on the same layer and are located on the side of the gate G away from the substrate PI.

[0091] The first virtual trace 51, the first segment 41 (not shown in the figure) and the second sub-power signal line 62 are on the same layer as the source S of the transistor T. The second virtual trace 52, the second segment 42 (not shown in the figure), the data signal line 30 and the first sub-power signal line 61 are located between the source S of the transistor T and the first electrode 21 of the light-emitting device 20.

[0092] Figure 8 This is a plan view of another display panel provided in an embodiment of this application.

[0093] In one embodiment of this application, such as Figure 8 As shown, the display panel 01 also includes multiple first voltage signal lines 80. The first voltage signal lines 80 extend along the second direction X and are arranged along the first direction Y. The first voltage signal lines 80 are electrically connected to the pixel circuit 10 and are used to transmit reset voltage or bias adjustment voltage to the pixel circuit 10.

[0094] For example, the first voltage signal line 80 can be used to, for example, Figure 3 The pixel circuit 10 shown transmits a first reset voltage Vref1 and / or a second reset voltage Vref2.

[0095] For example, the first voltage signal line 80 can be used to, for example, Figure 9 The pixel circuit 10 shown transmits the bias adjustment voltage DVH. Figure 9 This is a schematic diagram of yet another pixel circuit provided in an embodiment of this application. Figure 9 The pixel circuit shown is Figure 3 The difference in the pixel circuit shown is that the pixel circuit 10 also includes a bias adjustment transistor T7. The first terminal of the bias adjustment transistor T7 receives the bias adjustment voltage DVH, the second terminal is electrically connected to the first terminal of the driving transistor Td, and the gate is electrically connected to the fourth scan line S4.

[0096] Among them, multiple second virtual traces 52 are arranged along the second direction X, and at least some of the second virtual traces 52 are electrically connected to the first voltage signal line 80.

[0097] In this embodiment, at least a portion of the second virtual traces 52 arranged along the second direction X are electrically connected to the first voltage signal line 80. Therefore, in the display panel 01, the second virtual traces 52 extending along the first direction Y and the first voltage signal line 80 extending along the second direction X can form a mesh structure and transmit reset voltage or bias adjustment voltage to the pixel circuit 10. This helps reduce the voltage drop of the reset voltage or adjustment voltage in the display area AA, improves the uniformity of the reset voltage or adjustment voltage at different locations in the display area AA, and thus helps improve the display quality of the display panel 01.

[0098] Optionally, in the display panel 01, a portion of the second virtual traces 52 are electrically connected to a portion of the first voltage signal lines 80 to transmit reset voltage to the pixel circuit 10, and a portion of the second virtual traces 52 are electrically connected to a portion of the first voltage signal lines 80 to transmit bias adjustment voltage to the pixel circuit 10. This improves both the uniformity of the reset voltage at different positions in the display area AA and the uniformity of the bias adjustment voltage at different positions in the display area AA.

[0099] In one embodiment of this application, combined with Figure 3 and Figure 7 As shown, the pixel circuit 10 includes a storage capacitor Cst, which includes a first electrode C1 and a second electrode C2 opposite to each other. The second electrode C2 is located on the side of the first electrode C1 away from the substrate PI.

[0100] The first power signal line 60 is located on the side of the second electrode C2 away from the substrate PI, and the first power signal line 60 is electrically connected to the second electrode C2.

[0101] For example, such as Figure 7 As shown, the first electrode C1 is on the same layer as the gate G of transistor T, and the second electrode C2 is located between the source S and the gate G of transistor T.

[0102] Combination Figure 10 As shown, Figure 10 This is a plan view of another display panel provided in an embodiment of the present application. The display panel 01 also includes a plurality of connection structures MC on the same layer as the second electrode plate C2. Among the plurality of connection structures MC, there is a first connection structure MC1 extending along the first direction Y and a second connection structure MC2 extending along the second direction X.

[0103] At least some of the second electrode plates C2 arranged along the first direction Y are connected by the first connecting structure MC1, and at least some of the second electrode plates C2 arranged along the second direction X are connected by the second connecting structure MC2.

[0104] In other words, among the multiple pixel circuits 10 arranged in the first direction Y, the second plates C2 of the storage capacitor Cst in at least some of the pixel circuits 10 can be connected sequentially through the first connection structure MC1. Similarly, among the multiple pixel circuits 10 arranged in the second direction X, the second plates C2 of the storage capacitor Cst in at least some of the pixel circuits 10 can be connected sequentially through the second connection structure MC2.

[0105] In this embodiment, the second electrode plate C2 arranged along the first direction Y and the second electrode plate C2 arranged along the second direction X can be connected by the connecting structure MC to form a grid structure. Since the second electrode plate C2 is electrically connected to the first power signal line 60, the first power supply voltage PVDD on the first power signal line 60 can also be transmitted through the grid-shaped second electrode plate C2 in the display area AA. This is beneficial to further reduce the voltage drop of the first power supply voltage PVDD, thereby further improving the uniformity of the first power supply voltage PVDD at different positions in the display area AA and further improving the brightness uniformity of the display panel 01.

[0106] Please continue to refer to this. Figure 10 In one embodiment of this application, the display panel 01 includes multiple reset voltage signal lines XL, which extend along a second direction X and are electrically connected to the pixel circuit 10.

[0107] For example, the reset voltage signal line XL can be used to, for example, Figure 3 The pixel circuit 10 shown transmits a first reset voltage Vref1 and / or a second reset voltage Vref2.

[0108] The reset voltage signal line XL and the second electrode C2 are located in different film layers.

[0109] This configuration helps to avoid interference with the reset voltage signal line XL when the second electrode C2 is connected in a grid-like structure via the connection structure MC, and also helps to reduce the manufacturing difficulty of connecting the second electrode C2 in a grid-like structure.

[0110] Optionally, the reset voltage signal line XL is located on the side of the second electrode C2 away from the substrate PI.

[0111] For example, the reset voltage signal line XL is on the same layer as the first virtual trace 51. In this way, the reset voltage signal line XL can be fabricated using the same process and materials as the first virtual trace 51, which helps to reduce the resistance of the reset voltage signal line XL, thereby helping to reduce the loss of the power signal on the reset voltage signal line XL.

[0112] Figure 11 This is a plan view of another display panel provided in an embodiment of this application.

[0113] In one embodiment of this application, combined with Figure 7 and Figure 11 As shown, the pixel circuit 10 includes multiple transistors T( Figure 7 (Only one is shown), the display panel 01 also includes a shielding structure BSM, which is located between the transistor T and the substrate PI. Specifically, the shielding structure BSM is located between the semiconductor layer FT of the transistor T and the substrate PI.

[0114] Along the direction Z perpendicular to the plane containing the substrate PI, the shielding structure BSM at least partially overlaps with the semiconductor layer FT of the transistor T. The shielding structure BSM can be used to protect the semiconductor layer FT of the transistor T, and can also be used as the bottom gate of the transistor T.

[0115] The shielding structure BSM is electrically connected to the first power signal line 60 (not shown in the figure), and the shielding structure BSM is in the form of a mesh.

[0116] In this embodiment, the shielding structure BSM is set to be grid-like. In the display area AA, the first power supply voltage PVDD on the first power signal line 60 can also be transmitted through the grid-like shielding structure BSM, which is beneficial to further reduce the voltage drop of the first power supply voltage PVDD, thereby further improving the uniformity of the first power supply voltage PVDD at different positions in the display area AA and improving the brightness uniformity of the display panel 01.

[0117] Figure 12 This is a plan view of another display panel provided in an embodiment of this application.

[0118] like Figure 12 As shown, in one embodiment of this application, the non-display area NA includes a first non-display area NA1 located on one side of the display area AA. The first non-display area NA1 and the display area AA are arranged along the first direction Y. The first non-display area NA1 can be the "bottom" border of the display panel 01.

[0119] The first non-display area NA1 includes a first power supply electrode DY1, which is electrically connected to the first power signal line 60. The first power supply electrode DY1 can transmit the received first power supply voltage PVDD to the first power signal line 60 in the display area AA.

[0120] The display panel 01 includes a first edge B1 extending along a first direction Y. The first edge B1 can be either the "left" edge or the "right" edge of the display panel 01. The first power electrode DY1 includes a first portion DY11 near the first edge B1. Due to the limited space at the first edge B1, the width of the first portion DY1 is typically narrow.

[0121] Combination Figure 13 As shown, Figure 13 for Figure 12 A schematic diagram of the structure of the first part, the first part DY11 includes a first sublayer M1, a second sublayer M2 and a third sublayer M3 electrically connected, the second sublayer M2 is located between the first sublayer M1 and the third sublayer M3, and the third sublayer M3 is located on the side of the first sublayer M1 away from the substrate PI.

[0122] For example, an insulating layer is included between the first sub-layer M1 and the second sub-layer M2, and an insulating layer is included between the second sub-layer M2 and the third sub-layer M3. The first sub-layer M1 and the second sub-layer M2 are connected by a via, and the second sub-layer M2 and the third sub-layer M3 are connected by a via.

[0123] Combination Figure 3 and Figure 7 As shown, the pixel circuit 10 includes a storage capacitor Cst, which includes a first electrode C1 and a second electrode C2. The second electrode C2 is located on the side of the first electrode C1 away from the substrate PI, and the second electrode C2 is electrically connected to the first power signal line 60.

[0124] In this section, the first sub-layer M1 of the first division DY11 is on the same layer as the second electrode plate C2.

[0125] In this embodiment, the first sub-section DY11 is configured to include an electrically connected first sub-layer M1, a second sub-layer M2, and a third sub-layer M3. This reduces the impedance of the first sub-section DY11, which helps to reduce the voltage drop of the first power supply voltage PVDD on the first sub-section DY11. This, in turn, helps to improve the accuracy of the first power supply voltage PVDD on the first power signal line 60 in the display area AA, and further improves the uniformity of the first power supply voltage PVDD at different locations in the display area AA.

[0126] Meanwhile, by setting the first sub-layer M1 of the first division DY11 to be on the same layer as the second electrode plate C2, since the second electrode plate C2 is electrically connected to the first power signal line 60, the first division DY11 can be directly connected to the second electrode plate C2 of the display area AA through the first sub-layer M1. The electrical connection between the first division DY11 and the first power signal line 60 can be achieved without drilling holes and changing wires, which helps to reduce the process complexity of the display panel 01 and reduce costs.

[0127] Optionally, the third sublayer M3 is on the same layer as the data signal line 30, and the second sublayer M2 is on the same layer as the first virtual trace 51. Both the third sublayer M3 and the second sublayer M2 can be titanium-aluminum-titanium structures to reduce the impedance of the first section DY11 to a greater extent.

[0128] Figure 14 for Figure 12 Another structural diagram of the first part.

[0129] In one embodiment of this application, such as Figure 14 As shown, the first sub-section DY11 also includes a fourth sub-layer M4, which is located on the side of the first sub-layer M1 close to the substrate PI.

[0130] Optionally, the fourth sublayer M4 is on the same layer as the gate G of transistor T.

[0131] Based on this configuration, the embodiments of this application can further reduce the impedance of the first section DY11, thereby helping to further reduce the voltage drop of the first power supply voltage PVDD on the first section DY11 and improve the uniformity of the first power supply voltage PVDD in the display area AA.

[0132] Figure 15 This is a plan view of another display panel provided in an embodiment of this application.

[0133] In one embodiment of this application, such as Figure 15 As shown, the non-display area NA includes multiple first power supply voltage detection lines 90, which are electrically connected to the first power supply signal line 60 in the display area AA.

[0134] Among them, at least a portion of the first power supply voltage detection line 90 is electrically connected to the first power supply signal line 60 at different edges of the display area AA.

[0135] For example, such as Figure 15 As shown, the display area AA includes edges E1 and E2 opposite to each other along the second direction X, and also includes an edge E3 away from the first non-display area NA1. Edges E1 and E2 can be the "left" edge and "right" edge of the display area AA, respectively, and edge E3 can be the "top" edge of the display area AA.

[0136] The multiple first power supply voltage detection lines 90 include a first sub-power supply voltage detection line 91, a second sub-power supply voltage detection line 92, and a third sub-power supply voltage detection line 93. The first sub-power supply voltage detection line 91 is electrically connected to the first power signal line 60 near edge E1, the second sub-power supply voltage detection line 92 is electrically connected to the first power signal line 60 near edge E2, and the third sub-power supply voltage detection line 93 is electrically connected to the first power signal line 60 near edge E3.

[0137] In this embodiment, the first power supply voltage PVDD on the first power signal line 60 at different edges of the display area AA can be detected by the first power supply voltage detection line 90. In this way, the control chip can adjust the brightness at different positions of the display area AA according to the actual potential of the first power supply voltage PVDD at different edges of the display area AA, so as to improve the brightness uniformity of the display panel 01.

[0138] In addition, a compensation voltage can be transmitted from the first power supply voltage detection line 90 to the first power supply signal line 60 at a lower potential, so that the potential of the first power supply voltage PVDD at different edges of the display area AA tends to be consistent, thereby improving the uniformity of the first power supply voltage PVDD in the display area AA.

[0139] Optional, such as Figure 15As shown, the non-display area NA also includes a second power supply electrode DY2, which is electrically connected to the second power signal line 70. The second power supply electrode DY2 can be used to transmit the second power supply voltage PVEE to the second power signal line 70 in the display area AA. The second power supply electrode DY2 can surround the display area AA.

[0140] The second power supply electrode DY2 is located on the side of the first power supply voltage detection line 90 away from the substrate PI, and overlaps with the first power supply voltage detection line 90 along a direction perpendicular to the plane of the substrate PI.

[0141] This configuration helps reduce the area occupied by the second power electrode DY2 and the first power voltage detection line 90 as a whole in the non-display area NA, thereby avoiding increasing the width of the non-display area NA and facilitating the realization of a narrow bezel on the display panel 01.

[0142] Figure 16 This is a schematic diagram of a display device provided in an embodiment of this application.

[0143] This application provides a display device 02, such as... Figure 16 As shown, the display device 02 includes the display panel 01 as provided in the above embodiments. Exemplary examples show that the display device 02 can be an electronic device such as a mobile phone, computer, television, vehicle display, or wearable display, and this application does not impose any specific limitations.

[0144] In the display device 02, a first power signal line 60 extending along the first direction Y is provided and electrically connected to a first virtual trace 51 extending along the second direction X. In the display panel 01, the first power signal line 60 and the first virtual trace 51 can form a grid structure and transmit the same first power supply voltage PVDD. This helps to reduce the voltage drop of the first power supply voltage PVDD in the display area AA and improve the uniformity of the first power supply voltage PVDD at different positions in the display area AA, thereby improving the brightness uniformity of the display panel 01.

[0145] Meanwhile, since the first virtual trace 51 is on the same layer as the first segment 41 of the connecting signal line 40, the first virtual trace 51 can be made of the same material as the connecting signal line 40. The sheet resistance of the material of the connecting signal line 40, which is electrically connected to the data signal line 30, is usually small. Therefore, making the first virtual trace 51 and the first power signal line 60 electrically connected to form a mesh structure is also beneficial to reduce the impedance of the mesh structure to a large extent, further reducing the voltage drop of the first power supply voltage PVDD in the display area AA, thereby further improving the uniformity of the first power supply voltage PVDD at different locations in the display area AA.

[0146] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, Includes a substrate and a display area and a non-display area located on one side of the substrate, the non-display area surrounding at least a portion of the display area, the display area comprising: A light-emitting device and a pixel circuit, wherein the pixel circuit is electrically connected to the light-emitting device; Multiple data signal lines, the data signal lines extending along a first direction, the multiple data signal lines arranged along a second direction, the first direction intersecting the second direction; Multiple connection signal lines, each connection signal line including an electrically connected first segment and a second segment, the first segment extending along a second direction and the second segment extending along the first direction; the connection signal line is electrically connected to the data signal line in the edge region; Multiple virtual traces, including a first virtual trace extending along the second direction and a second virtual trace extending along the first direction, wherein the first virtual trace is on the same layer as the first segment and the second virtual trace is on the same layer as the second segment; Multiple first power signal lines extend along the first direction, and multiple first power signal lines are arranged along the second direction. The first power signal lines are electrically connected to the pixel circuit. At least a portion of the first virtual trace is electrically connected to the first power signal line.

2. The display panel according to claim 1, characterized in that, Multiple first virtual traces are arranged along the first direction, and the multiple first virtual traces include a first sub-virtual trace and a second sub-virtual trace; At least a portion of the second virtual trace serves as a second power signal line. The first sub-virtual trace is electrically connected to the first power signal line, and the second sub-virtual trace is electrically connected to the second power signal line. The first sub-virtual trace and the second sub-virtual trace are arranged at intervals.

3. The display panel according to claim 2, characterized in that, In the first direction, the first sub-virtual trace and the second sub-virtual trace are arranged alternately in rows.

4. The display panel according to claim 2, characterized in that, At least a portion of the second virtual trace is electrically connected to the first sub-virtual trace.

5. The display panel according to claim 4, characterized in that, Multiple second virtual traces are arranged along the second direction. Among the multiple second virtual traces, there are a third sub-virtual trace and a fourth sub-virtual trace. The third sub-virtual trace is electrically connected to the first sub-virtual trace, and the fourth sub-virtual trace serves as the second power signal line. In the second direction, the third sub-virtual trace and the fourth sub-virtual trace are arranged at intervals.

6. The display panel according to claim 5, characterized in that, The first sub-virtual trace intersects with the third sub-virtual trace, and the first sub-virtual trace also intersects with the fourth sub-virtual trace; The first sub-virtual trace and the third sub-virtual trace are connected by a via, while the first sub-virtual trace and the fourth sub-virtual trace are not connected by a via.

7. The display panel according to claim 1, characterized in that, The first power signal line includes a first sub-power signal line and a second sub-power signal line disposed in different layers. Both the first sub-power signal line and the second sub-power signal line extend along the first direction and along a direction perpendicular to the plane where the substrate is located. The first sub-power signal line and the second sub-power signal line overlap. The first sub-power signal line is located on the side of the second sub-power signal line away from the substrate. The second sub-power signal line is connected to the first virtual trace.

8. The display panel according to claim 7, characterized in that, The second sub-power signal line is on the same layer as the first virtual trace.

9. The display panel according to claim 7, characterized in that, The first sub-power signal line is a continuous structure, while the second sub-power signal line is a discontinuous structure.

10. The display panel according to claim 1, characterized in that, The first virtual trace is located on the side of the second virtual trace closer to the substrate, and the second virtual trace is on the same layer as the data signal line.

11. The display panel according to claim 1, characterized in that, The display panel further includes a first voltage signal line extending along the second direction, the first voltage signal line being electrically connected to the pixel circuit, and the first voltage signal line being used to transmit a reset voltage or a bias adjustment voltage to the pixel circuit. Among them, multiple second virtual traces are arranged along the second direction, and at least some of the second virtual traces are electrically connected to the first voltage signal line.

12. The display panel according to claim 1, characterized in that, The pixel circuit includes a storage capacitor, which includes a first electrode plate and a second electrode plate, wherein the second electrode plate is located on the side of the first electrode plate away from the substrate; The first power signal line is located on the side of the second electrode plate away from the substrate, and the first power signal line is electrically connected to the second electrode plate; The display panel also includes a plurality of connection structures on the same layer as the second electrode plate, including a first connection structure extending along the first direction and a second connection structure extending along the second direction; Wherein, at least a portion of the second electrode plates arranged along the first direction are connected by the first connecting structure, and at least a portion of the second electrode plates arranged along the second direction are connected by the second connecting structure.

13. The display panel according to claim 12, characterized in that, The display panel includes multiple reset voltage signal lines, which extend along the second direction and are electrically connected to the pixel circuit. The reset voltage signal line and the second electrode are located in different film layers.

14. The display panel according to claim 13, characterized in that, The reset voltage signal line is located on the side of the second electrode away from the substrate.

15. The display panel according to claim 1, characterized in that, The pixel circuit includes a plurality of transistors, and the display panel further includes a shielding structure located between the transistors and the substrate along a direction perpendicular to the plane of the substrate, wherein the shielding structure at least partially overlaps with the semiconductor layer of the transistors; The shielding structure is electrically connected to the first power signal line, and the shielding structure is in the form of a mesh.

16. The display panel according to claim 1, characterized in that, The non-display area includes a first non-display area located on one side of the display area, and the first non-display area and the display area are arranged along the first direction; The first non-display area includes a first power electrode, which is electrically connected to the first power signal line; The display panel includes a first edge extending along the first direction, and the first power electrode includes a first portion near the first edge. The first portion includes a first sublayer, a second sublayer, and a third sublayer that are electrically connected. The second sublayer is located between the first sublayer and the third sublayer, and the third sublayer is located on the side of the first sublayer away from the substrate. The pixel circuit includes a storage capacitor, which includes a first electrode plate and a second electrode plate. The second electrode plate is located on the side of the first electrode plate away from the substrate, and the second electrode plate is electrically connected to the first power signal line. The first sub-layer is on the same layer as the second electrode plate.

17. The display panel according to claim 16, characterized in that, The third sub-layer is on the same layer as the data signal line.

18. The display panel according to claim 16, characterized in that, The first sub-section further includes a fourth sub-layer located on the side of the first sub-layer closer to the substrate.

19. The display panel according to claim 1, characterized in that, The non-display area includes multiple first power voltage detection lines, which are electrically connected to the first power signal lines. At least a portion of the first power supply voltage detection lines are electrically connected to the first power supply signal lines at different edges of the display area.

20. The display panel according to claim 19, characterized in that, The non-display area further includes a second power electrode, which is located on the side of the first power voltage detection line away from the substrate, along a direction perpendicular to the plane of the substrate, and overlaps with the first power voltage detection line.

21. A display device, characterized in that, Includes the display panel as described in any one of claims 1-20.

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