A low-emi high-reliability enhanced gallium nitride drive circuit

Abstract

This invention discloses a low-EMI, high-reliability enhanced gallium nitride (GaN) drive circuit, comprising a drive-on control network, a drive-off control network, a segmented drive network, a clamping network, a fast-turn-off network, and a drive output network connected in sequence. For driving GaN power devices, a unique segmented drive current control structure is proposed, breaking away from the traditional fixed drive current mode. This effectively controls the dv / dt of GaN power devices without affecting switching speed and losses. Furthermore, by designing a clamping circuit, this invention stabilizes the drive voltage and current, reduces the generation of high-frequency harmonics, lowers EMI, limits overshoot voltage to a safe range, absorbs excess energy, improves the reliability of the drive circuit, and effectively protects GaN power devices.

Description

Technical Field

[0001] This invention belongs to the field of gallium nitride power device technology, specifically relating to the design of an enhanced gallium nitride drive circuit with low EMI and high reliability. Background Technology

[0002] Compared to silicon power devices, wide-bandgap gallium nitride (GaN) power devices have smaller parasitic capacitance and superior conductivity, enabling power converters to achieve switching frequencies of several megahertz or even tens of megahertz, significantly improving power efficiency. However, the increased switching speed generates larger di / dt (rate of change of current) and dv / dt (rate of change of voltage) during the turn-on transition, leading to a series of reliability issues. The common-mode transient noise generated by dv / dt affects the isolation structure, while increased di / dt and dv / dt also exacerbate electromagnetic interference (EMI) noise and gate oscillation. In addition, at the moment of switch turn-off, the sudden current change causes the inductor to generate a high induced electromotive force, which, when superimposed on the supply voltage, creates an overshoot. Summary of the Invention

[0003] The purpose of this invention is to propose an enhanced gallium nitride (GaN) drive circuit with low EMI and high reliability, which can effectively control the dv / dt of GaN power devices without affecting the switching speed and losses.

[0004] The technical solution of this invention is as follows: a low-EMI, high-reliability enhanced gallium nitride (GaN) drive circuit, comprising a drive-on control network, a drive-off control network, a segmented drive network, a clamping network, a fast-turn-off network, and a drive output network connected in sequence. The segmented drive network is connected to the source of a high-voltage NMOS transistor HN3. The gate of the high-voltage NMOS transistor HN3 is connected to a control signal NB1. The drain of the high-voltage NMOS transistor HN3 is connected to the drain of PMOS transistor P2, one end of resistor R7, the drain of PMOS transistor P3, the gate of PMOS transistor P3, and the gate of PMOS transistor P4 through resistor R8. The gate of PMOS transistor P2 is connected to the drive-off control network. The source of PMOS transistor P2, the other end of resistor R7, the source of PMOS transistor P3, and the source of PMOS transistor P4 are all connected to the power supply HVDD. The drain of PMOS transistor P4 is connected to the clamping network, the fast-turn-off network, and the drive output network. The drive output network outputs the drive voltage DRI of the GaN power device.

[0005] Furthermore, the drive-on control network includes an NMOS transistor N1. The source of NMOS transistor N1 is grounded, its gate is connected to the PWM enable signal PWM_ON, and its drain is connected to the source of a high-voltage NMOS transistor HN1 through a resistor R16. The gate of the high-voltage NMOS transistor HN1 is connected to the control signal NB1, and its drain is connected to one end of a resistor R2. The other end of resistor R2 is connected to one end of resistor R1, the anode of diode DZ1, and one end of resistor R3. The other end of resistor R1 and the cathode of diode DZ1 are both connected to the power supply HVDD, and the other end of resistor R3 is connected to the drive-off control network.

[0006] Furthermore, the drive shutdown control network includes an NMOS transistor N3. The source of NMOS transistor N3 is grounded, its gate is connected to the PWM shutdown signal PWM_OFF, and its drain is connected to the source of the high-voltage NMOS transistor HN2 through resistor R17. The gate of the high-voltage NMOS transistor HN2 is connected to the control signal NB1, and its drain is connected to the drain of PMOS transistor P1, one end of resistor R4, and one end of resistor R5. The gate of PMOS transistor P1 is connected to the other end of resistor R3, and the source of PMOS transistor P1 and the other end of resistor R4 are both connected to the power supply HVDD. The other end of resistor R5 is connected to the gate of PMOS transistor P2.

[0007] Furthermore, the segmented drive network includes three parallel current mirror replication circuits. The first current mirror replication circuit includes a triple current amplification MOSFET and a switching transistor S1. The source of the switching transistor S1 is grounded, and its drain is connected to the source of the triple current amplification MOSFET. The second current mirror replication circuit includes a double current amplification MOSFET and a switching transistor S2. The source of the switching transistor S2 is grounded, and its drain is connected to the source of the double current amplification MOSFET. The third current mirror replication circuit includes a single current amplification MOSFET and a switching transistor S3. The source of the switching transistor S3 is grounded, and its drain is connected to the source of the single current amplification MOSFET. The gates of the single current amplification MOSFET, the double current amplification MOSFET, and the triple current amplification MOSFET are all connected to the control signal NB2. The drains of the single current amplification MOSFET, the double current amplification MOSFET, and the triple current amplification MOSFET are all connected to the source of the high-voltage NMOS transistor HN3.

[0008] Furthermore, the clamping network includes a source follower P5, the source of which is connected to the anode of diode DZ2, its gate is connected to the source potential sampling signal CS of the gallium nitride power device, its drain is connected to the grounding resistor R14, and the cathode of diode DZ2 is connected to the drain of PMOS transistor P4 through resistor R10.

[0009] Furthermore, the fast turn-off network includes a high-voltage NMOS transistor HN7. The source of the high-voltage NMOS transistor HN7 is grounded, its gate is connected to the PWM turn-off signal PWM_OFF, its drain is connected to one end of resistor R13, the other end of resistor R13 is connected to one end of resistor R11 and the drive output network, and the other end of resistor R11 is connected to the drain of PMOS transistor P4.

[0010] Furthermore, the drive output network includes high-voltage NMOS transistors HN4, HN5, and HN6. The source of high-voltage NMOS transistor HN6 is grounded, its gate is connected to the PWM off signal PWM_OFF, and its drain is connected to the source of high-voltage NMOS transistors HN4 and HN5, as well as the grounding resistor R15. It serves as the output terminal of the drive output network to output the drive voltage DRI of the gallium nitride power device. The drain of high-voltage NMOS transistor HN5 is connected to the power supply HVDD, and its gate is connected to the gate of high-voltage NMOS transistor HN4, the drain of high-voltage NMOS transistor HN4, one end of resistor R12, and the other end of resistor R13. The other end of resistor R12 is connected to the drain of PMOS transistor P4.

[0011] The beneficial effects of this invention are:

[0012] (1) This invention proposes a unique segmented drive current control structure for driving gallium nitride power devices, which breaks the traditional fixed drive current mode and can effectively control the dv / dt of gallium nitride power devices without affecting the switching speed and loss.

[0013] (2) By designing a clamping circuit, the present invention stabilizes the driving voltage and current, reduces the generation of high-frequency harmonics, reduces EMI, limits overshoot voltage to a safe range, absorbs excess energy, improves the reliability of the driving circuit, and can effectively protect gallium nitride power devices. Attached Figure Description

[0014] Figure 1 The diagram shown is a schematic of an enhanced gallium nitride driver circuit structure with low EMI and high reliability provided in an embodiment of the present invention. Detailed Implementation

[0015] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, and are not intended to limit the scope of the invention.

[0016] This invention provides an enhanced gallium nitride (GaN) drive circuit with low EMI and high reliability, such as... Figure 1As shown, the system includes a drive-on control network, a drive-off control network, a segmented drive network, a clamping network, a fast-turn-off network, and a drive output network connected in sequence. The segmented drive network is connected to the source of the high-voltage NMOS transistor HN3. The gate of the high-voltage NMOS transistor HN3 is connected to the control signal NB1. The drain of the high-voltage NMOS transistor HN3 is connected to the drain of PMOS transistor P2, one end of resistor R7, the drain of PMOS transistor P3, the gate of PMOS transistor P3, and the gate of PMOS transistor P4 through resistor R8. The gate of PMOS transistor P2 is connected to the drive-off control network. The source of PMOS transistor P2, the other end of resistor R7, the source of PMOS transistor P3, and the source of PMOS transistor P4 are all connected to the power supply HVDD. The drain of PMOS transistor P4 is connected to the clamping network, the fast-turn-off network, and the drive output network. The drive output network outputs the drive voltage DRI of the gallium nitride power device.

[0017] like Figure 1 As shown, the drive-on control network is used to drive the gallium nitride power device to turn on, including an NMOS transistor N1. The source of NMOS transistor N1 is grounded, its gate is connected to the PWM turn-on signal PWM_ON, and its drain is connected to the source of high-voltage NMOS transistor HN1 through resistor R16. The gate of high-voltage NMOS transistor HN1 is connected to the control signal NB1, and its drain is connected to one end of resistor R2. The other end of resistor R2 is connected to one end of resistor R1, the anode of diode DZ1, and one end of resistor R3. The other end of resistor R1 and the cathode of diode DZ1 are both connected to the power supply HVDD, and the other end of resistor R3 is connected to the drive-off control network.

[0018] like Figure 1 As shown, the drive shutdown control network is used to control the shutdown of gallium nitride power devices. It includes an NMOS transistor N3, whose source is grounded and whose gate is connected to the PWM shutdown signal PWM_OFF. Its drain is connected to the source of a high-voltage NMOS transistor HN2 through a resistor R17. The gate of the high-voltage NMOS transistor HN2 is connected to the control signal NB1. Its drain is connected to the drain of a PMOS transistor P1, one end of a resistor R4, and one end of a resistor R5. The gate of the PMOS transistor P1 is connected to the other end of a resistor R3. The source of the PMOS transistor P1 and the other end of a resistor R4 are both connected to the power supply HVDD. The other end of a resistor R5 is connected to the gate of the PMOS transistor P2.

[0019] like Figure 1As shown, a segmented drive network is used to implement low-EMI, low-power gallium nitride drive. It includes three parallel current mirror replication circuits. The first current mirror replication circuit includes a triple current amplifier MOSFET and a switch S1. The source of switch S1 is grounded, and its drain is connected to the source of the triple current amplifier MOSFET. The second current mirror replication circuit includes a double current amplifier MOSFET and a switch S2. The source of switch S2 is grounded, and its drain is connected to the source of the double current amplifier MOSFET. The third current mirror replication circuit includes a single current amplifier MOSFET and a switch S3. The source of switch S3 is grounded, and its drain is connected to the source of the single current amplifier MOSFET. The gates of the single current amplifier MOSFET, the double current amplifier MOSFET, and the triple current amplifier MOSFET are all connected to the control signal NB2. The drains of the single current amplifier MOSFET, the double current amplifier MOSFET, and the triple current amplifier MOSFET are all connected to the source of the high-voltage NMOS transistor HN3.

[0020] like Figure 1 As shown, the clamping network is used to prevent circuit overshoot and reduce EMI. It includes a source follower P5, whose source is connected to the anode of diode DZ2, whose gate is connected to the source potential sampling signal CS of the gallium nitride power device, and whose drain is connected to the grounding resistor R14. The cathode of diode DZ2 is connected to the drain of PMOS transistor P4 through resistor R10.

[0021] like Figure 1 As shown, the fast turn-off network includes a high-voltage NMOS transistor HN7. The source of the high-voltage NMOS transistor HN7 is grounded, its gate is connected to the PWM turn-off signal PWM_OFF, its drain is connected to one end of resistor R13, the other end of resistor R13 is connected to one end of resistor R11 and the drive output network, and the other end of resistor R11 is connected to the drain of PMOS transistor P4.

[0022] like Figure 1 As shown, the drive output network is used to implement the drive control of gallium nitride power devices, including high-voltage NMOS transistors HN4, HN5, and HN6. The source of high-voltage NMOS transistor HN6 is grounded, its gate is connected to the PWM off signal PWM_OFF, and its drain is connected to the source of high-voltage NMOS transistors HN4 and HN5, as well as the grounding resistor R15. It serves as the output terminal of the drive output network to output the drive voltage DRI of the gallium nitride power devices. The drain of high-voltage NMOS transistor HN5 is connected to the power supply HVDD, and its gate is connected to the gate of high-voltage NMOS transistor HN4, the drain of high-voltage NMOS transistor HN4, one end of resistor R12, and the other end of resistor R13. The other end of resistor R12 is connected to the drain of PMOS transistor P4.

[0023] The following is combined Figure 1 The working principle and process of this invention are described in detail below:

[0024] The enhanced gallium nitride (GaN) drive circuit provided in this embodiment of the invention employs segmented current drive. When the drive circuit is turned on, the PWM enable signal PWM_ON is high, and the PWM disable signal PWM_OFF is low. NMOS transistor N1 is turned on, pulling down the gate potential of PMOS transistor P1 and raising the gate potential of PMOS transistor P2, at which point PMOS transistor P2 is turned off. When the PWM enable signal PWM_ON is high, switches S1, S2, and S3 are all high, forming a current path from PMOS transistor P3 to ground. The maximum current mirroring is 6 times. After being mirrored by PMOS transistor P4, the current reaches 6 times the drive current, rapidly pulling up the drive voltage DRI until it reaches the Miller plateau voltage VMP. When the drive voltage DRI reaches the Miller plateau voltage VMP, switch S1 is turned off, while switches S2 and S3 remain on. The current decreases to 3 times the drive current, and the rise rate of the drive voltage DRI slows down. During the Miller plateau period, the low drive current reduces EMI. After the Miller plateau, switch S1 turns on again, S2 turns on, and S3 turns off. At this point, the current rises again to five times the drive current, accelerating the speed at which the drive voltage DRI reaches its peak. Finally, to reduce power consumption, switches S1 and S2 are turned off, and switch S3 is turned on, using one times the drive current to drive the gallium nitride power device to turn on. This segmented drive control achieves a low-power, low-EMI drive process.

[0025] During the period when the gallium nitride power device is turned on, the driving voltage DRI gradually rises. The clamping network samples the source potential of the gallium nitride power device by the signal CS, and clamps the voltage of DRI through the source follower P5 and the diode DZ2. Its maximum voltage DRI_max = VCS + VDZ2 + VTH_P4 - VTH_HN5, where VCS represents the voltage of the source potential sampling signal CS, VDZ2 represents the voltage across the diode DZ2, VTH_P4 represents the threshold voltage of the PMOS transistor P4, and VTH_HN5 represents the threshold voltage of the high-voltage NMOS transistor HN5.

[0026] During the turn-off process of the drive circuit, the PWM enable signal PWM_ON is low and the PWM disable signal PWM_OFF is high, which quickly pulls the high-voltage NMOS transistors HN7 and HN6 low, thereby achieving rapid turn-off of the gallium nitride power device.

[0027] In the initial stage of power device startup, the gate of the GaN power device is charged with the maximum drive current to shorten the time from 0 to the Miller plateau voltage VMP. During the Miller plateau, the gate drive current of the GaN power device dynamically changes with the rising slope of the source voltage VS to achieve dynamic dv / dt control and reduce conduction losses. When the source voltage VS reaches the input voltage VIN, the drive current increases again to accelerate the gate-source voltage VGH to reach its final value. Afterward, in order to further reduce power consumption, the drive current is reduced and maintained at a low current to sustain the drive process.

[0028] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A low-EMI, high-reliability enhanced gallium nitride driver circuit, characterized in that, The system includes a drive-on control network, a drive-off control network, a segmented drive network, a clamping network, a fast-turn-off network, and a drive output network connected in sequence. The segmented drive network is connected to the source of a high-voltage NMOS transistor HN3. The gate of the high-voltage NMOS transistor HN3 is connected to a control signal NB1. The drain of the high-voltage NMOS transistor HN3 is connected to the drain of PMOS transistor P2, one end of resistor R7, the drain of PMOS transistor P3, the gate of PMOS transistor P3, and the gate of PMOS transistor P4 through resistor R8. The gate of PMOS transistor P2 is connected to the drive-off control network. The source of PMOS transistor P2, the other end of resistor R7, the source of PMOS transistor P3, and the source of PMOS transistor P4 are all connected to the power supply HVDD. The drain of PMOS transistor P4 is connected to the clamping network, the fast-turn-off network, and the drive output network. The drive output network outputs the drive voltage DRI of the gallium nitride power device. The segmented drive network includes three parallel current mirror replication circuits. The first current mirror replication circuit includes a triple current amplification MOSFET and a switching transistor S1. The source of the switching transistor S1 is grounded, and its drain is connected to the source of the triple current amplification MOSFET. The second current mirror replication circuit includes a double current amplification MOSFET and a switching transistor S2. The source of the switching transistor S2 is grounded, and its drain is connected to the source of the double current amplification MOSFET. The third current mirror replication circuit includes a single current amplification MOSFET and a switching transistor S3. The source of the switching transistor S3 is grounded, and its drain is connected to the source of the single current amplification MOSFET. The gates of the single current amplification MOSFET, the double current amplification MOSFET, and the triple current amplification MOSFET are all connected to the control signal NB2. The drains of the single current amplification MOSFET, the double current amplification MOSFET, and the triple current amplification MOSFET are all connected to the source of the high-voltage NMOS transistor HN3.

2. The low-EMI, high-reliability enhanced gallium nitride drive circuit according to claim 1, characterized in that, The drive-on control network includes an NMOS transistor N1, whose source is grounded, its gate is connected to the PWM enable signal PWM_ON, and its drain is connected to the source of a high-voltage NMOS transistor HN1 through a resistor R16. The gate of the high-voltage NMOS transistor HN1 is connected to the control signal NB1, and its drain is connected to one end of a resistor R2. The other end of the resistor R2 is connected to one end of a resistor R1, the anode of a diode DZ1, and one end of a resistor R3. The other end of the resistor R1 and the cathode of the diode DZ1 are both connected to the power supply HVDD. The other end of the resistor R3 is connected to the drive-off control network.

3. The low-EMI, high-reliability enhanced gallium nitride drive circuit according to claim 2, characterized in that, The drive shutdown control network includes an NMOS transistor N3, whose source is grounded, its gate is connected to the PWM shutdown signal PWM_OFF, and its drain is connected to the source of a high-voltage NMOS transistor HN2 through a resistor R17. The gate of the high-voltage NMOS transistor HN2 is connected to the control signal NB1, and its drain is connected to the drain of a PMOS transistor P1, one end of a resistor R4, and one end of a resistor R5. The gate of the PMOS transistor P1 is connected to the other end of a resistor R3. The source of the PMOS transistor P1 and the other end of a resistor R4 are both connected to the power supply HVDD, and the other end of a resistor R5 is connected to the gate of the PMOS transistor P2.

4. The low-EMI, high-reliability enhanced gallium nitride drive circuit according to claim 1, characterized in that, The clamping network includes a source follower P5, the source of which is connected to the anode of diode DZ2, its gate is connected to the source potential sampling signal CS of gallium nitride power device, and its drain is connected to grounding resistor R14. The cathode of diode DZ2 is connected to the drain of PMOS transistor P4 through resistor R10.

5. The low-EMI, high-reliability enhanced gallium nitride drive circuit according to claim 1, characterized in that, The fast shutdown network includes a high-voltage NMOS transistor HN7. The source of the high-voltage NMOS transistor HN7 is grounded, its gate is connected to the PWM turn-off signal PWM_OFF, its drain is connected to one end of a resistor R13, the other end of the resistor R13 is connected to one end of a resistor R11 and the drive output network, and the other end of the resistor R11 is connected to the drain of a PMOS transistor P4.

6. The low-EMI, high-reliability enhanced gallium nitride drive circuit according to claim 5, characterized in that, The drive output network includes high-voltage NMOS transistors HN4, HN5, and HN6. The source of high-voltage NMOS transistor HN6 is grounded, its gate is connected to the PWM off signal PWM_OFF, and its drain is connected to the source of high-voltage NMOS transistors HN4 and HN5, as well as the grounding resistor R15. It serves as the output terminal of the drive output network to output the drive voltage DRI of the gallium nitride power device. The drain of high-voltage NMOS transistor HN5 is connected to the power supply HVDD, and its gate is connected to the gate of high-voltage NMOS transistor HN4, the drain of high-voltage NMOS transistor HN4, one end of resistor R12, and the other end of resistor R13. The other end of resistor R12 is connected to the drain of PMOS transistor P4.

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