A high-performance red light micro LED epitaxial structure based on a tunnel junction and a preparation method thereof

Abstract

The application discloses a high-performance red light Micro LED epitaxial structure based on a tunnel junction and a preparation method thereof. The structure comprises a GaAs substrate, an n-type GaAs buffer layer, an n-type AlGaInP etching stop layer, a tunnel junction structure, an n-type AlInP confinement layer, an InGaP / AlInP multi-quantum well light-emitting layer, a p-type AlInP confinement layer and a p-type GaP contact layer. The tunnel junction structure is composed of a high-doped n-type GaP layer, a high-doped p-type GaP layer and a low-doped p-type GaP layer from bottom to top, and the tunnel junction structure is used for realizing ohmic contact between a subsequent transparent electrode and an epitaxial layer and assisting lateral current expansion. The application realizes low-resistance ohmic contact between ITO and the epitaxial layer, improves brightness, reduces current uniformity error, prolongs the service life of a device, is compatible with an existing production line and is suitable for high-density Mini / Micro LED display, AR / VR near-eye display and other scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Micro LED display, in particular to a high-performance red Micro LED epitaxial structure based on a tunnel junction and a preparation method thereof, which is suitable for high-density Mini / Micro LED display panels, vehicle displays, AR / VR near-eye displays and other scenarios with high requirements for red light brightness, current uniformity and reliability. BACKGROUND

[0002] As a new generation of display technology, Micro LED has advantages such as high brightness, high contrast, low power consumption and long service life, and red Micro LED is a key component for realizing full-color display. However, the existing red Micro LED has the following core problems in structure design and preparation process:

[0003] 1. Conflict between electrode light blocking and light transmittance: Traditional red Micro LED uses metal reflective electrodes (such as Ag, Al) to improve light extraction efficiency, but the metal electrodes will block 30%-50% of the light-emitting area, resulting in a decrease in actual brightness; if a transparent electrode (such as ITO) is used, the ohmic contact resistance between ITO and the red epitaxial layer (such as AlGaInP system) is too high (usually >10Ω), which can easily cause current concentration and severe heating.

[0004] 2. Uneven current distribution: The size of the Micro LED light-emitting mesa is usually less than 50μm, and the current in the traditional structure is easily concentrated at the edge of the electrode, resulting in uneven brightness of the light-emitting area and the phenomenon of "bright edges and dark centers", which affects the display quality.

[0005] 3. Etching damage to epitaxial layer: During the preparation of the light-emitting mesa, the traditional ICP etching process can easily cause physical damage (such as lattice distortion and increased defects) to the InGaP / AlInP multi-quantum well (MQW) light-emitting layer, resulting in a 10%-20% decrease in internal quantum efficiency (IQE).

[0006] 4. Poor bonding reliability of substrate removal: The bonding of GaAs substrates to heterogeneous substrates (such as silicon substrates and integrated circuit substrates) often relies on high-temperature (>700℃) processes, which can easily cause the diffusion of doped atoms in the epitaxial layer; when GaAs substrates are simply chemically etched, the etching rate is difficult to control, and substrate fragments are easily left behind, affecting the electrical performance of the device.

[0007] To solve the above problems, the prior art focuses on "metal electrode optimization", "etching process parameter adjustment" and other local improvements, and does not propose a systematic solution from the synergistic perspective of epitaxial structure and preparation process. For example, some patents reduce etching damage by adding a "doping-free interface layer", but do not solve the problem of ohmic contact of transparent electrodes; another patent uses "multi-active region stacking" to improve brightness, but the structure is complex and the cost is high, which is difficult to adapt to the miniaturization demand of Micro LED. SUMMARY

[0008] The purpose of the present application is to overcome the technical defects of existing red Micro LED, provide a high-performance red Micro LED epitaxial structure based on tunnel junction and a preparation method, solve the following problems: realize low-resistance ohmic contact (contact resistance < 5Ω) between transparent electrode (ITO) and red epitaxial layer, while avoiding light blocking by metal electrode; optimize current distribution, make the current uniformly diffuse in the Micro LED mesa, eliminate the phenomenon of uneven brightness; reduce the damage of etching process to multi-quantum well light emitting layer, ensure the internal quantum efficiency; realize low-temperature and high-efficiency substrate removal and heterojunction bonding, and improve the reliability of the device.

[0009] To solve the above technical problems, the technical scheme adopted by the present application is:

[0010] A high-performance red Micro LED epitaxial structure based on tunnel junction, from bottom to top, includes: GaAs substrate, n-type GaAs buffer layer, n-type AlGaInP etching stop layer, tunnel junction structure, n-type AlInP confinement layer, InGaP / AlInP multi-quantum well light emitting layer, p-type AlInP confinement layer and p-type GaP contact layer; the tunnel junction structure is composed of a highly doped n-type GaP layer, a highly doped p-type GaP layer and a low-doped p-type GaP layer from bottom to top, and the tunnel junction structure is used to realize ohmic contact between the subsequent transparent electrode and the epitaxial layer, and to assist the lateral expansion of the current.

[0011] In a preferred scheme, the thickness of the n-type GaAs buffer layer is 50-500nm, and the source gas used during growth is a combination of trimethylgallium TMGa and arsine , or a combination of triethylgallium TEGa and arsine , and the doping source is monosilane or disilane .

[0012] In a preferred scheme, the thickness of the n-type AlGaInP etching stop layer is 50-500nm, and the source gas used during growth includes trimethylaluminum TMAl, gallium-containing source gas, trimethylindium TMIn and phosphine , and the doping source is monosilane or disilane .

[0013] Preferably, the thickness of the high-doped n-type GaP layer is 1-20 nm, the thickness of the high-doped p-type GaP layer is 1-20 nm, and the thickness of the low-doped p-type GaP layer is 1-100 nm; the doping source of the high-doped n-type GaP layer is monosilane , the doping source of the high-doped p-type GaP layer and the low-doped p-type GaP layer is dimethyl magnesium .

[0014] Preferably, the InGaP / AlInP multi-quantum well light-emitting layer is formed by 3-10 periods of InGaP well layers and AlInP barrier layers stacked alternately, wherein the thickness of the InGaP well layer is 5-15 nm, and the thickness of the AlInP barrier layer is 10-30 nm.

[0015] The application also provides a preparation method of a high-performance red light Micro LED epitaxial structure based on a tunnel junction, comprising the following steps:

[0016] S1, epitaxial structure growth, using MOCVD method to grow n-type GaAs buffer layer, n-type AlGaInP etching stop layer, tunnel junction structure, n-type AlInP confinement layer, InGaP / AlInP multi-quantum well light-emitting layer, p-type AlInP confinement layer and p-type GaP contact layer on a GaAs substrate in sequence to obtain an epitaxial wafer; wherein the MOCVD growth temperature is uniformly controlled at 600-750℃, and the growth rate is 0.02-0.5 nm / s;

[0017] S2, film deposition, using EB method to deposit a lower ITO buffer layer with a thickness of 150 nm on the front surface of the epitaxial wafer, the mole ratio of indium and tin of the ITO target material is 9:1, and the deposition rate is 1 nm / s, then a bonding metal layer composed of 300 nm of Cr, 300 nm of Pt and 200 nm of Au is deposited on the lower ITO buffer layer in sequence, and the deposition rate is 1 nm / s; at the same time, the same structure of the bonding metal layer is deposited on the substrate by using the EB method;

[0018] S3, bonding and substrate removal, aligning and bonding the bonding metal layer of the epitaxial wafer with the bonding metal layer of the substrate, using a large pressure bonder to bond under the conditions of temperature 400-700℃, pressure 3000-9000 kg, time 10-60 minutes; then immersing the sample in an alkaline and oxidizing solution with a volume ratio of 6:1 to remove the GaAs substrate;

[0019] S4, mask layer preparation, using PECVD method to deposit a mask layer with a thickness of 300 nm on the surface of the sample , the reaction gas is + , The flow rate is 1200 sccm. The flow rate was 300 sccm, the plasma source power was 100 W, and the deposition temperature was 250 °C; subsequently... A 500-3000 nm thick positive photoresist is spin-coated onto the mask layer, followed by UV exposure and development to form a patterned photoresist. Then, an ICP etching process is used to etch the areas not covered by the photoresist. , to obtain a graphical representation The photoresist is removed using an organic solvent after the mask layer is applied.

[0020] S5, Light-emitting mesa fabrication, in a patterned manner The mask layer serves as a barrier, and the epitaxial layer is etched using ICP etching to form the Micro LED light-emitting mesa. The etching gas used is... + + , Flow rate 40 sccm Flow rate 20 sccm, etching time 200 s, etching rate 40 Å / s;

[0021] S6 The passivation layer was prepared by deposition using the PECVD method. For the passivation layer, the sample tilt angle was 30°, the stage rotation speed was 10 rpm, and the deposition time was 900 s to ensure a thickness of 300 nm. Then, the patterned photoresist process of S4 was repeated, followed by ICP etching of the areas not covered by the photoresist. A passivation layer is applied, and simultaneously, a 20-40 nm thick epitaxial layer is etched away to expose the tunnel junction structure. Finally, the photoresist is removed to obtain the patterned structure. passivation layer;

[0022] S7, Top ITO electrode fabrication: A 150 nm thick transparent ITO electrode was deposited on the sample surface using the EB method. The indium-tin molar ratio of the ITO target was 9:1, and the deposition rate was 1 nm / s, thus completing the device fabrication.

[0023] In a preferred embodiment, during the growth of the tunnel junction structure in S1, the source gas for the highly doped n-type GaP layer is trimethylgallium (TMGa) or triethylgallium (TEGa) with phosphine. Doping source: silane The flow rate is 5-20 sccm; the source gas for both highly p-doped and poorly p-doped GaP layers is trimethylgallium (TMGa) or triethylgallium (TEGa) with phosphine. Magnesium dicerope source The flow rates were 10-30 sccm and 1-5 sccm, respectively.

[0024] Preferably, in S2, when the substrate is a silicon substrate, the silicon substrate surface is first subjected to a hydroxylation treatment, and then a bonding metal layer is deposited.

[0025] Preferably, in S5, when the ICP etches the epitaxial layer, the radio frequency power is controlled to be 200-400 W, the bias power is 50-150 W, and the etching pressure is 0.5-2 Pa, so as to avoid etching damage to the multi-quantum well light-emitting layer.

[0026] Preferably, in S6, the PECVD deposition Before the passivation layer, the surface of the sample is subjected to plasma cleaning, with a power of 80-120 W and a processing time of 30-60 s, to remove surface impurities.

[0027] Thanks to the use of the above technical solutions, the present application has the following beneficial effects compared with the prior art:

[0028] 1. Synergistic optimization of light transmittance and ohmic contact: the low-resistance ohmic contact (contact resistance <5Ω) of ITO and the epitaxial layer is realized through the "abrupt junction" of the tunnel junction, and the light transmittance of the ITO transparent electrode is >90%, solving the light blocking problem of traditional metal electrodes and improving the brightness by 30%-50%;

[0029] 2. Improved current distribution uniformity: the low-doped p-type GaP layer (high resistivity) of the tunnel junction forces the current to expand horizontally, so that the current density difference in the Micro LED mesa is <5%, eliminating the "bright edges and dark center" phenomenon and significantly improving the display quality;

[0030] 3. Significant reduction of etching damage: the high etching selectivity (>10:1) of the n-type AlGaInP etching stop layer and the polymer protection of ICP etching make the defect density of the multi-quantum well light-emitting layer reduce by more than 50%, and the internal quantum efficiency retention rate >90%;

[0031] 4. Improved process reliability: low-temperature bonding (400-700℃) avoids the diffusion of doped atoms, and the alkaline and oxidizing mixed solution realizes residue-free removal of the GaAs substrate, with a device bonding strength >5N / cm and a service life improved to more than 100 hours;

[0032] 5. Strong compatibility: the preparation process is compatible with the existing Micro LED production line (MOCVD, EB, ICP, PECVD) without the need for additional equipment, and can be directly mass-produced and applied. BRIEF DESCRIPTION OF DRAWINGS

[0033] ​​​In order to make the technical solution in the specific embodiment of the present application or the prior art clearer, the drawings needed to be used in the specific embodiment or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0034] Figure 1 A schematic diagram of a high-performance red Micro LED epitaxial structure based on a tunnel junction of the present application;

[0035] Figure 2 A flowchart of a preparation method of a high-performance red Micro LED epitaxial structure based on a tunnel junction of the present application;

[0036] 1, GaAs substrate; 2, n-type GaAs buffer layer; 3, n-type AlGaInP etching stop layer; 4, tunnel junction structure; 41, high-doped n-type GaP layer; 42, high-doped p-type GaP layer; 43, low-doped p-type GaP layer; 5, n-type AlInP confinement layer; 6, InGaP / AlInP multi-quantum well light-emitting layer; 7, p-type AlInP confinement layer; 8, p-type GaP contact layer. DETAILED DESCRIPTION

[0037] In order to make the technical solution in the specific embodiment of the present application or the prior art clearer, the drawings needed to be used in the specific embodiment or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0038] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0039] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not intended to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0040] In addition, in addition to indicating the orientation or positional relationship, the above-mentioned partial terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the present application can be understood according to the specific circumstances.

[0041] In addition, the terms "mounting", "setting", "provided with", "connecting", "connecting", "sleeving" should be broadly understood. For example, it can be fixedly connected, detachably connected, or integrally constructed; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific circumstances.

[0042] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0043] Embodiment one

[0044] Please refer to Figure 1 A high-performance red light Micro LED epitaxial structure based on a tunnel junction, from bottom to top, includes: a GaAs substrate 1, an n-type GaAs buffer layer 2, an n-type AlGaInP etching stop layer 3, a tunnel junction structure 4, an n-type AlInP confinement layer 5, an InGaP / AlInP multi-quantum well light emitting layer 6, a p-type AlInP confinement layer 7 and a p-type GaP contact layer 8; the tunnel junction structure 4 is composed of a high-doped n-type GaP layer 41, a high-doped p-type GaP layer 42 and a low-doped p-type GaP layer 43 from bottom to top, and the tunnel junction structure 4 is used to realize the ohmic contact between the subsequent transparent electrode and the epitaxial layer, and to assist the lateral expansion of the current; the specific is as follows:

[0045] GaAs substrate 1: a semi-insulating or low-doped GaAs substrate 1 with a (100) crystal orientation, 300-500 μm thick, providing stable lattice support for subsequent epitaxial layer growth;

[0046] n-type GaAs buffer layer 2: thickness 50-500 nm, doping concentration - Using TMGa / orTEGa / As the source gas, or It serves as a doping source, compensating for lattice defects in the GaAs substrate 1 and providing a smooth growth interface for the upper n-type AlGaInP etching stop layer 3.

[0047] n-type AlGaInP etching stop layer 3: thickness 50-500nm, Al composition 0.3-0.6, using TMAl / TMGa or TEGa / TMIn / As the source gas, or As a doping source, its etching rate is much lower than that of the adjacent low-doped p-type GaP layer 43 (etch selectivity ratio > 10:1), which can precisely terminate the etching during subsequent mesa etching and protect the underlying tunnel junction structure 4.

[0048] Tunnel structure 4: Composed of a highly n-doped GaP layer 41, a highly p-doped GaP layer 42, and a low-doped GaP layer from bottom to top, this is the core innovation of the present invention.

[0049] Highly doped n-type GaP layer 41: thickness 1-20 nm, doping concentration - , As a doping source, it forms a " " with the highly p-doped GaP layer 42 "Sudden junction" utilizes the quantum tunneling effect to achieve low-resistance conduction;

[0050] Highly p-doped GaP layer 42: thickness 1-20 nm, doping concentration - , As a doping source, it works synergistically with the highly n-doped GaP layer 41 to reduce the tunnel junction voltage drop (<0.5V).

[0051] Low-doped p-type GaP layer 43: thickness 1-20 nm, doping concentration - , As a doping source, its high resistivity can force the current to spread laterally from the electrode region to the edge of the mesa, thus solving the problem of current concentration.

[0052] n-type AlInP confinement layer 5: thickness 50-300 nm, doping concentration - Using TMA1 / TMIn / As the source gas, As a doping source, the function is to limit the diffusion of electrons in the p-type region of the multi-quantum well light-emitting layer;

[0053] The InGaP / AlInP multi-quantum well light-emitting layer 6 is formed by alternately stacking 3-10 periods of InGaP well layers (thickness 5-15 nm, In component 0.4-0.6) and AlInP barrier layers (thickness 10-30 nm, Al component 0.5-0.7), the InGaP well layer is a red light (620-660 nm) emission region, and the AlInP barrier layer can limit electrons and holes in the well layer due to the larger band gap than the InGaP, thereby improving the radiation recombination efficiency;

[0054] The p-type AlInP limiting layer 7 has a thickness of 50-300 nm and a doping concentration - TMAl / TMIn is used as a source gas, As a doping source, the function is to limit the diffusion of holes in the n-type region of the multi-quantum well light-emitting layer;

[0055] The p-type GaP contact layer 8 has a thickness of 100-500 nm and a doping concentration - TMGa is used as a source gas, As a doping source, it has strong adhesion to the bonding metal layer (Cr / Pt / Au) (peeling strength > 10 N / cm), which can improve the reliability of heterojunction bonding.

[0056] Example two

[0057] Please refer to Figure 2 , a preparation method of a high-performance red light Micro LED epitaxial structure based on a tunnel junction, comprising the following steps:

[0058] S1, epitaxial structure growth, using the MOCVD method to grow an n-type GaAs buffer layer 2, an n-type AlGaInP etching stop layer 3, a tunnel junction structure 4, an n-type AlInP limiting layer 5, an InGaP / AlInP multi-quantum well light-emitting layer 6, a p-type AlInP limiting layer 7, and a p-type GaP contact layer 8 on a GaAs substrate 1 in sequence, to obtain an epitaxial wafer;

[0059] Among them, the MOCVD growth temperature is uniformly controlled at 600-750℃ (taking into account the lattice matching and doping efficiency of each layer), and the growth rate is 0.02-0.5 nm / s;

[0060] In addition, the growth of the tunnel junction structure 4 adopts a "segmented variable doping" strategy: the high-doped n-type GaP layer 41 uses TMGa (or TEGa) as a source gas, as a source gas, Flow 5-20 sccm; TMGa (or TEGa) for high-doped p-type GaP layer 42 As source gas, Flow 10-30 sccm; TEGa for low-doped p-type GaP layer 43 Flow reduced to 1-5 sccm to ensure resistivity gradient.

[0061] S2, film deposition, EB method used to deposit a 150-nm-thick lower ITO buffer layer on the front surface of the epitaxial wafer, ITO target indium-tin molar ratio 9:1, deposition rate 1 nm / s, then a bonding metal layer composed of 300 nm of Cr, 300 nm of Pt, and 200 nm of Au deposited in sequence on the lower ITO buffer layer, deposition rate 1 nm / s; at the same time, the EB method used to deposit a bonding metal layer of the same structure on the substrate;

[0062] Specifically, the EB method used to deposit a “lower ITO buffer layer + bonding metal layer” on the front surface of the epitaxial wafer:

[0063] Lower ITO buffer layer: thickness 150 nm, ITO target indium-tin molar ratio 9:1, deposition rate 1 nm / s, ITO light transmittance > 90% (620-660 nm wavelength band), providing a bottom layer for electrical connection of the subsequent transparent electrode;

[0064] Bonding metal layer: 300 nm of Cr (to improve adhesion), 300 nm of Pt (to block diffusion), and 200 nm of Au (low-resistance conduction) deposited in sequence, deposition rate 1 nm / s;

[0065] At the same time, a bonding metal layer of the same structure deposited on the substrate (silicon substrate or integrated circuit substrate); if the substrate is a silicon substrate, it needs to be hydroxylated (immersed in a 1:1:5 volume ratio of ammonia solution / hydrogen peroxide / deionized water mixture for 10 minutes) to form hydroxyl groups (-OH) on the silicon surface, improving the adhesion to the Cr layer.

[0066] S3, bonding and substrate removal, the bonding metal layer of the epitaxial wafer aligned and attached to the bonding metal layer of the substrate, a large-pressure bonder used to bond at a temperature of 400-700°C, a pressure of 3000-9000 kg, and a time of 10-60 minutes (high temperature and high pressure ensure intermetallic diffusion welding, bonding strength > 5 N / cm); then a 6:1 volume ratio of alkaline (ammonia) and oxidizing (hydrogen peroxide) mixed solution used to soak the sample for 10-60 minutes, ammonia etching GaAs to generate soluble , hydrogen peroxide oxidizing As elements to , both of which work together to achieve residue-free removal of the GaAs substrate 1.

[0067] S4, Mask layer preparation, PECVD method is used to deposit a thickness of 300 nm on the surface of the sample Mask layer (good insulation, high etching precision), reaction gas is + , Flow rate is 1200 sccm, Flow rate is 300 sccm, plasma source power is 100 W, deposition temperature is 250 ℃ (low temperature to avoid damage to the epitaxial layer); then 500-3000 nm thick 5214 positive photoresist is spin-coated on the mask layer, and the patterned photoresist is formed by ultraviolet exposure with an exposure dose of 100-200 ), 2.38% TMAH aqueous solution development (development time is 2 minutes); then ICP etching process is used to etch the (etching gas + + , Flow rate is 25 sccm, etching time is 400 s, etching rate is 1.2 nm / s), to obtain a patterned mask layer, and finally the photoresist is removed by soaking in an organic solvent (acetone / isopropyl alcohol (volume ratio 1:1)).

[0068] S5, light emitting mesa preparation, using the patterned mask layer as a barrier, ICP etching process is used to etch the epitaxial layer to form a Micro LED light emitting mesa with a size of 5-50 μm, wherein the etching gas is + + , Flow rate is 40 sccm, Flow rate is 20 sccm, radio frequency power is 200-400 W, bias power is 50-150 W, etching gas pressure is 0.5-2 Pa, etching time is 200 s, etching rate is 40 Å / s; wherein a polymer protective film can be formed to reduce the physical damage of etching to the multi-quantum well light emitting layer, so that the internal quantum efficiency retention rate is > 90%.

[0069] S6, passivation layer preparation, PECVD method is used to deposit passivation layer (consistent with the deposition parameters of S4), the sample inclination angle is 30°, the sample table rotation speed is 10 rpm, and the deposition time is 900 s to ensure the thickness of 300 nm, and ensure that the passivation layer on the mesa sidewall is uniformly covered; then the patterned photoresist process of S4 is repeated, and the passivation layer is etched to remove the 20-40 nm thick epitaxial layer to accurately expose the high-doped n-type GaP layer 41 of the tunnel junction, and the sample surface needs to be cleaned before etching Plasma cleaning (power 80-120W, processing time 30-60s), removing surface-adsorbed impurities (such as carbon, oxygen), avoiding affecting the combination of the passivation layer and the epitaxial layer, and finally removing photoresist to obtain patterning passivation layer.

[0070] S7, top ITO electrode preparation, using EB method to deposit a top ITO transparent electrode with a thickness of 150nm on the sample surface, the ITO target material indium tin molar ratio is 9:1, the deposition rate is 1nm / s, the top ITO forms an ohmic contact (contact resistance <5Ω) with the high-doped n-type GaP layer 41 of the tunnel junction; finally, the obtained red light Micro LED device has a brightness >500 , current uniformity error <5%, lifetime > 1000 hours.

[0071] Example three

[0072] The application provides a preparation of a high-performance red light Micro LED epitaxial structure based on a tunnel junction, comprising:

[0073] GaAs substrate 1 selection: (100) crystal orientation, semi-insulating GaAs substrate 1, thickness 400μm;

[0074] n-type GaAs buffer layer 2 growth: MOCVD temperature 650℃, growth rate 0.2nm / s, source gas TMGa / , flow rate 10sccm, thickness 200nm, doping concentration ;

[0075] n-type AlGaInP etching stop layer 3 growth: MOCVD temperature 680℃, growth rate 0.15nm / s, source gas TMAl / TMGa / TMIn / , flow rate 8sccm, Al component 0.4, thickness 200nm, doping concentration ;

[0076] Tunnel junction structure 4 growth:

[0077] High-doped n-type GaP layer 41: MOCVD temperature 650℃, growth rate 0.1nm / s, source gas TMGa / , flow rate 15sccm, thickness 5nm, doping concentration ;

[0078] High-doped p-type GaP layer 42: MOCVD temperature 650℃, growth rate 0.1nm / s, source gas TMGa / , Flow 20 sccm, thickness 5 nm, doping concentration ;

[0079] Low-doped p-type GaP layer 43: MOCVD temperature 650℃, growth rate 0.1 nm / s, source gas TMGa / TMIn / TMGa , Flow 3 sccm, thickness 50 nm, doping concentration ;

[0080] n-type AlInP confinement layer 5 growth: MOCVD temperature 680℃, growth rate 0.15 nm / s, source gas TMAl / TMIn , Flow 8 sccm, thickness 150 nm, doping concentration ;

[0081] InGaP / AlInP multiple quantum well light-emitting layer 6 growth: MOCVD temperature 620℃, growth rate 0.1 nm / s, 6 periods (InGaP well layer thickness 10 nm, In component 0.5; AlInP barrier layer thickness 20 nm, Al component 0.6);

[0082] p-type AlInP confinement layer 7 growth: MOCVD temperature 680℃, growth rate 0.15 nm / s, source gas TMAl / TMIn , Flow 15 sccm, thickness 150 nm, doping concentration ;

[0083] p-type GaP contact layer 8 growth: MOCVD temperature 650℃, growth rate 0.2 nm / s, source gas TMGa , Flow 25 sccm, thickness 300 nm, doping concentration .

[0084] Based on the above epitaxial structure, a red Micro LED device is prepared, specifically as follows:

[0085] S2, film deposition: 150 nm of ITO (indium-tin ratio 9:1, rate 1 nm / s) is deposited by EB method, and then Cr (300 nm) / Pt (300 nm) / Au (200 nm) bonding metal layer (rate 1 nm / s) is deposited; after the silicon substrate is treated by hydroxylation, the same metal layer is deposited;

[0086] S3, bonding and substrate removal: bonding temperature 500℃, pressure 6000kg, time 30 minutes; 6:1 ammonia-hydrogen peroxide mixture is soaked for 30 minutes to remove GaAs substrate 1;

[0087] S4, Mask layer preparation: PECVD deposition of 300nm... mask layer ( Flow rate 1200 sccm Flow rate 300 sccm, plasma source power 100 W, deposition temperature 250℃; spin-coating 1000 nm 5214 photoresist, UV exposure (150 °C). ), 2.38% TMAH development for 2 minutes; ICP etching mask layer ( Flow rate 25 sccm, etching time 400 s);

[0088] S5, Light-emitting mesa fabrication: ICP etching ( Flow rate 40 sccm (Flow rate 20 sccm, RF 300W, bias voltage 100W, etching gas pressure 0.8Pa, etching time 200s) to form a 20μm×20μm light-emitting mesa;

[0089] S6, Passivation layer preparation: PECVD deposition of 300nm Passivation layer (sample tilt angle 30°, rotation speed 10 rpm); Plasma cleaning (power 100W, processing time 45s); ICP etching of passivation layer and removal of 30nm epitaxial layer to expose tunnel junction;

[0090] S7, Top ITO electrode fabrication: 150nm top ITO (indium-tin ratio 9:1, rate 1nm / s) was deposited using the EB method to obtain a red Micro LED device.

[0091] The fabricated red Micro LED device was tested, and the results are as follows:

[0092] Brightness: 620nm band brightness 650 (Drive current 100μA);

[0093] Contact resistance: The contact resistance between the top ITO and the tunnel junction is 3.2Ω;

[0094] Current uniformity: Current density difference within the platform is 3.5%;

[0095] Internal quantum efficiency: 85% (90% without etch damage, retention rate 94.4%).

[0096] Lifetime: Under a constant current drive of 100μA, the time for brightness to decay to 70% of its initial value is 1.2× Hour.

[0097] Finally, it should be noted that the above is only the preferred embodiment of the present application, and is not intended to limit the present application, although the foregoing embodiments of the present application are described in detail, for those skilled in the art, it can still be modified to the technical solutions described in the foregoing embodiments, or part of the technical features are equivalent to replace, as long as within the spirit and principles of the present application, any modification, equivalent replacement, improvement, etc. made, should be included within the scope of the present application.

Claims

1. A high-performance red Micro LED epitaxial structure based on a tunnel junction, characterized in that, From bottom to top, successively include: GaAs substrate, n-type GaAs buffer layer, n-type AlGaInP etching stop layer, tunnel junction structure, n-type AlInP confinement layer, InGaP / AlInP multi-quantum well light emitting layer, p-type AlInP confinement layer and p-type GaP contact layer; the tunnel junction structure is composed of high-doped n-type GaP layer, high-doped p-type GaP layer and low-doped p-type GaP layer from bottom to top, and the tunnel junction structure is used to realize ohmic contact of subsequent transparent electrode and epitaxial layer, and assist current lateral expansion. 2.The high-performance red tunnel junction-based Micro LED epitaxial structure of claim 1, wherein, The n-type GaAs buffer layer has a thickness of 50-500 nm, and source gases used in growth are a combination of trimethyl gallium (TMGa) and arsine , or a combination of triethyl gallium (TEGa) and arsine , and a doping source is monosilane or disilane . 3.The high-performance red tunnel junction-based Micro LED epitaxial structure of claim 1, wherein, The thickness of the n-type AlGaInP etching stop layer is 50-500nm, and the source gas used in growth includes trimethylaluminum TMAl, gallium-containing source gas, trimethylindium TMIn and phosphine , and the doping source is monosilane or disilane . 4.The high-performance red tunnel junction-based Micro LED epitaxial structure of claim 1, wherein, The thickness of the high-doped n-type GaP layer is 1-20 nm, the thickness of the high-doped p-type GaP layer is 1-20 nm, and the thickness of the low-doped p-type GaP layer is 1-100 nm; the doping source of the high-doped n-type GaP layer is monosilane , and the doping source of the high-doped p-type GaP layer and the low-doped p-type GaP layer is dimethyl magnesium . 5.The high-performance red tunnel junction-based Micro LED epitaxial structure of claim 1, wherein, The InGaP / AlInP multi-quantum well light emitting layer is alternately stacked by 3-10 periods of InGaP well layer and AlInP barrier layer, wherein the thickness of InGaP well layer is 5-15 nm, and the thickness of AlInP barrier layer is 10-30 nm.

6. A method for preparing the high-performance red light Micro LED epitaxial structure based on a tunnel junction according to any one of claims 1-5, characterized in that, The method comprises the following steps: S1, epitaxial structure growth, using MOCVD method to grow n-type GaAs buffer layer, n-type AlGaInP etching stop layer, tunnel junction structure, n-type AlInP confinement layer, InGaP / AlInP multi-quantum well light emitting layer, p-type AlInP confinement layer and p-type GaP contact layer on GaAs substrate in sequence, to obtain an epitaxial wafer; wherein, the MOCVD growth temperature is uniformly controlled at 600-750 DEG C, and the growth rate is 0.02-0.5 nm / s; S2, film deposition, using EB method to deposit a lower ITO buffer layer with a thickness of 150 nm on the front surface of the epitaxial wafer, the mole ratio of indium and tin of ITO target material is 9:1, and the deposition rate is 1 nm / s, then a bonding metal layer composed of 300 nm of Cr, 300 nm of Pt and 200 nm of Au is deposited on the lower ITO buffer layer in sequence, and the deposition rate is 1 nm / s; at the same time, using EB method to deposit a bonding metal layer with the same structure on the substrate; S3, bonding and substrate removal, aligning and adhering the bonding metal layer of the epitaxial wafer with the bonding metal layer of the substrate, using a large pressure bonding machine to bond under the conditions of temperature 400-700 DEG C, pressure 3000-9000 kg, time 10-60 minutes; then immerse the sample in an alkaline and oxidizing solution with a volume ratio of 6:1 to remove the GaAs substrate; S4, Mask layer preparation, PECVD method was used to deposit a thickness of 300 nm on the surface of the sample Mask layer, the reaction gas is , The flow rate is 1200 sccm, The flow rate is 300 sccm, the plasma source power is 100 W, the deposition temperature is 250 ℃; then spin-coating 500-3000 nm thick positive photoresist on the mask layer, UV exposure, developing solution development to form patterned photoresist; then use ICP etching process to etch the , get patterned Mask layer, finally use organic solvent to remove photoresist;​ S5, light-emitting mesa preparation, patterning The mask layer is a barrier, and the epitaxial layer is etched by an ICP etching process to form a Micro LED light-emitting mesa, wherein the etching gas is + + , flow rate 40 sccm, flow rate 20 sccm, etching time 200 s, etching rate 40 Å / s; S6, Passivation layer preparation, PECVD deposition Passivation layer, sample inclination 30°, sample stage rotation speed 10 rpm, deposition time 900 s to ensure thickness 300 nm; then repeat the S4 photoresist process, and then use ICP to etch the Passivation layer, while etching to remove 20-40 nm thick epitaxial layer to expose the tunnel junction structure, and finally remove the photoresist to obtain the patterned Passivation layer; S7, top ITO electrode preparation, using EB method to deposit a top ITO transparent electrode with a thickness of 150 nm on the surface of the sample, the mole ratio of indium and tin of ITO target material is 9:1, and the deposition rate is 1 nm / s, to complete the device preparation.

7. The preparation method of the tunnel junction-based high-performance red Micro LED epitaxial structure according to claim 6, characterized in that, In S1, when growing the tunnel junction structure: the source gas of the high-doped n-type GaP layer is trimethylgallium TMGa or triethylgallium TEGa and phosphine , the flow rate of the doping source silane is 5-20 sccm; the source gas of the high-doped p-type GaP layer and the low-doped p-type GaP layer is trimethylgallium TMGa or triethylgallium TEGa and phosphine , the flow rates of the doping source dimethyl magnesium are 10-30 sccm and 1-5 sccm, respectively.

8. The preparation method of the tunnel junction-based high-performance red Micro LED epitaxial structure according to claim 6, characterized in that, In S2, when the substrate is a silicon substrate, first perform hydroxylation treatment on the surface of the silicon substrate, immerse in a mixed solution of ammonia, hydrogen peroxide and deionized water with a volume ratio of 1:1:5 for 10 minutes, and then deposit the bonding metal layer.

9. The preparation method of the tunnel junction-based high-performance red Micro LED epitaxial structure according to claim 6, characterized in that, In S5, when etching the epitaxial layer by ICP, the radio frequency power is controlled at 200-400 W, the bias power is 50-150 W, and the etching pressure is 0.5-2 Pa, so as to avoid etching damage to the multi-quantum well light emitting layer.

10. The preparation method of the high-performance red tunnel junction-based Micro LED epitaxial structure according to claim 6, characterized in that, In S6, PECVD deposition Before passivation layer, the sample surface is treated Plasma cleaning, power 80-120 W, treatment time 30-60 s, remove surface impurities.

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