Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a display area and a binding area arranged on one side of the display area, the display area comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprises a pixel driving circuit, and the binding area at least comprises a plurality of data outgoing lines; the display area further comprises a plurality of data signal lines and a plurality of data connecting lines, the data signal lines are configured to provide data signals for the pixel driving circuits, and the data signal lines are connected with the data outgoing lines through the data connecting lines; the at least one data connecting line comprises at least two transverse sub-lines extending in the first direction and at least two vertical sub-lines extending in the second direction, the two transverse sub-lines are arranged in different unit rows, and the two vertical sub-lines are arranged in different unit columns. According to the invention, the twill watermarks can be reduced or even eliminated.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Currently, existing OLED display devices suffer from issues such as mura (watermarks). Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by this disclosure is to provide a display substrate and its preparation method, as well as a display device, to solve the problems of diagonal watermarks existing in existing display devices.

[0006] On one hand, this disclosure provides a display substrate, including a display area and a bonding area disposed on one side of the display area. The display area includes multiple circuit units forming multiple cell rows and multiple cell columns, at least one circuit unit including a pixel driving circuit. The bonding area includes at least multiple data lead-out lines. The display area also includes multiple data signal lines and multiple data connection lines. The data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines through the data connection lines. At least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction. The two horizontal sub-lines are disposed in different cell rows, and the two vertical sub-lines are disposed in different cell columns. The first direction and the second direction intersect.

[0007] In an exemplary embodiment, at least two horizontal sub-lines are provided in at least one cell row, the two horizontal sub-lines connecting different vertical sub-lines.

[0008] In an exemplary embodiment, at least two vertical sub-lines are provided in at least one unit column, and the two vertical sub-lines connect different horizontal sub-lines.

[0009] In an exemplary embodiment, the orthographic projection of at least one horizontal sub-line on the display substrate at least partially overlaps with the orthographic projection of at least one vertical sub-line on the display substrate.

[0010] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display area includes multiple conductive layers, the two horizontal sub-lines are disposed in the same conductive layer, the two vertical sub-lines are disposed in the same conductive layer, and the horizontal sub-lines and the vertical sub-lines are disposed in different conductive layers.

[0011] In an exemplary embodiment, the plurality of conductive layers include at least a first source / drain metal layer disposed on a substrate and a second source / drain metal layer disposed on the side of the first source / drain metal layer away from the substrate, wherein the horizontal sub-line is disposed in the first source / drain metal layer and the vertical sub-line is disposed in the second source / drain metal layer.

[0012] In an exemplary embodiment, the at least two horizontal sub-lines include at least a first horizontal sub-line and a second horizontal sub-line, and the at least two vertical sub-lines include at least a first vertical sub-line and a second vertical sub-line; the data signal line is connected to the data lead-out line through the data connection line, including: a first end of the first vertical sub-line is connected to the data lead-out line; a second end of the first vertical sub-line extends away from the binding area and is connected to the first end of the first horizontal sub-line; a second end of the first horizontal sub-line extends towards the second vertical sub-line and is connected to the first end of the second vertical sub-line; a second end of the second vertical sub-line extends away from the binding area and is connected to the first end of the second horizontal sub-line; and a second end of the second horizontal sub-line extends towards the data signal line and is connected to the data signal line.

[0013] In an exemplary embodiment, the display area further includes a plurality of first data connection blocks; in at least one circuit unit, the first data connection block is connected to a first end of the first horizontal sub-line, and the second end of the first vertical sub-line is connected to the first data connection block through a via; in at least another circuit unit, the first data connection block is connected to a first end of the second horizontal sub-line, and the second end of the second vertical sub-line is connected to the first data connection block through a via.

[0014] In an exemplary embodiment, the display area further includes a plurality of data transfer strips. In at least one circuit unit, the first end of the first horizontal sub-line is connected to the first data connection block via the data transfer strip; in at least another circuit unit, the first end of the second horizontal sub-line is connected to the first data connection block via the data transfer strip.

[0015] In an exemplary embodiment, in at least one circuit unit, the first horizontal sub-line, the first data connection block, and the data transition strip are interconnected as an integral structure; in at least another circuit unit, the second horizontal sub-line, the first data connection block, and the data transition strip are interconnected as an integral structure.

[0016] In an exemplary embodiment, the display area further includes a plurality of first dummy electrodes, wherein at least one of the first dummy electrodes is located and connected in a circuit unit in the same position and connection structure as at least one of the first data connection blocks in another circuit unit.

[0017] In an exemplary embodiment, in at least one circuit unit, the first vertical sub-line is connected to at least one of the first dummy electrodes via a via; in at least another circuit unit, the second vertical sub-line is connected to at least one of the first dummy electrodes via a via.

[0018] In an exemplary embodiment, the display area further includes a plurality of second data connection blocks; in at least one circuit unit, the second data connection block is connected to the second end of the first horizontal sub-line, and the first end of the second vertical sub-line is connected to the second data connection block through a via.

[0019] In an exemplary embodiment, in at least one circuit unit, the first lateral sub-line and the second data connection block are an integral structure that are interconnected.

[0020] In an exemplary embodiment, the display area further includes a plurality of second dummy electrodes, wherein the position and connection structure of at least one second dummy electrode in one circuit unit is the same as the position and connection structure of at least one second data connection block in another circuit unit.

[0021] In an exemplary embodiment, in at least one circuit unit, the first vertical sub-line is connected to at least one second dummy electrode via a via; in at least another circuit unit, the second vertical sub-line is connected to at least one second dummy electrode via a via.

[0022] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0023] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate including a display area and a bonding area disposed on one side of the display area, the display area including a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, at least one circuit unit including a pixel driving circuit; the fabrication method includes:

[0024] Multiple data signal lines and multiple data connection lines are formed in the display area, and multiple data lead-out lines are formed in the bonding area. The data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines through the data connection lines. At least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction. The two horizontal sub-lines are arranged in different cell rows, and the two vertical sub-lines are arranged in different cell columns. The first direction and the second direction intersect.

[0025] This disclosure provides a display substrate and its preparation method, as well as a display device. By setting at least one data connection line as at least two horizontal sub-lines and at least two vertical sub-lines, with the two horizontal sub-lines set in different unit rows and the two vertical sub-lines set in different unit columns, the difference in the number of data connection line coupling unit columns in different unit rows can be effectively reduced, which can effectively alleviate or even eliminate the appearance of diagonal watermarks at the two corners of the display area near the bonding area.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0028] Figure 1 This is a schematic diagram of the structure of a display device;

[0029] Figure 2 This is a schematic diagram of the structure of a display substrate;

[0030] Figure 3 This is a schematic diagram of a planar structure of a display area within a display region;

[0031] Figure 4 This is a schematic diagram of a cross-sectional structure of a display area within a display region;

[0032] Figure 5 This is an equivalent circuit diagram of a pixel driving circuit;

[0033] Figure 6This is a schematic diagram of the structure of a data connection line in a display substrate;

[0034] Figure 7 This is a schematic diagram of the structure of a data connection line as an exemplary embodiment of the present disclosure;

[0035] Figure 8 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 9 This is a schematic diagram showing the formation of the first semiconductor layer pattern according to an embodiment of the present disclosure;

[0037] Figure 10A and Figure 10B This is a schematic diagram showing the formation of the first conductive layer pattern according to an embodiment of the present disclosure;

[0038] Figure 11A and Figure 11B This is a schematic diagram showing the formation of the second conductive layer pattern according to an embodiment of the present disclosure;

[0039] Figure 12A and Figure 12B This is a schematic diagram showing the formation of the second semiconductor layer pattern according to an embodiment of this disclosure;

[0040] Figure 13A and Figure 13B This is a schematic diagram showing the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0041] Figure 14 This is a schematic diagram showing the formation of the sixth insulating layer pattern according to an embodiment of the present disclosure;

[0042] Figure 15A and Figure 15B This is a schematic diagram showing the formation of the fourth conductive layer pattern according to an embodiment of the present disclosure;

[0043] Figure 16 This is a schematic diagram showing the formation of the first planarization layer pattern according to an embodiment of this disclosure;

[0044] Figure 17A and Figure 17B This is a schematic diagram showing the formation of the fifth conductive layer pattern according to an embodiment of this disclosure;

[0045] Figure 17C This is a schematic diagram illustrating the connection between horizontal and vertical sub-lines in an exemplary embodiment of this disclosure.

[0046] Figure 18 This is a schematic diagram showing the formation of the second planarization layer pattern according to an embodiment of this disclosure;

[0047] Figure 19A and Figure 19B This is a schematic diagram of the anode conductive layer pattern formed according to an embodiment of the present disclosure.

[0048] Explanation of reference numerals in the attached figures:

[0049] 11—First active layer; 12—Second active layer; 13—Third active layer;

[0050] 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer;

[0051] 17—Seventh active layer; 18—Eighth active layer; 21—First scan signal line;

[0052] 22—Second scan signal line; 23—Third scan signal line; 24—Fourth scan signal line;

[0053] 25—Light-emitting signal line; 31—First electrode plate; 32—Second electrode plate;

[0054] 33—Opening; 34—Electrode plate connecting strip; 35—Shielding line;

[0055] 41—First initial signal line; 42—Second initial signal line; 43—Third initial signal line;

[0056] 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode;

[0057] 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode;

[0058] 57—Seventh connecting electrode; 58—Eighth connecting electrode; 59—Ninth connecting electrode;

[0059] 61—First initial connection line; 62—Second initial connection line; 71—First power supply line;

[0060] 72—Data signal line; 73—Anode connection electrode; 74—Power supply shield;

[0061] 80—Data lead-out line; 81—First data connection line; 82—Second data connection line;

[0062] 83—Data transfer strip; 84—First data connection block; 85—Second data connection block;

[0063] 86—First dummy electrode; 87—Second dummy electrode; 91—First power supply trace;

[0064] 92—Second power supply trace; 100—Display area; 101—Substrate;

[0065] 102—Driving structure layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer;

[0066] 110—First Zone; 120—Second Zone; 200—Binding Zone;

[0067] 300—Border area. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0069] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0070] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0071] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0072] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0073] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0074] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0075] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0076] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0077] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0078] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0079] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc., of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0080] Figure 2 This is a schematic diagram of the structure of a display substrate. (Example) Figure 2As shown, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels forming a pixel array, the plurality of sub-pixels being configured to display moving images or still images, and the display area 100 may be referred to as the active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0081] In an exemplary embodiment, the bonding region 200 may include a lead area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead area is connected to the display area 100 and includes at least data leads. The bending area is connected to the lead area and may include at least a composite insulating layer with grooves configured to bend the bonding area to the back side of the display area. The driver chip area may include an integrated circuit (IC) configured to connect to multiple data leads. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0082] In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region sequentially arranged along a direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate driving circuit connected to scan signal lines and light emission signal lines in the display region 100. The power line region is connected to the circuit region and may include at least bezel power leads extending parallel to the edge of the display region and connected to a cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks formed on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display substrate have been prepared, a cutting device cuts along the cutting grooves respectively.

[0083] In an exemplary embodiment, the lead-out area in the binding area 200 and the power line area in the border area 300 may be provided with isolation dams. The isolation dams may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the binding area or the border area of ​​the display area.

[0084] Figure 3This is a schematic diagram of a planar structure of a display area in a display substrate. For example... Figure 3 As shown, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0085] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG pattern.

[0086] In other exemplary embodiments, a pixel unit may include three sub-pixels, which may be arranged in a horizontal or vertical manner, and this disclosure does not limit this arrangement.

[0087] Figure 4 This is a schematic cross-sectional view of a display area in a display substrate, illustrating the structure of four sub-pixels within the display area. Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0088] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0089] Figure 5 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 5 As shown, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. The pixel driving circuit is connected to ten signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power supply line VDD).

[0090] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the storage capacitor C. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8. The third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0091] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power line VDD.

[0092] In an exemplary embodiment, the first transistor T1 may be referred to as the first reset transistor. The gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the third node N3.

[0093] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor. The gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0094] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0095] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0096] In an exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0097] In an exemplary embodiment, the sixth transistor T6 can be referred to as the second light-emitting control transistor. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0098] In an exemplary embodiment, the seventh transistor T7 can be referred to as the second reset transistor. The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0099] In an exemplary embodiment, the eighth transistor T8 can be referred to as the third reset transistor. The gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0100] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0101] In an exemplary embodiment, the first power line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second voltage signal to the light-emitting device, wherein the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial voltage signal, the second initial voltage signal, and the third initial voltage signal can be constant voltage signals, and this disclosure does not limit them.

[0102] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0103] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be a low-temperature polycrystalline silicon (LTPS) transistor, or an oxide transistor, or a combination of LTPS and metal-oxide transistors. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the metal-oxide transistor is made of metal-oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and metal-oxide transistors onto a single display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0104] In an exemplary embodiment, the second transistor T2 may be a metal-oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 may be low-temperature polysilicon transistors.

[0105] With the development of display technology, consumers have increasingly higher requirements for the display effect and quality of display products. Full-screen and narrow-bezel products, with their large screen-to-body ratio and ultra-narrow bezels, have gradually become the development trend of display products. Therefore, narrowing bezels or even borderless designs are receiving increasing attention in OLED display product design. In one type of display substrate, a fanout-in-panel (FIP) structure is adopted. Multiple data connection lines are set in the display area. One end of these data connection lines is connected to multiple data signal lines in the display area, and the other end extends to the bonding area, connecting to the integrated circuit through multiple data leads in the lead-out area. Since the lead-out area does not need to have fan-shaped diagonal lines, the width of the lead-out area is reduced, thus reducing the width of the bottom bezel.

[0106] Figure 6 This is a schematic diagram of the structure of a data connection line in a display substrate. Figure 6 As shown, the display area 100 may include multiple data signal lines 72, multiple first data connection lines 81, and multiple second data connection lines 82, and the binding area 200 may include multiple data lead-out lines 80. The multiple first data connection lines 81 may be straight lines or broken lines extending along a first direction X, and the multiple data signal lines 72, multiple second data connection lines 82, and multiple data lead-out lines 80 may be straight lines or broken lines extending along a second direction Y.

[0107] In an exemplary embodiment, at least one data signal line 72 is connected to multiple pixel driving circuits in a unit column, and the data signal line 72 is configured to provide data signals to the connected pixel driving circuits. Multiple first data connection lines 81 are sequentially arranged at predetermined intervals in the second direction Y, and multiple second data connection lines 82 are sequentially arranged at predetermined intervals in the first direction X, forming a structure arranged layer by layer outwards. The first end of the second data connection line 82 is connected to the data lead-out line 80 in the bonding area 200, and the second end of the second data connection line 82 is connected to the first end of the first data connection line 81. The second end of the first data connection line 81 is connected to the data signal line 72, such that the data signal line 72 in the display area is connected to the data lead-out line 80 in the bonding area through the first data connection line 81 and the second data connection line 82, forming an FIP structure (also called a FIAA structure). In an exemplary embodiment, the first data connection line 81 and the second data connection line 82 are collectively referred to as data connection lines.

[0108] In an exemplary embodiment, since the data connection cable is located in a portion of the display area, the display area can be divided into a first area 110 and a second area 120 based on the presence or absence of the data connection cable. The first area 110 can be the area where the first data connection cable 81 and the second data connection cable 82 are located. Figure 6 The dark area in the middle), the second area 120 can be an area where the first data connection line 81 and the second data connection line 82 are not set (in the dark area ...). Figure 6 (Areas other than the dark areas). In an exemplary embodiment, the first region 110 may be referred to as the FIP region, and the second region 120 may be referred to as the non-FIP region.

[0109] Currently, OLED display devices using the FIP structure suffer from problems such as mura (diagonal watermark). The inventors of this application have discovered that the mura problem is caused by a significant difference in the number of coupling unit columns among multiple first data connection lines. For example... Figure 6 As shown, the first data connection line farther from the binding area has a longer extension length and couples with more unit columns, while the first data connection line closer to the binding area has a shorter extension length and couples with fewer unit columns. Because of the significant difference in the number of unit columns coupled by the first data connection line in different unit rows, diagonal watermarks appear at the two corners of the display area closest to the binding area.

[0110] To eliminate diagonal watermarks, an exemplary embodiment of this disclosure provides a display substrate. In an exemplary embodiment, the display substrate includes a display area and a bonding area disposed on one side of the display area. The display area includes multiple circuit units forming multiple cell rows and multiple cell columns. At least one circuit unit includes a pixel driving circuit. The bonding area includes at least multiple data lead-out lines. The display area also includes multiple data signal lines, multiple first data connection lines, and multiple second data connection lines. The data signal lines are configured to provide data signals to the pixel driving circuit. The data lead-out lines are connected to the data signal lines through the first data connection lines and the second data connection lines. At least one first data connection line includes at least two horizontal sub-lines extending along a first direction, the two horizontal sub-lines being disposed in different cell rows. At least one second data connection line includes at least two vertical sub-lines extending along a second direction, the two vertical sub-lines being disposed in different cell columns. The first direction and the second direction intersect.

[0111] In an exemplary embodiment, at least two horizontal sub-lines are provided in at least one cell row, the two horizontal sub-lines connecting different vertical sub-lines.

[0112] In an exemplary embodiment, at least two vertical sub-lines are provided in at least one unit column, and the two vertical sub-lines connect different horizontal sub-lines.

[0113] In an exemplary embodiment, the orthographic projection of at least one horizontal sub-line on the display substrate at least partially overlaps with the orthographic projection of at least one vertical sub-line on the display substrate.

[0114] In an exemplary embodiment, the two horizontal sub-lines are a first horizontal sub-line and a second horizontal sub-line, and the two vertical sub-lines are a first vertical sub-line and a second vertical sub-line; the data signal line is connected to the data lead-out line through the data connection line, including: the first end of the first vertical sub-line is connected to the data lead-out line; the second end of the first vertical sub-line extends away from the binding area and is connected to the first end of the first horizontal sub-line; the second end of the first horizontal sub-line extends towards the second vertical sub-line and is connected to the first end of the second vertical sub-line; the second end of the second vertical sub-line extends away from the binding area and is connected to the first end of the second horizontal sub-line; and the second end of the second horizontal sub-line extends towards the data signal line and is connected to the data signal line.

[0115] This exemplary embodiment provides a display substrate employing a fanout-in-panel (FIP) structure. In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The driving structure layer of the display area 100 may include multiple circuit units, and the light-emitting structure layer of the display area 100 may include multiple light-emitting units.

[0116] In an exemplary embodiment, multiple circuit units can form multiple unit rows and multiple unit columns. Multiple circuit units in each unit row are sequentially arranged along a first direction X, and multiple circuit units in each unit column are sequentially arranged along a second direction Y, forming an array of circuit units. The first direction X intersects the second direction Y. Multiple light-emitting units can form multiple light-emitting rows and multiple light-emitting columns. Multiple light-emitting units in each light-emitting row are sequentially arranged along the first direction X, and multiple light-emitting units in each light-emitting column are sequentially arranged along the second direction Y, forming an array of light-emitting units. In an exemplary embodiment, at least one circuit unit can include at least a pixel driving circuit, and at least one circuit unit can include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0117] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0118] Figure 7 This is a schematic diagram of the structure of a data connection line as an exemplary embodiment of this disclosure. Figure 7 As shown, the display area 100 may include multiple data signal lines 72 and multiple data connection lines, and the bonding area 200 may include multiple data lead-out lines 80. The multiple data signal lines 72 and multiple data lead-out lines 80 can be straight lines extending along the second direction Y or broken lines. The multiple data connection lines can be broken lines, including both straight lines extending along the first direction X and straight lines extending along the second direction Y. The data signal lines 72 are configured to provide data signals to the connected pixel driving circuit, and the data signal lines 72 are connected to the data lead-out lines 80 via data connection lines. Specifically, the first ends of the multiple data connection lines are connected to the multiple data lead-out lines 80 in the bonding area 200, and the second ends of the multiple data connection lines extend away from the bonding area 200 and are connected to the multiple data signal lines 72, so that the data signal lines 72 in the display area are connected to the data lead-out lines 80 in the bonding area via data connection lines, forming an FIP structure (also known as a FIAA structure). Since the data connection cable is located in the display area, the lead-out area does not need to be set with a fan-shaped diagonal line, thus reducing the length of the second direction Y of the binding area, reducing the width of the bottom bezel, increasing the screen ratio, and facilitating the realization of full-screen display.

[0119] In an exemplary embodiment, the display area 100 may have a center line O, and multiple data signal lines 72, multiple data connection lines and multiple data lead-out lines 80 may be mirror-symmetrical with respect to the center line O. The center line O may be a straight line that bisects multiple unit columns in multiple display areas and extends along the second direction Y.

[0120] In an exemplary embodiment, at least one data connection line may include at least two horizontal sub-lines and at least two vertical sub-lines. The shape of the horizontal sub-lines may be a straight line or a broken line extending along a first direction X, and the shape of the vertical sub-lines may be a straight line or a broken line extending along a second direction Y. The two horizontal sub-lines may be set in different cell rows, and the two vertical sub-lines may be set in different cell columns. The horizontal sub-lines and the vertical sub-lines are connected to each other to form a broken line data connection line including horizontal sub-lines and vertical sub-lines.

[0121] In an exemplary embodiment, at least two horizontal sub-lines may be provided in at least one cell row, and the two horizontal sub-lines may connect different vertical sub-lines.

[0122] In an exemplary embodiment, at least two vertical sub-lines may be provided in at least one unit column, and the two vertical sub-lines may connect different horizontal sub-lines.

[0123] In an exemplary embodiment, the orthographic projection of at least one horizontal sub-line on the display substrate at least partially overlaps with the orthographic projection of at least one vertical sub-line on the display substrate.

[0124] In an exemplary embodiment, the two horizontal sub-lines can be a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2 extending along a first direction X, and the two vertical sub-lines can be a first vertical sub-line 82-1 and a second vertical sub-line 82-2 extending along a second direction Y. The first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 are respectively disposed in different cell rows. The first horizontal sub-line 81-1 can be disposed in a cell row closer to the binding area, and the second horizontal sub-line 81-2 can be disposed in a cell row on the side of the first horizontal sub-line 81-1 away from the binding area. The first vertical sub-line 82-1 and the second vertical sub-line 82-2 are respectively disposed in different cell columns. The first vertical sub-line 82-1 can be disposed in a cell column closer to the center line O, and the second vertical sub-line 82-2 can be disposed in a cell column on the side of the first vertical sub-line 82-1 away from the center line O.

[0125] In an exemplary embodiment, in the first direction X, the first horizontal sub-line 81-1 can be disposed on the side of the first vertical sub-line 82-1 away from the center line O, and the second vertical sub-line 82-2 can be disposed on the side of the first horizontal sub-line 81-1 away from the center line O, and the second horizontal sub-line 81-2 can be disposed on the side of the second vertical sub-line 82-2 away from the center line O. In the second direction Y, the first horizontal sub-line 81-1 can be disposed on the side of the first vertical sub-line 82-1 away from the binding area, and the second vertical sub-line 82-2 can be disposed on the side of the first horizontal sub-line 81-1 away from the binding area, and the second horizontal sub-line 81-2 can be disposed on the side of the second vertical sub-line 82-2 away from the binding area.

[0126] In an exemplary embodiment, the connection of the data signal line 72 to the data lead-out line 80 via the data connection line may include: the first end of the first vertical sub-line 82-1 is connected to the data lead-out line 80; the second end of the first vertical sub-line 82-1 extends away from the binding area and is connected to the first end of the first horizontal sub-line 81-1; the second end of the first horizontal sub-line 81-1 extends away from the center line O (towards the second vertical sub-line 82-2) and is connected to the first end of the second vertical sub-line 82-2; the second end of the second vertical sub-line 82-2 extends away from the binding area and is connected to the first end of the second horizontal sub-line 81-2; and the second end of the second horizontal sub-line 81-2 extends away from the center line O (towards the data signal line 72) and is connected to the data signal line 72.

[0127] In an exemplary embodiment, at least one horizontal sub-line may be connected to two vertical sub-lines. For example, the first end of the first horizontal sub-line 81-1 is connected to the first vertical sub-line 82-1, and the second end of the first horizontal sub-line 81-1 is connected to the second vertical sub-line 82-2.

[0128] In an exemplary embodiment, at least one vertical sub-line may be connected to two horizontal sub-lines. For example, the first end of the second vertical sub-line 82-2 is connected to the first horizontal sub-line 81-1, and the second end of the second vertical sub-line 82-2 is connected to the second horizontal sub-line 81-2.

[0129] In an exemplary embodiment, the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 can be referred to as the first data connection line 81, and the first vertical sub-line 82-1 and the second vertical sub-line 82-2 can be referred to as the second data connection line 82. That is, the data connection line may include the first data connection line 81 and the second data connection line 82. The first data connection line 81 may include the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2, and the second data connection line 82 may include the first vertical sub-line 82-1 and the second vertical sub-line 82-2.

[0130] In an exemplary embodiment, the number of data connection lines in the display area can be the same as the number of data signal lines, with each data signal line connected to a corresponding lead-out line via a data connection line. Alternatively, the number of data connection lines in the display area can be less than the number of data signal lines, with some data signal lines in the display area connected to corresponding data lead-out lines via data connection lines, and other data signal lines directly connected to data lead-out lines. This disclosure does not impose any limitations on this aspect.

[0131] In an exemplary embodiment, the data lead 80 can be directly connected to the data signal line 72 and the data connection line, or they can be connected through a via; this disclosure does not limit the connection.

[0132] In an exemplary embodiment, the display area can be divided into a first area 110 and a second area 120, wherein the first area 110 can be an area provided with horizontal sub-lines and vertical sub-lines. Figure 7 The dark area in the middle), the second area 120 can be an area without horizontal and vertical sub-lines set ( Figure 7 (Areas other than medium-dark areas).

[0133] Figure 8 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating... Figure 7 The structure of region A. In an exemplary embodiment, the display area may include multiple circuit units forming multiple cell rows and multiple cell columns. At least one circuit unit may include a pixel driving circuit, which is connected to the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light emission signal line 25, the first initial signal line 41, the second initial signal line 42, the third initial signal line 43, the first power supply line 71, and the data signal line 72, respectively.

[0134] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, and the light emission signal line 25 are configured to provide a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a light emission control signal to the pixel driving circuit, respectively. The first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively. The first power supply line 71 is configured to provide a first power supply signal to the pixel driving circuit, and the data signal line 72 is configured to provide a data signal to the pixel driving circuit. The multiple signal lines connected to the pixel driving circuit can be located within corresponding circuit units.

[0135] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light emission signal line 25, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first power line 71 and the data signal line 72 can be straight lines or broken lines extending along the second direction Y of the main body.

[0136] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0137] In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The storage capacitor may include a first electrode and a second electrode stacked together, and the plurality of transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second reset transistor, and an eighth transistor T8 as a third reset transistor. The second transistor T2 may be a metal-oxide-semiconductor transistor, and the first transistor T1, the third transistor T3 through the eighth transistor T8 may be low-temperature polysilicon transistors.

[0138] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 23, the first terminal of the first transistor T1 is connected to the first initial signal line 41, and the second terminal of the first transistor T1 is connected to the second terminals of the second transistor T2, the third transistor T3, and the sixth transistor T6, respectively. The gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, and the first terminal of the second transistor T2 is connected to the first plate of the storage capacitor (which is also the gate electrode of the third transistor T3). The first terminal of the third transistor T3 is connected to the second terminals of the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8, respectively. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first terminal of the fourth transistor T4 is connected to the data signal line 72. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 25, and the first terminal of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 25, and the second terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the second scan signal line 22, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0139] In an exemplary embodiment, in at least one circuit unit, the fourth scan signal line 24 can be disposed on the side opposite to the second direction Y of the storage capacitor (third transistor T3), the first scan signal line 21 can be disposed on the side of the fourth scan signal line 24 away from the storage capacitor, the third scan signal line 23 and the second initial signal line 42 can be disposed on the side of the first scan signal line 21 away from the storage capacitor, and the first initial signal line 41 can be disposed on the side of the third scan signal line 23 away from the storage capacitor. The light-emitting signal line 25 can be disposed on the side of the storage capacitor in the second direction Y, and the second scan signal line 22 and the third initial signal line 43 can be disposed on the side of the light-emitting signal line 25 away from the storage capacitor.

[0140] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the third scan signal line 23 on the substrate, and the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 22 on the substrate.

[0141] In an exemplary embodiment, at least one circuit unit may further include a first initial connection line 61. The shape of the first initial connection line 61 may be a straight line or a broken line with the main body extending along the second direction Y, and it is connected to the first initial signal line 41. The first initial signal line 41 and the first initial connection line 61 form a mesh-like interconnected structure for transmitting the first initial signal.

[0142] In an exemplary embodiment, at least one circuit unit may further include a second initial connection line 62. The shape of the second initial connection line 62 may be a straight line or a broken line with the main body extending along the second direction Y, and it is connected to the second initial signal line 42. The second initial signal line 42 and the second initial connection line 62 form a mesh-like interconnected structure for transmitting the second initial signal.

[0143] In an exemplary embodiment, the display area may further include multiple data connection lines, at least one of which may include a first horizontal sub-line 81-1, a second horizontal sub-line 81-2, a first vertical sub-line 82-1, and a second vertical sub-line 82-2. The first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 may be straight lines or broken lines extending along a first direction X. The first horizontal sub-line 81-1 may be located in the M+5th unit row, and the second horizontal sub-line 81-2 may be located in the Mth unit row. The first vertical sub-line 82-1 and the second vertical sub-line 82-2 may be straight lines or broken lines extending along a second direction Y. The first vertical sub-line 82-1 may be located between the N+10th and N+11th unit columns, and the second vertical sub-line 82-2 may be located between the Nth and N+1th unit columns.

[0144] In an exemplary embodiment, the first end of the first vertical sub-line 82-1 is connected to the data lead-out line of the binding area. The second end of the first vertical sub-line 82-1 extends in the opposite direction of the second direction Y (towards the first horizontal sub-line 81-1) and is connected to the first end of the first horizontal sub-line 81-1. The second end of the first horizontal sub-line 81-1 extends in the opposite direction of the first direction X (towards the second vertical sub-line 82-2) and is connected to the first end of the second vertical sub-line 82-2. The second end of the second vertical sub-line 82-2 extends in the opposite direction of the second direction Y (towards the second horizontal sub-line 81-2) and is connected to the first end of the second horizontal sub-line 81-2. The second end of the second horizontal sub-line 81-2 extends in the opposite direction of the first direction X (towards the data signal line 72) and is connected to the data signal line 72.

[0145] In an exemplary embodiment, at least one circuit unit may further include a data transfer strip 83 and a first data connection block 84. The data transfer strip 83 may be a strip extending along the second direction Y, and the first data connection block 84 may be a block shape (such as a rectangle). The first end of the data transfer strip 83 is connected to either the first horizontal sub-line 81-1 or the second horizontal sub-line 81-2, and the second end of the data transfer strip 83 is connected to the first data connection block 84. The first data connection block 84 is configured to connect to either the first vertical sub-line 82-1 or the second vertical sub-line 82-2. For example, in the Mth unit row, the first data connection block 84 is connected to the second horizontal sub-line 81-2 via the data transfer strip 83, and the second end of the second vertical sub-line 82-2 is connected to the first data connection block 84, thus realizing the connection between the second end of the second vertical sub-line 82-2 and the first end of the second horizontal sub-line 81-2. For example, in the M+5th unit row, the first data connection block 84 is connected to the first horizontal sub-line 81-1 through the data transfer strip 83, and the second end of the first vertical sub-line 82-1 is connected to the first data connection block 84, thus realizing the connection between the second end of the first vertical sub-line 82-1 and the first end of the first horizontal sub-line 81-1.

[0146] In an exemplary embodiment, at least one circuit unit may further include a second data connection block 85. The second data connection block 85 may be block-shaped (e.g., rectangular) and connected to the second end of the first horizontal sub-line 81-1. The second data connection block 85 is configured to connect to the first end of the second vertical sub-line 82-2. For example, in the M+5th unit row, the second data connection block 85 is connected to the second end of the first horizontal sub-line 81-1, and the first end of the second vertical sub-line 82-2 is connected to the second data connection block 85, thus realizing the connection between the second end of the first horizontal sub-line 81-1 and the first end of the second vertical sub-line 82-2.

[0147] In an exemplary embodiment, at least one circuit unit may further include a first dummy electrode 86, which may be block-shaped (e.g., rectangular) and configured to connect to a vertical sub-line. The position and connection structure of the first dummy electrode 86 in one circuit unit may be substantially the same as the position and connection structure of the first data connection block 84 in another circuit unit, except that the first dummy electrode 86 is isolated.

[0148] In an exemplary embodiment, at least one circuit unit may further include a second dummy electrode 87. The second dummy electrode 87 may be block-shaped (e.g., rectangular) and configured to connect to a vertical sub-line. The position and connection structure of the second dummy electrode 87 in one circuit unit may be substantially the same as the position and connection structure of the second data connection block 85 in another circuit unit, except that the second dummy electrode 87 is isolated.

[0149] In an exemplary embodiment, in the direction perpendicular to the display substrate, the driving structure layer of the display area may include multiple conductive layers. Horizontal sub-lines may be disposed in the same conductive layer, vertical sub-lines may be disposed in the same conductive layer, or horizontal and vertical sub-lines may be disposed in different conductive layers.

[0150] In an exemplary embodiment, the plurality of conductive layers may include at least a first source / drain metal layer (SD1) disposed on the substrate and a second source / drain metal layer (SD2) disposed on the side of the first source / drain metal layer away from the substrate. Horizontal sub-lines may be disposed in the first source / drain metal layer and vertical sub-lines may be disposed in the second source / drain metal layer.

[0151] In an exemplary embodiment, the first data connection block 84, the second data connection block 85, the first dummy electrode 86, and the second dummy electrode 87 may be disposed in the first source / drain metal layer.

[0152] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0153] In an exemplary embodiment, taking 72 circuit units (6 units in rows and 12 units in columns) as an example, the fabrication process of the display substrate may include the following operations.

[0154] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film using a patterning process to form a first insulating layer disposed on the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, such as... Figure 9 As shown.

[0155] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integral structure interconnected, while the first active layer 11 and the eighth active layer 18 are separately configured.

[0156] In an exemplary embodiment, in the first direction X, the first active layer 11 and the sixth active layer 16 may be located on one side of the third active layer 13 in this circuit unit, and the fourth active layer 14 and the fifth active layer 15 may be located on the other side of the third active layer 13 in this circuit unit. In the second direction Y, the first active layer 11 and the fourth active layer 14 may be located on the opposite side of the third active layer 13 in the second direction Y in this circuit unit, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be located on one side of the third active layer 13 in the second direction Y in this circuit unit.

[0157] In an exemplary embodiment, the third active layer 13 may be shaped like an "Ω", the fourth active layer 14 and the sixth active layer 16 may be shaped like an "L", and the first active layer 11, the fifth active layer 15, the seventh active layer 17 and the eighth active layer 18 may be shaped like an "I".

[0158] In an exemplary embodiment, the first active layer 11 and the third active layers 13 to the eighth active layers 18 may each include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may simultaneously serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer may be interconnected, and the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be interconnected, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first active layer's first zone 11-1, the first active layer's second zone 11-2, the fourth active layer's first zone 14-1, the fifth active layer's first zone 15-1, the seventh active layer's first zone 17-1, the eighth active layer's first zone 18-1, and the eighth active layer's second zone 18-2 can be set individually.

[0159] In an exemplary embodiment, in a cell row, the first region 15-1 of the fifth active layer in some adjacent circuit cells can be interconnected, and the fifth active layers in the two circuit cells can be an integral structure interconnected. For example, the fifth active layer of the Nth cell column and the fifth active layer of the N+1th cell column can be an integral structure interconnected, the fifth active layer of the N+2th cell column and the fifth active layer of the N+3th cell column can be an integral structure interconnected, the fifth active layer of the N+4th cell column and the fifth active layer of the N+5th cell column can be an integral structure interconnected, the fifth active layer of the N+6th cell column and the fifth active layer of the N+7th cell column can be an integral structure interconnected, the fifth active layer of the N+8th cell column and the fifth active layer of the N+9th cell column can be an integral structure interconnected, and the fifth active layer of the N+10th cell column and the fifth active layer of the N+11th cell column can be an integral structure interconnected. Since the first region of the fifth active layer in each circuit unit is configured to be connected to the first power line formed subsequently, by forming an integrated structure in which the fifth active layers of adjacent circuit units are interconnected, it can be ensured that the first pole of the fifth transistor T5 of adjacent circuit units has the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0160] In an exemplary embodiment, the first semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to the column boundaries. For example, the first semiconductor layers of the Nth cell column and the N+1th cell column may be mirror-symmetrical with respect to the column boundaries, and the first semiconductor layers of the N+1th cell column and the N+2th cell column may be mirror-symmetrical with respect to the column boundaries. In an exemplary embodiment, the shapes of the first semiconductor layers in multiple cell rows may be substantially the same.

[0161] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning the first transistor, the third transistor, to the seventh transistor are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; performing a hydrogen removal treatment on the amorphous silicon thin film; and then performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0162] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the first semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A A planar schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0163] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light-emitting signal line 25, and a first electrode 31 of a storage capacitor.

[0164] In an exemplary embodiment, the first electrode plate 31 can be rectangular in shape, with chamfered corners. The orthographic projection of the first electrode plate 31 onto the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode plate 31 can simultaneously serve as the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0165] In an exemplary embodiment, the shape of the first scan signal line 21 can be a straight line or a broken line extending along the first direction X of the main body. The first scan signal line 21 can be located on the side opposite to the second direction Y of the first electrode plate 31. The area where the first scan signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0166] In an exemplary embodiment, the shape of the second scan signal line 22 can be a straight line or a broken line extending along the first direction X of the main body. The second scan signal line 22 can be located on one side of the first electrode plate 31 in the second direction Y. The area where the second scan signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7. The area where the second scan signal line 22 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0167] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line extending along the first direction X of the main body. The third scan signal line 23 can be located on the side of the first scan signal line 21 away from the first electrode plate 31. The area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.

[0168] In an exemplary embodiment, the shape of the light-emitting signal line 25 can be a straight line or a broken line extending along the first direction X of the main body. The light-emitting signal line 25 can be located between the second scan signal line 22 and the first electrode plate 31. The area where the light-emitting signal line 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5. The area where the light-emitting signal line 25 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0169] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can be designed with non-uniform widths, with the width being the dimension of the second direction Y. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0170] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 may include regions that overlap with the first semiconductor layer and regions that do not overlap with the first semiconductor layer. The width of the signal line in the region that overlaps with the first semiconductor layer may be greater than the width of the signal line in the region that does not overlap with the first semiconductor layer.

[0171] In an exemplary embodiment, the first conductive layer of adjacent cell columns may be mirror-symmetrical with respect to the column boundary line. For example, the first conductive layer of the Nth cell column and the first conductive layer of the N+1th cell column may be mirror-symmetrical with respect to the column boundary line, and the first conductive layer of the N+1th cell column and the first conductive layer of the N+2th cell column may be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the shape of the first conductive layer in multiple cell rows may be substantially the same.

[0172] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1, the third transistor T3 to the eighth transistor T8. The first semiconductor layer in the area not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first transistor T1, the third transistor T3 to the eighth transistor T8 are both conducted.

[0173] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 11A and Figure 11B As shown, Figure 11B for Figure 11A A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0174] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a second electrode 32 of a storage capacitor, a shielding line 35, and a first initial signal line 41.

[0175] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as the upper electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0176] In an exemplary embodiment, the second electrode plate 32 is provided with an opening 33. The opening 33 may be rectangular in shape and may be located in the middle of the second electrode plate 32, so that the second electrode plate 32 forms an annular structure. The opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a subsequently formed thirteenth via. The thirteenth via is located within the opening 33 and exposes the first electrode plate 31, so that the subsequently formed first connecting electrode is connected to the first electrode plate 31.

[0177] In an exemplary embodiment, a plate connecting strip 34 is provided on the second plate 32. The shape of the plate connecting strip 34 can be a strip extending along the first direction X, and it can be disposed on one side of the second plate 32 in the first direction X or on the opposite side of the first direction X. The first end of the plate connecting strip 34 is connected to the second plate 32 in this circuit unit, and the second end of the plate connecting strip 34 is connected to the second plate 32 in an adjacent circuit unit in the first direction X or the opposite direction of the first direction X.

[0178] In an exemplary embodiment, in a unit row, the second electrode plates 32 and electrode plate connecting strips 34 in two adjacent circuit units are interconnected as an integral structure. Since the second electrode plate 32 in each circuit unit is connected to the subsequently formed first power line, by forming an interconnected integral structure of the second electrode plates 32 of adjacent circuit units, the integral structure of the second electrode plates can be reused as power signal lines. This ensures that the second electrode plates of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0179] In an exemplary embodiment, the shape of the shielding line 35 can be a straight line or a broken line extending along the first direction X of the main body, and can be located between the first scan signal line 21 and the second electrode 32. The shielding line 35 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2 to ensure the electrical performance of the oxide second transistor T2, and is also configured as the bottom gate electrode of the second transistor T2.

[0180] In an exemplary embodiment, the masking line 35 can be designed with non-uniform width, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines.

[0181] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line extending along the first direction X of the main body. The first initial signal line 41 can be located on the side of the third scan signal line 23 away from the second electrode plate 32. A first initial connection block 41-1 can be provided on the first initial signal line 41 of each circuit unit. The shape of the first initial connection block 41-1 can be block-shaped (such as rectangular) and connected to the first initial signal line 41. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a subsequently formed seventh connection electrode.

[0182] In an exemplary embodiment, some of the first initial connection blocks 41-1 of adjacent circuit units in the first direction X can be interconnected to form an interconnected integral structure, so that some adjacent circuit units share the same first initial connection block 41-1. For example, the first initial connection block 41-1 of the N+1th unit column and the first initial connection block 41-1 of the N+2th unit column are interconnected integral structures. As another example, the first initial connection block 41-1 of the N+3th unit column and the first initial connection block 41-1 of the N+4th unit column are interconnected integral structures.

[0183] In an exemplary embodiment, the second conductive layers of adjacent cell columns can be mirror-symmetrical with respect to the column boundaries. For example, the second conductive layers of the Nth cell column and the N+1th cell column can be mirror-symmetrical with respect to the column boundaries, and the second conductive layers of the N+1th cell column and the N+2th cell column can be mirror-symmetrical with respect to the column boundaries. In an exemplary embodiment, the shapes of the second conductive layers in multiple cell rows can be substantially the same.

[0184] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the second semiconductor film using a patterning process to form a fourth insulating layer covering the substrate; and a second semiconductor layer pattern disposed on the fourth insulating layer, such as... Figure 12A and Figure 12B As shown, Figure 12B for Figure 12A A planar schematic diagram of the second semiconductor layer.

[0185] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least the second active layer 12 of the second transistor T2.

[0186] In an exemplary embodiment, the second active layer 12 may be in the shape of an "L" and the orthographic projection of the second active layer 12 on the substrate may at least partially overlap with the orthographic projection of the shielding line 35 on the substrate.

[0187] In an exemplary embodiment, the first region 12-1 of the second active layer may be located on the side of the shielding line 35 away from the second electrode plate 32, and the second region 12-2 of the second active layer may be located on the side of the shielding line 35 close to the second electrode plate 32.

[0188] In an exemplary embodiment, the second semiconductor layers in adjacent cell columns may be mirror-symmetrical with respect to the column boundaries. For example, the second semiconductor layers in the Nth cell column and the (N+1)th cell column may be mirror-symmetrical with respect to the column boundaries, and the second semiconductor layers in the (N+1)th cell column and the (N+2)th cell column may be mirror-symmetrical with respect to the column boundaries. In an exemplary embodiment, the shapes of the second semiconductor layers in multiple cell rows may be substantially the same.

[0189] In an exemplary embodiment, the second semiconductor layer may be an oxide layer, i.e., the second transistor T2 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film may be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0190] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer; and a third conductive layer pattern disposed on the fifth insulating layer, such as... Figure 13A and Figure 13B As shown, Figure 13B for Figure 13A A schematic planar view of the third conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the third gate metal (GATE3) layer.

[0191] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least: a fourth scan signal line 24, a second initial signal line 42, and a third initial signal line 43.

[0192] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a broken line extending along the first direction X of the main body. The fourth scan signal line 24 can be located between the first scan signal line 21 and the second electrode 32. The area where the fourth scan signal line 24 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0193] In an exemplary embodiment, the orthographic projection of the fourth scan signal line 24 on the substrate and the orthographic projection of the blocking line 35 on the substrate at least partially overlap. The fourth scan signal line 24 and the blocking line 35 can be connected to the same signal source, so that the blocking line 35 can serve as the bottom gate electrode of the second transistor T2 and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming a top-gate and bottom-gate structure for the second transistor T2.

[0194] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line extending along the first direction X of the main body. The second initial signal line 42 can be located on the side of the first scan signal line 21 away from the second electrode plate 32. A second initial connection block 42-1 can be provided on the second initial signal line 42 of each circuit unit. The shape of the second initial connection block 42-1 can be block-shaped (such as rectangular) and connected to the second initial signal line 42. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through the subsequently formed eighth connection electrode.

[0195] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the third scan signal line 23 on the substrate. The second initial signal line 42, which transmits a constant voltage, can shield the influence of the third scan signal line 23 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0196] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line extending along the first direction X of the main body. The third initial signal line 43 can be located between the second electrode plate 32 and the first initial signal line 41. A third initial connection block 43-1 can be provided on the third initial signal line 43 of each circuit unit. The shape of the third initial connection block 43-1 can be block-shaped (such as rectangular) and connected to the third initial signal line 43. The third initial connection block 43-1 is configured to be connected to the first region of the eighth active layer through the subsequently formed ninth connection electrode.

[0197] In an exemplary embodiment, the third initial connection blocks 43-1 of some adjacent circuit units in the first direction X can be interconnected to form an interconnected integral structure, so that some adjacent circuit units share the same third initial connection block 43-1. For example, the third initial connection block 43-1 of the Nth unit column and the third initial connection block 43-1 of the N+1th unit column are interconnected integral structures. As another example, the third initial connection block 43-1 of the N+2th unit column and the third initial connection block 43-1 of the N+3th unit column are interconnected integral structures.

[0198] In an exemplary embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 22 on the substrate. The third initial signal line 43, which transmits a constant voltage, can shield the second scan signal line 22 from the influence on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0199] In an exemplary embodiment, the third conductive layer of adjacent cell columns can be mirror-symmetrical with respect to the column boundary line. For example, the third conductive layer of the Nth cell column and the third conductive layer of the N+1th cell column can be mirror-symmetrical with respect to the column boundary line, and the third conductive layer of the N+1th cell column and the third conductive layer of the N+2th cell column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the shape of the third conductive layer in multiple cell rows can be substantially the same.

[0200] (6) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer has a plurality of vias, such as... Figure 14 As shown.

[0201] In an exemplary embodiment, the plurality of vias in each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0202] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow a subsequently formed seventh connection electrode to be connected to the first region of the first active layer through the via.

[0203] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second region of the first active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the second via V2 are etched away, exposing the surface of the second region of the first active layer. The second via V2 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the first active layer through the via.

[0204] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the second active layer onto the substrate. The sixth and fifth insulating layers within the third via V3 are etched away, exposing the surface of the first region of the second active layer. The third via V3 is configured to allow a subsequently formed first connection electrode to be connected to the first region of the second active layer through the via.

[0205] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the second region of the second active layer onto the substrate. The sixth and fifth insulating layers within the fourth via V4 are etched away, exposing the surface of the second region of the second active layer. The fourth via V4 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the second active layer through the via.

[0206] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer) onto the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer). The fifth via V5 is configured to allow a subsequently formed fifth connection electrode to be connected to the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer) through the via.

[0207] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is located within the range of the orthographic projection of the second region of the third active layer (which is also the first region of the sixth active layer) onto the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the second region of the third active layer (which is also the first region of the sixth active layer). The sixth via V6 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the third active layer (which is also the first region of the sixth active layer) through the via.

[0208] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the fourth active layer. The seventh via V7 is configured to allow a subsequently formed third connection electrode to be connected to the first region of the fourth active layer through the via.

[0209] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the first region of the fifth active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the fifth active layer. The eighth via V8 is configured to allow a subsequently formed fourth connection electrode to connect to the first region of the fifth active layer through this via. In an exemplary embodiment, since the first regions of the fifth active layer of some adjacent circuit units in a cell row are interconnected, some adjacent circuit units can share a single eighth via V8.

[0210] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The ninth via V9 is configured to allow a subsequently formed sixth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0211] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the first region of the seventh active layer. The tenth via V10 is configured to allow the subsequently formed eighth connection electrode to be connected to the first region of the seventh active layer through the via.

[0212] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the first region of the eighth active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first region of the eighth active layer. The eleventh via V11 is configured to allow the subsequently formed ninth connection electrode to be connected to the first region of the eighth active layer through the via.

[0213] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the range of the orthographic projection of the second region of the eighth active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the second region of the eighth active layer. The twelfth via V12 is configured to allow a subsequently formed fifth connection electrode to be connected to the second region of the eighth active layer through the via.

[0214] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the opening 33 on the substrate. The sixth, fifth, fourth and third insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first electrode plate 31. The thirteenth via V13 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 31 through the via.

[0215] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the orthographic projection of the electrode connecting strip 34 of the second electrode 32 onto the substrate. The sixth, fifth, and fourth insulating layers within the fourteenth via V14 are etched away, exposing the surface of the electrode connecting strip 34. The fourteenth via V14 is configured to allow a subsequently formed fourth connection electrode to be connected to the electrode connecting strip 34 through this via. In an exemplary embodiment, since the second electrode 32 of adjacent circuit units in a cell row are interconnected via the electrode connecting strip 34, adjacent circuit units in a cell row can share a fourteenth via V14.

[0216] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the first initial connection block 41-1 on the substrate of the first initial signal line 41. The sixth, fifth, and fourth insulating layers within the fifteenth via V15 are etched away, exposing the surface of the first initial connection block 41-1. The fifteenth via V15 is configured to allow the subsequently formed seventh connection electrode to be connected to the first initial connection block 41-1 through the via.

[0217] In an exemplary embodiment, since the first initial connection block 41-1 of some adjacent circuit units in a cell row is an integral structure that is interconnected, and adjacent circuit units share the same first initial connection block 41-1, some adjacent circuit units can share a fifteenth via V15.

[0218] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the second initial connection block 42-1 on the substrate of the second initial signal line 42. The sixth insulating layer in the sixteenth via V16 is etched away, exposing the surface of the second initial connection block 42-1. The sixteenth via V16 is configured to allow the subsequently formed eighth connection electrode to be connected to the second initial connection block 42-1 through the via.

[0219] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the range of the orthographic projection of the third initial connection block 43-1 of the third initial signal line 43 onto the substrate. The sixth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the third initial connection block 43-1. The seventeenth via V17 is configured to allow the subsequently formed ninth connection electrode to be connected to the third initial connection block 43-1 through the via.

[0220] In an exemplary embodiment, since the third initial connection block 43-1 of some adjacent circuit units in a cell row is an integral structure that is interconnected, and the adjacent circuit units share the same third initial connection block 43-1, some adjacent circuit units can share a seventeenth via V17.

[0221] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, such as... Figure 15A and Figure 15B As shown, Figure 15B for Figure 15A A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0222] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, a seventh connecting electrode 57, an eighth connecting electrode 58, and a ninth connecting electrode 59.

[0223] In an exemplary embodiment, the first connecting electrode 51 can be a strip shape in which the main body extends along the second direction Y. The first end of the first connecting electrode 51 is connected to the first region of the second active layer through the third via V3. After the second end of the first connecting electrode 51 extends along the second direction Y, it is connected to the first electrode plate 31 through the thirteenth via V13. In an exemplary embodiment, since the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connecting electrode 51 makes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 have the same potential, forming the first node N1 of the pixel driving circuit.

[0224] In an exemplary embodiment, the second connecting electrode 52 can be a strip shape in which the main body extends along the second direction Y. The first end of the second connecting electrode 52 is connected to the second region of the first active layer through the second via V2. After the second end of the second connecting electrode 52 extends along the second direction Y, it is connected to the second region of the third active layer (which is also the first region of the sixth active layer) through the sixth via V6. The portion between the first end and the second end of the second connecting electrode 52 is connected to the second region of the second active layer through the fourth via V4. In an exemplary embodiment, the second connecting electrode 52 makes the second terminals of the first transistor T1, the second terminals of the second transistor T2, the second terminals of the third transistor T3, and the first terminal of the sixth transistor T6 have the same potential, forming the third node N3 of the pixel driving circuit.

[0225] In an exemplary embodiment, the third connection electrode 53 may be block-shaped (e.g., rectangular), and the third connection electrode 53 is connected to the first region of the fourth active layer through the seventh via V7. The third connection electrode 53 is configured to be connected to a subsequently formed data signal line.

[0226] In an exemplary embodiment, the fourth connecting electrode 54 can be a strip extending along the second direction Y. The first end of the fourth connecting electrode 54 is connected to the first region of the fifth active layer through the eighth via V8. The second end of the fourth connecting electrode 54 extends in the opposite direction of the second direction Y and is connected to the electrode connecting strip 34 through the fourteenth via V14. Since the electrode connecting strip 34 is connected to the second electrode 32, the first electrode of the fifth transistor T5 and the second electrode 32 of the storage capacitor in the circuit unit have the same potential.

[0227] In an exemplary embodiment, since some adjacent circuit units in a cell row share an eighth via V8 and a fourteenth via V14, some adjacent circuit units can share a fourth connection electrode 54.

[0228] In an exemplary embodiment, at least one circuit unit may further include a power connection block 54-1. The power connection block 54-1 may be a strip shape extending along a first direction X. A first end of the power connection block 54-1 is connected to a second end of a fourth connection electrode 54, and the second end of the power connection block 54-1 extends in a direction away from the fourth connection electrode 54. The power connection block 54-1 is configured to connect to a subsequently formed first power line.

[0229] In an exemplary embodiment, in at least one circuit unit, the fourth connection electrode 54 and the power connection block 54-1 can be an integral structure interconnected with each other. Since some adjacent circuit units can share a fourth connection electrode 54, the fourth connection electrode 54 and the power connection block 54-1 in some adjacent circuit units can be an integral structure interconnected with each other. This ensures that the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor in some adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0230] In an exemplary embodiment, the fifth connecting electrode 55 can be a strip shape extending along the second direction Y of the main body. The first end of the fifth connecting electrode 55 is connected to the first region of the third active layer through the fifth via V5, and the second end of the fifth connecting electrode 55 is connected to the second region of the eighth active layer through the twelfth via V12. In an exemplary embodiment, since the first region of the third active layer also serves as the second region of the fourth active layer and the second region of the fifth active layer, the fifth connecting electrode 55 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming the second node N2 of the pixel driving circuit.

[0231] In an exemplary embodiment, the sixth connection electrode 56 can be block-shaped (e.g., rectangular), and is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the ninth via V9. In an exemplary embodiment, the sixth connection electrode 56 can simultaneously serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7, and is configured to connect to the subsequently formed anode connection electrode.

[0232] In an exemplary embodiment, the seventh connection electrode 57 can be a strip extending along the first direction X. The first end of the seventh connection electrode 57 is connected to the first region of the first active layer through a first via V1, and the second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 through a fifteenth via V15. In this exemplary embodiment, since the first initial connection block 41-1 is connected to the first initial signal line 41, the seventh connection electrode 57 enables the writing of the first initial signal transmitted by the first initial signal line 41 to the first electrode of the first transistor T1.

[0233] In an exemplary embodiment, since some adjacent circuit units share the same first initial connection block 41-1, the seventh connection electrodes 57 of some adjacent circuit units can be interconnected as a single structure. This ensures that the first electrodes of the first transistors T1 of some adjacent circuit units have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate. For example, the seventh connection electrodes 57 of the N+1th unit column and the seventh connection electrodes 57 of the N+2th unit column are interconnected as a single structure. Similarly, the seventh connection electrodes 57 of the N+3th unit column and the seventh connection electrodes 57 of the N+4th unit column are interconnected as a single structure.

[0234] In an exemplary embodiment, the eighth connection electrode 58 can be a strip extending along the first direction X. The first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer through a tenth via V10, and the second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 through a sixteenth via V16. In this exemplary embodiment, since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 enables the writing of the second initial signal transmitted by the second initial signal line 42 to the first electrode of the seventh transistor T7.

[0235] In an exemplary embodiment, the ninth connection electrode 59 can be a strip extending along the first direction X. The first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer via the eleventh via V11, and the second end of the ninth connection electrode 59 is connected to the third initial connection block 43-1 via the seventeenth via V17. In this exemplary embodiment, since the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 enables the writing of the third initial signal transmitted by the third initial signal line 43 to the first electrode of the eighth transistor T8.

[0236] In an exemplary embodiment, since some adjacent circuit units share the same third initial connection block 43-1, the ninth connection electrodes 59 of some adjacent circuit units can be interconnected as a single structure. This ensures that the first electrodes of the eighth transistors T8 of some adjacent circuit units have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate. For example, the ninth connection electrodes 59 of the Nth unit column and the N+1th unit column are interconnected as a single structure. Similarly, the ninth connection electrodes 59 of the N+2th unit column and the N+3th unit column are interconnected as a single structure.

[0237] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a seventh connection block 57-1. The seventh connection block 57-1 may be a strip shape extending along the second direction Y and connected to the seventh connection electrode 57. The seventh connection block 57-1 is configured to connect to a subsequently formed first initial connection line.

[0238] In an exemplary embodiment, the seventh connection block 57-1 may be disposed between some adjacent circuit units, and adjacent circuit units share the same seventh connection block 57-1. The seventh connection electrode 57 in the two circuit units and the shared seventh connection block 57-1 are an integral structure that is interconnected.

[0239] In an exemplary embodiment, the seventh connecting block 57-1 may be disposed between the (N-1)th cell column and the Nth cell column. Alternatively, the seventh connecting block 57-1 may be disposed between the N+3th cell column and the N+4th cell column. Yet another example is that the seventh connecting block 57-1 may be disposed between the N+7th cell column and the N+8th cell column.

[0240] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include an eighth connection block 58-1. The eighth connection block 58-1 may be shaped as a broken line extending along the second direction Y and connected to the eighth connection electrode 58. The eighth connection block 58-1 is configured to connect to a subsequently formed second initial connection line.

[0241] In an exemplary embodiment, the eighth connection blocks 58-1 of some adjacent circuit units can be interconnected, and the eighth connection electrodes 58 and the eighth connection blocks 58-1 in two circuit units are an integral structure interconnected. For example, the eighth connection blocks 58-1 can be disposed in the N+1th and N+2th unit columns. Alternatively, the eighth connection blocks 58-1 can be disposed in the N+5th and N+6th unit columns. Yet another example is that the eighth connection blocks 58-1 can be disposed in the N+9th and N+10th unit columns.

[0242] In an exemplary embodiment, the fifth conductive layer may further include multiple first traces. The shape of the first traces may be a straight line or a broken line extending along the first direction X, and may be located between the first scan signal line and the first initial signal line 41.

[0243] In an exemplary embodiment, at least one first trace may include a horizontal sub-trace and a first power trace 91. A first break K1 is provided between the horizontal sub-trace and the first power trace 91. The first break K1 can sever the horizontal sub-trace and the first power trace 91, so that the horizontal sub-trace and the first power trace 91 on both sides of the first break K1 are mutually insulated. For example, the first trace in the Mth unit row may include a second horizontal sub-trace 81-2 and a first power trace 91 arranged sequentially along the first direction X. As another example, the first trace in the M+1th unit row may include a fourth horizontal sub-trace 81-4 and a first power trace 91 arranged sequentially along the first direction X. As yet another example, the first trace in the M+2th unit row may include a sixth horizontal sub-trace 81-6 and a first power trace 91 arranged sequentially along the first direction X.

[0244] In an exemplary embodiment, at least one first trace may include one horizontal sub-trace and two first power traces 91. A first break K1 is provided between each of the two first power traces 91 and the horizontal sub-trace, and the first break K1 can sever the horizontal sub-trace from the first power trace 91. For example, the first trace in the M+5th cell row may include a first power trace 91, a first horizontal sub-trace 81-1, and a first power trace 91 arranged sequentially along the first direction X.

[0245] In an exemplary embodiment, at least one first trace may include two horizontal sub-traces and a first power trace 91. A first break K1 may be provided between the two horizontal sub-traces, which can sever the two horizontal sub-traces, making the two horizontal sub-traces on both sides of the first break K1 mutually insulated. The first break K1 is provided between the horizontal sub-traces and the first power trace 91, which can sever the horizontal sub-traces from the first power trace 91. For example, the first trace in the M+3rd unit row may include a seventh horizontal sub-traces 81-7, a fifth horizontal sub-traces 81-5, and a first power trace 91 arranged sequentially along the first direction X. As another example, the first trace in the M+4th unit row may include an eighth horizontal sub-traces 81-8, a third horizontal sub-traces 81-3, and a first power trace 91 arranged sequentially along the first direction X.

[0246] In an exemplary embodiment, the first horizontal sub-line 81-1 in the M+5th unit row and the second horizontal sub-line 81-2 in the Mth unit row can be referred to as the first first data connection line 81. One end of the two horizontal sub-lines can be connected together by a subsequently formed second vertical sub-line. The other end of the first horizontal sub-line 81-1 is configured to be connected to the subsequently formed first vertical sub-line, and the other end of the second horizontal sub-line 81-2 is configured to be connected to the subsequently formed data signal line.

[0247] In an exemplary embodiment, the third horizontal sub-line 81-3 in the M+4th unit row and the fourth horizontal sub-line 81-4 in the M+1th unit row can be referred to as the second first data connection line 81. One end of the two horizontal sub-lines can be connected together by a subsequently formed fourth vertical sub-line. The other end of the third horizontal sub-line 81-3 is configured to be connected to the subsequently formed third vertical sub-line, and the other end of the fourth horizontal sub-line 81-4 is configured to be connected to the subsequently formed data signal line.

[0248] In an exemplary embodiment, the fifth horizontal sub-line 81-5 in the M+3 unit row and the sixth horizontal sub-line 81-6 in the M+2 unit row can be referred to as the third first data connection line 81. One end of the two horizontal sub-lines can be connected together by the subsequently formed sixth vertical sub-line. The other end of the fifth horizontal sub-line 81-5 is configured to be connected to the subsequently formed fifth vertical sub-line, and the other end of the sixth horizontal sub-line 81-6 is configured to be connected to the subsequently formed data signal line.

[0249] In an exemplary embodiment, the seventh horizontal sub-line 81-7 in the M+3 unit row can be referred to as the fourth first data connection line 81. The first end of the seventh horizontal sub-line 81-7 is configured to connect with the subsequently formed seventh vertical sub-line, and the second end of the seventh horizontal sub-line 81-7 is configured to connect with the subsequently formed data signal line.

[0250] In an exemplary embodiment, the eighth horizontal sub-line 81-8 in the M+4th unit row can be referred to as the fifth first data connection line 81. The first end of the eighth horizontal sub-line 81-8 is configured to connect with the subsequently formed eighth vertical sub-line, and the second end of the eighth horizontal sub-line 81-8 is configured to connect with the subsequently formed data signal line.

[0251] In an exemplary embodiment, at least one circuit unit may further include a data transfer strip 83 and a first data connection block 84. The data transfer strip 83 may be a strip extending along the second direction Y, and the first data connection block 84 may be a block shape (such as a rectangle). The data transfer strip 83 and the first data connection block 84 may be disposed on the side of the horizontal sub-line near the second electrode plate 32. The first end of the data transfer strip 83 is connected to the side of the horizontal sub-line near the second electrode plate 32, and the second end of the data transfer strip 83 extends toward the second electrode plate 32 and is connected to the horizontal sub-line. The first data connection block 84 is configured to connect to the subsequently formed vertical sub-line.

[0252] In an exemplary embodiment, the data transfer strip 83 and the first data connection block 84 can be disposed between some adjacent circuit units in the first direction X. For example, in the Mth unit row, the data transfer strip 83 and the first data connection block 84 can be disposed between the Nth and N+1th unit columns, with the first data connection block 84 connected to the second horizontal sub-line 81-2 via the data transfer strip 83. As another example, in the M+1th unit row, the data transfer strip 83 and the first data connection block 84 can be disposed between the N+2th and N+3th unit columns, with the first data connection block 84 connected to the fourth horizontal sub-line 81-4 via the data transfer strip 83. Yet another example, in the M+2nd unit row, the data transfer strip 83 and the first data connection block 84 can be disposed between the N+4th and N+5th unit columns, with the first data connection block 84 connected to the sixth horizontal sub-line 81-6 via the data transfer strip 83. For example, in the M+3 cell row, the data transfer bar 83 and the first data connection block 84 can be positioned between the N+4 and N+5 cell columns, with the first data connection block 84 connected to the seventh horizontal sub-line 81-7 via the data transfer bar 83. Also, the data transfer bar 83 and the first data connection block 84 can be positioned between the N+6 and N+7 cell columns, with the first data connection block 84 connected to the fifth horizontal sub-line 81-5 via the data transfer bar 83. For example, in the M+4 cell row, the data transfer bar 83 and the first data connection block 84 can be positioned between the N+2 and N+3 cell columns, with the first data connection block 84 connected to the eighth horizontal sub-line 81-8 via the data transfer bar 83. Also, the data transfer bar 83 and the first data connection block 84 can be positioned between the N+8 and N+9 cell columns, with the first data connection block 84 connected to the third horizontal sub-line 81-3 via the data transfer bar 83. For example, in the M+5th cell row, the data transfer bar 83 and the first data connection block 84 can be set between the N+10th cell column and the N+11th cell column, and the first data connection block 84 is connected to the first horizontal sub-line 81-1 through the data transfer bar 83.

[0253] In an exemplary embodiment, in at least one circuit unit, the horizontal sub-line, the data transfer bar 83, and the first data connection block 84 can be an integral structure that is interconnected.

[0254] In an exemplary embodiment, at least one circuit unit may further include a second data connection block 85. The second data connection block 85 may be block-shaped (e.g., rectangular) and connected to a horizontal sub-line, and the second data connection block 85 is configured to connect to a subsequently formed vertical sub-line.

[0255] In an exemplary embodiment, the second data connection block 85 may be disposed between some adjacent circuit units in the first direction X. For example, no second data connection block 85 may be disposed in the row from the Mth unit to the (M+2)th unit. Alternatively, in the (M+3)th unit row, the second data connection block 85 may be disposed between the (N+4)th and (N+5)th unit columns and connected to the fifth horizontal sub-line 81-5. Yet another example is that in the (M+4)th unit row, the second data connection block 85 may be disposed between the (N+2)th and (N+3)th unit columns and connected to the third horizontal sub-line 81-3. And yet another example is that in the (M+5)th unit row, the second data connection block 85 may be disposed between the (N)th and (N+1)th unit columns and connected to the first horizontal sub-line 81-1.

[0256] In an exemplary embodiment, in at least one circuit unit, the lateral sub-line and the second data connection block 85 can be an integral structure that is interconnected.

[0257] In an exemplary embodiment, at least one cell row may contain only a first data connection block 84. For example, a horizontal sub-line (a second horizontal sub-line 81-2, a fourth horizontal sub-line 81-4, or a sixth horizontal sub-line 81-6) may be provided in the Mth cell row to the M+2th cell row, one end of which is connected to the first data connection block 84.

[0258] In an exemplary embodiment, at least one cell row may simultaneously include a first data connection block 84 and a second data connection block 85, with the first data connection block 84 and the second data connection block 85 respectively located at both ends of the horizontal sub-line in the first direction X. For example, the M+3 cell row may have two horizontal sub-lines (the fifth horizontal sub-line 81-5 and the seventh horizontal sub-line 81-7), and the M+4 cell row may have two horizontal sub-lines (the third horizontal sub-line 81-3 and the eighth horizontal sub-line 81-8). In each cell row, one end of one horizontal sub-line is connected to the first data connection block 84, and the two ends of the other horizontal sub-line are respectively connected to the first data connection block 84 and the second data connection block 85.

[0259] In an exemplary embodiment, the first data connection block 84 and the second data connection block 85 may be located on both sides of the second direction Y of the horizontal sub-line, respectively.

[0260] In an exemplary embodiment, the orthographic projection of at least one lateral sub-line on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 on the substrate, such that the second initial signal line 42 with a constant potential can effectively shield the influence of voltage jumps in the lateral sub-line on the pixel driving circuit.

[0261] In an exemplary embodiment, in at least one cell row, the first trace may consist of only the first power trace 91.

[0262] In an exemplary embodiment, at least one circuit unit may further include a first dummy electrode 86, which may be block-shaped (e.g., rectangular) and configured to connect to a subsequently formed vertical sub-line. In the first direction X, the first dummy electrode 86 may be disposed between some adjacent circuit units in the first direction X. In the second direction Y, the first dummy electrode 86 may be disposed on the side of the transverse sub-line near the second electrode plate 32.

[0263] In an exemplary embodiment, the position and connection structure of the first dummy electrode 86 in one circuit unit can be substantially the same as the position and connection structure of the first data connection block 84 in another circuit unit. The difference is that the first dummy electrode 86 is isolated and is neither connected to the lateral sub-line nor to other electrodes. In an exemplary embodiment, the morphology and connection structure of the first dummy electrode 86 are substantially the same as those of the first data connection block 84. This disclosure, through the design of the same transition area, not only improves the uniformity of subsequent etching processes but also ensures that different positions achieve the same display effect under transmitted and reflected light, achieving shadow elimination and effectively avoiding appearance defects and mura on the display substrate, thus improving display quality and display performance.

[0264] In an exemplary embodiment, at least one circuit unit may further include a second dummy electrode 87, which may be block-shaped (e.g., rectangular) and configured to connect to a subsequently formed vertical sub-line. In the first direction X, the second dummy electrode 87 may be disposed between some adjacent circuit units in the first direction X. In the second direction Y, the second dummy electrode 87 may be disposed on the side of the transverse sub-line away from the second electrode plate 32.

[0265] In an exemplary embodiment, the position and connection structure of the second dummy electrode 87 in one circuit unit can be substantially the same as the position and connection structure of the second data connection block 85 in another circuit unit. The difference is that the second dummy electrode 87 is isolated and is neither connected to the lateral sub-line nor to other electrodes. In an exemplary embodiment, the morphology and connection structure of the second dummy electrode 87 are substantially the same as those of the second data connection block 85. This disclosure, through the design of the same transition area, not only improves the uniformity of subsequent etching processes but also ensures that different positions achieve the same display effect under transmitted and reflected light, achieving shadow elimination and effectively avoiding appearance defects and mura on the display substrate, thereby improving display quality and display performance.

[0266] In an exemplary embodiment, the first dummy electrode 86 and the second dummy electrode 87 may be located on opposite sides of the second direction Y of the transverse sub-line, respectively, relative to a transverse sub-line.

[0267] (8) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, patterning the first planarization film using a patterning process to form a first planarization layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planarization layer, such as... Figure 16 As shown.

[0268] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0269] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the third connection electrode 53 on the substrate. The first planarization layer within the 21st via V21 is etched away, exposing the surface of the third connection electrode 53. The 21st via V21 is configured to allow subsequently formed data signal lines to be connected to the third connection electrode 53 through the via.

[0270] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the power connection block 54-1 of the fourth connection electrode 54 on the substrate. The first planarization layer within the 22nd via V22 is etched away, exposing the surface of the power connection block 54-1. The 22nd via V22 is configured to allow the subsequently formed first power line to be connected to the power connection block 54-1 through the via.

[0271] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the 6th connecting electrode 56 on the substrate. The first planarization layer within the 23rd via V23 is etched away, exposing the surface of the 6th connecting electrode 56. The 23rd via V23 is configured to allow a subsequently formed anode connecting electrode to be connected to the 6th connecting electrode 56 through the via.

[0272] In an exemplary embodiment, at least one circuit unit may further include a twenty-fourth via V24. The orthographic projection of the twenty-fourth via V24 onto the substrate lies within the range of the orthographic projection of the seventh connecting block 57-1 onto the substrate. The first planarization layer within the twenty-fourth via V24 is etched away, exposing the surface of the seventh connecting block 57-1. The twenty-fourth via V24 is configured to allow a subsequently formed first initial connection line to be connected to the seventh connecting block 57-1 through the via.

[0273] In an exemplary embodiment, the 24th via V24 may be disposed between some adjacent circuit cells. For example, the 24th via V24 may be disposed between the N+3rd cell column and the N+4th cell column. Alternatively, the 24th via V24 may be disposed between the N+7th cell column and the N+8th cell column.

[0274] In an exemplary embodiment, at least one circuit unit may further include a twenty-fifth via V25. The orthographic projection of the twenty-fifth via V25 onto the substrate lies within the range of the orthographic projection of the eighth connecting block 58-1 onto the substrate. The first planarization layer within the twenty-fifth via V25 is etched away, exposing the surface of the eighth connecting block 58-1. The twenty-fifth via V25 is configured to allow a subsequently formed second initial connection line to be connected to the eighth connecting block 58-1 through the via.

[0275] In an exemplary embodiment, the 25th via V25 can be disposed between some adjacent circuit cells. For example, the 25th via V25 can be disposed between the (N+1)th cell column and the (N+2)th cell column. Alternatively, the 25th via V25 can be disposed between the (N+5)th cell column and the (N+6)th cell column. Yet another example is that the 25th via V25 can be disposed between the (N+9)th cell column and the (N+10)th cell column.

[0276] In an exemplary embodiment, at least one circuit unit may further include a second sixteenth via V26. The orthographic projection of the second sixteenth via V26 onto the substrate lies within the range of the orthographic projection of the first data connection block 84 onto the substrate. The first planarization layer within the second sixteenth via V26 is etched away, exposing the surface of the first data connection block 84. The second sixteenth via V26 is configured to allow subsequently formed vertical sub-lines to be connected to the first data connection block 84 through the via.

[0277] In an exemplary embodiment, at least one circuit unit may further include a twenty-seventh via V27. The orthographic projection of the twenty-seventh via V27 onto the substrate lies within the range of the orthographic projection of the second data connection block 85 onto the substrate. The first planarization layer within the twenty-seventh via V27 is etched away, exposing the surface of the second data connection block 85. The twenty-seventh via V27 is configured to allow subsequently formed vertical sub-lines to be connected to the second data connection block 85 through the via.

[0278] In an exemplary embodiment, at least one circuit unit may further include a second eighteenth via V28. The orthographic projection of the second eighteenth via V28 onto the substrate lies within the range of the orthographic projection of the first dummy electrode 86 onto the substrate. The first planarization layer within the second eighteenth via V28 is etched away, exposing the surface of the first dummy electrode 86. The second eighteenth via V28 is configured to allow subsequently formed vertical sub-lines to connect to the first dummy electrode 86 through the via.

[0279] In an exemplary embodiment, at least one circuit unit may further include a second nineteenth via V29. The orthographic projection of the second nineteenth via V29 onto the substrate lies within the range of the orthographic projection of the second dummy electrode 87 onto the substrate. The first planarization layer within the second nineteenth via V29 is etched away, exposing the surface of the second dummy electrode 87. The second nineteenth via V29 is configured to allow subsequently formed vertical sub-lines to connect to the second dummy electrode 87 through the via.

[0280] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first planarization layer, such as... Figure 17A and Figure 17B As shown, Figure 17B for Figure 17A A planar schematic diagram of the fifth conductive layer. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0281] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least: a first power line 71, a data signal line 72, and an anode connection electrode 73.

[0282] In an exemplary embodiment, the shape of the first power line 71 can be a straight line or a broken line extending along the second direction Y. The first power line 71 is connected to the power connection block 54-1 through the twenty-second via V32. Since the power connection block 54-1 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is connected to the first region of the fifth active layer and the second plate 32 of the storage capacitor, the first power line 71 writes the first power signal into the fifth transistor T5 and the second plate 32 of the storage capacitor.

[0283] In an exemplary embodiment, the first power line 71 can be a non-uniform width polygonal line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.

[0284] In an exemplary embodiment, a power shielding block 74 may be disposed on the first power line 71. The power shielding block 74 may be block-shaped (e.g., rectangular), and may be disposed on the side of the first power line 71 near the second transistor T2 and connected to the first power line 71. The orthographic projection of the power shielding block 74 on the substrate at least partially overlaps with the orthographic projection of the second active layer of the second transistor T2 on the substrate. In an exemplary embodiment, the power shielding block 74 can block the second active layer, preventing the light emitted by the light-emitting device and the reflected light from the film layer from illuminating the oxide second transistor T2, thus preventing the oxide transistor from experiencing characteristic drift due to light exposure and improving the electrical characteristics of the oxide transistor.

[0285] In an exemplary embodiment, the orthographic projections of the first power line 71 and the power shield 74 on the substrate at least partially overlap with the orthographic projection of the first connecting electrode 51 on the substrate. Therefore, the first power line 71 and the power shield 74, which have a constant potential, can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby avoiding the influence of data voltage jumps and other signals on the potential of the first node N1 and improving the driving performance of the pixel driving circuit.

[0286] In an exemplary embodiment, in at least one circuit unit, the first power line 71 and the power shield block 74 can be an integral structure that is interconnected.

[0287] In an exemplary embodiment, the data signal line 72 can be a straight line or a broken line extending along the second direction Y. The data signal line 72 is connected to the third connection electrode 53 through the twenty-first via V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via, the connection between the data signal line 72 and the first electrode of the fourth transistor T4 is realized, and the data signal line 72 can write data signals to the first electrode of the fourth transistor T4.

[0288] In an exemplary embodiment, the anode connection electrode 73 can be a strip shape extending along the second direction Y. The anode connection electrode 73 is connected to the sixth connection electrode 56 through the twenty-third via V23, and the anode connection electrode 73 is configured to connect with the subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through the via, the connection between the subsequently formed anode and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 can be realized, and the pixel driving circuit can drive the light-emitting device to emit light.

[0289] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a first initial connection line 61. The shape of the first initial connection line 61 may be a straight line or a broken line extending along the second direction Y. The first initial connection line 61 is connected to the seventh connection block 57-1 through the twenty-fourth via V24. Since the seventh connection block 57-1 is connected to the seventh connection electrode 57, and the seventh connection electrode 57 is connected to the first initial signal line 41, the interconnection between the first initial signal line 41 extending along the first direction X and the first initial connection line 61 extending along the second direction Y is realized. The first initial signal line 41 and the first initial connection line 61 form a mesh-like interconnected structure for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improves display uniformity, and enhances display quality.

[0290] In an exemplary embodiment, the first initial connection line 61 may be disposed between two first power lines 71 in a portion of adjacent cell columns, and four first power lines 71 may be disposed between two adjacent first initial connection lines 61 in the first direction X. For example, the first initial connection line 61 may be disposed between the first power line 71 in the N+3 cell column and the first power line 71 in the N+4 cell column. As another example, the first initial connection line 61 may be disposed between the first power line 71 in the N+7 cell column and the first power line 71 in the N+8 cell column.

[0291] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second initial connection line 62. The shape of the second initial connection line 62 may be a straight line or a broken line extending along the second direction Y. The second initial connection line 62 is connected to the eighth connection block 58-1 through the twenty-fifth via V25. Since the eighth connection block 58-1 is connected to the eighth connection electrode 58, and the eighth connection electrode 58 is connected to the second initial signal line 42, the interconnection between the second initial signal line 42 extending along the first direction X and the second initial connection line 62 extending along the second direction Y is realized. The second initial signal line 42 and the second initial connection line 62 form a mesh-like interconnected structure for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial signal line and the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, effectively improves display uniformity, and enhances display quality.

[0292] In an exemplary embodiment, the second initial connection line 62 may be disposed between two first power lines 71 in a portion of adjacent cell columns, and four first power lines 71 may be disposed between two adjacent second initial connection lines 62 in the first direction X. For example, the second initial connection line 62 may be disposed between the first power line 71 in the (N+1)th cell column and the first power line 71 in the (N+2)th cell column. Another example is that the second initial connection line 62 may be disposed between the first power line 71 in the (N+5)th cell column and the first power line 71 in the (N+6)th cell column. Yet another example is that the second initial connection line 62 may be disposed between the first power line 71 in the (N+9)th cell column and the first power line 71 in the (N+10)th cell column.

[0293] In an exemplary embodiment, in the first direction X, the first initial connecting line 61 and the second initial connecting line 62 can be alternately arranged. A second initial connecting line 62 can be arranged between adjacent first initial connecting lines 61 in the first direction X, and a first initial connecting line 61 can be arranged between adjacent second initial connecting lines 62 in the first direction X.

[0294] In some possible implementations, the fifth conductive layer of at least one circuit unit may further include a third initial connection line extending along the second direction Y of the main body portion. The third initial connection line may be connected to a third initial signal line through a via to form a mesh-like mesh-like interconnected structure for transmitting the third initial signal. This disclosure does not limit the scope of the invention.

[0295] In an exemplary embodiment, the fifth conductive layer may further include multiple second traces. The shape of the second traces may be a straight line or a broken line extending along the second direction Y of the main body. They may be located between two data signal lines 72 in some adjacent cell columns. Two first power lines 71 and two data signal lines 72 may be disposed between two adjacent second traces in the first direction X. For example, the second traces may be located between the data signal lines 72 of the Nth cell column and the data signal lines 72 of the (N+1)th cell column. Another example is that the second traces may be located between the data signal lines 72 of the (N+2)th cell column and the data signal lines 72 of the (N+3)th cell column. Yet another example is that the second traces may be located between the data signal lines 72 of the (N+4)th cell column and the data signal lines 72 of the (N+5)th cell column.

[0296] In an exemplary embodiment, at least one second trace may include a vertical sub-trace and a second power trace 92. A second break K2 may be provided between the vertical sub-trace and the second power trace 92. The second break K2 can sever the vertical sub-trace and the second power trace 92, so that the vertical sub-trace and the second power trace 92 on both sides of the second break K2 are insulated from each other. For example, the second trace located between the N+6th and N+7th unit columns may include a second power trace 92 and a fifth vertical sub-trace 82-5 arranged sequentially along the second direction Y. As another example, the second trace located between the N+8th and N+9th unit columns may include a second power trace 92 and a third vertical sub-trace 82-3 arranged sequentially along the second direction Y. As yet another example, the second trace located between the N+10th and N+11th unit columns may include a second power trace 92 and a first vertical sub-trace 82-1 arranged sequentially along the second direction Y.

[0297] In an exemplary embodiment, at least one second trace may include one vertical sub-line and two second power traces 92. A second break K2 is provided between each of the two second power traces 92 and the vertical sub-line, allowing the vertical sub-line and the second power trace 92 to be severed. For example, the second trace located between the Nth and N+1th unit columns may include a second power trace 92, a second vertical sub-line 82-2, and a second power trace 92 arranged sequentially along the second direction Y.

[0298] In an exemplary embodiment, at least one second trace may include two vertical sub-traces and a second power trace 92. A second break K2 may be provided between the two vertical sub-traces, which can cut off the two vertical sub-traces, making the two vertical sub-traces on both sides of the second break K2 mutually insulated. The second break K2 is provided between the vertical sub-traces and the second power trace 92, and the second break K2 can cut off the vertical sub-traces from the second power trace 92. For example, the second trace located between the N+2nd and N+3rd unit columns may include a second power trace 92, a fourth vertical sub-traces 82-4, and an eighth vertical sub-traces 82-8 arranged sequentially along the second direction Y. As another example, the second trace located between the N+4th and N+5th unit columns may include a second power trace 92, a sixth vertical sub-traces 82-6, and a seventh vertical sub-traces 82-7 arranged sequentially along the second direction Y.

[0299] In an exemplary embodiment, at least one vertical sub-line is configured to extend to the binding area and connect to the data lead-out line at one end, and the other end is connected to the first data connection block 84 through the twenty-sixth via V26, thus realizing the interconnection between a vertical sub-line and a horizontal sub-line.

[0300] In an exemplary embodiment, at least one vertical sub-line is connected at one end to the second data connection block 85 through the twenty-seventh via V27, and at the other end to the first data connection block 84 through the twenty-sixth via V26, thus realizing the interconnection between one vertical sub-line and two horizontal sub-lines.

[0301] In an exemplary embodiment, at least one vertical sub-line is also connected to the first dummy electrode 86 through the twenty-eighth via V28, so that each position of the display substrate presents the same morphology and connection structure.

[0302] In an exemplary embodiment, at least one vertical sub-line is also connected to the second dummy electrode 87 through the twenty-ninth via V29, so that each position of the display substrate presents the same morphology and connection structure.

[0303] In an exemplary embodiment, the first vertical sub-line 82-1 between the N+10th and N+11th unit columns and the second vertical sub-line 82-2 between the Nth and N+1th unit columns can be referred to as the first second data connection line 82. The first vertical sub-line 82-1 is connected to the first horizontal sub-line 81-1, and the second vertical sub-line 82-2 is connected to the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2, respectively.

[0304] In an exemplary embodiment, the third vertical sub-line 82-3 between the N+8th and N+9th unit columns and the fourth vertical sub-line 82-4 between the N+2th and N+3th unit columns can be referred to as the second second data connection line 82. The third vertical sub-line 82-3 is connected to the third horizontal sub-line 81-3, and the fourth vertical sub-line 82-4 is connected to both the third horizontal sub-line 81-3 and the fourth horizontal sub-line 81-4.

[0305] In an exemplary embodiment, the fifth vertical sub-line 82-5 between the N+6th and N+7th unit columns and the sixth vertical sub-line 82-6 between the N+4th and N+5th unit columns can be referred to as the third second data connection line 82. The fifth vertical sub-line 82-5 is connected to the fifth horizontal sub-line 81-5, and the sixth vertical sub-line 82-6 is connected to both the fifth horizontal sub-line 81-5 and the sixth horizontal sub-line 81-6.

[0306] In an exemplary embodiment, the seventh vertical sub-line 82-7 between the N+4th and N+5th unit columns can be referred to as the fourth second data connection line 82, and the seventh vertical sub-line 82-7 is connected to the seventh horizontal sub-line 81-7.

[0307] In an exemplary embodiment, the eighth vertical sub-line 82-8 between the N+2nd and N+3rd unit columns can be referred to as the fifth second data connection line 82, and the eighth vertical sub-line 82-8 is connected to the eighth horizontal sub-line 81-8.

[0308] Figure 17C This is a schematic diagram illustrating the connection between horizontal and vertical sub-lines in an exemplary embodiment of this disclosure. Figure 17A , Figure 17B and Figure 17C As shown, multiple data connection lines may include at least a first data connection line 80A, a second data connection line 80B, a third data connection line 80C, a fourth data connection line 80D, and a fifth data connection line 80E.

[0309] In an exemplary embodiment, the first data connection line 80A may include at least a first data connection line and a first second data connection line. The first data connection line may include at least a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2. The first second data connection line may include at least a first vertical sub-line 82-1 and a second vertical sub-line 82-2. The first horizontal sub-line 81-1 may be located in the (M+5)th cell row, the second horizontal sub-line 81-2 may be located in the (M)th cell row, the first vertical sub-line 82-1 may be located between the (N+10)th and (N+11)th cell columns, and the second vertical sub-line 82-2 may be located between the (N)th and (N+1)th cell columns.

[0310] In an exemplary embodiment, the first end of the first vertical sub-line 82-1 is connected to a data lead-out line in the binding area. The second end of the first vertical sub-line 82-1 extends in the opposite direction of the second direction Y and is connected to the first end of the first horizontal sub-line 81-1 via the first data connection block 84. The second end of the first horizontal sub-line 81-1 extends in the first direction X or in the opposite direction of the first direction X and is connected to the first end of the second vertical sub-line 82-2 via the second data connection block 85. The second end of the second vertical sub-line 82-2 extends in the opposite direction of the second direction Y and is connected to the first end of the second horizontal sub-line 81-2 via the first data connection block 84. The second end of the second horizontal sub-line 81-2 extends in the first direction X or in the opposite direction of the first direction X and is connected to a data signal line.

[0311] In an exemplary embodiment, the second data connection line 80B may include at least a second first data connection line and a second second data connection line. The second first data connection line may include at least a third horizontal sub-line 81-3 and a fourth horizontal sub-line 81-4. The second second data connection line may include at least a third vertical sub-line 82-3 and a fourth vertical sub-line 82-4. The first horizontal sub-line 81-1 may be located in the M+4th cell row, the fourth horizontal sub-line 81-4 may be located in the M+1th cell row, the third vertical sub-line 82-3 may be located between the N+8th and N+9th cell columns, and the fourth vertical sub-line 82-4 may be located between the N+2th and N+3th cell columns.

[0312] In an exemplary embodiment, the first end of the third vertical sub-line 82-3 is connected to another data lead-out line in the binding area. The second end of the third vertical sub-line 82-3 extends in the opposite direction of the second direction Y and is connected to the first end of the third horizontal sub-line 81-3 via the first data connection block 84. The second end of the third horizontal sub-line 81-3 extends in the first direction X or in the opposite direction of the first direction X and is connected to the first end of the fourth vertical sub-line 82-4 via the second data connection block 85. The second end of the fourth vertical sub-line 82-4 extends in the opposite direction of the second direction Y and is connected to the first end of the fourth horizontal sub-line 81-4 via the first data connection block 84. The second end of the fourth horizontal sub-line 81-4 extends in the first direction X or in the opposite direction of the first direction X and is connected to another data signal line.

[0313] In an exemplary embodiment, the third data connection line 80C may include at least a third first data connection line and a third second data connection line. The third first data connection line may include at least a fifth horizontal sub-line 81-5 and a sixth horizontal sub-line 81-6. The third second data connection line may include at least a fifth vertical sub-line 82-5 and a sixth vertical sub-line 82-6. The fifth horizontal sub-line 81-5 may be located in the M+3rd cell row, the sixth horizontal sub-line 81-6 may be located in the M+2nd cell row, the fifth vertical sub-line 82-5 may be located between the N+6th and N+7th cell columns, and the sixth vertical sub-line 82-6 may be located between the N+4th and N+5th cell columns.

[0314] In an exemplary embodiment, the first end of the fifth vertical sub-line 82-5 is connected to another data lead-out line in the binding area. The second end of the fifth vertical sub-line 82-5 extends in the opposite direction of the second direction Y and is connected to the first end of the fifth horizontal sub-line 81-5 via the first data connection block 84. The second end of the fifth horizontal sub-line 81-5 extends in the first direction X or in the opposite direction of the first direction X and is connected to the first end of the sixth vertical sub-line 82-6 via the second data connection block 85. The second end of the sixth vertical sub-line 82-6 extends in the opposite direction of the second direction Y and is connected to the first end of the sixth horizontal sub-line 81-6 via the first data connection block 84. The second end of the sixth horizontal sub-line 81-6 extends in the first direction X or in the opposite direction of the first direction X and is connected to another data signal line.

[0315] In an exemplary embodiment, the fourth data connection line 80D may include at least a fourth first data connection line and a fourth second data connection line. The fourth first data connection line may include at least a seventh horizontal sub-line 81-7, and the fourth second data connection line may include at least a seventh vertical sub-line 82-7. The seventh horizontal sub-line 81-7 may be located in the M+3rd cell row, and the seventh vertical sub-line 82-7 may be located between the N+4th cell column and the N+5th cell column.

[0316] In an exemplary embodiment, the first end of the seventh vertical sub-line 82-7 is connected to another data lead-out line in the binding area. The second end of the seventh vertical sub-line 82-7 extends in the opposite direction of the second direction Y and is connected to the seventh horizontal sub-line 81-7 through the first data connection block 84. The second end of the seventh horizontal sub-line 81-7 extends in the first direction X or the opposite direction of the first direction X and is connected to another data signal line.

[0317] In an exemplary embodiment, the fifth data connection line 80E may include at least a fifth first data connection line and a fifth second data connection line. The fifth first data connection line may include at least an eighth horizontal sub-line 81-8, and the fifth second data connection line may include at least an eighth vertical sub-line 82-8. The eighth horizontal sub-line 81-8 may be located in the M+4th cell row, and the eighth vertical sub-line 82-8 may be located between the N+2th cell column and the N+3th cell column.

[0318] In an exemplary embodiment, the first end of the eighth vertical sub-line 82-8 is connected to another data lead-out line in the binding area, and the second end of the eighth vertical sub-line 82-8 extends in the opposite direction of the second direction Y and is connected to the eighth horizontal sub-line 81-8 through the first data connection block 84. The second end of the eighth horizontal sub-line 81-8 extends in the first direction X or the opposite direction of the first direction X and is connected to another data signal line.

[0319] In an exemplary embodiment, the first power line 91 and the second power line 92 can be interconnected to form a mesh-like interconnected structure, which is not limited herein.

[0320] In an exemplary embodiment, the first power trace 91 and the second power trace 92 can be connected to the power lead transmitting the second power signal through the bezel area or the bonding area, realizing that the second power line is located in the panel (VSS inPanel, or SIP) structure. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, achieving low power consumption, but also effectively improves the uniformity of the second power signal in the display substrate, thus improving display uniformity, display quality, and display performance. Furthermore, it can significantly reduce the width of the bezel power lead, greatly reducing the bezel width, increasing the screen-to-body ratio, and facilitating the realization of full-screen display.

[0321] In an exemplary embodiment, the first power line 71 of an adjacent cell column may be mirror-symmetrical with respect to the column boundary line, and the data signal line 72 of an adjacent cell column may be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the shapes of the first power line 71 and the data signal line 72 in multiple cell rows may be substantially the same.

[0322] In an exemplary embodiment, the orthographic projection of at least one second trace on the substrate at least partially overlaps with the orthographic projection of the column boundary line on the substrate.

[0323] In an exemplary embodiment, in the first direction X, a second trace and two data signal lines 72 can be disposed between two first power lines 71 in adjacent cell columns. The two first power lines 71 can be mirror-symmetrical with respect to the second trace, and the two data signal lines 72 can be mirror-symmetrical with respect to the second trace.

[0324] In an exemplary embodiment, in the first direction X, two first power lines 71 and two data signal lines 72 can be arranged between adjacent second traces, and the two second traces can be mirror-symmetrical with respect to the column boundary line.

[0325] (10) Forming a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, patterning the second planarization film using a patterning process to form a second planarization layer covering the fifth conductive layer pattern, wherein a plurality of anode vias V30 are provided on the second planarization layer, such as... Figure 18 As shown.

[0326] In an exemplary embodiment, the orthographic projection of the anode via V30 of each circuit unit onto the substrate is within the range of the orthographic projection of the anode connection electrode 73 onto the substrate. The second planarization layer within the anode via V30 is removed, exposing the surface of the anode connection electrode 73. The anode via V30 is configured to allow a subsequently formed anode to be connected to the anode connection electrode 73 through the via.

[0327] At this point, the driving circuit layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, as well as a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light emission signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0328] In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planarization layer, a fifth conductive layer, and a second planarization layer, sequentially disposed on the substrate. The first semiconductor layer may include at least a first transistor and an active layer of a third to an eighth transistor. The first conductive layer may include at least a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, and a first electrode of a storage capacitor. The second conductive layer may include at least a first initial signal line and a second electrode of a storage capacitor. The second semiconductor layer may include at least a second transistor active layer. The third conductive layer may include at least a second initial signal line, a third initial signal line, and a fourth scan signal line. The fourth conductive layer may include at least a first data connection line and multiple connection electrodes. The fifth conductive layer may include at least a first power line, a data signal line, a first initial signal line, a second initial signal line, and a second data connection line.

[0329] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0330] In an exemplary embodiment, the first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the aforementioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, fifth, and sixth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first and second planarization layers can be made of organic materials, such as resins.

[0331] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit cells within a cell row can be substantially mirror-symmetric with respect to a column boundary line, which is a straight line located between two adjacent circuit cells and extending along a second direction Y. For example, the pixel driving circuits in the Nth cell column and the (N+1)th cell column can be mirror-symmetric with respect to the column boundary line. Similarly, the pixel driving circuits in the (N+1)th cell column and the (N+2)th cell column can be mirror-symmetric with respect to the column boundary line.

[0332] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units can be substantially mirror-symmetrical with respect to the column boundary line, including any one or more of the following: the first semiconductor layer in two adjacent circuit units in a cell row can be mirror-symmetrical with respect to the column boundary line; the first conductive layer in two adjacent circuit units in a cell row can be mirror-symmetrical with respect to the column boundary line; the second conductive layer in two adjacent circuit units in a cell row can be mirror-symmetrical with respect to the column boundary line; the second semiconductor layer in two adjacent circuit units in a cell row can be mirror-symmetrical with respect to the column boundary line; the third conductive layer in two adjacent circuit units in a cell row can be mirror-symmetrical with respect to the column boundary line; the fourth conductive layer (excluding the first trace and data transition strip) in two adjacent circuit units in a cell row can be mirror-symmetrical with respect to the column boundary line; and the fifth conductive layer (excluding the second trace and anode connection electrode) in two adjacent circuit units in a cell row can be mirror-symmetrical with respect to the column boundary line.

[0333] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer can be fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0334] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer disposed on a second planarization layer. The anode conductive layer includes at least a plurality of anode patterns, such as... Figure 19A and Figure 19B As shown, Figure 19B for Figure 19A A planar schematic diagram of the anode conductive layer.

[0335] In an exemplary embodiment, the plurality of anode patterns may include a first anode 90A located in a red light-emitting unit that emits red light, a second anode 90B located in a blue light-emitting unit that emits blue light, a third anode 90C located in a first green light-emitting unit that emits green light, and a fourth anode 90D located in a second green light-emitting unit that emits green light. The first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may be connected to the anode connection electrode 73 of the circuit unit through the anode via V30, respectively.

[0336] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may include an anode body portion and an anode connecting portion that are connected to each other. The shape of the anode body portion may be rhomboid, and the rectangular corners may be provided with rounded chamfers. The shape of the anode connecting portion may be strip-shaped. The first end of the anode connecting portion is connected to the anode body portion, and the second end of the anode connecting portion extends away from the anode body portion and is connected to the anode connecting electrode 73 through the anode through-hole V30.

[0337] In an exemplary embodiment, the orthographic projections of the first anode 90A, the third anode 90C, and the fourth anode 90D onto the substrate do not overlap with the orthographic projections of the twenty-sixth via V26 (or the twenty-eighth via V28) onto the substrate.

[0338] In an exemplary embodiment, the orthographic projections of the first anode 90A, the third anode 90C, and the fourth anode 90D onto the substrate do not overlap with the orthographic projections of the twenty-seventh via V27 (or the twenty-ninth via V29) onto the substrate.

[0339] In an exemplary embodiment, the orthographic projections of the first anode 90A, the third anode 90C, and the fourth anode 90D onto the substrate do not overlap with the orthographic projections of the first data connection block 84 (or the first dummy electrode 86) and the second data connection block 85 (or the second dummy electrode 87) onto the substrate.

[0340] In an exemplary embodiment, the orthographic projection of the second anode 90B onto the substrate at least partially overlaps with the orthographic projection of the twenty-sixth via V26 (or the twenty-eighth via V28) onto the substrate.

[0341] In an exemplary embodiment, the orthographic projection of the second anode 90B onto the substrate at least partially overlaps with the orthographic projection of the twenty-seventh via V27 (or the twenty-ninth via V29) onto the substrate.

[0342] In an exemplary embodiment, the orthographic projection of the second anode 90B onto the substrate at least partially overlaps with the orthographic projections of the twenty-sixth via V26 (or the twenty-eighth via V28) and the twenty-seventh via V27 (or the twenty-ninth via V29) onto the substrate.

[0343] In an exemplary embodiment, the second anode 90B may have an anode centerline, which may be a broken line extending along the first direction X, passing through the geometric center of the anode body of the second anode. The twenty-sixth via V26 (or the twenty-eighth via V28) may be located on one side of the anode centerline in the second direction Y, and the twenty-seventh via V27 (or the twenty-ninth via V29) may be located on the opposite side of the anode centerline in the second direction Y, that is, the twenty-sixth via V26 (or the twenty-eighth via V28) and the twenty-seventh via V27 (or the twenty-ninth via V29) may be disposed vertically relative to the anode centerline.

[0344] In an exemplary embodiment, in the second direction Y, the geometric center of the 26th via V26 (or the 28th via V28) has a first distance from the anode centerline, and the geometric center of the 27th via V27 (or the 29th via V29) has a second distance from the anode centerline. The anode centerline may be a broken line that passes through the geometric center of the anode body of the second anode and extends along the first direction X.

[0345] In an exemplary embodiment, the ratio of the first distance to the second distance can be approximately 0.9 to 1.1, meaning that the twenty-sixth via V26 (or the twenty-eighth via V28) and the twenty-seventh via V27 (or the twenty-ninth via V29) can correspond vertically to the anode centerline.

[0346] In an exemplary embodiment, the ratio of the first distance to the second distance can be approximately 1.0.

[0347] In an exemplary embodiment, the anode conductive layer can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can be a multi-layer composite structure, such as ITO / Ag / ITO.

[0348] In an exemplary embodiment, the subsequent fabrication process may include: first, forming a pixel definition layer with multiple pixel openings, which expose a first anode, a second anode, a third anode, and a fourth anode, respectively. Then, an organic light-emitting layer is formed using vapor deposition or inkjet printing. Next, a cathode is formed on the organic light-emitting layer, followed by the formation of an encapsulation structure layer. This encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is positioned between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0349] An exemplary embodiment of this disclosure provides a display substrate that effectively reduces the difference in the number of data connection line coupling unit columns in different unit rows by splitting a long first data connection line into two horizontal sub-lines and arranging the two horizontal sub-lines in different unit rows. This can effectively reduce or even eliminate the appearance of diagonal watermarks at the two corners of the display area near the bonding area.

[0350] In an exemplary implementation, to Figure 6 Taking a first data connection line 81 that is far from the binding area as an example, this disclosure splits the first data connection line into a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2. Although Figure 6 The number of unit columns coupled by the first data connection line 81 is basically the same as the sum of the number of unit columns coupled by the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 of this disclosure. However, since the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 of this disclosure are set in different unit rows, the number of unit columns coupled in the unit row where the first horizontal sub-line 81-1 is located is less, and the number of unit columns coupled in the unit row where the second horizontal sub-line 81-2 is located is less. Moreover, the number of unit columns coupled by the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 is similar, thus effectively reducing the difference in the number of data connection line coupled unit columns in different unit rows.

[0351] In an exemplary implementation, to Figure 6 Taking the first data connection line 81, which is relatively close to the binding area, as an example, although Figure 6 The first data connection line has a relatively short extension length and is coupled with fewer cell columns. However, since this disclosure splits other first data connection lines into two horizontal sub-lines, the cell row where the first data connection line is located is provided with horizontal sub-lines of other data connection lines. This increases the number of cell columns coupled by data connection lines in the cell row and makes it similar to the number of cell columns coupled by data connection lines in other cell rows. Therefore, it effectively reduces the difference in the number of cell columns coupled by data connection lines in different cell rows.

[0352] Compare Figure 6 As can be seen from the first region 110 of this disclosure, by splitting the long first data connection line into two horizontal sub-lines and the long second data connection line into two vertical sub-lines, this disclosure effectively reduces the area of ​​the first region (FIP region), which is beneficial to increasing the number of power supply traces, reducing the power signal voltage drop, effectively improving display uniformity, and enhancing display quality and display performance.

[0353] This embodiment of the disclosure achieves an FIP structure by setting data connection lines within the display area and connecting the data lead-out lines of the binding area to the data signal lines through the data connection lines. This eliminates the need for fan-shaped diagonal lines in the lead-out line area, effectively reducing the length of the lead-out line area, greatly reducing the width of the bottom bezel, increasing the screen ratio, and facilitating the realization of full-screen display.

[0354] This embodiment of the disclosure achieves a SIP structure by setting a first power line and a second power line within the display area. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, thus achieving low power consumption and improving the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality, and display performance, but also significantly reduces the width of the bezel power leads, greatly reducing the bezel width, increasing the screen-to-body ratio, and facilitating the realization of full-screen display.

[0355] This embodiment of the present disclosure provides a first initial connection line and a second initial connection line within the display area. The first initial connection line and the first initial signal line form a mesh-like interconnected structure, and the second initial connection line and the second initial signal line also form a mesh-like interconnected structure. This not only effectively reduces the resistance of the initial signal lines and decreases the voltage drop of the initial signals, but also effectively improves the uniformity of the initial signals in the display substrate, thereby improving display uniformity and display quality.

[0356] This embodiment of the present disclosure sets up a first dummy electrode and a second dummy electrode. The morphology and connection structure of the first dummy electrode are substantially the same as those of the first data connection block, and the morphology and connection structure of the second dummy electrode are substantially the same as those of the second data connection block. This makes the display area have substantially the same transition area structure, improves the uniformity of the etching process, and enables different areas to achieve the same display effect under transmitted and reflected light. This achieves shadow elimination, effectively avoids appearance defects of the display substrate and the occurrence of screen-off watermarks, and improves display quality.

[0357] This embodiment of the invention provides a second anode that covers the first flat layer via a transition via, and the two transition vias are positioned vertically relative to the anode centerline, thereby giving the anode good flatness and effectively improving color shift.

[0358] The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0359] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0360] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0361] This disclosure also provides a method for fabricating a display substrate to produce the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a display area and a bonding area disposed on one side of the display area. The display area includes a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, and at least one circuit unit includes a pixel driving circuit. The fabrication method may include:

[0362] Multiple data signal lines and multiple data connection lines are formed in the display area, and multiple data lead-out lines are formed in the bonding area. The data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines through the data connection lines. At least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction. The two horizontal sub-lines are arranged in different cell rows, and the two vertical sub-lines are arranged in different cell columns. The first direction and the second direction intersect.

[0363] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, characterized in that, The device includes a display area and a binding area disposed on one side of the display area. The display area includes multiple circuit units forming multiple cell rows and multiple cell columns. At least one circuit unit includes a pixel driving circuit. The binding area includes at least multiple data lead-out lines. The display area also includes multiple data signal lines and multiple data connection lines. The data signal lines are configured to provide data signals to the pixel driving circuit. The data signal lines are connected to the data lead-out lines through the data connection lines. At least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction. The two horizontal sub-lines are disposed in different cell rows, and the two vertical sub-lines are disposed in different cell columns. The first direction and the second direction intersect.

2. The display substrate according to claim 1, characterized in that, At least one unit row has at least two horizontal sub-lines, which connect different vertical sub-lines.

3. The display substrate according to claim 1, characterized in that, At least one unit column has at least two vertical sub-lines, which connect different horizontal sub-lines.

4. The display substrate according to claim 1, characterized in that, The orthographic projection of at least one horizontal sub-line on the display substrate and the orthographic projection of at least one vertical sub-line on the display substrate at least partially overlap.

5. The display substrate according to claim 1, characterized in that, In a direction perpendicular to the display substrate, the display area includes multiple conductive layers, the two horizontal sub-lines are disposed in the same conductive layer, the two vertical sub-lines are disposed in the same conductive layer, and the horizontal sub-lines and the vertical sub-lines are disposed in different conductive layers.

6. The display substrate according to claim 5, characterized in that, The plurality of conductive layers include at least a first source / drain metal layer disposed on a substrate and a second source / drain metal layer disposed on the side of the first source / drain metal layer away from the substrate, wherein the horizontal sub-line is disposed in the first source / drain metal layer and the vertical sub-line is disposed in the second source / drain metal layer.

7. The display substrate according to any one of claims 1 to 6, characterized in that, The at least two horizontal sub-lines include at least a first horizontal sub-line and a second horizontal sub-line, and the at least two vertical sub-lines include at least a first vertical sub-line and a second vertical sub-line; the data signal line is connected to the data lead-out line through the data connection line, including: a first end of the first vertical sub-line is connected to the data lead-out line; a second end of the first vertical sub-line extends away from the binding area and is connected to the first end of the first horizontal sub-line; a second end of the first horizontal sub-line extends towards the second vertical sub-line and is connected to the first end of the second vertical sub-line; a second end of the second vertical sub-line extends away from the binding area and is connected to the first end of the second horizontal sub-line; and a second end of the second horizontal sub-line extends towards the data signal line and is connected to the data signal line.

8. The display substrate according to claim 7, characterized in that, The display area further includes a plurality of first data connection blocks; in at least one circuit unit, the first data connection block is connected to a first end of the first horizontal sub-line, and the second end of the first vertical sub-line is connected to the first data connection block through a via; in at least another circuit unit, the first data connection block is connected to a first end of the second horizontal sub-line, and the second end of the second vertical sub-line is connected to the first data connection block through a via.

9. The display substrate according to claim 8, characterized in that, The display area also includes multiple data transfer strips. In at least one circuit unit, the first end of the first horizontal sub-line is connected to the first data connection block via the data transfer strip; in at least another circuit unit, the first end of the second horizontal sub-line is connected to the first data connection block via the data transfer strip.

10. The display substrate according to claim 9, characterized in that, In at least one circuit unit, the first horizontal sub-line, the first data connection block, and the data transition strip are interconnected as a single integrated structure; in at least another circuit unit, the second horizontal sub-line, the first data connection block, and the data transition strip are interconnected as a single integrated structure.

11. The display substrate according to claim 8, characterized in that, The display area also includes a plurality of first dummy electrodes, wherein at least one of the first dummy electrodes is located and connected in a circuit unit in the same way as at least one of the first data connection blocks is located and connected in another circuit unit.

12. The display substrate according to claim 11, characterized in that, In at least one circuit unit, the first vertical sub-line is connected to at least one of the first dummy electrodes via a via; in at least another circuit unit, the second vertical sub-line is connected to at least one of the first dummy electrodes via a via.

13. The display substrate according to claim 7, characterized in that, The display area further includes a plurality of second data connection blocks; in at least one circuit unit, the second data connection block is connected to the second end of the first horizontal sub-line, and the first end of the second vertical sub-line is connected to the second data connection block through a via.

14. The display substrate according to claim 13, characterized in that, In at least one circuit unit, the first horizontal sub-line and the second data connection block are an integral structure that are interconnected.

15. The display substrate according to claim 13, characterized in that, The display area also includes a plurality of second dummy electrodes, wherein the position and connection structure of at least one second dummy electrode in one circuit unit is the same as the position and connection structure of at least one second data connection block in another circuit unit.

16. The display substrate according to claim 15, characterized in that, In at least one circuit unit, the first vertical sub-line is connected to at least one second dummy electrode via a via; in at least another circuit unit, the second vertical sub-line is connected to at least one second dummy electrode via a via.

17. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 16.

18. A method for preparing a display substrate, characterized in that, The display substrate includes a display area and a bonding area disposed on one side of the display area. The display area includes multiple circuit units forming multiple cell rows and multiple cell columns, and at least one circuit unit includes a pixel driving circuit. The fabrication method includes: Multiple data signal lines and multiple data connection lines are formed in the display area, and multiple data lead-out lines are formed in the bonding area. The data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines through the data connection lines. At least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction. The two horizontal sub-lines are arranged in different cell rows, and the two vertical sub-lines are arranged in different cell columns. The first direction and the second direction intersect.

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