In-memory encryption circuit, encryption method and system based on resistive random access memory

Abstract

The invention discloses an in-memory encryption circuit, encryption method and system based on a resistive random access memory, and relates to the technical field of semiconductors and in-memory encryption, the in-memory encryption circuit comprises an in-memory calculation chip integrating a true random number generator, a physical unclonable function, a logic calculation function and a storage function, the computing macro unit is used for storing and processing bit data containing an encrypted plaintext and a key; the master control unit is used for uniformly managing control signals of the computing macro-units and ensuring cooperative work of the computing macro-units; the switch matrix is used for realizing external input and output of logic signals and data interaction among the computing macro units; and the input and output module is used for realizing external driving and internal driving of the in-memory computing chip and completing signal and data butt joint between the in-memory computing chip and external equipment. According to the method, deep integration of encryption algorithms can be realized, and the security of in-memory encryption is improved while the area overhead is reduced.

Description

Technical Field

[0001] This application relates to the fields of semiconductor and in-memory encryption technology, and in particular to an in-memory encryption circuit, encryption method and system based on resistive random access memory. Background Technology

[0002] In the field of information security, the AES (Advanced Encryption Standard) encryption algorithm, as a mainstream symmetric encryption technology, has been widely used in traditional CMOS (Complementary Metal-Oxide-Semiconductor) circuits, and its ability to protect against mathematical algorithm attacks (such as machine learning attacks) has been verified. However, traditional encryption systems employ a storage-compute separation architecture, requiring data to be frequently moved between memory and computing units. This process generates significant electromagnetic leakage, providing opportunities for side-channel attacks.

[0003] Side-channel attacks infer sensitive data by monitoring the physical parameters of a device during operation (such as power consumption, electromagnetic radiation, and timing information). Experiments show that, using differential power analysis technology, attackers only need to collect power consumption trajectories 2000 times to crack the AES-128 key. Furthermore, in traditional architectures, external key management modules are vulnerable to attack, and keys are at risk of being intercepted or stolen during transmission, further exacerbating system security vulnerabilities.

[0004] To address the aforementioned issues, in-memory computing architecture has been proposed. This architecture tightly integrates computing and storage, reducing data movement requirements and mitigating the risk of electromagnetic leakage at its source. However, existing in-memory encryption technologies still face the following technical challenges:

[0005] (1) Limitations of algorithm implementation: It focuses on single bit encryption and ignores the overall position information substitution. Attackers can use partial attack strategies to crack key ciphertext fragments, thereby increasing the system's vulnerability.

[0006] (2) Excessive area overhead: The in-memory computing circuit and functional modules such as the true random number generator (TRNG) and physical unclonable function (PUF) need to be designed separately, which leads to a surge in the area requirements of memory and peripheral circuits, making it difficult to adapt to resource-constrained scenarios.

[0007] (3) Module separation risk: TRNG and PUF are separated from the encryption computing system. The key needs to be input externally. There is still a risk of physical information leakage during transmission, which weakens the overall security of the system.

[0008] Therefore, there is an urgent need for an in-memory encryption scheme that can achieve deep integration of encryption algorithms, low overhead, and high security to meet the application requirements of high-security scenarios. Summary of the Invention

[0009] The purpose of this application is to provide an in-memory encryption circuit, encryption method and system based on resistive random access memory, which can achieve deep integration of encryption algorithms, reduce area overhead and improve the security of in-memory encryption.

[0010] To achieve the above objectives, this application provides the following solution.

[0011] In a first aspect, this application provides an in-memory encryption circuit based on resistive random access memory (RRAM). The in-memory encryption circuit based on RRAM includes an in-memory computing chip that integrates a true random number generator, a physically unclonable function (PUF), logic calculation functions, and storage functions. The true random number generator is used to generate a random number string and use the random number string as encrypted plaintext. The physically unclonable function is used to generate a PUF response and generate the key required for the AES encryption algorithm based on the PUF response.

[0012] The in-memory computing chip includes several computing macro units, a main control unit, a switch matrix, and input / output circuits. Each computing macro unit is connected to the main control unit, the switch matrix, and the input / output circuits, respectively. The main control unit is connected to the switch matrix and the input / output circuits, respectively. The switch matrix is ​​also connected to the input / output circuits.

[0013] The computational macro unit is used to store and process bit data containing the encrypted plaintext and the key.

[0014] The central control unit is used to uniformly manage the control signals of each computing macro unit, ensuring that each computing macro unit works in coordination.

[0015] The switching matrix is ​​used to realize the external input and output of logic signals and the data interaction between the various computational macrounits.

[0016] The input / output module is used to drive the in-memory computing chip externally and internally, and to complete the signal and data interface between the in-memory computing chip and external devices.

[0017] Optionally, each of the computing macro units includes several resistive random access memory (RRAM) subarrays, each RRAM subarray is provided with a row driving module, a column driving module, a sensing amplifier and a logic control module, and each computing macro unit also includes a switching submatrix and a computing macro overall control module.

[0018] Each of the resistive random access memory (RRAM) subarrays includes a plurality of RRAM cells, which are connected by cross-connected signal lines. Each row driver module and each column driver module are respectively connected to the signal lines of the corresponding RRAM subarray. Each sense amplifier is respectively connected to the corresponding logic control module, and each sense amplifier and each logic control module are respectively connected to the column driver module and the switch submatrix. The computational macro total control module is respectively connected to the row driver module, each column driver module, each sense amplifier, each logic control module, and the switch submatrix.

[0019] The resistive switching memory unit is used to store the encrypted plaintext, the key, and intermediate data during the encryption process.

[0020] The row driving module and the column driving module are used to select the resistive switching memory cell at the corresponding position in the resistive switching memory subarray according to the input address signal.

[0021] The sensing amplifier is used to read the current difference signal of a selected group of resistive variable memory cells, amplify the current difference signal, and output the amplified logic signal.

[0022] The logic control module is used to perform logic calculations based on the amplified logic signal and output basic logic values.

[0023] The switch submatrix is ​​used to control the signal interaction between the basic logic values ​​output by each of the logic control modules.

[0024] The computational macro control module is used to manage the clock signals and address signals of each computational macro unit, so that each computational macro unit receives input external signals under the unified synchronous clock drive.

[0025] Optionally, the in-memory computing chip includes eight computing macrounits, each of which is used to store and process eight bits of each byte of the encrypted plaintext or key bit data.

[0026] Optionally, each of the computing macro units includes four resistive random access memory subarrays, four row driving modules, four column driving modules, four sense amplifiers, four logic control modules, one switch submatrix, and one computing macro total control module.

[0027] Secondly, this application provides an in-memory encryption method based on an in-memory encryption circuit of resistive random access memory (RRAM). The in-memory encryption method of RRAM is implemented based on the in-memory encryption circuit of RRAM described in the first aspect. All operations of the in-memory encryption method are completed within the in-memory computing chip of the in-memory encryption circuit, and the parallel operation of multiple RRAM subarrays is used to achieve parallelization of logic computation. The in-memory encryption method of RRAM includes the following steps.

[0028] S1: Generate plaintext and key, which includes the following steps.

[0029] A true random number generator in the in-memory encryption circuit is used to generate a random number string in parallel, and the random number string is used as the encrypted plaintext.

[0030] The Physically Unclonable Function (PUF) response is generated in parallel using the Physically Unclonable Function in the in-memory encryption circuit, and the PUF response is used as the key for the AES encryption algorithm; wherein, both the encrypted plaintext and the key are stored in a resistive random access memory (RRAM) subarray.

[0031] S2: Perform encryption operations, which include the following steps.

[0032] Based on the encrypted plaintext and the key, the AES encryption algorithm is sequentially executed, including round key application, row shifting, byte substitution, and column obfuscation operations, to complete the encryption and obtain the encrypted data.

[0033] The encrypted data is stored in the resistive switching memory subarray.

[0034] S3: Perform the decryption operation, which includes the following steps.

[0035] If decryption is required, the AES decryption algorithm is sequentially executed based on the encrypted data, performing reverse column obfuscation, reverse byte substitution, reverse row shift, and reverse wheel key application operations to complete the decryption and obtain the decrypted data.

[0036] Optionally, each byte of the encrypted plaintext, consisting of 8 bits, is stored in 8 computational macro modules, and the 8 bits of the same byte are located in the same column in the corresponding resistive random access memory subarrays of the 8 computational macro modules. The key and the corresponding encrypted plaintext are located in the same column in the resistive random access memory subarrays.

[0037] Optionally, the application of the round key specifically includes the following steps.

[0038] The key matrix element K stored in the resistive random access memory subarray i,j and plaintext matrix element D i,jAs a logic input unit, the corresponding row and column logic reference unit is selected to perform an XOR operation to obtain the operation result.

[0039] The calculation result is temporarily stored in the sensing amplifier in the form of a voltage signal, and the elements of the state matrix are updated with the calculation result S. i,j .

[0040] Optionally, the row shifting specifically includes the following steps.

[0041] The state matrix is ​​periodically shifted according to a preset offset. The first row remains unchanged, the second row shifts each bit to the left by 1 bit, the third row shifts each bit to the left by 2 bits, and the fourth row shifts each bit to the left by 3 bits. The position migration of the state matrix elements is realized through a system-level switch matrix, and the migration result is written back to the corresponding position of the resistive random access memory subarray. The row shift operation supports 32-bit parallel execution.

[0042] Optionally, the byte substitution specifically includes the following steps.

[0043] The S-cell is implemented based on the resistive random access memory subarray. The S-cell has a pre-programmed lookup table structure. The input of the lookup table is encoded by the row address of the memristor cell, and the output is represented by the conductance state of the corresponding memristor cell.

[0044] The 8-bit voltage signal of the state matrix element is converted into a row address signal using the sensing amplifier. The conductance value of the memristor cell corresponding to each resistive random access memory subarray is read in parallel, and the 8-bit replacement value is obtained and temporarily stored.

[0045] The 8-bit replacement value is written into the target cell column of the resistive random access memory (RRAM) subarray to complete the state matrix element update; wherein, the RRAM subarrays with the same index in the 8 computational macrocells store each bit of the output value, and the memristor cells used are located in the same column.

[0046] The column obfuscation specifically includes the following steps.

[0047] A reversible linear transformation method is used to combine the state matrix columns of each computational macrounit to achieve ciphertext obfuscation between different columns and between different bits of the same byte. The reversible linear transformation method is implemented by multiplying the data matrix by a preset known matrix in a finite field, and the intermediate results of the transformation process are stored in the resistive random access memory subarray.

[0048] Thirdly, this application provides an in-memory encryption system based on an in-memory encryption circuit of a resistive random access memory (RRAM). The in-memory encryption system based on the RRAM includes the in-memory encryption circuit based on the RRAM described in the first aspect, and the in-memory encryption system based on the RRAM operates the in-memory encryption method based on the RRAM described in the second aspect.

[0049] According to the specific embodiments provided in this application, this application has the following technical effects.

[0050] This application provides an in-memory encryption circuit, encryption method, and system based on resistive random access memory (RRAM). It employs an in-memory computing chip integrating a true random number generator, physically unclonable functions, logic calculation functions, and storage functions. Within this in-memory computing chip, several computational macrocells, a central control unit, a switch matrix, and input / output circuits are configured. The computational macrocells store and process bit data containing encrypted plaintext and a key. The central control unit manages the control signals of each computational macrocell, ensuring coordinated operation. The switch matrix enables external input / output of logic signals and data interaction between the computational macrocells. The input / output module drives the in-memory computing chip both externally and internally, facilitating signal and data interface between the in-memory computing chip and external devices. This application integrates a true random number generator, a physically unclonable function, logic calculation functions, and storage functions into a single in-memory computing chip. It also designs and optimizes the computing macrocell, the main control unit, the switch matrix, and the input / output circuits, enabling the in-memory computing chip to support parallel operations across multiple rows and columns. This achieves efficient data encryption and storage integration, and further enables deep integration of encryption algorithms, reducing area overhead while improving the security of in-memory encryption. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of an in-memory encryption circuit based on resistive random access memory (RRAM) according to an embodiment of this application.

[0053] Figure 2 for Figure 1 A magnified view of a single computational macrocell.

[0054] Figure 3 for Figure 2A magnified view of a single resistive random access memory (RRAM) subarray.

[0055] Figure 4 This is a schematic diagram showing the distribution of encrypted plaintext in a computational macrocell according to an embodiment of this application.

[0056] Figure 5 This is a flowchart illustrating the encryption / decryption operation process provided in one embodiment of this application.

[0057] Figure 6 This is a schematic diagram illustrating the key addition and row shifting operations performed during the execution of an encryption algorithm provided in an embodiment of this application.

[0058] Figure 7 A schematic diagram showing the energy efficiency comparison between the present invention and CPU-based systems, GPU-based systems, and ASIC-based systems, provided as an embodiment of this application.

[0059] Figure 8 This is a schematic flowchart illustrating an in-memory encryption method based on an in-memory encryption circuit of a resistive random access memory (RRAM) according to an embodiment of this application. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0061] The purpose of this application is to provide an in-memory encryption circuit, encryption method and system based on resistive random access memory, which aims to solve the problems faced by current traditional in-memory encryption technology in a distributed deployment environment due to its resource-constrained characteristics (such as computing power, storage capacity and energy consumption limitations), such as low logic cascading efficiency, insufficient anti-attack capability, high complexity of multi-module integration and large area and power consumption overhead.

[0062] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0063] like Figure 1As shown, this embodiment provides an in-memory encryption circuit based on resistive random access memory (RRAM). The in-memory encryption circuit based on RRAM includes an in-memory computing chip that integrates a true random number generator, a physically unclonable function (PUF), logic calculation functions, and storage functions. The true random number generator is used to generate a random number string and use the random number string as encrypted plaintext. The physically unclonable function is used to generate a PUF response and generate the key required for the AES encryption algorithm based on the PUF response.

[0064] The in-memory computing chip includes several computing macro units, a main control unit, a switch matrix, and input / output circuits. Each computing macro unit is connected to the main control unit, the switch matrix, and the input / output circuits, respectively. The main control unit is connected to the switch matrix and the input / output circuits, respectively. The switch matrix is ​​also connected to the input / output circuits.

[0065] The computational macro unit is used to store and process bit data containing the encrypted plaintext and the key.

[0066] The central control unit is used to uniformly manage the control signals of each computing macro unit, ensuring that each computing macro unit works in coordination.

[0067] The switching matrix is ​​used to realize the external input and output of logic signals and the data interaction between the various computational macrounits.

[0068] The input / output module is used to drive the in-memory computing chip externally and internally, and to complete the signal and data interface between the in-memory computing chip and external devices.

[0069] As one possible implementation, each of the computing macrocells includes several resistive random access memory (RRAM) subarrays (hereinafter referred to as subarrays), each RRAM subarray is provided with a row driving module, a column driving module, a sense amplifier (SA) and a logic control module, and each computing macrocell also includes a switching submatrix and a computing macro total control module.

[0070] Each of the resistive random access memory (RRAM) subarrays includes a plurality of RRAM cells, which are connected by cross-connected signal lines. Each row driver module and each column driver module are respectively connected to the signal lines of the corresponding RRAM subarray. Each sense amplifier is respectively connected to the corresponding logic control module, and each sense amplifier and each logic control module are respectively connected to the column driver module and the switch submatrix. The computational macro total control module is respectively connected to the row driver module, each column driver module, each sense amplifier, each logic control module, and the switch submatrix.

[0071] The resistive switching memory unit is used to store the encrypted plaintext, the key, and intermediate data during the encryption process.

[0072] The row driving module and the column driving module are used to select the resistive switching memory cell at the corresponding position in the resistive switching memory subarray according to the input address signal.

[0073] The sensing amplifier is used to read the current difference signal of a selected group of resistive variable memory cells, amplify the current difference signal, and output the amplified logic signal.

[0074] The logic control module is used to perform logic calculations based on the amplified logic signal and output basic logic values.

[0075] The switch submatrix is ​​used to control the signal interaction between the basic logic values ​​output by each of the logic control modules.

[0076] The computational macro control module is used to manage the clock signals and address signals of each computational macro unit, so that each computational macro unit receives input external signals under the unified synchronous clock drive.

[0077] As one possible implementation, the in-memory computing chip includes eight computing macrounits, each of which is used to store and process eight bits of each byte of bit data in the encrypted plaintext or key.

[0078] As one possible implementation, each of the computational macrocells includes four resistive random access memory subarrays, four row drive modules, four column drive modules, four sense amplifiers, four logic control modules, one switch submatrix, and one computational macrocell overall control module.

[0079] This embodiment proposes an in-memory encryption circuit based on resistive random access memory (RRAM), adopting an in-memory encryption system architecture oriented towards privacy protection mutual authentication (PPMA) protocol. It consists of an in-memory computing chip that integrates TRNG, PUF, logic and storage functions, with RRAM (memristor devices such as RRAM and PCM) as the main storage medium, and a corresponding mapping method for AES encryption / decryption algorithms in the in-memory computing architecture.

[0080] The in-memory computing chip in this embodiment integrates TRNG, PUF, logic, and memory functions. The overall chip architecture consists of 8 computing macro units, a control unit, a switch matrix, and input / output circuits. The 8 computing macro units are used to process 8 bits of each byte of encrypted plaintext or key. The structure of the computing macro unit includes a resistive random access memory subarray, a row driver module, a column driver module, a sense amplifier and a logic control module, a switch matrix, and a computing macro overall control module.

[0081] Compared to other hardware circuits used for in-memory encryption, this embodiment integrates the logic calculation functions and storage functions for generating keys and plaintext, encryption and decryption onto the same chip. On the one hand, this reduces the overall system area and power consumption. On the other hand, since both the keys and plaintext are generated by dedicated on-chip circuits, all operations are performed on-chip, thereby fundamentally avoiding the risk of side-channel attacks and improving system security.

[0082] The in-memory encryption circuit based on resistive random access memory (RRAM) proposed in this embodiment includes eight computational macrocells, a control unit, a switch matrix, and input / output circuits. Address, clock, and other signals between the computational macrocells are uniformly managed by the control unit. External input / output of the logic bitstream and data interaction between different computational macrocells are selected through a specific switch matrix. External and internal driving of the chip are implemented by the input / output circuits. The computational macrocells, which handle most of the computation and storage functions in the system, include a resistive random access memory (RRAM) subarray, row / column driver modules (WL / SL / BLdriver), a sense amplifier and logic control module, a switch matrix, and a general computational macrocell control module. The RRAM subarray is composed of non-volatile memory devices connected by vertically intersecting bit lines (BL), word lines (WL), and source lines (SL). The row / column driver module selects the corresponding memory cell based on the input address signal. Logic calculation and selection are performed by the sense amplifier and logic control module integrated on the column driver module. Finally, a specific switch matrix controls the information interaction between different RRAM subarrays within the computational macrocell. The above operations correspond to the logical calculations and logical selections in the AES encryption and decryption algorithms. Finally, the data is stored in the non-volatile storage devices in the resistive random access memory (RRAM) subarrays after interaction between different RRAM subarrays and different computational macrocells.

[0083] The encryption / decryption operation method in this embodiment is as follows: First, a random number string and a PUF response are generated in parallel through a dedicated circuit. The random number string serves as the encrypted plaintext, and the PUF response generates the key required by the AES encryption algorithm. Then, the steps of the AES encryption algorithm are executed sequentially: round key application, row shifting, byte substitution, and column obfuscation to complete the encryption process. The encrypted data is stored in the resistive random access memory (TRNG) subarray of the chip. If necessary, the decryption algorithm can be executed last, performing reverse column obfuscation, reverse row shifting, reverse byte substitution, and reverse round key application operations to complete the decryption process. Both the encryption and decryption processes are implemented based on the TRNG subarray. Logical calculations are completed through parallel operation of multiple TRNG subarrays. All operations (including TRNG, PUF, logical calculations, and data storage) are completed within the same chip. The key is dynamically generated without external transmission, demonstrating high security and energy efficiency advantages.

[0084] In this embodiment, the non-volatile storage medium used to store encrypted plaintext, keys, and intermediate data generated during encryption and decryption is resistive random access memory (RRAM, PCM, and other memristor devices). The connection topology on the RRAM subarray is as follows: bit lines are parallel to source lines and perpendicular to word lines. Sensing amplifiers and logic control modules are connected at the bit line ends of the array. The encryption algorithm used is AES, which is one of the most mainstream symmetric encryption algorithms.

[0085] like Figure 1 As shown, the architecture of the self-designed in-memory computing chip in this embodiment consists of eight computing macrocells and some peripheral circuits. The eight computing macrocells are named Computing Macrocell 0, Computing Macrocell 1, Computing Macrocell 2, Computing Macrocell 3, Computing Macrocell 4, Computing Macrocell 5, Computing Macrocell 6, and Computing Macrocell 7, respectively. The address, clock, and other signals between the various computing macrocells are uniformly managed by the control unit. The input and output of the logic bitstream to the outside and the data interaction between different computing macrocells are selected through a specific switch matrix. The external and internal driving of the chip is implemented by the input and output circuits.

[0086] In this embodiment, since the AES algorithm encrypts 16 bytes, and each byte contains 8 bits, this application sets the number of computational macrounits to 8. These 8 bits are stored in 8 computational macrounits respectively, and computation is performed separately to obtain clearer and more intuitive output results, thereby saving control costs.

[0087] Figure 2 It shows Figure 1The structure of one of the eight computing macrocells is as follows: The computing macrocell undertakes the core computing and storage functions. Each computing macrocell includes four resistive random access memory subarrays, four row drive modules and four column drive modules, four sense amplifiers and logic control modules, one switch submatrix and one computing macro control module.

[0088] Figure 3 This is a magnified view of a partial resistive random access memory (RRAM) subarray. In the RRAM subarray, the word lines are perpendicular to the bit lines and source lines, while the bit lines and source lines are parallel to each other.

[0089] The row driver module and column driver module are directly connected to the word lines, bit lines and source lines of the resistive random access memory subarray, and are respectively responsible for decoding the input address signals into signals that drive the corresponding word lines, bit lines and source lines.

[0090] The sense amplifier can read the slight current difference on a selected set of resistive switching memory cells and amplify it into NAND or OR logic signals. The logic control module is a set of logic gates responsible for further calculating all the basic logic values ​​from the logic signals output by the sense amplifier and selecting the required output. The functions of the sense amplifier and logic control module include generating TRNG random numbers, generating PUF responses, performing logic calculations, and making logic selections.

[0091] In this embodiment, since the AES algorithm encrypts 16 bytes at a time, and the operation on a single bit (e.g., bit 0) of these 16 bytes is performed entirely within a single computational macrounit, and these 16 bytes are evenly distributed across four resistive random access memory (RRAM) subarrays, four bytes (bit 0) can be processed in parallel. The four RRAM subarrays repeat the above operation four times sequentially to complete the encryption of a batch of 16 bytes. This embodiment sets the number of sensing amplifiers to four to process four bytes at a time, thus ensuring a certain degree of parallelism. The number of sensing amplifiers can also be set to two, eight, or other numbers. However, it is important to note that the parallelism should not be too high, otherwise it will affect subsequent column obfuscation operations. Therefore, considering the final tape-out, this embodiment preferably uses four sensing amplifiers.

[0092] The switch submatrix contains a multi-input, multi-output switch circuit matrix, which is responsible for controlling the signal interaction between the sense amplifiers and logic control modules under different resistive random access memory subarrays and the final output logic values.

[0093] The computational macro control module is responsible for managing the input of clock, address and other signals of the computational macro units, ensuring that all modules receive external signal input under the unified synchronous clock drive.

[0094] Running the AES encryption algorithm on this in-memory computing chip can implement the PPMA protocol, which requires the simultaneous presence of PUF and TRNG on the client side, as well as the ability to implement encryption functions and XOR logic operations.

[0095] In the security mechanism of the PPMA protocol, the plaintext data that the system needs to encrypt is a string of random numbers generated in real time, while the encryption key comes from the PUF response.

[0096] The distribution of encrypted plaintext data in the resistive random access memory (RRAM) subarray and the array circuit architecture, such as Figure 4 As shown, each computational macrocell contains four resistive random access memory (RRAM) subarrays, and each RRAM subarray contains 32 columns of memory cells. Based on the input address signal, the multiplexer in the column driver module selects the address and drives the corresponding signal line. After performing a read or write operation on the selected RRAM cell, a weak current signal is sent to the sense amplifier corresponding to that RRAM subarray to execute the logic function.

[0097] Each computational macrocell consists of four resistive random access memory (RRAM) subarrays. This task requires a total of eight computational macrocells, thus the system can achieve parallel operation of 32 RRAM subarrays and their corresponding sense amplifiers and logic control modules. To achieve parallel computation, the row addresses of the four data points in each RRAM subarray must correspond one-to-one with the row addresses of the four data points in other RRAM subarrays, as shown in the specific distribution below. Figure 4 As shown, the plaintext matrix is ​​displayed in hexadecimal and contains 16 bytes. Each 8 bits of the encrypted plaintext are stored in 8 different computational macrocells. Within each computational macrocell, since the AES algorithm encrypts 16 bytes at a time, the same bit of these 16 bytes is distributed sequentially within the four resistive random access memory (RRAM) subarrays of the same computational macrocell according to the state matrix arrangement. Furthermore, the four data points within the same RRAM subarray are located in the same column, allowing the multiplexer under each RRAM subarray to select the same column address and simultaneously drive that column of RRAM cells. Finally, the analog signal is sent to the sense amplifier under each RRAM subarray for subsequent logic calculations.

[0098] The mapping method of the key in the array is consistent with that of the encrypted plaintext data, that is, the key unit in each resistive random access memory subarray is located in the same column as the corresponding encrypted plaintext data.

[0099] like Figure 5 As shown, the encryption / decryption operation of the in-memory computing chip in this embodiment is generally described as follows (the contents of steps 1 and 2 are used to generate the plaintext to be encrypted and the key).

[0100] Step 1: Random number generation adopts a distributed architecture, with each computational macro consisting of a resistive random access memory subarray (e.g., ...). Figure 4Two memristor units are selected as entropy source units in the diagram. The high-frequency noise characteristics of the memristor device are accurately extracted using a sensing amplifier. The quantized random number result is written back to the storage array through a switching matrix and is used as plaintext to await encryption.

[0101] Step 2: In Figure 4 The computational macrocell shown selects memristor cells participating in the PUF response and pre-sets them all to a low-conductance state. First, the first row of the PUF response cell array is selected. The conductance values ​​of two selected cells in each resistive random access memory (RRAM) subarray are compared in parallel using a sense amplifier. The comparison results are independently written back to a row of the corresponding RRAM subarray key cell (the column address is consistent with the encrypted cell). This process is repeated until all four rows of PUF keys are generated.

[0102] Step 3: First, perform the round key application. During AES encryption, the data to be encrypted (D... i,j Each one of them is like Figure 4 The diagram shows the regular distribution in the computational macrocell, while the round key (K) i,j The distribution of the matrix is ​​in the same column as the plaintext matrix. Round key application is performed in the resistive random access memory subarray, setting K... i,j (key matrix elements) and D i,j The plaintext matrix elements serve as logic input units. By selecting the logic reference units in the corresponding rows and columns, an XOR operation is performed. The result is temporarily stored in the sense amplifier latch as a voltage signal, and the state matrix elements are updated to S. i,j .

[0103] Step 4: After the round key is added, a row shift operation is performed. In this step, each byte of the state matrix is ​​periodically shifted by a specific offset: the first row remains unchanged, each byte of the second row shifts 1 bit to the left, each byte of the third row shifts 2 bits to the left, and each byte of the fourth row shifts 3 bits to the left, implemented using a dedicated switching matrix. See the attached image for the specific operation results. Figure 6 For example, after a row shift operation, S 1,0 The state needs to be shifted from the second row, first column to the second row, fourth column of the state matrix, so it is written back to the corresponding position in the fourth resistive random access memory subarray of the output unit. The row shift operation also supports 32-bit parallel execution.

[0104] Step 5: After the row shift operation, a byte substitution operation is performed. This operation enhances the algorithm's security by using a substitution box (S-box) based on a resistive random access memory (RRAM) subarray to perform a nonlinear transformation on the state matrix elements. To achieve an 8-bit output, the system stores each bit of the output value in eight independent RRAM subarrays with the same index, with the memristor cells located in the same column. In the specific implementation, the S-box uses a pre-programmed lookup table structure, where the lookup table input is encoded by the row address of the memristor cell, and the output is represented by the conductance state of the corresponding cell. During operation, the sense amplifier first converts the 8-bit voltage signal of the state matrix element into a row address signal, reads the conductance value of the corresponding cell in each RRAM subarray in parallel, temporarily stores the obtained 8-bit substitution value, and then writes it to the target cell column, finally completing the update of the state matrix elements.

[0105] Step 6: After byte substitution, perform column obfuscation. Use a reversible linear transformation to combine each column of the state matrix of different computational macrounits to achieve sufficient obfuscation between different columns and between different bits of the same byte in the encrypted ciphertext. This is achieved by applying a finite field GF(2^3) to the data matrix. 8 This is achieved by multiplying the plaintext by a known matrix. In the specific implementation, the matrix after replacing the bytes in the previous step is subjected to logical calculation with the known matrix through a sensing amplifier. The intermediate results of each step are stored in the resistive random access memory subarray, and finally the encryption of the current plaintext is completed.

[0106] Step 7: For the AES decryption algorithm, the process is equivalent to performing the reverse process of encryption. The decryption algorithm sequentially performs reverse column obfuscation, reverse row shift, reverse byte substitution, and reverse round key application operations.

[0107] This embodiment's in-memory encryption system integrates the in-memory computing array and data storage array within the same resistive random access memory (RRAM) subarray, while also tightly integrating peripheral circuitry, thereby reducing data transfer overhead. Based on post-simulation results of the chip, the power consumption required for the operation of each module in the designed array was statistically analyzed. Experiments show that, compared to traditional CPU / GPU-based encryption systems and ASIC (Application Specific Integrated Circuit) chips used only to accelerate data encryption algorithms, it can significantly reduce the energy consumption of the data encryption / decryption process. Figure 7 As shown.

[0108] Experiments show that, because this embodiment fundamentally avoids the risk of side-channel attacks, the in-memory encryption system of this application has extremely high security when facing power analysis attacks under test vector leakage assessment (TVLA). Attackers need to pay a huge price to successfully steal information, thus effectively ensuring the security and reliability of the system.

[0109] This embodiment proposes and designs an AES encryption and decryption method based on resistive random access memory (RRAM, PCM, and other memristor devices) arrays. Encryption operations are implemented through in-memory logic computation, achieving in-memory parallel mapping of the AES encryption algorithm. Experiments verify the correctness and feasibility of the encryption and decryption method. By designing and manufacturing a chip integrating TRNG, PUF, and logic and storage functions, the performance of each module is optimized. The chip supports multi-row / column parallel operations, achieving efficient data encryption and storage integration.

[0110] This embodiment evaluates the performance of the in-memory encryption method and system based on resistive random access memory (RRAM) in terms of area, energy consumption, and speed. It also verifies the ability to resist side-channel attacks through test vector leakage evaluation. Compared with traditional in-memory encryption technology, it demonstrates advantages in high security and energy efficiency.

[0111] In one exemplary embodiment, such as Figure 8 As shown, an in-memory encryption method based on a resistive random access memory (RRAM) in-memory encryption circuit is provided. This in-memory encryption method is implemented based on the RRAM-based in-memory encryption circuit described above. All operations of the in-memory encryption method are completed within the in-memory computing chip in the in-memory encryption circuit, and the parallel operation of multiple RRAM subarrays is used to achieve parallelization of logic computation. The in-memory encryption method based on the RRAM in-memory encryption circuit includes the following steps.

[0112] S1: Generate plaintext and key, which includes the following steps.

[0113] S11: Use the true random number generator in the in-memory encryption circuit to generate a random number string in parallel, and use the random number string as the encrypted plaintext.

[0114] S12: Generate a PUF response in parallel using the physically unclonable function in the in-memory encryption circuit, and use the PUF response as the key for the AES encryption algorithm; wherein the encrypted plaintext and the key are both stored in a resistive random access memory subarray.

[0115] S2: Perform encryption operations, which include the following steps.

[0116] S21: Based on the encrypted plaintext and the key, sequentially execute the AES encryption algorithm's round key application, row shifting, byte substitution, and column obfuscation operations to complete the encryption and obtain the encrypted data.

[0117] S22: Store the encrypted data in the resistive switching memory subarray.

[0118] S3: Perform the decryption operation, which includes the following steps.

[0119] If decryption is required, the AES decryption algorithm is sequentially executed based on the encrypted data, performing reverse column obfuscation, reverse byte substitution, reverse row shift, and reverse wheel key application operations to complete the decryption and obtain the decrypted data.

[0120] As an optional implementation, each 8 bits of the encrypted plaintext are stored in 8 computational macro modules, and the 8 bits of the same byte are located in the same column in the corresponding resistive random access memory subarray of the 8 computational macro modules. The key and the corresponding encrypted plaintext are located in the same column in the resistive random access memory subarray.

[0121] As an optional implementation, the application of the round key specifically includes the following steps.

[0122] The key matrix element K stored in the resistive random access memory subarray i,j and plaintext matrix element D i,j As a logic input unit, the corresponding row and column logic reference unit is selected to perform an XOR operation to obtain the operation result.

[0123] The calculation result is temporarily stored in the sensing amplifier in the form of a voltage signal, and the elements of the state matrix are updated with the calculation result S. i,j .

[0124] As an optional implementation, the row shift specifically includes the following steps.

[0125] The state matrix is ​​periodically shifted according to a preset offset. The first row remains unchanged, the second row shifts each bit to the left by 1 bit, the third row shifts each bit to the left by 2 bits, and the fourth row shifts each bit to the left by 3 bits. The position migration of the state matrix elements is realized through a system-level switch matrix, and the migration result is written back to the corresponding position of the resistive random access memory subarray. The row shift operation supports 32-bit parallel execution.

[0126] As an optional implementation, the byte substitution specifically includes the following steps.

[0127] The S-cell is implemented based on the resistive random access memory subarray. The S-cell has a pre-programmed lookup table structure. The input of the lookup table is encoded by the row address of the memristor cell, and the output is represented by the conductance state of the corresponding memristor cell.

[0128] The 8-bit voltage signal of the state matrix element is converted into a row address signal using the sensing amplifier. The conductance value of the memristor cell corresponding to each resistive random access memory subarray is read in parallel, and the 8-bit replacement value is obtained and temporarily stored.

[0129] The 8-bit replacement value is written into the target cell column of the resistive random access memory (RRAM) subarray to complete the state matrix element update; wherein, the RRAM subarrays with the same index in the 8 computational macrocells store each bit of the output value, and the memristor cells used are located in the same column.

[0130] As an optional implementation, the column obfuscation specifically includes the following steps.

[0131] A reversible linear transformation method is used to combine the state matrix columns of each computational macrounit to achieve ciphertext obfuscation between different columns and between different bits of the same byte. The reversible linear transformation method is implemented by multiplying the data matrix by a preset known matrix in a finite field, and the intermediate results of the transformation process are stored in the resistive random access memory subarray.

[0132] In one exemplary embodiment, an in-memory encryption system based on a resistive random access memory (RRAM) in-memory encryption circuit is provided. The in-memory encryption system based on the RRAM in-memory encryption circuit includes the RRAM in-memory encryption circuit, and the in-memory encryption system based on the RRAM in-memory encryption circuit runs the in-memory encryption method based on the RRAM in-memory encryption circuit.

[0133] This application proposes an in-memory encryption circuit, encryption method, and system based on resistive random access memory (RRAM, PCM, and other memristor devices) to address the side-channel attack problem caused by frequent data movement in traditional memory-compute separation architectures. By deeply mapping the AES encryption algorithm into the RRAM subarray, the entire process of key dynamic generation, encryption, and decryption is parallelized within memory. The core design includes an in-memory computing chip integrating a true random number generator, physically unclonable functions, and logic computation and storage functions, containing an RRAM storage array that supports multi-row / column parallel operations. The key is generated in-situ by the PUF response, avoiding external transmission risks; the encryption process is performed in parallel by the RRAM subarray, performing round key addition, row shifting, byte substitution, and column obfuscation operations, while the decryption process is implemented in reverse. Experiments show that compared to traditional solutions, this in-memory encryption system significantly improves the security and energy efficiency of the encryption system while reducing electromagnetic leakage, area, and power consumption, providing a reliable solution for high-security scenarios.

[0134] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An in-memory encryption circuit based on resistive random access memory, characterized in that, The in-memory encryption circuit based on resistive random access memory includes an in-memory computing chip that integrates a true random number generator, a physically unclonable function, logic calculation functions, and storage functions. The true random number generator is used to generate a random number string and use the random number string as encrypted plaintext. The physically unclonable function is used to generate a PUF response and generate the key required for the AES encryption algorithm based on the PUF response. The in-memory computing chip includes several computing macro units, a main control unit, a switch matrix, and input / output circuits. Each computing macro unit is connected to the main control unit, the switch matrix, and the input / output circuits, respectively. The main control unit is connected to the switch matrix and the input / output circuits, respectively. The switch matrix is ​​also connected to the input / output circuits. The computational macro unit is used to store and process bit data containing the encrypted plaintext and the key; The central control unit is used to uniformly manage the control signals of each computing macro unit, ensuring that each computing macro unit works collaboratively. The switching matrix is ​​used to realize the external input and output of logic signals and the data interaction between the various computational macro units; The input / output module is used to drive the in-memory computing chip externally and internally, and to complete the signal and data interface between the in-memory computing chip and external devices.

2. The in-memory encryption circuit based on resistive random access memory according to claim 1, characterized in that, Each of the aforementioned computational macro units includes several resistive random access memory (RRAM) subarrays. Each RRAM subarray is correspondingly provided with a row driving module, a column driving module, a sensing amplifier, and a logic control module. Each of the aforementioned computational macro units also includes a switching submatrix and a computational macro total control module. Each of the resistive random access memory (RRAM) subarrays includes a plurality of RRAM cells, which are connected by cross-connected signal lines. Each row driver module and each column driver module are respectively connected to the signal lines of the corresponding RRAM subarray. Each sense amplifier is respectively connected to the corresponding logic control module, and each sense amplifier and each logic control module are respectively connected to the column driver module and the switch submatrix. The computational macro total control module is respectively connected to the row driver module, each column driver module, each sense amplifier, each logic control module, and the switch submatrix. The resistive switching memory unit is used to store the encrypted plaintext, the key, and intermediate data during the encryption process; The row driving module and the column driving module are used to select the resistive switching memory cell at the corresponding position in the resistive switching memory subarray according to the input address signal. The sensing amplifier is used to read the current difference signal of a selected group of resistive switching memory cells, amplify the current difference signal, and output the amplified logic signal. The logic control module is used to perform logic calculations based on the amplified logic signal and output basic logic values. The switch submatrix is ​​used to control the signal interaction between the basic logic values ​​output by each of the logic control modules; The computational macro control module is used to manage the clock signals and address signals of each computational macro unit, so that each computational macro unit receives input external signals under the unified synchronous clock drive.

3. The in-memory encryption circuit based on resistive random access memory according to claim 2, characterized in that, The in-memory computing chip includes eight computing macro units, each of which is used to store and process eight bits of each byte of encrypted plaintext or key bit data.

4. The in-memory encryption circuit based on resistive random access memory according to claim 3, characterized in that, Each of the aforementioned computational macrocells includes four resistive random access memory subarrays, four row driving modules, four column driving modules, four sense amplifiers, four logic control modules, one switch submatrix, and one computational macrocell overall control module.

5. An in-memory encryption method based on an in-memory encryption circuit of a resistive random access memory (RRAM), characterized in that, The in-memory encryption method based on the resistive random access memory (RRAM) is implemented using the RRAM-based in-memory encryption circuit according to any one of claims 1-4. All operations of the in-memory encryption method are completed within the in-memory computing chip of the in-memory encryption circuit, and the parallel operation of multiple RRAM subarrays is used to achieve parallelization of logic computation. The in-memory encryption method based on the RRAM includes: S1: Generate plaintext and key, including: A true random number generator in the in-memory encryption circuit is used to generate a random number string in parallel, and the random number string is used as the encrypted plaintext. The Physically Unclonable Function (PUF) response is generated in parallel using the Physically Unclonable Function in the in-memory encryption circuit, and the PUF response is used as the key for the AES encryption algorithm; wherein, both the encrypted plaintext and the key are stored in a resistive random access memory (RRAM) subarray; S2: Perform encryption operations, including: Based on the encrypted plaintext and the key, the AES encryption algorithm's round key application, row shifting, byte substitution, and column obfuscation operations are executed sequentially to complete the encryption and obtain the encrypted data. The encrypted data is stored in the resistive switching memory subarray; S3: Perform decryption operations, including: If decryption is required, the AES decryption algorithm is sequentially executed based on the encrypted data, performing reverse column obfuscation, reverse byte substitution, reverse row shift, and reverse wheel key application operations to complete the decryption and obtain the decrypted data.

6. The in-memory encryption method based on the in-memory encryption circuit of resistive random access memory according to claim 5, characterized in that, Each byte of the encrypted plaintext, consisting of 8 bits, is stored in 8 computational macro modules. The 8 bits of the same byte are located in the same column in the corresponding resistive random access memory (RRAM) subarrays of the 8 computational macro modules. The key and the corresponding encrypted plaintext are located in the same column in the RRAM subarrays.

7. The in-memory encryption method based on the in-memory encryption circuit of resistive random access memory according to claim 5, characterized in that, The application of the round key specifically includes: The key matrix element K stored in the resistive random access memory subarray i,j and plaintext matrix element D i,j As a logic input unit, the corresponding row and column logic reference unit is selected to perform an XOR operation to obtain the operation result; The calculation result is temporarily stored in the sensing amplifier in the form of a voltage signal, and the elements of the state matrix are updated with the calculation result S. i,j .

8. The in-memory encryption method based on the in-memory encryption circuit of resistive random access memory according to claim 7, characterized in that, The row shift specifically includes: The state matrix is ​​periodically shifted according to a preset offset. The first row remains unchanged, the second row shifts each bit to the left by 1 bit, the third row shifts each bit to the left by 2 bits, and the fourth row shifts each bit to the left by 3 bits. The position migration of the state matrix elements is realized through a system-level switch matrix, and the migration result is written back to the corresponding position of the resistive random access memory subarray. The row shift operation supports 32-bit parallel execution.

9. The in-memory encryption method based on the in-memory encryption circuit of resistive random access memory according to claim 8, characterized in that, The byte substitution specifically includes: The S-cell is implemented based on the resistive random access memory subarray. The S-cell is a pre-programmed lookup table structure. The input of the lookup table is encoded by the row address of the memristor cell, and the output is represented by the conductance state of the corresponding memristor cell. The sensing amplifier is used to convert the 8-bit voltage signal of the state matrix element into a row address signal, and the conductance value of the memristor cell corresponding to each resistive random access memory subarray is read in parallel to obtain and temporarily store the 8-bit replacement value. The 8-bit replacement value is written into the target cell column of the resistive random access memory subarray to complete the state matrix element update; wherein, the resistive random access memory subarrays with the same index in the 8 computational macrocells store each bit of the output value, and the memristor cells used are located in the same column. The column obfuscation specifically includes: A reversible linear transformation method is used to combine the state matrix columns of each computational macrounit to achieve ciphertext obfuscation between different columns and between different bits of the same byte. The reversible linear transformation method is implemented by multiplying the data matrix by a preset known matrix in a finite field, and the intermediate results of the transformation process are stored in the resistive random access memory subarray.

10. An in-memory encryption system based on an in-memory encryption circuit of a resistive random access memory (RRAM), characterized in that, The in-memory encryption system based on resistive switching memory includes the in-memory encryption circuit based on resistive switching memory as described in any one of claims 1-4, and the in-memory encryption system based on resistive switching memory operates the in-memory encryption method based on resistive switching memory as described in any one of claims 5-9.

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