Display panel and display device

Abstract

The utility model relates to the technical field of display, and provides a display panel and a display device.The display panel comprises a substrate, a plurality of pixel driving circuit sets, a data line set and a plurality of data connecting lines, the pixel driving circuit sets are distributed in an array mode in the row-column direction, and each pixel driving circuit set comprises a plurality of pixel driving circuit subsets distributed in the row direction; the pixel driving circuit subgroup comprises one or more rows of pixel driving circuits; the data line group and the pixel driving circuit group are correspondingly arranged, the data line group comprises a plurality of data lines, orthographic projections of the data lines on the substrate extend in the column direction, and the data lines in the data line group are located on one side or two sides of the pixel driving circuit group corresponding to the data lines in the row direction; the data connecting lines extend in the row direction, the data lines and the pixel driving circuit subgroups are correspondingly arranged, and the data lines are connected with the pixel driving circuits located in the same row in the corresponding pixel driving circuit subgroups through the data connecting lines. The display panel has a good display effect.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] In the related art, some display panels have high requirements on the luminance of sub-pixel units. The display panels generally drive one or a small number of light-emitting units to emit light through a plurality of pixel driving circuits. In the sub-pixel unit, the plurality of pixel driving circuits can be connected in parallel to drive one or a small number of light-emitting units to emit light. In the display panel, a plurality of pixel driving circuits in the sub-pixel unit need to be correspondingly provided with a plurality of data lines. A large parasitic capacitance is formed between the plurality of data lines and the pixel driving circuits and other signal lines, thereby causing serious horizontal face crosstalk (H-talk) and vertical face crosstalk (V-talk) of the display panel.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. CONTENT OF THE UTILITY MODEL

[0004] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel comprises:

[0005] a substrate substrate;

[0006] a plurality of pixel driving circuit groups, the plurality of pixel driving circuit groups are arrayed along a row-column direction, the pixel driving circuit group comprises a plurality of pixel driving circuit subgroups distributed along a row direction, the pixel driving circuit subgroup comprises one or more rows of pixel driving circuits, each row of pixel driving circuits comprises a plurality of pixel driving circuits distributed along the row direction, and the output ends of the plurality of pixel driving circuits in the same pixel driving circuit subgroup are connected in parallel;

[0007] a data line group, and the data line group is correspondingly provided with the pixel driving circuit group, the data line group comprises a plurality of data lines, the orthogonal projection of the data line on the substrate substrate extends along the column direction, and the orthogonal projection of the data line in the data line group on the substrate substrate is located on one side or both sides of the orthogonal projection of the pixel driving circuit group corresponding to the data line on the substrate substrate in the row direction;

[0008] a plurality of data connection lines, the orthogonal projection of the data connection line on the substrate substrate extends along the row direction, the data line and the pixel driving circuit subgroup are correspondingly provided, and the data line connects the pixel driving circuits in the same row in the pixel driving circuit subgroup corresponding to the data line through the data connection line.

[0009] In an example embodiment of the present disclosure, the display panel further comprises a plurality of constant-voltage signal lines, wherein the plurality of constant-voltage signal lines comprises at least one first constant-voltage signal line, a projection of the first constant-voltage signal line on the substrate substrate extends along a column direction, and the projection of the first constant-voltage signal line on the substrate substrate is located between projections of two adjacent data lines on the substrate substrate.

[0010] In an example embodiment of the present disclosure, the display panel further comprises a plurality of constant-voltage signal lines, wherein the plurality of constant-voltage signal lines comprises at least one second constant-voltage signal line, a projection of the second constant-voltage signal line on the substrate substrate extends along a row direction, and the projection of the second constant-voltage signal line on the substrate substrate is located between projections of two adjacent data connection lines on the substrate substrate.

[0011] In an example embodiment of the present disclosure, the constant-voltage signal line is configured to provide a power signal or an initial signal to the pixel driving circuit.

[0012] In an example embodiment of the present disclosure, the plurality of constant-voltage signal lines comprises at least one first constant-voltage signal line.

[0013] The projection of the first constant-voltage signal line on the substrate substrate extends along a column direction, and the projection of the first constant-voltage signal line on the substrate substrate is located between projections of two adjacent data lines on the substrate substrate.

[0014] At least part of the second constant-voltage signal line is connected to at least part of the first constant-voltage signal line intersecting therewith.

[0015] In an example embodiment of the present disclosure, the display panel further comprises:

[0016] A bridge line extending along a column direction, and the data connection line connects the pixel driving circuit through the bridge line.

[0017] The projection of the second constant-voltage signal line on the substrate substrate intersects with a projection of the bridge line on the substrate substrate, and the part of the second constant-voltage signal line intersecting with the bridge line is located in a different conductive layer from the bridge line.

[0018] In an example embodiment of the present disclosure, the display panel further comprises:

[0019] A first initial signal line, a projection of the first initial signal line on the substrate substrate extends along a row direction, and the first initial signal line is configured to provide a first initial signal to the pixel driving circuit.

[0020] A first initial connection line, a projection of the first initial connection line on the substrate substrate extends along a row direction.

[0021] A first initial bridge line, a projection of which on the substrate substrate extends in a column direction, connects a first initial connection line and a first initial connection line in the same pixel driving circuit group;

[0022] The first initial connection line forms a second constant voltage signal line.

[0023] In an example embodiment of the present disclosure, the data line group includes a first data line and a second data line on the same side of the pixel driving circuit group.

[0024] The data connection line includes a first data connection line and a second data connection line, the first data connection line connects the first data line, and the second data connection line connects the second data line.

[0025] In the connected data connection line and pixel driving circuit, the projection of the first data connection line on the substrate substrate is located between the projection of the pixel driving circuit on the substrate substrate and the projection of the second data connection line on the substrate substrate.

[0026] The projection of the first data connection line on the substrate substrate and the projection of the pixel driving circuit connected thereto on the substrate substrate are arranged opposite in the column direction, and the projection of the first data connection line on the substrate substrate and the projection of the pixel driving circuit connected to the second data connection line on the substrate substrate are not arranged opposite in the column direction.

[0027] The projection of the second data connection line on the substrate substrate and the projection of the pixel driving circuit connected thereto on the substrate substrate are arranged opposite in the column direction, and the projection of the second data connection line on the substrate substrate and the projection of the pixel driving circuit connected to the first data connection line on the substrate substrate are arranged opposite in the column direction.

[0028] In an example embodiment of the present disclosure, the display panel further comprises:

[0029] A first source-drain layer is located on one side of the substrate substrate, and the data connection line is located in the first source-drain layer.

[0030] A second source-drain layer is located on the side of the first source-drain layer away from the substrate substrate, and the data line is located in the second source-drain layer.

[0031] In an example embodiment of the present disclosure, the plurality of pixel driving circuit subgroups in the pixel driving circuit group comprises a first pixel driving circuit subgroup, a second pixel driving circuit subgroup, and a third pixel driving circuit subgroup, the first pixel driving circuit subgroup is configured to provide driving current to a red light emitting unit, the second pixel driving circuit subgroup is configured to provide driving current to a green light emitting unit, and the third pixel driving circuit subgroup is configured to provide driving current to a blue light emitting unit.

[0032] The plurality of data lines in the data line group comprises a first data line, a second data line, and a third data line, the first data line is connected to the pixel driving circuit in the first pixel driving circuit subgroup, the second data line is connected to the pixel driving circuit in the second pixel driving circuit subgroup, and the third data line is connected to the pixel driving circuit in the third pixel driving circuit subgroup.

[0033] In the corresponding pixel driving circuit group and data line group, the orthogonal projection of the first data line and the second data line on the substrate substrate is located on the same side of the orthogonal projection of the pixel driving circuit group on the substrate substrate in the row direction, and the orthogonal projection of the first data line and the third data line on the substrate substrate is located on both sides of the orthogonal projection of the pixel driving circuit group on the substrate substrate in the row direction.

[0034] In an example embodiment of the present disclosure, the pixel driving circuit group is correspondingly provided with two groups of data line groups, and the orthogonal projection of the two groups of data line groups on the substrate substrate is respectively located on both sides of the orthogonal projection of the corresponding pixel driving circuit group on the substrate substrate in the row direction.

[0035] The same kind of data line located on both sides of the pixel driving circuit group is connected by the data connection line.

[0036] In an example embodiment of the present disclosure, the plurality of pixel driving circuit subgroups in the pixel driving circuit group comprises a first pixel driving circuit subgroup, a second pixel driving circuit subgroup, and a third pixel driving circuit subgroup.

[0037] The plurality of data connection lines comprises a first data connection line, a second data connection line, and a third data connection line.

[0038] In the connected data connection line and pixel driving circuit, the orthogonal projection of the second data connection line on the substrate substrate is located on the side away from the orthogonal projection of the pixel driving circuit on the substrate substrate of the orthogonal projection of the first data connection line on the substrate substrate, and the orthogonal projection of the third data connection line on the substrate substrate is located on the side away from the orthogonal projection of the pixel driving circuit on the substrate substrate of the orthogonal projection of the second data connection line on the substrate substrate.

[0039] The display panel further includes:

[0040] A bridge line extends in the column direction, and the data connection line connects the pixel driving circuit through the bridge line, and the bridge line and the data connection line are located in different conductive layers.

[0041] In an example embodiment of the present disclosure, the display panel further includes:

[0042] A first annular power supply line is arranged corresponding to the pixel driving circuit group, and a normal projection of the pixel driving circuit group on the substrate substrate is located in an annular opening of a normal projection of the first annular power supply line on the substrate substrate.

[0043] A second annular power supply line is arranged corresponding to the pixel driving circuit group, and a normal projection of the first annular power supply line on the substrate substrate is located in an annular opening of a normal projection of the second annular power supply line on the substrate substrate.

[0044] The first annular power supply line and the second annular power supply line respectively provide the pixel driving circuit with power signals of opposite polarities.

[0045] In an example embodiment of the present disclosure, the plurality of constant voltage signal lines include at least one third constant voltage signal line, a normal projection of the third constant voltage signal line on the substrate substrate extends in the column direction, the normal projection of the third constant voltage signal line on the substrate substrate and the normal projection of the first constant voltage signal line on the substrate substrate are located on both sides of the normal projection of the pixel driving circuit group on the substrate substrate, and the third constant voltage signal line and the first constant voltage signal line are connected.

[0046] According to an aspect of the present disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0047] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0048] The drawings herein are incorporated into the specification and form part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0049] Figure 1 The structure of the pixel driving circuit in the display panel of the present disclosure is shown in the schematic diagram.

[0050] Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0051] Figure 3 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0052] Figure 4 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0053] Figure 5 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0054] Figure 6 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0055] Figure 7 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0056] Figure 8 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0057] Figure 9 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0058] Figure 10 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 2 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0059] Figure 11 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0060] Figure 12 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0061] Figure 13 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0062] Figure 14 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown.

[0063] Figure 15 A structural layout of a display panel in an exemplary embodiment of the present disclosure is shown. Figure 14 An enlarged view of a partial region AA of a display panel is shown.

[0064] Figure 16A structural schematic diagram of another exemplary embodiment of the display panel of the present disclosure;

[0065] Figure 17 A structural layout of an exemplary embodiment of the display panel of the present disclosure;

[0066] Figure 18 A structural schematic diagram of another exemplary embodiment of the display panel of the present disclosure; Figure 17 An enlarged view of a partial region BB of the display panel shown;

[0067] Figure 19 A structural schematic diagram of another exemplary embodiment of the display panel of the present disclosure;

[0068] Figure 20 A structural layout of an exemplary embodiment of the display panel of the present disclosure;

[0069] Figure 21 A structural schematic diagram of another exemplary embodiment of the display panel of the present disclosure; Figure 20 An enlarged view of a partial region CC of the display panel shown. DETAILED DESCRIPTION

[0070] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, the example embodiments can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the drawings.

[0071] The terms "one", "a", "said" are used to indicate that there is one or more of the elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusion of elements / components / etc. in the resulting system, apparatus, etc. and do not preclude additional elements / components / etc.

[0072] As Figure 1As shown, it is a structural schematic diagram of a pixel driving circuit in a display panel of the present disclosure. The pixel driving circuit comprises a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C1. The first electrode of the driving transistor T3 is connected to a first power supply end VDD, the second electrode is connected to a third node N3, and the gate electrode is connected to a first node N1; the first electrode of the second transistor T2 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate electrode is connected to a gate driving signal end Gate; the first electrode of the first transistor T1 is connected to a data signal end Data, the second electrode is connected to a second node N2, and the gate electrode is connected to the gate driving signal end Gate; the capacitor C is connected between the first node N1 and the second node N2; the first electrode of the fourth transistor T4 is connected to a first initial signal end Vinit1, the second electrode is connected to the first node N1, and the gate electrode is connected to a reset signal end Re; the first electrode of the fifth transistor T5 is connected to a reference voltage end Vref, the second electrode is connected to the second node N2, and the gate electrode is connected to the reset signal end Re; the first electrode of the sixth transistor T6 is connected to the reference voltage end Vref, the second electrode is connected to the second node N2, and the gate electrode is connected to an enable signal end EM; the first electrode of the seventh transistor T7 is connected to the third node N3, the second electrode is connected to a fourth node N4, and the gate electrode is connected to the enable signal end EM; the first electrode of the eighth transistor T8 is connected to a second initial signal end Vinit2, the second electrode is connected to the fourth node N4, and the gate electrode is connected to the reset signal end Re. The first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be N-type transistors. The pixel driving circuit is used for driving a light emitting unit L to emit light, and the light emitting unit L is connected between the fourth node N4 and a second power supply end VSS.

[0073] The driving method of the pixel driving circuit comprises a reset stage, a threshold compensation stage and a light emitting stage. In the reset stage, the reset signal end Re outputs a high level signal, the fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 are turned on, the first initial signal end Vinit1 inputs a first initial signal to the first node N1, the second initial signal end Vinit2 inputs a second initial signal to the fourth node N4, and the reference signal end Vref inputs a reference voltage Vf to the second node N2. In the threshold compensation stage, the gate driving signal end outputs a high level signal, the first transistor T1 and the second transistor T2 are turned on, the first power supply end VDD inputs a compensation voltage Vdd+Vth to the first node N1, wherein Vdd is the voltage of the first power supply end, and Vth is the threshold voltage of the driving transistor, and meanwhile, the data signal end Data inputs a data signal to the second node N2. In the light emitting stage, the enable signal end EM1 outputs a high level signal, the sixth transistor T6 and the seventh transistor T7 are turned on, the reference voltage end inputs the reference voltage Vf to the second node N2, the voltage of the second node N2 changes from Vdata to Vf, Vdata is the voltage of the data signal, and under the coupling effect of the capacitor C, the voltage of the first node N1 changes to Vdd+Vth+Vf-Vdata. According to the output current formula of the driving transistor in the saturation region, the output current I of the driving transistor T3 is (μWCox / 2L)(Vgs-Vth) 2 =(μWCox / 2L)(Vdd+Vth+Vf-Vdata-Vdd-Vth) 2 =(μWCox / 2L)(Vf-Vdata) 2 , wherein I is the output current of the driving transistor, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and Vgs is the gate-source voltage difference of the driving transistor. The pixel driving circuit can avoid the influence of the threshold of the driving transistor on the output current thereof.

[0074] The present example embodiment also provides a display panel, which can comprise a substrate, an active layer, a first gate layer, a second gate layer, a first source-drain layer and a second source-drain layer arranged in sequence. Figures 2-10 As shown in Figure 2 , the structure layout of the display panel in an example embodiment of the present disclosure is shown, Figure 3 As shown in Figure 2 , the structure layout of the active layer in the display panel is shown, Figure 4 As shown in Figure 2 , the structure layout of the first gate layer in the display panel is shown, Figure 5 As shown in Figure 2 , the structure layout of the second gate layer in the display panel is shown, Figure 6 As shown in Figure 2The diagram shown is a structural layout of the first source / drain layer in the display panel. Figure 7 for Figure 2 The diagram shows the structural layout of the second source / drain layer in the display panel. Figure 8 for Figure 2 The diagram shown contains a source layer and a first gate layer in the display panel. Figure 9 for Figure 2 The diagram shown illustrates the structural layout of the display panel, which includes a source layer, a first gate layer, and a second gate layer. Figure 10 for Figure 2 The diagram shown shows the structural layout of the display panel, which includes a source layer, a first gate layer, a second gate layer, and a first source / drain layer.

[0075] The display panel may include multiple pixel driving circuits arranged in an array along the row direction (X) and column direction (Y). The equivalent circuit of the pixel driving circuit can be as follows: Figure 1 As shown.

[0076] like Figure 2 , 3 As shown in Figure 8, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, a nineteenth active section 719, and a twentieth active section 720. The first active portion 71 is used to form the channel region of the first transistor T1, and the second active portion 72 is used to form the channel region of the second transistor T2. The second active portion 72 includes a first sub-active portion 721 and a second sub-active portion 722. The third active portion 73 can be used to form the channel region of the driving transistor T3. The fourth active portion 74 can be used to form the channel region of the fourth transistor T4. The fifth active portion 75 can be used to form the channel region of the fifth transistor T5. The sixth active portion 76 can be used to form the channel region of the sixth transistor T6. The seventh active portion 77 can be used to form the channel region of the seventh transistor T7. The eighth active portion 78 can be used to form the channel region of the eighth transistor T8.

[0077] like Figure 2 , 4 As shown in Figure 8, the first gate layer may include: a first conductive portion 11, a second conductive portion 12, an enable signal line EM, and a gate line Gate. The gate line Gate can be used to provide... Figure 1 The gate drive signal terminal; the enable signal line EM can be used to provide Figure 1The positive projection of the gate line Gate on the substrate and the positive projection of the enable signal line EM on the substrate can extend along the row direction X. Part of the structure of the enable signal line EM is used to form the gate of the sixth transistor T6 and the seventh transistor T7 respectively, part of the structure of the gate line Gate is used to form the gate of the first transistor T1 and the second transistor T2 respectively, the first conductive part 11 is used to form the gate of the driving transistor T3, and part of the structure of the second conductive part 12 is used to form the gate of the fifth transistor T5, the fourth transistor T4 and the eighth transistor T8 respectively. The display panel can use the first gate layer as a mask to perform conductorization processing on the active layer, that is, the region of the active layer covered by the first gate layer can form the channel region of the transistor, and the region of the active layer not covered by the first gate layer forms a conductor structure.

[0078] As shown in Figure 2 、 4 , the positive projection of the enable signal line EM on the substrate and the positive projection of the ninth active part 79 on the substrate overlap. In the light-emitting stage of the pixel driving circuit, the enable signal line EM changes from low to high, and the enable signal line EM can pull up the voltage of the driving transistor T3 through the ninth active part 79.

[0079] As shown in Figure 2 、 5 , the second gate layer can include: a third conductive part 23, a fourth conductive part 24, a fifth conductive part 25, and a first initial connection line 2Vinit1. The positive projection of the third conductive part 23 on the substrate and the positive projection of the first conductive part 11 on the substrate at least partially overlap, and the first conductive part 11 is used to form the first electrode of the capacitor C, and the third conductive part 23 is used to form the second electrode of the capacitor C. The fifth conductive part 25 and the first initial connection line 2Vinit1 are connected, the positive projection of the fifth conductive part 25 on the substrate and the positive projection of the twentieth active part 720 on the substrate overlap, and the fifth conductive part 25 is used to stabilize the voltage of the twentieth active part 720 to reduce the leakage current of the twentieth active part 720 to the source-drain electrode of the second transistor.

[0080] As shown in Figure 2 、 6As shown in Figure 10, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a first initial signal line Vinit1, a second initial signal line Vinit2, a reset signal line Re, a reference voltage line Vref, a gate connection line 3G, and a first initial connection line 2 Vinit1. The orthogonal projections of the first initial signal line Vinit1, the second initial signal line Vinit2, the reset signal line Re, the reference voltage line Vref, the gate connection line 3G, and the first initial connection line 2 Vinit1 on the substrate extend along the row direction X. The first initial signal line Vinit1 is used to provide... Figure 1 The first initial signal terminal and the second initial signal line Vinit2 are used to provide... Figure 1 The second initial signal terminal, the reset signal line Re, is used to provide... Figure 1 The reset signal terminal in the circuit uses the reference voltage line Vref to provide... Figure 1 The reference voltage terminal in the middle, the gate connection line 3G is used to provide Figure 1 The gate drive signal terminal in the middle.

[0081] like Figure 2 , 6 As shown in Figure 10, the first bridging portion 31 is connected to the eighteenth active portion 718 via a via, thereby connecting to the first terminal of the first transistor T1. The second bridging portion 32 is connected to the sixteenth active portion 716 via a via, thereby connecting to the first terminal of the driving transistor T3. The third bridging portion 33 is connected to the fourteenth active portion 714 and the fourth conductive portion 24 via vias, respectively. The first initial signal line Vinit1 is connected to the fourth conductive portion 24 via a via, thereby connecting the first initial signal terminal and the first terminal of the fourth transistor. The fourth bridging portion 34 is connected to the thirteenth active portion 713 via a via. The fifth bridging portion 35 is connected to the twelfth active portion 712, the first conductive portion 11, and the nineteenth active portion 719 via vias, respectively, thereby connecting to the second terminal of the fourth transistor T4, the gate of the driving transistor T3, and the first terminal of the second transistor T2. The sixth bridging part 36 is connected to the eleventh active part 711, the third conductive part 23, and the seventeenth active part 717 through vias, so as to connect the second electrode of the sixth transistor, the second electrode of the capacitor C, and the second electrode of the first transistor T1.

[0082] like Figure 2 , 6 As shown in Figure 10, the second initial signal line Vinit2 can be connected to the fifteenth active section 715 via a via, thereby connecting the second initial signal terminal and the first terminal of the eighth transistor T8. The reference voltage line Vref is connected to the tenth active section 710 via a via, thereby connecting the reference voltage terminal and the first terminal of the fifth transistor T5 and the first terminal of the sixth transistor T6. The gate connection line 3G is connected to the gate line Gate via a via, thereby reducing the resistance of the gate line Gate.

[0083] As shown in Figure 2 , 7 , the second source-drain layer can include a data line Da and a first power supply line VDD. The orthogonal projection of the data line Da and the first power supply line VDD on the substrate extends along the column direction Y, the data line Da is configured to provide a data signal terminal in Figure 1 , and the first power supply line VDD is configured to provide a first power supply terminal in Figure 1 . The data line Da is connected to the first bridge portion 31 through a via hole to connect the first electrode of the first transistor T1. The first power supply line VDD is connected to the second bridge portion 32 through a via hole to connect the first electrode of the driving transistor T3.

[0084] In the related art, some display panels have high requirements on the luminance of the sub-pixel units, and the display panels generally drive one or a small number of light emitting units to emit light through a plurality of pixel driving circuits. For example, as shown in Figure 11 , it is a structural schematic diagram of a sub-pixel unit in an exemplary embodiment of the display panel of the present disclosure. In the sub-pixel unit, a plurality of pixel driving circuits can be connected in parallel to realize that a plurality of pixel driving circuits drive one or a small number of light emitting units to emit light. It should be noted that the present exemplary embodiment only exemplarily shows an embodiment in which two pixel driving circuits drive one light emitting unit, and in other exemplary embodiments, the number of parallel pixel driving circuits can also be other numbers.

[0085] As shown in Figure 12 , it is a structural schematic diagram of a display panel in the related art. The sub-pixel unit in the display panel includes a plurality of arrayed pixel driving circuits Pix, and the pixel driving circuits in the same sub-pixel unit are connected in parallel. For example, the red sub-pixel unit includes a plurality of arrayed first pixel driving circuits Pixr, the green sub-pixel unit includes a plurality of arrayed second pixel driving circuits Pixg, and the blue sub-pixel unit includes a plurality of arrayed third pixel driving circuits Pixb. The plurality of data lines Da in the display panel further include a first data line Dar, a second data line Dag, and a third data line Dab. The first data line Dar is configured to provide driving data signals to the first pixel driving circuits Pixr, the second data line Dag is configured to provide driving data signals to the second pixel driving circuits Pixg, and the third data line Dab is configured to provide driving data signals to the third pixel driving circuits Pixb. As shown in Figure 12As shown, each column of pixel driving circuit is correspondingly provided with a data line, and a parasitic capacitor is formed between the data line Da and the first node N1 and the second node N2 in the pixel driving circuit Pix. Since in the same sub-pixel unit, multiple data lines form parasitic capacitors with the first node N1 and the second node N2 in the pixel driving circuit Pix corresponding to the data lines, the parasitic capacitors accumulated by the multiple data lines are large, which causes the vertical crosstalk of the display panel to be relatively serious. Meanwhile, the parasitic capacitors formed by the multiple data lines and the power lines, the initial signal lines and other signal lines are large, which causes the horizontal crosstalk of the display panel to be relatively serious.

[0086] Based on this, the present example embodiment provides a display panel, as shown in Figure 13 As shown, the display panel is a structural schematic diagram of an example embodiment of the display panel of the present disclosure. The display panel comprises a substrate, a plurality of pixel driving circuit groups Pz, a data line group Daz, and a plurality of data connection lines Dal. The plurality of pixel driving circuit groups Pz are arrayed along a row direction X and a column direction Y. The pixel driving circuit group Pz comprises a plurality of pixel driving circuit subgroups Piz arrayed along the row direction X. The pixel driving circuit subgroup Piz comprises one or more rows of pixel driving circuits Pix. Each row of pixel driving circuits comprises a plurality of pixel driving circuits Pix arrayed along the row direction X. The output ends of the plurality of pixel driving circuits in the same pixel driving circuit subgroup Piz are connected in parallel. The data line group Daz and the pixel driving circuit group are correspondingly provided. The data line group Daz comprises a plurality of data lines Da. The orthogonal projection of the data line Da on the substrate extends along the column direction Y. The orthogonal projection of the data line Da in the data line group Daz on the substrate is located on one side of the orthogonal projection of the pixel driving circuit group Pz corresponding to the data line Da on the substrate in the row direction. The orthogonal projection of the plurality of data connection lines Dal on the substrate extends along the row direction X. The data line Da and the pixel driving circuit subgroup Piz are correspondingly provided. The data line Da connects the pixel driving circuits Pix in the same row in the pixel driving circuit subgroup Piz corresponding to the data line Da through the data connection line Dal.

[0087] The present example embodiment sets the data line group Daz for providing data signals to the pixel driving circuit group Pz on the same side of the pixel driving circuit group Pz. This setting can reduce the parasitic capacitor between the data line and the pixel driving circuit, thereby improving the problem of vertical crosstalk of the display panel. Meanwhile, this setting can reduce the number of intersection points of the data line and the power line, the initial signal line and other signal lines, thereby improving the problem of horizontal crosstalk of the display panel.

[0088] In the present example embodiment, as shown in Figure 13As shown in FIG. 1, the display panel further includes a plurality of constant-voltage signal lines Lh, which include at least one first constant-voltage signal line Lh1. A projection of the first constant-voltage signal line Lh1 on the substrate substrate extends along the column direction Y, and the projection of the first constant-voltage signal line Lh1 on the substrate substrate is located between the projections of two adjacent data lines Da on the substrate substrate. The first constant-voltage signal line Lh1 can shield the signal crosstalk between the two adjacent data lines Da.

[0089] In the example embodiment, as shown in FIG. 1, Figure 13 As shown in FIG. 1, the display panel further includes a plurality of constant-voltage signal lines Lh, which include at least one second constant-voltage signal line Lh2. A projection of the second constant-voltage signal line Lh2 on the substrate substrate extends along the row direction X, and the projection of the second constant-voltage signal line Lh2 on the substrate substrate is located between the projections of two adjacent data connection lines Dal on the substrate substrate. The second constant-voltage signal line Lh2 can shield the signal crosstalk between the two adjacent data connection lines Dal.

[0090] In the example embodiment, as shown in FIG. 1, Figure 13 As shown in FIG. 1, the constant-voltage signal line Lh can be used to provide a power signal or an initial signal to the pixel driving circuit. For example, the constant-voltage signal line Lh can be connected to any one of the first power line VDD, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 in FIG. 1. Figure 2

[0091] In the example embodiment, as shown in FIG. 1, Figure 13 As shown in FIG. 1, the plurality of constant-voltage signal lines Lh further include at least one third constant-voltage signal line Lh3. A projection of the third constant-voltage signal line Lh3 on the substrate substrate extends along the column direction Y, and the projection of the third constant-voltage signal line Lh3 on the substrate substrate and the projection of the first constant-voltage signal line Lh1 on the substrate substrate are located on both sides of the projection of the pixel driving circuit group Pz on the substrate substrate, and the third constant-voltage signal line Lh3 and the first constant-voltage signal line Lh1 are connected. On the one hand, the third constant-voltage signal line Lh3 and the first constant-voltage signal line Lh1 can make the pixel driving circuit group Pz have a more uniform electric field environment, thereby improving the display uniformity of the display panel. On the other hand, the third constant-voltage signal line Lh3 can further reduce the resistance of the constant-voltage signal line, i.e., the resistance of the power line and the initial signal line.

[0092] In the example embodiment, as shown in FIG. 1, Figure 13 ​As shown, at least part of the second constant-voltage signal line Lh2 can be connected to at least part of the first constant-voltage signal line Lh1 intersecting therewith, and at least part of the second constant-voltage signal line Lh2 can be connected to at least part of the third constant-voltage signal line Lh3 intersecting therewith. That is, the first constant-voltage signal line Lh1, the second constant-voltage signal line Lh2, and the third constant-voltage signal line Lh3 can form a mesh structure, which can further reduce the resistance of the constant-voltage signal line.

[0093] In the present exemplary embodiment, as shown in Figure 13 As shown, the data line group Daz includes a first data line Da1 and a second data line Da2 located on the same side of the pixel driving circuit group; the plurality of data connection lines include a first data connection line Dal1 and a second data connection line Dal2, the first data connection line Dal1 is connected to the first data line Da1, and the second data connection line Dal2 is connected to the second data line Da2; in the connected data connection line Dal and the pixel driving circuit Pix, the orthogonal projection of the first data connection line Dal1 on the substrate substrate is located between the orthogonal projection of the pixel driving circuit Pix on the substrate substrate and the orthogonal projection of the second data connection line Dal2 on the substrate substrate; the orthogonal projection of the first data connection line Dal1 on the substrate substrate and the orthogonal projection of the pixel driving circuit Pix connected thereto on the substrate substrate are oppositely arranged in the column direction Y, and the orthogonal projection of the first data connection line Dal1 on the substrate substrate and the orthogonal projection of the pixel driving circuit connected to the second data connection line Dal2 on the substrate substrate are not oppositely arranged in the column direction; the orthogonal projection of the second data connection line Dal2 on the substrate substrate and the orthogonal projection of the pixel driving circuit connected thereto on the substrate substrate are oppositely arranged in the column direction Y, and the orthogonal projection of the second data connection line Dal2 on the substrate substrate and the orthogonal projection of the pixel driving circuit connected to the first data connection line Dal1 on the substrate substrate are oppositely arranged in the column direction. The orthogonal projection of structure A on the substrate substrate and the orthogonal projection of structure B on the substrate substrate are oppositely arranged in the column direction, which can be understood as the overlapping of the covered area of the orthogonal projection of structure A on the substrate substrate along the column direction and the covered area of the orthogonal projection of structure B on the substrate substrate along the column direction, and correspondingly, the orthogonal projection of structure A on the substrate substrate and the orthogonal projection of structure B on the substrate substrate are not oppositely arranged in the column direction, which can be understood as the non-overlapping of the covered area of the orthogonal projection of structure A on the substrate substrate along the column direction and the covered area of the orthogonal projection of structure B on the substrate substrate along the column direction. On the one hand, this arrangement can reduce the length of the first data connection line Dal1, thereby reducing the signal interference between the first data connection line Dal1 and the second data connection line Dal2, and on the other hand, this arrangement can avoid short-circuiting of the first data connection line Dal1 and the second data connection line Dal2.

[0094] As shown in Figure 14 , 15As shown, Figure 14 A structure layout of an exemplary embodiment of the display panel of the present disclosure is shown, Figure 15 As shown, Figure 14 An enlarged view of a local area AA of the display panel is shown. The structure layout of the pixel driving circuit in the display panel can be as shown, Figure 2 As shown, the structure layout only shows part of the structure layout in the pixel driving circuit. The display panel can further include a first initial signal line Vinit1, a first initial connection line 2Vinit1, and a first initial bridge line 1Vinit1. The orthogonal projection of the first initial signal line Vinit1 and the first initial connection line 2Vinit1 on the substrate substrate extends along the row direction X. The orthogonal projection of the first initial bridge line 1Vinit1 on the substrate substrate extends along the column direction Y, and the first initial bridge line 1Vinit1 connects a plurality of first initial connection lines Vinit1 and a plurality of first initial connection lines 2Vinit1 in the same pixel driving circuit group; wherein the first initial connection line 2Vinit1 can form a second constant voltage signal line Lh2.

[0095] As shown, Figure 14 , 15 The display panel can further include a first annular power supply line VDDh and a second annular power supply line VSSh. The first annular power supply line VDDh and the pixel driving circuit group Pz are correspondingly arranged, and the orthogonal projection of the pixel driving circuit group Pz on the substrate substrate is located within the annular opening of the orthogonal projection of the corresponding first annular power supply line VDDh on the substrate substrate. The second annular power supply line VSSh and the pixel driving circuit group Pz are correspondingly arranged, and the orthogonal projection of the first annular power supply line VDDh on the substrate substrate is located within the annular opening of the orthogonal projection of the second annular power supply line VSSh on the substrate substrate. The first annular power supply line VDDh can be connected to the corresponding first power supply line VDD of the pixel driving circuit, and the second annular power supply line VSSh can be connected to the common electrode layer in the display panel. The common electrode layer can be located on the side of the light emitting unit away from the substrate substrate, and the common electrode layer can provide Figure 1 the second power supply end in the display panel.

[0096] As shown, Figure 14 , 15 The first constant voltage signal line Lh1 can be connected to the first annular power supply line VDDh through a via. Another second constant voltage signal line Lh2 can be connected to the first constant voltage signal line Lh1. The second constant voltage signal line Lh2 can be located in the first gate layer, and the second constant voltage signal line Lh2 can be connected to the first constant voltage signal line Lh1 located in the second source-drain layer through the first bridge line 3L in the first source-drain layer.

[0097] As shown, Figure 14 , 15As shown, the display panel can further include a second initial bridge line 1Vinit2, a reference voltage bridge line 1Vref, and a projection of the second initial bridge line 1Vinit2, the reference voltage bridge line 1Vref on the substrate in the column direction Y extends. The second initial bridge line 1Vinit2 can be connected to multiple second initial signal lines Vinit2 in the same pixel driving circuit group, and the first initial bridge line 1Vinit1 can be connected to multiple first initial signal lines Vinit1 in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group.

[0098] As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group. Figure 14 、 15 As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group.

[0099] In the same pixel driving circuit sub-group Piz, the fourth bridge part 34 in the same row of pixel driving circuits can be connected by a bridge line in the present exemplary embodiment.

[0100] As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group. Figure 16 As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group.

[0101] As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group. Figure 17 、 18 As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group. Figure 17 As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group. Figure 18 As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group. Figure 17 As shown in FIG. 1A, the display panel can further include a first initial bridge line 1Vinit1, a second initial bridge line 1Vinit2, and a reference voltage bridge line 1Vref. The first initial bridge line 1Vinit1 and the second initial bridge line 1Vinit2 can be connected to multiple initial signal lines Vinit in the same pixel driving circuit group. The reference voltage bridge line 1Vref can be connected to multiple reference voltage lines Vref in the same pixel driving circuit group. Figure 2As shown, the structure layout only shows part of the structure layout in the pixel driving circuit. The plurality of pixel driving circuit subgroups Piz in the pixel driving circuit group Pz include a first pixel driving circuit subgroup Piz1, a second pixel driving circuit subgroup Piz2, and a third pixel driving circuit subgroup Piz3; the plurality of data connection lines Dal include a first data connection line Dal1, a second data connection line Dal2, and a third data connection line Dal3; in the connected data connection line Dal and pixel driving circuit, the orthographic projection of the second data connection line Dal2 on the substrate substrate is located on the side away from the orthographic projection of the pixel driving circuit on the substrate substrate of the orthographic projection of the first data connection line Dal1 on the substrate substrate, and the orthographic projection of the third data connection line Dal3 on the substrate substrate is located on the side away from the orthographic projection of the pixel driving circuit on the substrate substrate of the orthographic projection of the second data connection line Dal2 on the substrate substrate; the display panel further includes: a bridge line Daq, the bridge line Daq extends along the column direction Y, the data connection line Dal connects the pixel driving circuit through the bridge line Daq, and the bridge line Daq and the data connection line Dal are located in different conductive layers. This setting can avoid short circuit between different data connection lines Dal.

[0102] As shown in the present exemplary embodiment, Figure 17 , 18 The bridge line Daq can be located in the active layer.

[0103] It should be understood that in other exemplary embodiments, the orthographic projection of the data line Da in the data line group Daz on the substrate substrate can also be located on both sides of the orthographic projection of the corresponding pixel driving circuit group Pz on the substrate substrate in the row direction. As Figure 19As shown, it is a structural schematic diagram of another exemplary embodiment of the display panel of the present disclosure. The plurality of pixel driving circuit subgroups in the pixel driving circuit group Pz include a first pixel driving circuit subgroup Piz1, a second pixel driving circuit subgroup Piz2, and a third pixel driving circuit subgroup Piz3. The first pixel driving circuit subgroup Piz1 is configured to provide driving current to red light emitting units, the second pixel driving circuit subgroup Piz2 is configured to provide driving current to green light emitting units, and the third pixel driving circuit subgroup Piz3 is configured to provide driving current to blue light emitting units. The plurality of data lines in the data line group Daz include a first data line Da1, a second data line Da2, and a third data line Da3. The first data line Da1 is connected to the pixel driving circuits in the first pixel driving circuit subgroup Piz1, the second data line Da2 is connected to the pixel driving circuits in the second pixel driving circuit subgroup Piz2, and the third data line Da3 is connected to the pixel driving circuits in the third pixel driving circuit subgroup Piz3. In the corresponding pixel driving circuit group and data line group, the orthographic projection of the first data line Da1 and the second data line Da2 on the substrate is located on the same side of the orthographic projection of the pixel driving circuit group Pz on the substrate in the row direction X, and the orthographic projection of the first data line Da1 and the third data line Da3 on the substrate is located on both sides of the orthographic projection of the pixel driving circuit group Pz on the substrate in the row direction. Since the blue light emitting unit is more sensitive, the third data line Da3 connected to the third pixel driving circuit is placed on one side of the pixel driving circuit group Pz, which can reduce the interference of other data lines on the third data line Da3.

[0104] As shown in Figure 20 , 21 , Figure 20 , it is a structural layout of an exemplary embodiment of the display panel of the present disclosure, Figure 21 , Figure 20 , it is an enlarged view of a local area CC of the display panel. The structural layout of the pixel driving circuit in the display panel can be as shown in Figure 2 , Figure 14 , 15 . The difference between the display panels shown in

[0105] As shown in Figures 3-21 , the black square drawn on the side of the first source-drain layer away from the substrate represents a via connecting other levels facing the substrate on the side of the first source-drain layer; the black square drawn on the side of the second source-drain layer away from the substrate represents a via connecting other levels facing the substrate on the side of the second source-drain layer. Different vias represented by black squares at different positions can penetrate different insulating layers.

[0106] It should be noted that the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto, for example: the width-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure, and the drawings described in the present disclosure are only schematic diagrams. In addition, the adjectives first, second, etc. are only used to define different structure names, and do not have the meaning of a specific order, and the same structure layer can be formed by the same patterning process. In the present exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as that the orthographic projection of the structure on the substrate extends linearly or bends along the direction.

[0107] In the present exemplary embodiment, the display panel can be a spliced screen. The present exemplary embodiment also provides a display device, which comprises the display panel described above. The display device can be a mobile phone, a tablet computer, a television, etc.

[0108] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the content of the present disclosure. This application is intended to cover any variations, uses or adaptive changes of the present disclosure that follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field of the present disclosure not disclosed by the present disclosure. The specification and examples are only considered as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0109] It should be understood that the present disclosure is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A display panel, wherein, The display panel comprises: a substrate substrate; a plurality of pixel driving circuit groups, the plurality of pixel driving circuit groups are arrayed along a row-column direction, the pixel driving circuit group comprises a plurality of pixel driving circuit subgroups distributed along a row direction, the pixel driving circuit subgroup comprises one or more rows of pixel driving circuits, each row of pixel driving circuits comprises a plurality of pixel driving circuits distributed along the row direction, and the output ends of the plurality of pixel driving circuits in the same pixel driving circuit subgroup are connected in parallel; a data line group corresponding to the pixel driving circuit group, the data line group comprises a plurality of data lines, the orthogonal projection of the data line on the substrate substrate extends along the column direction, and the orthogonal projection of the data line in the data line group on the substrate substrate is located on one side or both sides of the orthogonal projection of the pixel driving circuit group corresponding to the data line on the substrate substrate in the row direction; a plurality of data connection lines, the orthogonal projection of the data connection line on the substrate substrate extends along the row direction, the data line and the pixel driving circuit subgroup correspond to each other, and the data line is connected to the pixel driving circuit in the same row in the pixel driving circuit subgroup corresponding to the data line through the data connection line.

2. The display panel of claim 1, wherein, The display panel further comprises a plurality of constant voltage signal lines, and the plurality of constant voltage signal lines comprise at least one first constant voltage signal line, the orthogonal projection of the first constant voltage signal line on the substrate substrate extends along the column direction, and the orthogonal projection of the first constant voltage signal line on the substrate substrate is located between the orthogonal projections of adjacent two data lines on the substrate substrate.

3. The display panel of claim 1, wherein, The display panel further comprises a plurality of constant voltage signal lines, and the plurality of constant voltage signal lines comprise at least one second constant voltage signal line, the orthogonal projection of the second constant voltage signal line on the substrate substrate extends along the row direction, and the orthogonal projection of the second constant voltage signal line on the substrate substrate is located between the orthogonal projections of adjacent two data connection lines on the substrate substrate.

4. The display panel of claim 2 or 3, wherein, The constant voltage signal line is used for providing a power supply signal or an initial signal to the pixel driving circuit.

5. The display panel of claim 3, wherein, The plurality of constant voltage signal lines comprise at least one first constant voltage signal line; The orthogonal projection of the first constant voltage signal line on the substrate substrate extends along the column direction, and the orthogonal projection of the first constant voltage signal line on the substrate substrate is located between the orthogonal projections of adjacent data lines on the substrate substrate; At least part of the second constant voltage signal line is connected to at least part of the first constant voltage signal line intersecting therewith.

6. The display panel of claim 3, wherein, The display panel further comprises: a bridge line extending along the column direction, and the data connection line connects the pixel driving circuit through the bridge line; The orthogonal projection of the second constant voltage signal line on the substrate substrate intersects with the orthogonal projection of the bridge line on the substrate substrate, and the part of the second constant voltage signal line intersecting with the bridge line is located in different conductive layers from the bridge line.

7. The display panel of claim 3, wherein, The display panel further comprises: a first initial signal line, the orthogonal projection of the first initial signal line on the substrate substrate extends along the row direction, and the first initial signal line is used for providing a first initial signal to the pixel driving circuit; a first initial connection line, the orthogonal projection of the first initial connection line on the substrate substrate extends along the row direction; A first initial bridge line, a projection of which on the substrate substrate extends in a column direction, connects a first initial connection line and a first initial connection line in the same pixel drive circuit group; The first initial connection line forms a second constant voltage signal line.

8. The display panel of claim 1, wherein, The data line group includes a first data line and a second data line on the same side of the pixel drive circuit group; The data line group includes a first data line and a second data line on the same side of the pixel drive circuit group; The first data line is connected to the first data line, and the second data line is connected to the second data line; The first data line is connected to the first data line, and the second data line is connected to the second data line; The first data line is connected to the first data line, and the second data line is connected to the second data line; 9. The display panel of claim 1, wherein, The first data line is connected to the first data line, and the second data line is connected to the second data line; The display panel further comprises: A first source drain layer is located on one side of the substrate substrate, and the data connection line is located in the first source drain layer; 10. The display panel of claim 1, wherein, A second source drain layer is located on the side of the first source drain layer away from the substrate substrate, and the data line is located in the second source drain layer. The pixel drive circuit group includes a first pixel drive circuit sub-group, a second pixel drive circuit sub-group, and a third pixel drive circuit sub-group, the first pixel drive circuit sub-group is used to provide driving current to the red light emitting unit, the second pixel drive circuit sub-group is used to provide driving current to the green light emitting unit, and the third pixel drive circuit sub-group is used to provide driving current to the blue light emitting unit; The data line group includes a first data line, a second data line, and a third data line, the first data line is connected to the pixel drive circuit in the first pixel drive circuit sub-group, the second data line is connected to the pixel drive circuit in the second pixel drive circuit sub-group, and the third data line is connected to the pixel drive circuit in the third pixel drive circuit sub-group; The first data line and the second data line are located on the same side of the orthogonal projection of the pixel driving circuit group on the substrate in the row direction.

11. The display panel of claim 1, wherein, The orthogonal projection of the two groups of data line groups on the substrate is located on the two sides of the orthogonal projection of the corresponding pixel driving circuit group on the substrate in the row direction. The same kind of data line located on the two sides of the pixel driving circuit group is connected through the data connection line.

12. The display panel of claim 11, wherein, The pixel driving circuit group includes a first pixel driving circuit sub-group, a second pixel driving circuit sub-group, and a third pixel driving circuit sub-group. The data connection line includes a first data connection line, a second data connection line, and a third data connection line. The orthogonal projection of the second data connection line on the substrate is located on the side away from the orthogonal projection of the pixel driving circuit on the substrate from the orthogonal projection of the first data connection line on the substrate. The display panel further includes: The bridge line is extended in the column direction, and the data connection line connects the pixel driving circuit through the bridge line.

13. The display panel of claim 1, wherein, The display panel further includes: The first annular power line is arranged corresponding to the pixel driving circuit group, and the orthogonal projection of the pixel driving circuit group on the substrate is located in the annular opening of the orthogonal projection of the first annular power line on the substrate. The second annular power line is arranged corresponding to the pixel driving circuit group, and the orthogonal projection of the first annular power line on the substrate is located in the annular opening of the orthogonal projection of the second annular power line on the substrate. The first annular power line and the second annular power line respectively provide the pixel driving circuit with power signals of opposite polarities.

14. The display panel of claim 2, wherein, The constant voltage signal line includes at least one third constant voltage signal line, and the orthogonal projection of the third constant voltage signal line on the substrate is extended in the column direction.

15. A display device, wherein, The display device includes the display panel of any one of claims 1-14.

Images