Pixel circuit and display device

Abstract

The invention relates to a pixel circuit and a display device. The pixel circuit includes: a first driving transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a write transistor configured to apply a data voltage to a second node; a first initialization transistor configured to apply an initialization voltage to the first node; a second initialization transistor configured to apply an initialization voltage to a third node; a second driving transistor including a control electrode connected to a fourth node, a first electrode receiving a first power supply voltage, and a second electrode connected to a fifth node; a third initialization transistor configured to apply an initialization voltage to a fourth node; a first capacitor configured to apply a sweep signal to the first node; a second capacitor including a first electrode and a second electrode connected to the third node and the fourth node; and a light emitting element configured to emit light based on the driving current.

Description

Technical Field

[0001] The embodiments of this disclosure relate to pixel circuits and display devices including such pixel circuits. Background Technology

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver, a data driver, and a drive controller. The gate driver outputs gate signals to the gate lines, the data driver outputs data voltages to the data lines, and the drive controller controls the gate driver and the data driver.

[0003] Conventional pixel circuits that are driven by pulse width modulation and perform internal compensation of the threshold voltage may include nineteen or more transistors and three or more capacitors, making it difficult to apply pixel circuits to ultra-high resolution display devices due to integration limitations.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background technology of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] An aspect of the embodiments of this disclosure relates to a pixel circuit driven by a pulse width modulation method, performing internal compensation of a threshold voltage, and including a small number of transistors, the pixel circuit being suitable for ultra-high resolution display devices.

[0006] Embodiments of this disclosure also relate to a display device including the pixel circuit. According to some embodiments of this disclosure, a pixel circuit is provided comprising: a first driving transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a write transistor configured to apply a data voltage to the second node in response to a compensation gate signal; a first initialization transistor configured to apply an initialization voltage to the first node in response to a first initialization gate signal; a second initialization transistor configured to apply an initialization voltage to the third node in response to a second initialization gate signal; a second driving transistor including a control electrode connected to a fourth node, a first electrode receiving a first power supply voltage, and a second electrode connected to a fifth node, and configured to apply a driving current; a third initialization transistor configured to apply an initialization voltage to the fourth node in response to a third initialization gate signal; a first capacitor configured to apply a sweep signal to the first node; a second capacitor including a first electrode connected to the third node and a second electrode connected to the fourth node; and a light-emitting element configured to emit light based on the driving current.

[0007] In some embodiments, the width-to-length (W / L) ratio of the second driving transistor may vary based on the color of the light-emitting element.

[0008] In some embodiments, the pixel circuit may further include: a first emission control transistor configured to apply a first power supply voltage to a second node in response to a first emission signal; and a second emission control transistor configured to apply a drive current to a light-emitting element in response to a second emission signal.

[0009] In some embodiments, the pixel circuit may further include: a first compensation transistor configured to connect a first node and a third node in response to a compensation gate signal; and a second compensation transistor configured to connect a fourth node and a fifth node in response to a second compensation gate signal.

[0010] In some embodiments, the pixel circuit may further include: a fourth initialization transistor configured to apply a second power supply voltage, different from the first power supply voltage, to the first electrode of the light-emitting element in response to a second initialization gate signal.

[0011] In some embodiments, the write frame period during which the pixel circuit is driven may include an application period and a first transmit period, and during the application period, a data voltage may be applied to the first node and an initialization voltage may be applied to the fourth node.

[0012] In some embodiments, during the first sub-transmission period of the first transmission period, the first transmission signal may have an inactive level, the second transmission signal may have an inactive level, the second initialization gate signal may have an active level, and the sweep signal may have a first voltage level.

[0013] In some embodiments, during a second sub-transmission period following a first sub-transmission period of the first transmission period, the first transmission signal may have an active level, the second transmission signal may have an inactive level, and the sweep signal may have a second voltage level higher than the first voltage level.

[0014] In some embodiments, during a third sub-transmission period following the second sub-transmission period of the first transmission period, the first transmission signal may have an activation level, the second transmission signal may have an activation level, and the sweep signal may decrease from the second voltage level to a third voltage level lower than the second voltage level.

[0015] In some embodiments, the write frame period may further include a second transmission period following the first transmission period, during which the light-emitting element emits light, and during the second transmission period, an initialization voltage may be applied to the fourth node, and the light-emitting element may emit light.

[0016] In some embodiments, the frame period in which the pixel circuit is driven may include: a write frame in which a data voltage is applied and the light-emitting element emits light; and a hold frame in which no data voltage is applied and the light-emitting element emits light.

[0017] In some embodiments, the pixel circuit may further include: a first compensation transistor configured to connect a first node and a third node in response to a compensation gate signal; and a second compensation transistor configured to connect a fourth node and a fifth node in response to a second compensation gate signal, wherein the write frame period during which the pixel circuit is driven includes an initialization period, a compensation period, an application period, and a first transmit period, and wherein, during the initialization period, the first initialization gate signal has an active level, the second initialization gate signal has an inactive level, the third initialization gate signal has an active level, and the second compensation gate signal has an inactive level.

[0018] In some embodiments, during the compensation period following the initialization period, the third initialization gate signal may have an inactive level, and the second compensation gate signal may have an active level.

[0019] In some embodiments, a data voltage may be applied to the first node during the application period following the compensation period.

[0020] In some embodiments, during a first sub-transmission period of a first transmission period following the applied period, the first transmission signal may have an inactive level, the second transmission signal may have an inactive level, the second initialization gate signal may have an active level, and the sweep signal may have a first voltage level.

[0021] In some embodiments, during a second sub-transmission period following a first sub-transmission period of the first transmission period, the first transmission signal may have an active level, the second transmission signal may have an inactive level, and the sweep signal may have a second voltage level higher than the first voltage level.

[0022] In some embodiments, during a third sub-transmission period following the second sub-transmission period of the first transmission period, the first transmission signal may have an activation level, the second transmission signal may have an activation level, and the sweep signal may decrease from the second voltage level to a third voltage level lower than the first voltage level.

[0023] In some embodiments, the write frame period may further include a second transmission period following the first transmission period, during which the light-emitting element may emit light, and during the second transmission period, an initialization voltage may be applied to the fourth node, and the light-emitting element emits light.

[0024] According to some embodiments of this disclosure, a display device is provided, comprising: a display panel including pixel circuitry; a gate driver configured to apply a gate signal to the display panel; a data driver configured to apply a data voltage to the display panel; an emitter driver configured to apply an emitter signal to the display panel; and a drive controller configured to control the gate driver, the data driver, and the emitter driver. The pixel circuitry includes: a first drive transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a write transistor configured to apply a data voltage to a second node in response to a compensation gate signal; and a first initialization transistor configured to apply a first initialization signal in response to a first initialization signal. An initialization gate signal applies an initialization voltage to a first node; a second initialization transistor is configured to apply an initialization voltage to a third node in response to the second initialization gate signal; a second driving transistor includes a control electrode connected to a fourth node, a first electrode receiving a first power supply voltage, and a second electrode connected to a fifth node, and the second driving transistor is configured to apply a driving current; a third initialization transistor is configured to apply an initialization voltage to a fourth node in response to a third initialization gate signal; a first capacitor is configured to apply a sweep frequency signal to the first node; a second capacitor includes a first electrode connected to the third node and a second electrode connected to the fourth node; and a light-emitting element is configured to emit light based on the driving current.

[0025] In some embodiments, the write frame period during which the pixel circuit is driven may include an application period, a first emission period, and a second emission period. During the application period, a data voltage may be applied to a first node, and an initialization voltage may be applied to a fourth node. During the first emission period, the light-emitting element emits light, and during the second emission period, the initialization voltage is applied to the fourth node, and the light-emitting element emits light.

[0026] According to some embodiments of this disclosure, an electronic device (or electronic apparatus) is provided, comprising: a display panel including pixel circuitry; a gate driver configured to apply a gate signal to the display panel; a data driver configured to apply a data voltage to the display panel; a transmit driver configured to apply a transmit signal to the display panel; a drive controller configured to control the gate driver, data driver, and transmit driver based on an input control signal; and a processor configured to output the input control signal, wherein the pixel circuitry includes: a first drive transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a write transistor configured to apply a data voltage to a second node in response to a compensation gate signal; and a first... An initialization transistor is configured to apply an initialization voltage to a first node in response to a first initialization gate signal; a second initialization transistor is configured to apply an initialization voltage to a third node in response to a second initialization gate signal; a second driving transistor includes a control electrode connected to a fourth node, a first electrode receiving a first power supply voltage, and a second electrode connected to a fifth node, and the second driving transistor is configured to apply a driving current; a third initialization transistor is configured to apply an initialization voltage to a fourth node in response to a third initialization gate signal; a first capacitor is configured to apply a sweep frequency signal to the first node; a second capacitor includes a first electrode connected to the third node and a second electrode connected to the fourth node; and a light-emitting element is configured to emit light based on the driving current.

[0027] As described above, the W / L ratio of the second driving transistor included in the pixel circuit can vary depending on the color of the light-emitting element. Therefore, the pixel circuit may not include a transistor for applying a constant current voltage. Furthermore, the display device may not include a line for applying the constant current voltage. Therefore, the integration density of the display device including the pixel circuit can be improved. Additionally, the power consumption of the display device including the pixel circuit can be reduced.

[0028] Furthermore, in a display device including pixel circuitry, the first transmission signal can have an activation level before the second transmission signal. Therefore, a first power supply voltage can be applied to the first electrode of the first driving transistor included in the pixel circuit before the first driving transistor is turned on. This reduces the impact of the hysteresis characteristics of the first driving transistor.

[0029] Furthermore, the pixel circuit can emit light multiple times during the write frame period. Therefore, the emission efficiency of the pixel circuit can be improved (e.g., increased). Additionally, flickering in display devices including pixel circuits can be reduced. Attached Figure Description

[0030] The illustrative, non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0031] Figure 1 This is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0032] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 The circuit diagram of the pixel circuit of the display panel.

[0033] Figure 3 This illustrates the application of [something] during the write frame period according to some embodiments of the present disclosure. Figure 2 Timing diagram of the input signals of the pixel circuit.

[0034] Figure 4 This illustrates the application of [something] during the write frame period according to some embodiments of the present disclosure. Figure 2 Timing diagram of the input signals of the pixel circuit.

[0035] Figure 5 This illustrates some embodiments according to the present disclosure. Figure 1 A conceptual diagram of the driving frequency of the display panel.

[0036] Figure 6 This illustrates the application of [something] during the hold frame period according to some embodiments of the present disclosure. Figure 2 Timing diagram of the input signals of the pixel circuit.

[0037] Figure 7 This illustrates the application of [something] during the hold frame period according to some embodiments of the present disclosure. Figure 2 Timing diagram of the input signals of the pixel circuit.

[0038] Figure 8 This illustrates some embodiments according to the present disclosure. Figure 1 The circuit diagram of the pixel circuit of the display panel.

[0039] Figure 9 This illustrates the application of [something] during the write frame period according to some embodiments of the present disclosure. Figure 8 Timing diagram of the input signals of the pixel circuit.

[0040] Figure 10 This illustrates the application of [something] during the write frame period according to some embodiments of the present disclosure. Figure 8 Timing diagram of the input signals of the pixel circuit.

[0041] Figure 11 This illustrates the application of [something] during the hold frame period according to some embodiments of the present disclosure. Figure 8 Timing diagram of the input signals of the pixel circuit.

[0042] Figure 12This illustrates the application of [something] during the hold frame period according to some embodiments of the present disclosure. Figure 8 Timing diagram of the input signals of the pixel circuit.

[0043] Figure 13 This illustrates the application of some embodiments of the present disclosure to... Figure 1 The timing diagram of the transmission signal of the transmission line of the display device.

[0044] Figure 14 This is a block diagram illustrating an electronic device according to some embodiments of the present disclosure.

[0045] Figure 15 This illustrates some embodiments according to the present disclosure. Figure 14 The diagram shows an example of an electronic device implemented as a smartphone.

[0046] Figure 16 This illustrates some embodiments according to the present disclosure. Figure 14 The diagram shows an example of an electronic device implemented as a smartwatch. Detailed Implementation

[0047] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be embodied in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques that are not essential for those skilled in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore redundant descriptions may not be repeated.

[0048] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device is flipped in the accompanying drawings, an element described as “below,” “below,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented additionally (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0049] In the accompanying drawings, the first direction D1, the second direction D2, and the third direction are not limited to the directions of the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the first direction D1, the second direction D2, and the third direction can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0050] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be designated as a second element, component, region, layer, or portion.

[0051] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediary elements or intermediary layers may exist. Similarly, when a layer, area, or element is referred to as being "electrically connected" to another layer, area, or element, the layer, area, or element may be directly electrically connected to the other layer, area, or element, and / or may be indirectly electrically connected to the other layer, area, or element with one or more intermediary layers, intermediary areas, or intermediary elements intervening therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediary elements or intermediary layers may exist.

[0052] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “one” are also intended to include the plural forms. It will also be understood that, when used in this specification, the terms “comprises,” “include,” and “has, have, having” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When preceding a list of elements, expressions such as “at least one of…” modify the entire list of elements without modifying any individual element in that list. For example, the expressions “at least one of a, c and b” and “at least one selected from the group consisting of a, b and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or variations thereof.

[0053] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to describe inherent biases in measurements or calculations that will be recognized by those skilled in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure.” As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized.”

[0054] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed in a single integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Additionally, various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media such as CD-ROMs or flash drives. Furthermore, those skilled in the art will recognize that the functionality of various computing devices can be combined or integrated into a single computing device, or the functionality of a particular computing device can be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present disclosure.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their context in the relevant field and / or their meaning in this specification, and should not be interpreted in an idealized or overly formalized sense.

[0056] Figure 1 This is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0057] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver may also include a transmitter driver 600.

[0058] The display panel 100 has a display area for displaying images and a peripheral area adjacent to the display area.

[0059] The display panel 100 may include multiple gate lines GL, multiple data lines DL, multiple emitter lines EL, and multiple pixels PX electrically connected to the gate lines GL, data lines DL, and emitter lines EL. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 intersecting the first direction D1. The emitter lines EL may extend in the first direction D1.

[0060] The drive controller 200 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0061] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0062] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and can output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0063] The drive controller 200 can generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and can output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0064] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0065] The drive controller 200 can generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and can output the third control signal CONT3 to the gamma reference voltage generator 400.

[0066] The drive controller 200 can generate a fourth control signal CONT4 for controlling the operation of the transmitter driver 600 based on the input control signal CONT, and can output the fourth control signal CONT4 to the transmitter driver 600.

[0067] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL. For example, the gate signal may include... Figure 2 The first initialization gate signal GI[n] Figure 2 The second initialization gate signal GI2[n] Figure 2 The compensation gate signal GC[n] Figure 2 The third initialization gate signal ICCG[n] and Figure 2 The second compensation gate signal CCCG[n].

[0068] In some embodiments, the gate driver 300 may be disposed in the peripheral region. In some embodiments, the gate driver 300 may be integrated into the peripheral region.

[0069] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to the level of the data signal DATA.

[0070] For example, the gamma reference voltage generator 400 can be located in the drive controller 200 or in the data driver 500.

[0071] The data driver 500 can receive a second control signal CONT2 and a data signal DATA from the drive controller 200, and can receive a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage VDATA of analog type. The data driver 500 can output the data voltage VDATA to the data line DL.

[0072] In some embodiments, the data drive 500 may be located in the peripheral area. In some embodiments, the data drive 500 may be integrated into the peripheral area.

[0073] The transmitter driver 600 can generate a transmission signal for driving the transmitter line EL in response to a fourth control signal CONT4 received from the drive controller 200. The transmitter driver 600 can output the transmission signal to the display panel 100. The transmission signal may include... Figure 2 The first transmitted signal EM1[n] and Figure 2 The second transmitted signal EM2[n].

[0074] In some embodiments, the transmitter driver 600 may be located in the peripheral region. In some embodiments, the transmitter driver 600 may be integrated into the peripheral region.

[0075] Although for the sake of explanation, in Figure 1 The gate driver 300 is disposed on the first side of the display panel 100, and the emitter driver 600 is disposed on the second side of the display panel 100, but this disclosure is not limited thereto. The gate driver 300 and the emitter driver 600 may be disposed on the first side of the display panel 100. For example, the gate driver 300 and the emitter driver 600 may be disposed on the same side of the display area of ​​the display panel 100 in the peripheral area of ​​the display panel 100. For example, the gate driver 300 and the emitter driver 600 may be integrally formed with each other.

[0076] In some embodiments, the display panel driver can output to the display panel 100. Figure 2 The sweep frequency signal SWEEP[n].

[0077] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 The circuit diagram of the pixel circuit 110 of the pixel PX of the display panel 100.

[0078] Reference Figure 1 and Figure 2 The pixel circuit 110 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a light-emitting element E1. For example, the pixel circuit 110 may have an 11T3C structure (e.g., eleven transistors and three capacitors).

[0079] The first transistor T1 may include a control electrode (e.g., a gate electrode) connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may apply a first supply voltage VDD to the third node N3 in response to the voltage at the first node N1. For example, the first transistor T1 may be referred to as (e.g., called) a first driving transistor. For example, the first transistor T1 may be referred to as a pulse-width driven transistor. In some embodiments, the first transistor T1 may be a P-type transistor.

[0080] The second transistor T2 may include a control electrode that receives a compensation gate signal GC[n], a first electrode that receives a data voltage VDATA, and a second electrode connected to the second node N2. The second transistor T2 may apply the data voltage VDATA to the second node N2 in response to the compensation gate signal GC[n]. For example, the second transistor T2 may be referred to as a write transistor. In some embodiments, the second transistor T2 may be an N-type transistor.

[0081] The third transistor T3 may include a control electrode receiving a compensation gate signal GC[n], a first electrode connected to the third node N3, and a second electrode connected to the first node N1. The third transistor T3 may connect the first node N1 and the third node N3 in response to the compensation gate signal GC[n]. For example, the third transistor T3 may diode-connect the first transistor T1 in response to the compensation gate signal GC[n]. Therefore, a first drive current can be applied to the first node N1 to compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 may be referred to as the first compensation transistor. For example, the third transistor T3 may be referred to as the pulse width compensation transistor. In some embodiments, the third transistor T3 may be an N-type transistor.

[0082] The fourth transistor T4 may include a control electrode receiving a first initialization gate signal GI[n], a first electrode receiving an initialization voltage VINT, and a second electrode connected to the first node N1. The fourth transistor T4 may apply the initialization voltage VINT to the first node N1 in response to the first initialization gate signal GI[n]. For example, the fourth transistor T4 may initialize the first node N1 to the initialization voltage VINT. For example, the fourth transistor T4 may be referred to as the first initialization transistor. In some embodiments, the fourth transistor T4 may be an N-type transistor.

[0083] The fifth transistor T5 may include a control electrode receiving a first transmit signal EM1[n], a first electrode receiving a first power supply voltage VDD, and a second electrode connected to the second node N2. The fifth transistor T5 may apply the first power supply voltage VDD to the second node N2 in response to the first transmit signal EM1[n]. For example, the fifth transistor T5 may be referred to as a first transmit control transistor. In some embodiments, the fifth transistor T5 may be a P-type transistor.

[0084] The sixth transistor T6 may include a control electrode receiving a second initialization gate signal GI2[n], a first electrode receiving an initialization voltage VINT, and a second electrode connected to the third node N3. The sixth transistor T6 may apply the initialization voltage VINT to the third node N3 in response to the second initialization gate signal GI2[n]. For example, the sixth transistor T6 may initialize the third node N3 to the initialization voltage VINT. For example, the sixth transistor T6 may be referred to as the second initialization transistor. In some embodiments, the sixth transistor T6 may be an N-type transistor.

[0085] The seventh transistor T7 may include a control electrode connected to the fourth node N4, a first electrode receiving a first power supply voltage VDD, and a second electrode connected to the fifth node N5. The seventh transistor T7 may generate a drive current in response to the voltage at the fourth node N4. The seventh transistor T7 may output a drive current in response to the voltage at the fourth node N4. For example, the seventh transistor T7 may be referred to as a second drive transistor. For example, the seventh transistor T7 may be referred to as a constant current drive transistor. In some embodiments, the seventh transistor T7 may be a P-type transistor.

[0086] In some embodiments, the W / L ratio of the seventh transistor T7 (e.g., the ratio of channel width to channel length) can vary based on the color of the light-emitting element EE (i.e., the color of the light emitted by the light-emitting element EE). For example, when the color of the light-emitting element EE is red, the W / L ratio of the seventh transistor T7 can have a first ratio. For example, when the color of the light-emitting element EE is green, the W / L ratio of the seventh transistor T7 can have a second ratio different from the first ratio. For example, when the color of the light-emitting element EE is blue, the W / L ratio of the seventh transistor T7 can have a third ratio different from the first and second ratios.

[0087] In conventional display devices, a constant current voltage can be applied to a constant current drive transistor. Therefore, conventional display devices may also include lines for applying the constant current voltage and transistors for applying the constant current voltage. Consequently, the integration density of conventional display devices may be degraded. Furthermore, the power consumption of conventional display devices may increase.

[0088] In some examples, in some embodiments of this disclosure, the W / L ratio of the seventh transistor T7 included in the pixel circuit 110 may vary based on the color of the light-emitting element EE. Therefore, the pixel circuit 110 may not include a transistor for applying a constant current voltage. Furthermore, the display device may not include a line for applying a constant current voltage. Therefore, the integration density of the display device including the pixel circuit 110 can be improved (e.g., increased). Furthermore, the power consumption of the display device including the pixel circuit 110 can be reduced.

[0089] The eighth transistor T8 may include a control electrode receiving a second compensation gate signal CCCG[n], a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4. The eighth transistor T8 may connect the fourth node N4 and the fifth node N5 in response to the second compensation gate signal CCCG[n]. For example, the eighth transistor T8 may diode-connect the seventh transistor T7 in response to the second compensation gate signal CCCG[n]. Therefore, a second drive voltage can be applied to the fourth node N4 to compensate for the threshold voltage of the seventh transistor T7. For example, the eighth transistor T8 may be referred to as a second compensation transistor. For example, the eighth transistor T8 may be referred to as a constant current compensation transistor. In some embodiments, the eighth transistor T8 may be an N-type transistor.

[0090] The ninth transistor T9 may include a control electrode receiving a third initialization gate signal ICCG[n], a first electrode receiving an initialization voltage VINT, and a second electrode connected to the fourth node N4. The ninth transistor T9 may apply the initialization voltage VINT to the fourth node N4 in response to the third initialization gate signal ICCG[n]. For example, the ninth transistor T9 may initialize the fourth node N4 to the initialization voltage VINT. For example, the ninth transistor T9 may be referred to as a third initialization transistor. For example, the ninth transistor T9 may be referred to as a constant current initialization transistor. In some embodiments, the ninth transistor T9 may be an N-type transistor.

[0091] The tenth transistor T10 may include a control electrode for receiving the second transmit signal EM2[n], a first electrode connected to the fifth node N5, and a second electrode connected to the sixth node N6. The tenth transistor T10 may apply a drive current to the sixth node N6 in response to the second transmit signal EM2[n]. For example, the tenth transistor T10 may be referred to as the second transmit control transistor. In some embodiments, the tenth transistor T10 may be a P-type transistor.

[0092] The eleventh transistor T11 may include a control electrode receiving a second initialization gate signal GI2[n], a first electrode receiving a second power supply voltage VSS, and a second electrode connected to the sixth node N6. The second power supply voltage VSS may be lower than the first power supply voltage VDD. The eleventh transistor T11 may apply the second power supply voltage VSS to the sixth node N6 in response to the second initialization gate signal GI2[n]. Therefore, the black characteristics of the light-emitting element EE can be improved. For example, the eleventh transistor T11 may be referred to as the fourth initialization transistor. For example, the eleventh transistor T11 may be referred to as the light-emitting element initialization transistor. In some embodiments, the eleventh transistor T11 may be an N-type transistor.

[0093] The first capacitor C1 may include a first electrode for receiving the sweep frequency signal SWEEP[n] and a second electrode connected to the first node N1.

[0094] The second capacitor C2 may include a first electrode connected to the third node N3 and a second electrode connected to the fourth node N4. The second capacitor C2 can couple the voltage of the third node N3 and apply a coupling voltage to the fourth node N4.

[0095] The third capacitor C3 may include a first electrode receiving the first power supply voltage VDD and a second electrode connected to the fourth node N4. In some embodiments, the pixel circuit 110 may include the third capacitor C3 to improve the hysteresis characteristics of the seventh transistor T7.

[0096] The light-emitting element EE may include a first electrode connected to the sixth node N6 and a second electrode receiving a second power supply voltage VSS. The light-emitting element EE may emit light based on a drive current. For example, the light-emitting element EE may be a light-emitting diode. In some embodiments, the light-emitting element EE may be a miniature light-emitting element.

[0097] Figure 3 This illustrates the application of [something] during the write frame period according to some embodiments of the present disclosure. Figure 2 Timing diagram of the input signals of pixel circuit 110.

[0098] Reference Figures 1 to 3 In some embodiments, the write frame period during which the pixel circuit 110 is driven may include an applying period (PRTP) and a first transmit period (EMTP1A). The applying period (PRTP) may include a first period (TP1A), a second period (TP2A), a third period (TP3A), a fourth period (TP4A), a fifth period (TP5A), a sixth period (TP6A), and a seventh period (TP7A). The first transmit period (EMTP1A) may include an eighth period (TP8A), a ninth period (TP9A), a tenth period (TP10A), and an eleventh period (TP11A).

[0099] In the first time period TP1A, the first transmit signal EM1[n] can have an inactive level (i.e., it can be at an inactive level voltage), the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an active level (i.e., it can be at an active level voltage), the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0100] In this paper, when the transistors to which the first transmit signal EM1[n], the second transmit signal EM2[n], the first initialization gate signal GI[n], the third initialization gate signal ICCG[n], the second initialization gate signal GI2[n], the compensation gate signal GC[n], and the second compensation gate signal CCCG[n] are applied are P-type transistors, the activation level can be low and the deactivation level can be high (i.e., the activation voltage can be low and the deactivation voltage can be high). Conversely, when the transistors to which the first transmit signal EM1[n], the second transmit signal EM2[n], the first initialization gate signal GI[n], the third initialization gate signal ICCG[n], the second initialization gate signal GI2[n], the compensation gate signal GC[n], and the second compensation gate signal CCCG[n] are applied are N-type transistors, the activation level can be high and the deactivation level can be low (i.e., the activation voltage can be high and the deactivation voltage can be low).

[0101] During the first time period TP1A, the sixth transistor T6 can be turned on in response to the second initialization gate signal GI2[n]. Therefore, the initialization voltage VINT can be applied to the third node N3. During the first time period TP1A, the eleventh transistor T11 can be turned on in response to the second initialization gate signal GI2[n]. Therefore, the second power supply voltage VSS can be applied to the sixth node N6. During the first time period TP1A, the fifth transistor T5 can be turned off in response to the first emit signal EM1[n]. During the first time period TP1A, the tenth transistor T10 can be turned off in response to the second emit signal EM2[n].

[0102] In the second time period TP2A following the first time period TP1A, the first transmit signal EM1[n] may have an active level, the second transmit signal EM2[n] may have an inactive level, the first initialization gate signal GI[n] may have an inactive level, the second initialization gate signal GI2[n] may have an inactive level, the compensation gate signal GC[n] may have an inactive level, the third initialization gate signal ICCG[n] may have an inactive level, the second compensation gate signal CCCG[n] may have an inactive level, and the sweep frequency signal SWEEP[n] may have a first voltage level.

[0103] During the second time period TP2A, the fifth transistor T5 can be turned on in response to the first transmit signal EM1[n]. Therefore, the first power supply voltage VDD can be applied to the second node N2.

[0104] In the third time period TP3A following the second time period TP2A, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an active level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0105] During the third time period TP3A, the fourth transistor T4 can be turned on in response to the first initialization gate signal GI[n]. Therefore, the initialization voltage VINT can be applied to the first node N1.

[0106] In the fourth period TP4A following the third period TP3A, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an active level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep signal SWEEP[n] can have a first voltage level.

[0107] In the fourth time period TP4A, the ninth transistor T9 can be turned on in response to the third initialization gate signal ICCG[n]. Therefore, the initialization voltage VINT can be applied to the fourth node N4.

[0108] In the fifth period TP5A following the fourth period TP4A, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an active level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0109] In the fifth time period TP5A, the eighth transistor T8 can be turned on in response to the second compensation gate signal CCCG[n]. Therefore, a second drive voltage can be applied to the fourth node N4 to compensate for the threshold voltage of the seventh transistor T7.

[0110] In the sixth period TP6A following the fifth period TP5A, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an active level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0111] In the sixth time period TP6A, the second transistor T2 can be turned on in response to the compensation gate signal GC[n]. In the sixth time period TP6A, the third transistor T3 can be turned on in response to the compensation gate signal GC[n]. Therefore, a voltage (e.g., a first drive voltage) based on the data voltage VDATA and the threshold voltage of the first transistor T1 can be applied to the first node N1. In the sixth time period TP6A, the voltage of the third node N3 can be changed. Therefore, the voltage of the fourth node N4 can be changed from the second drive voltage.

[0112] In the seventh period TP7A following the sixth period TP6A, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0113] In the eighth period TP8A following the seventh period TP7A, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an active level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep signal SWEEP[n] can have a first voltage level. For example, the eighth period TP8A can be referred to as the first sub-transmit period.

[0114] In the eighth time period TP8A, the sixth transistor T6 can be turned on in response to the second initialization gate signal GI2[n]. Therefore, the initialization voltage VINT can be applied to the third node N3. Therefore, the voltage of the fourth node N4 can be the second drive voltage. In the eighth time period TP8A, the eleventh transistor T11 can be turned on in response to the second initialization gate signal GI2[n]. Therefore, the second power supply voltage VSS can be applied to the sixth node N6.

[0115] In the ninth period TP9A following the eighth period TP8A, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep signal SWEEP[n] can have a second voltage level higher than the first voltage level. For example, the ninth period TP9A can be referred to as the second sub-transmit period.

[0116] During the ninth period TP9A, the fifth transistor T5 can be turned on in response to the first transmit signal EM1[n]. Therefore, the first power supply voltage VDD can be applied to the second node N2.

[0117] When a data voltage is applied to the first electrode of a conventional driving transistor, a conventional display device can begin to emit light. Therefore, due to the hysteresis characteristics of the conventional driving transistor, a ghost image may be detected. Furthermore, conventional display devices may have a first-frame delay.

[0118] In some examples, in a display device including pixel circuitry 110, a first power supply voltage VDD can be applied to the second node N2 in response to a first transmit signal EM1[n]. Therefore, the first power supply voltage VDD can be applied to the second node N2. Thus, the first power supply voltage VDD can be applied to the first electrode of the first transistor T1 before the first transistor T1 is turned on. Therefore, the effects of the hysteresis characteristics of the first transistor T1 can be reduced.

[0119] Furthermore, in the ninth time period TP9A, the sweep signal SWEEP[n] can have a second voltage level higher than the first voltage level. Therefore, the data voltage range of the data voltage VDATA can be reduced. Consequently, the power consumption of the display device can be reduced.

[0120] In the tenth period TP10A following the ninth period TP9A, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an active level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep signal SWEEP[n] can decrease from the second voltage level to the third voltage level.

[0121] In the tenth time period TP10A, the sweep signal SWEEP[n] can decrease from the second voltage level to the third voltage level. For example, the sweep signal SWEEP[n] can gradually decrease from the second voltage level to the third voltage level. The third voltage level can be lower than the first voltage level. Therefore, the voltage of the first node N1 can be reduced. In the tenth time period TP10A, the first transistor T1 can be turned off. In the tenth time period TP10A, the tenth transistor T10 can be turned on in response to the second emission signal EM2[n]. Therefore, a drive current can be applied to the light-emitting element EE. Therefore, the light-emitting element EE can emit light. For example, the tenth time period TP10A can be referred to as the emission turn-on period.

[0122] In the eleventh period TP11A following the tenth period TP10A, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an active level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep signal SWEEP[n] can be reduced to the third voltage level.

[0123] In the eleventh time period TP11A, when the voltage of the first node N1 is lower than the threshold voltage of the first transistor T1, the first transistor T1 can be turned on. Therefore, the first power supply voltage VDD can be applied to the third node N3. Therefore, the voltage of the fourth node N4 can be higher than the threshold voltage of the seventh transistor T7. Therefore, the seventh transistor T7 can be turned off. Therefore, the light-emitting element EE can stop emitting. For example, the eleventh time period TP11A can be referred to as the emission shutdown period.

[0124] For example, the tenth period TP10A to the eleventh period TP11A can be referred to as the third sub-transmission period.

[0125] Figure 4 This illustrates the application of [something] during the write frame period according to some embodiments of the present disclosure. Figure 2 Timing diagram of the input signals of pixel circuit 110.

[0126] Reference Figures 1 to 4 In some embodiments, the write frame period during which the pixel circuit 110 is driven may include an application period PRTP, a first transmit period EMTP1A, and a second transmit period EMTP2A. Figure 4 The timing of the application period PRTP and the first transmission period EMTP1A can be compared with... Figure 3 The timing of the application period RPTP and the first emission period EMTP1A are substantially the same. Furthermore, the timing of the input signal for the second emission period EMTP2A can be substantially the same as the timing of the input signal for the first emission period EMTP1A. Therefore, the same reference numerals will be used, and any repeated descriptions of the above-described components will be omitted.

[0127] In some embodiments, the write frame period may include an application period PRTP, a first emission period EMTP1A, and a second emission period EMTP2A. Therefore, the pixel circuit 110 may emit light multiple times during the write frame period. For example, the pixel circuit 110 may emit light once at a first driving frequency. In some embodiments, the pixel circuit 110 may emit light multiple times at the first driving frequency. Therefore, the luminous efficiency of the pixel circuit 110 can be improved. Furthermore, flickering in display devices including the pixel circuit 110 can be reduced. Although... Figure 4 The illustration shows that pixel circuit 110 emits light twice during the write frame period, but this disclosure is not limited to this number of light emission times. For example, pixel circuit 110 may emit light more than twice during the write frame period.

[0128] Figure 5 This illustrates some embodiments according to the present disclosure. Figure 1 A conceptual diagram of the driving frequency of the display panel 100.

[0129] Figure 6 This illustrates the application of [something] during the hold frame period according to some embodiments of the present disclosure. Figure 2 Timing diagram of the input signals of pixel circuit 110.

[0130] In addition to being able to drive the display panel 100 at a variable frequency, such as Figure 6 The driving timing of the display panel 100 shown according to some embodiments can be compared with the reference. Figures 2 to 4 The described drive timings are essentially the same. Therefore, the same reference numerals will be used, and any repeated descriptions of the above-described components will be omitted.

[0131] Reference Figures 1 to 6 The display panel 100 can be driven at a variable frequency. A first frame FR1 having a first frequency may include a first active period AC1 and a first blanking period BL1. A second frame FR2 having a second frequency different from the first frequency may include a second active period AC2 and a second blanking period BL2. A third frame FR3 having a third frequency different from the first and second frequencies may include a third active period AC3 and a third blanking period BL3.

[0132] The lengths of the first effective time interval AC1 and the second effective time interval AC2 can be the same or substantially the same, and the lengths of the first blanking time interval BL1 and the second blanking time interval BL2 can be different.

[0133] The lengths of the second effective time interval AC2 and the third effective time interval AC3 can be the same or substantially the same, and the lengths of the second blanking time interval BL2 and the third blanking time interval BL3 can be different.

[0134] Display devices supporting variable frequencies may include: write frames, in which data voltage is written to pixel PX; and hold frames, in which data voltage is not written to pixel PX and only emission is performed. Write frames may be arranged within active time periods AC1, AC2, and AC3. Hold frames may be arranged within blanking time periods BL1, BL2, and BL3.

[0135] For example, in a write frame, a data voltage VDATA can be applied to the first transistor T1, and the light-emitting element EE can emit light. Conversely, in a hold frame, the data voltage VDATA can be not applied to the first transistor T1, and the light-emitting element EE can still emit light.

[0136] In some embodiments, the hold frame period may include a non-applying period (VTPA) and a first transmit period (EMTP1B). The non-applying period (VTPA) may include a first period (TP1B) and a second period (TP2B). The first transmit period (EMTP1B) may include a third period (TP3B), a fourth period (TP4B), a fifth period (TP5B), and a sixth period (TP6B).

[0137] In the first time period TP1B, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an active level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep frequency signal SWEEP can have a first voltage level.

[0138] During the first time period TP1B, the sixth transistor T6 can be turned on in response to the second initialization gate signal GI2[n]. Therefore, the initialization voltage VINT can be applied to the third node N3. Therefore, the voltage of the fourth node N4 can be the second drive voltage.

[0139] In the second time period TP2B following the first time period TP1B, the first transmit signal EM1[n] may have an inactive level, the second transmit signal EM2[n] may have an inactive level, the first initialization gate signal GI[n] may have an inactive level, the second initialization gate signal GI2[n] may have an inactive level, the compensation gate signal GC[n] may have an inactive level, the third initialization gate signal ICCG[n] may have an inactive level, the second compensation gate signal CCCG[n] may have an inactive level, and the sweep frequency signal SWEEP may have a first voltage level.

[0140] In the third time period TP3B following the second time period TP2B, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an active level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep signal SWEEP can have a first voltage level.

[0141] In the fourth period TP4B following the third period TP3B, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep frequency signal SWEEP[n] can have a second voltage level.

[0142] In the fourth time period TP4B, the fifth transistor T5 can be turned on in response to the first transmit signal EM1[n]. Therefore, the first power supply voltage VDD can be applied to the second node N2.

[0143] When a data voltage is applied to the first electrode of a conventional driving transistor, a conventional display device can begin to emit light. Therefore, due to the hysteresis characteristics of the conventional driving transistor, a ghost image may be detected. Furthermore, conventional display devices may have a first-frame delay.

[0144] In some examples, in a display device including pixel circuitry 110, a first power supply voltage VDD can be applied to the second node N2 in response to a first transmit signal EM1[n]. Therefore, the first power supply voltage VDD can be applied to the second node N2. Thus, the first power supply voltage VDD can be applied to the first electrode of the first transistor T1 before the first transistor T1 is turned on. Therefore, the effects of the hysteresis characteristics of the first transistor T1 can be reduced.

[0145] Furthermore, in the fourth time period TP4B, the sweep signal SWEEP[n] can have a second voltage level higher than the first voltage level. Therefore, the data voltage range of the data voltage VDATA can be reduced. Consequently, the power consumption of the display device can be reduced.

[0146] In the fifth period TP5B following the fourth period TP4B, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an active level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep signal SWEEP[n] can decrease from the second voltage level to the third voltage level.

[0147] In the fifth time period TP5B, the sweep signal SWEEP[n] can decrease from the second voltage level to the third voltage level. For example, the sweep signal SWEEP[n] can gradually decrease from the second voltage level to the third voltage level. The third voltage level can be lower than the first voltage level. Therefore, the voltage of the first node N1 can be reduced. In the fifth time period TP5B, the first transistor T1 can be turned off. In the fifth time period TP5B, the tenth transistor T10 can be turned on in response to the second transmit signal EM2[n]. Therefore, a drive current can be applied to the light-emitting element EE. Therefore, the light-emitting element EE can emit light. For example, the fifth time period TP5B can be referred to as the transmit-on period.

[0148] In the sixth period TP6B following the fifth period TP5B, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an active level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG[n] can have an inactive level, the second compensation gate signal CCCG[n] can have an inactive level, and the sweep frequency signal SWEEP[n] can be reduced to the third voltage level.

[0149] In the sixth time period TP6B, when the voltage of the first node N1 is lower than the threshold voltage of the first transistor T1, the first transistor T1 can be turned on. Therefore, the first power supply voltage VDD can be applied to the third node N3. Therefore, the voltage of the fourth node N4 can be higher than the threshold voltage of the seventh transistor T7. Therefore, the seventh transistor T7 can be turned off. Therefore, the light-emitting element EE can stop emitting. For example, the sixth time period TP6B can be referred to as the emission shutdown period.

[0150] In some embodiments, during the hold frame period, the first initialization gate signal GI[n], the third initialization gate signal ICCG[n], and the second compensation gate signal CCCG[n] may have an inactive level. Therefore, the power consumption of the display device can be reduced.

[0151] Figure 7 This illustrates the application of [something] during the hold frame period according to some embodiments of the present disclosure. Figure 2 Timing diagram of the input signals of pixel circuit 110.

[0152] Reference Figure 2 as well as Figures 6 to 7 In some embodiments, the hold frame period during which the pixel circuit 110 is driven may include an unapplied period VTPA, a first transmit period EMTP1B, and a second transmit period EMTP2B. Figure 7 The timing of the non-application period VTPA and the first transmission period EMTP1B can be compared with... Figure 6 The timing of the non-application period VTPA and the first transmission period EMTP1B is substantially the same. Furthermore, the timing of the input signal in the second transmission period EMTP2B can be substantially the same as the timing of the input signal in the first transmission period EMTP1B.

[0153] In some embodiments, the hold frame period may include a non-application period VTPA, a first emission period EMTP1B, and a second emission period EMTP2B. Therefore, the pixel circuit 110 can emit light multiple times during the hold frame period. For example, the pixel circuit 110 can emit light once at a first driving frequency. In some embodiments, the pixel circuit 110 can emit light multiple times at the first driving frequency. Therefore, the luminous efficiency of the pixel circuit 110 can be improved. Furthermore, flickering in display devices including the pixel circuit 110 can be reduced. Although... Figure 7 The illustration shows that pixel circuit 110 emits light twice during the hold frame period, but this disclosure is not limited to this number of light emission times. For example, pixel circuit 110 may emit light more than twice during the hold frame period.

[0154] Figure 8 This illustrates some embodiments according to the present disclosure. Figure 1 The circuit diagram of the pixel circuit 120 of the pixel PX of the display panel 100.

[0155] Besides the third initialization gate signal ICCG and the second compensation gate signal CCCG being global signals, according to Figure 8 The pixel circuit 120 shown in some embodiments is... Figure 2 The pixel circuit 110 is essentially the same. Therefore, the same figures will be used, and any repeated descriptions of the above-described components will be omitted.

[0156] Reference Figure 8 The third initialization gate signal ICCG and the second compensation gate signal CCCG can be global signals. Global signals can be synchronization signals that have the same timing regardless of the pixel row. For example, global signals can have the same timing across at least two pixel rows. Therefore, the integration of the drivers used to generate the third initialization gate signal ICCG and the second compensation gate signal CCCG can be improved. Consequently, the power consumption of the display device including the pixel circuitry 120 can be reduced.

[0157] Figure 9 This illustrates the application of [something] during the write frame period according to some embodiments of the present disclosure. Figure 8 Timing diagram of the input signals of pixel circuit 120.

[0158] Reference Figure 1 and Figures 8 to 9 In some embodiments, the write frame period during which the pixel circuit 110 is driven may include an initialization period (ITP), a compensation period (CTP), an application period (ATP), and a first transmission period (EMTP1C). The initialization period (ITP) may include a first period (TP1C), a second period (TP2C), a third period (TP3C), and a fourth period (TP4C). The compensation period (CTP) may include a fifth period (TP5C), a sixth period (TP6C), a seventh period (TP7C), and an eighth period (TP8C). The application period (ATP) may include a ninth period (TP9C), a tenth period (TP10C), and an eleventh period (TP11C). The first transmission period (EMTP1C) may include a twelfth period (TP12C), a thirteenth period (TP13C), a fourteenth period (TP14C), and a fifteenth period (TP15C).

[0159] In the first time period TP1C, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an active level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0160] During the first time period TP1C, the ninth transistor T9 can be turned on in response to the third initialization gate signal ICCG. Therefore, the initialization voltage VINT can be applied to the fourth node N4.

[0161] In the second time period TP2C following the first time period TP1C, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an active level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an active level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0162] During the second time period TP2C, the fourth transistor T4 can be turned on in response to the first initialization gate signal GI[n]. Therefore, the initialization voltage VINT can be applied to the first node N1. Therefore, the first transistor T1 can be turned on. During the second time period TP2C, the fifth transistor T5 can be turned on in response to the first transmit signal EM1[n]. Therefore, the first power supply voltage VDD can be applied to the third node N3.

[0163] In the third time period TP3C following the second time period TP2C, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an active level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0164] In the fourth period TP4C following the third period TP3C, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an active level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0165] In the fifth period TP5A following the fourth period TP4A, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an active level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0166] In the fifth time period TP5C, the ninth transistor T9 can be turned off in response to the third initialization gate signal ICCG. In the fifth time period TP5C, the eighth transistor T8 can be turned on in response to the second compensation gate signal CCCG. Therefore, the voltage at the fourth node N4 can be the second drive voltage.

[0167] In the sixth period TP6C following the fifth period TP5C, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an active level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an active level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0168] In the sixth time period TP6C, the fourth transistor T4 can be turned on in response to the first initialization gate signal GI[n]. Therefore, the first power supply voltage VDD can be applied to the first node N1.

[0169] In the seventh period TP7C following the sixth period TP6C, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an active level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0170] In the eighth period TP8C following the seventh period TP7C, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an active level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0171] In the ninth period TP9C following the eighth period TP8C, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0172] In the tenth period TP10C following the ninth period TP9C, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an active level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0173] In the tenth time period TP10C, the fourth transistor T4 can be turned on in response to the first initialization gate signal GI[n]. Therefore, the initialization voltage VINT can be applied to the first node N1.

[0174] In the eleventh period TP11C following the tenth period TP10C, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an active level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0175] During the eleventh time period TP11C, the second transistor T2 can be turned on in response to the compensation gate signal GC[n]. During the eleventh time period TP11C, the third transistor T3 can be turned on in response to the compensation gate signal GC[n]. Therefore, a voltage (e.g., a first drive voltage) based on the data voltage VDATA and the threshold voltage of the first transistor T1 can be applied to the first node N1. During the eleventh time period TP11C, the voltage of the third node N3 can be changed. Therefore, the voltage of the fourth node N4 can be changed from the second drive voltage.

[0176] In the twelfth time period TP12C following the eleventh time period TP11C, the first transmit signal EM1[n] can have an inactive level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an active level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a first voltage level.

[0177] In the twelfth time period TP12C, the sixth transistor T6 can be turned on in response to the second initialization gate signal GI2[n]. Therefore, the initialization voltage VINT can be applied to the third node N3. Therefore, the voltage of the fourth node N4 can be the second drive voltage. In the twelfth time period TP12C, the eleventh transistor T11 can be turned on in response to the second initialization gate signal GI2[n]. Therefore, the second power supply voltage VSS can be applied to the sixth node N6.

[0178] In the thirteenth period TP13C following the twelfth period TP12C, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an inactive level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can have a second voltage level higher than the first voltage level.

[0179] During the thirteenth time period TP13C, the fifth transistor T5 can be turned on in response to the first transmit signal EM1[n]. Therefore, the first power supply voltage VDD can be applied to the second node N2.

[0180] When a data voltage is applied to the first electrode of a conventional driving transistor, a conventional display device can begin to emit light. Therefore, due to the hysteresis characteristics of the conventional driving transistor, a ghost image may be detected. Furthermore, conventional display devices may have a first-frame delay.

[0181] In some examples, in a display device including pixel circuitry 120, a first power supply voltage VDD can be applied to the second node N2 in response to a first transmit signal EM1[n]. Therefore, the first power supply voltage VDD can be applied to the second node N2. Thus, the first power supply voltage VDD can be applied to the first electrode of the first transistor T1 before the first transistor T1 is turned on. Therefore, the effects of the hysteresis characteristics of the first transistor T1 can be reduced.

[0182] Furthermore, in the thirteenth time period TP13C, the sweep signal SWEEP[n] can have a second voltage level higher than the first voltage level. Therefore, the data voltage range of the data voltage VDATA can be reduced. Consequently, the power consumption of the display device can be reduced.

[0183] In the fourteenth period TP14C following the thirteenth period TP13C, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an active level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can decrease from the second voltage level to the third voltage level.

[0184] In the fourteenth period TP14C, the sweep signal SWEEP[n] can decrease from the second voltage level to the third voltage level. For example, the sweep signal SWEEP[n] can gradually decrease from the second voltage level to the third voltage level. The third voltage level can be lower than the first voltage level. Therefore, the voltage of the first node N1 can be reduced. In the fourteenth period TP14C, the first transistor T1 can be turned off. In the fourteenth period TP14C, the tenth transistor T10 can be turned on in response to the second transmit signal EM2[n]. Therefore, a drive current can be applied to the light-emitting element EE. Therefore, the light-emitting element EE can emit light. For example, the fourteenth period TP14C can be referred to as the transmit-on period.

[0185] In the fifteenth period TP15C following the fourteenth period TP14C, the first transmit signal EM1[n] can have an active level, the second transmit signal EM2[n] can have an active level, the first initialization gate signal GI[n] can have an inactive level, the second initialization gate signal GI2[n] can have an inactive level, the compensation gate signal GC[n] can have an inactive level, the third initialization gate signal ICCG can have an inactive level, the second compensation gate signal CCCG can have an inactive level, and the sweep frequency signal SWEEP[n] can be reduced to the third voltage level.

[0186] In the fifteenth time period TP15C, when the voltage of the first node N1 is lower than the threshold voltage of the first transistor T1, the first transistor T1 can be turned on. Therefore, the first power supply voltage VDD can be applied to the third node N3. Therefore, the voltage of the fourth node N4 can be higher than the threshold voltage of the seventh transistor T7. Therefore, the seventh transistor T7 can be turned off. Therefore, the light-emitting element EE can stop emitting. For example, the fifteenth time period TP15C can be referred to as the emission shutdown period.

[0187] Figure 10 This illustrates the application of [something] during the write frame period according to some embodiments of the present disclosure. Figure 8 Timing diagram of the input signals of pixel circuit 120.

[0188] Reference Figure 1 as well as Figures 8 to 10 In some embodiments, the write frame period during which the pixel circuit 120 is driven may include an initialization period ITP, a compensation period CTP, an application period ATP, a first transmission period EMTP1C, and a second transmission period EMTP2C. Figure 10 The timing of the initialization period ITP, compensation period CTP, application period ATP, and first launch period EMTP1A can be compared with... Figure 9 The timing of the initialization period (ITOP), compensation period (CTP), application period (ATP), and first emission period (EMTP1C) is essentially the same. Furthermore, the timing of the input signal for the second emission period (EMTP2C) can be essentially the same as that for the input signal for the first emission period (EMTP1C).

[0189] In some embodiments, the write frame period may include an initialization period (ITP), a compensation period (CTP), an application period (ATP), a first emission period (EMTP1C), and a second emission period (EMTP2C). Therefore, the pixel circuit 120 can emit light multiple times during the write frame period. For example, the pixel circuit 120 can emit light once at a first driving frequency. In some embodiments, the pixel circuit 120 can emit light multiple times at the first driving frequency. Therefore, the luminous efficiency of the pixel circuit 120 can be improved. Furthermore, flickering in display devices including the pixel circuit 120 can be reduced. Although... Figure 10 The pixel circuit 120 is shown to emit light twice during the write frame period, but this disclosure is not limited to this number of emission times. For example, the pixel circuit 120 may emit light more than twice during the write frame period.

[0190] Figure 11 This illustrates the application of [something] during the hold frame period according to some embodiments of the present disclosure. Figure 8 Timing diagram of the input signals of pixel circuit 120.

[0191] In addition to driving the display panel 100 at a variable frequency, such as Figure 11 The driving timing and reference of the display panel 100 according to some embodiments shown Figures 8 to 10 The driving timing described is essentially the same, so the same reference numerals will be used, and any repeated descriptions of the above-mentioned components will be omitted.

[0192] In some embodiments, the hold frame period may include an unapplied period VTPB and a first transmit period EMTP1D. The unapplied period VTPB may include a first period TP1D and a second period TP2D. The first transmit period EMTP1D may include a third period TP3D, a fourth period TP4D, a fifth period TP5D, and a sixth period TP6D.

[0193] In some embodiments, Figure 11 The timing of the hold frames can be compared with... Figure 6 The timing of the holding frames is essentially the same. Therefore, the same reference numerals will be used, and any repeated descriptions of the above-mentioned elements will be omitted.

[0194] In some embodiments, during the hold frame period, the first initialization gate signal GI[n], the third initialization gate signal ICCG, and the second compensation gate signal CCCG may have inactive levels. Therefore, the power consumption of the display device can be reduced.

[0195] Figure 12 This illustrates the application of [something] during the hold frame period according to some embodiments of the present disclosure. Figure 8 Timing diagram of the input signals of pixel circuit 120.

[0196] Reference Figures 8 to 12 In some embodiments, the hold frame period during which the pixel circuit 120 is driven may include an unapplied period VTPB, a first transmit period EMTP1D, and a second transmit period EMTPD2. Figure 12 The timing of the non-application period VTPB and the first transmission period EMTP1D can be compared with... Figure 11 The timing of the non-application period VTPB and the second transmission period EMTP1D is substantially the same. Furthermore, the timing of the input signal of the second transmission period EMTP2D can be substantially the same as the timing of the input signal of the first transmission period EMTP1D. Therefore, the same reference numerals will be used, and any repeated descriptions of the above-described components will be omitted.

[0197] In some embodiments, the hold frame period may include a non-application period VTPB, a first emission period EMTP1D, and a second emission period EMTP2D. Therefore, the pixel circuit 120 may emit light multiple times during the hold frame period. For example, the pixel circuit 120 may emit light once at a first driving frequency. In some embodiments, the pixel circuit 120 may emit light multiple times at the first driving frequency. Therefore, the luminous efficiency of the pixel circuit 120 can be improved. Furthermore, flickering in display devices including the pixel circuit 120 can be reduced. Although... Figure 12 The illustration shows that pixel circuit 120 emits light twice during the hold frame period, but this disclosure is not limited to this number of emission times. For example, pixel circuit 110 may emit light more than twice during the hold frame period.

[0198] Figure 13 This illustrates the application of some embodiments of the present disclosure to... Figure 1 The timing diagram of the transmission signal of the transmission line of the display device.

[0199] Reference Figure 13 In some embodiments, the odd-numbered transmitter line groups may include a first transmitter line EL[1], a third transmitter line EL[3], a fifth transmitter line EL[5], and a seventh transmitter line EL[7]. The even-numbered transmitter line groups may include a second transmitter line EL[2], a fourth transmitter line EL[4], a sixth transmitter line EL[6], and an eighth transmitter line EL[8].

[0200] In some embodiments, the transmission signal applied to the odd-numbered transmission line group may have a first transmission frequency EFR1. The transmission signal applied to the even-numbered transmission line group may have a first transmission frequency EFR1.

[0201] Transmission signals applied to odd-numbered transmission line groups and transmission signals applied to even-numbered transmission line groups can be applied alternately. Therefore, even if a transmission signal with a first transmission frequency EFR1 is applied, the display panel 100 can be recognized at a second transmission frequency EFR2, which is higher than the first transmission frequency EFR1. Therefore, the power consumption of the display device can be further reduced.

[0202] Figure 14 This is a block diagram illustrating an electronic device 1000 according to some embodiments of the present disclosure. Figure 15 This illustrates some embodiments according to the present disclosure. Figure 14 The diagram shows an example of an electronic device implemented as a smartphone.

[0203] Reference Figure 14 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be... Figure 1 The display device. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0204] In some embodiments, such as Figure 15 As shown, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smartpad, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer and / or head-mounted display (HMD), etc.

[0205] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, a central processing unit (CPU), and / or an application processor (AP), etc. Processor 1010 can be coupled to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0206] Processor 1010 can... Figure 1 The drive controller 200 outputs input image data (IMG) (for example, see...). Figure 1 ), application (app) enable signal and input control signal CONT (for example, see Figure 1 ).

[0207] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and / or a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and / or a mobile DRAM device.

[0208] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, and CD-ROM devices, etc. I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, and touchscreen, and output devices such as a printer and speakers. In some embodiments, display device 1060 may be included in I / O device 1040. Power supply 1050 provides power for the operation of electronic device 1000. Display device 1060 may be coupled to other components via a bus or other communication link.

[0209] Reference Figure 15 The electronic device disclosed herein is shown as a smartphone, but the disclosure is not limited thereto. The electronic device may be a television set, monitor, laptop computer, or tablet computer, etc. Furthermore, the electronic device may be an automobile.

[0210] Figure 16 This illustrates some embodiments according to the present disclosure. Figure 14 The diagram shows an example of an electronic device implemented as a smartwatch.

[0211] Reference Figure 16 and Figure 14 The electronic device 1000 can be implemented as a smartwatch. A smartwatch can be an example of the electronic device 1000 utilizing an ultra-high resolution display panel.

[0212] The display device according to the embodiments can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart boards, portable multimedia players (PMPs), personal digital assistants (PDAs), or MP3 players.

[0213] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A pixel circuit, wherein, The pixel circuit includes: The first driving transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; Write transistors are configured to apply a data voltage to the second node in response to a compensation gate signal; The first initialization transistor is configured to apply an initialization voltage to the first node in response to a first initialization gate signal; The second initialization transistor is configured to apply the initialization voltage to the third node in response to the second initialization gate signal; The second driving transistor includes a control electrode connected to the fourth node, a first electrode receiving a first power supply voltage, and a second electrode connected to the fifth node, and the second driving transistor is configured to apply a driving current. The third initialization transistor is configured to apply the initialization voltage to the fourth node in response to a third initialization gate signal; The first capacitor is configured to apply a sweep frequency signal to the first node; The second capacitor includes a first electrode connected to the third node and a second electrode connected to the fourth node; and The light-emitting element is configured to emit light based on the driving current.

2. The pixel circuit according to claim 1, wherein, The aspect ratio of the second driving transistor varies depending on the color of the light-emitting element.

3. The pixel circuit according to claim 1, wherein, The pixel circuit also includes: A first transmit control transistor is configured to apply the first power supply voltage to the second node in response to a first transmit signal; and The second emitter control transistor is configured to apply the drive current to the light-emitting element in response to the second emitter signal.

4. The pixel circuit according to claim 3, wherein, The pixel circuit also includes: A first compensation transistor is configured to connect the first node and the third node in response to the compensation gate signal; and The second compensation transistor is configured to connect the fourth node and the fifth node in response to a second compensation gate signal.

5. The pixel circuit according to claim 3, wherein, The pixel circuit further includes a fourth initialization transistor configured to apply a second power supply voltage, different from the first power supply voltage, to the first electrode of the light-emitting element in response to the second initialization gate signal.

6. The pixel circuit according to claim 3, wherein, The write frame period during which the pixel circuit is driven includes an application period and a first transmit period, and During the application period, the data voltage is applied to the first node, and the initialization voltage is applied to the fourth node.

7. The pixel circuit according to claim 6, wherein, In the first sub-transmission period of the first transmission period, the first transmission signal has an inactive level, the second transmission signal has an inactive level, the second initialization gate signal has an active level, and the sweep signal has a first voltage level.

8. The pixel circuit according to claim 7, wherein, In the second sub-transmission period following the first sub-transmission period of the first transmission period, the first transmission signal has an active level, the second transmission signal has the inactive level, and the sweep signal has a second voltage level higher than the first voltage level.

9. The pixel circuit according to claim 8, wherein, In a third sub-transmission period following the second sub-transmission period of the first transmission period, the first transmission signal has the activation level, the second transmission signal has the activation level, and the sweep signal decreases from the second voltage level to a third voltage level lower than the second voltage level.

10. The pixel circuit according to claim 6, wherein, The write frame period also includes a second transmit period following the first transmit period. During the first emission period, the light-emitting element emits light, and During the second emission period, the initialization voltage is applied to the fourth node, and the light-emitting element emits light.

11. A display device, wherein, The display device includes: Display panel, including pixel circuitry; A gate driver configured to apply a gate signal to the display panel; A data driver configured to apply a data voltage to the display panel; A transmitter driver configured to apply a transmission signal to the display panel; and The drive controller is configured to control the gate driver, the data driver, and the transmit driver. The pixel circuit includes: The first driving transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A write transistor is configured to apply the data voltage to the second node in response to a compensation gate signal; The first initialization transistor is configured to apply an initialization voltage to the first node in response to a first initialization gate signal; The second initialization transistor is configured to apply the initialization voltage to the third node in response to the second initialization gate signal; The second driving transistor includes a control electrode connected to the fourth node, a first electrode receiving a first power supply voltage, and a second electrode connected to the fifth node, and the second driving transistor is configured to apply a driving current. The third initialization transistor is configured to apply the initialization voltage to the fourth node in response to a third initialization gate signal; The first capacitor is configured to apply a sweep frequency signal to the first node; The second capacitor includes a first electrode connected to the third node and a second electrode connected to the fourth node; and The light-emitting element is configured to emit light based on the driving current.

12. The display device according to claim 11, wherein, The write frame period during which the pixel circuit is driven includes an application period, a first transmission period, and a second transmission period. During the application period, the data voltage is applied to the first node, and the initialization voltage is applied to the fourth node. During the first emission period, the light-emitting element emits light, and During the second emission period, the initialization voltage is applied to the fourth node, and the light-emitting element emits light.

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