Display device

Abstract

A display device includes: a display panel including a plurality of emission areas and a non-emission area between the plurality of emission areas; and a sensing panel over the display panel and having a plurality of sensor patterns overlapping the non-emission area, and the plurality of sensor patterns including: a plurality of first sensor patterns extending in a first direction, a plurality of first sensor patterns spaced apart in a second direction crossing the first direction and each of the plurality of first sensor patterns having a first width in the second direction; a plurality of second sensor patterns at the same layer as the plurality of first sensor patterns, connected to the plurality of first sensor patterns, extending in the second direction and spaced apart in the first direction; and at least one dummy pattern at a different layer from the plurality of first sensor patterns and the plurality of second sensor patterns, and having a second width greater than the first width in the second direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0058487, filed on May 2, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] Recently, with increasing interest in information display, research and development of display devices are ongoing. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation systems, and smart televisions. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, or organic light-emitting diode displays.

[0005] Recent display devices may include a display panel for displaying images and a sensing panel for sensing objects. In this case, the sensing panel can be used to determine the location of touch input provided by a user. The sensing panel can be formed through a process separate from that of the display panel and then assembled to the display panel, or it can be integrally formed with the display panel through a continuous process.

[0006] In display devices in which the sensing panel and the display panel are integrally formed, there may be a problem where external light is reflected off the surface of the display device, making the pattern visible to the user. Methods to reduce or minimize this situation may be appropriate.

[0007] The above content is intended only to help understand the background technology of the technical ideas of this disclosure, and therefore should not be construed as corresponding to the prior art known to those skilled in the art. Summary of the Invention

[0008] Embodiments of this disclosure provide a display device with improved reliability. For example, the display device can improve external light visibility by setting dummy patterns at corresponding positions between emission areas.

[0009] According to one or more embodiments of the present disclosure, a display device includes: a display panel including a plurality of emitting regions and a non-emitting region between the plurality of emitting regions; and a sensing panel above the display panel and having a plurality of sensor patterns overlapping the non-emitting regions, wherein the plurality of sensor patterns includes: a plurality of first sensor patterns extending in a first direction and spaced apart in a second direction intersecting the first direction, and each of the plurality of first sensor patterns having a first width in the second direction; a plurality of second sensor patterns located on the same layer as the plurality of first sensor patterns, connected to the plurality of first sensor patterns, extending in the second direction and spaced apart in the first direction; and at least one dummy pattern located on a different layer from the plurality of first sensor patterns and the plurality of second sensor patterns, and the at least one dummy pattern having a second width in the second direction greater than the first width.

[0010] The display panel may include: an anode electrode in the emitting region; and a connecting electrode in the non-emitting region and on the same layer as the anode electrode, configured to transmit electrical voltage and overlapping with at least one dummy pattern.

[0011] The display panel may further include: power lines, below the connecting electrodes, configured to provide power voltage and electrically connected to the connecting electrodes, wherein the connecting electrodes are between the power lines and at least one dummy pattern.

[0012] The connecting electrode may have a third width in the second direction that is smaller than the second width.

[0013] The third width can be greater than the first width.

[0014] The display panel may include a pixel defining layer that partially covers the anode electrode and the connecting electrode, a light emitting layer that is above the anode electrode, and a cathode electrode that is completely above the pixel defining layer, the light emitting layer, and the connecting electrode and is electrically connected to the connecting electrode and the light emitting layer.

[0015] The plurality of sensor patterns may further include: a bridging pattern, which is on the same layer as at least one dummy pattern, extends in a first direction, and electrically connects the plurality of second sensor patterns to each other.

[0016] At least one dummy pattern may include a first portion protruding from the bridging pattern in a second direction and a second portion protruding in a direction opposite to the second direction.

[0017] The first part, the second part, and the portion of the bridging pattern that connects to the first part and the second part may have a second width in the second direction.

[0018] The bridging pattern can have a fourth width in the second direction that is smaller than the second width.

[0019] The bridging pattern can be located on a different layer than the layer in which multiple second sensor patterns are located.

[0020] The plurality of emission regions may include: emission regions in a first column of the plurality of emission regions, arranged along a second direction, and including: a first emission region; a second emission region spaced apart from the first emission region by a first distance in the second direction; and a third emission region spaced apart from the second emission region by a second distance greater than the first distance in the second direction; and emission regions in a second column of the plurality of emission regions, arranged along the second direction, wherein at least one dummy pattern is located between the second emission region and the third emission region in a plan view.

[0021] The second column of the multiple emission regions may include: a fourth emission region; a fifth emission region spaced a third distance from the fourth emission region in a second direction; and a sixth emission region spaced a fourth distance less than the third distance from the fifth emission region in a second direction, wherein the bridging pattern extends through the fourth and fifth emission regions in a first direction and has a second width between the fourth and fifth emission regions.

[0022] The first column of the emission region and the second column of the emission region can be configured to emit light of the same color.

[0023] At least one dummy pattern may overlap with one of a plurality of first sensor patterns.

[0024] At least one dummy pattern can be electrically levitated.

[0025] Each of the plurality of second sensor patterns may have a fifth width in a first direction, wherein at least one dummy pattern has a sixth width in the first direction that is greater than the fifth width.

[0026] The fifth width can be roughly equal to the first width.

[0027] The emission areas can be arranged in columns defined by a diagonal line direction intersecting the first and second directions, wherein at least one dummy pattern is between adjacent emission areas in each column. Attached Figure Description

[0028] The above and other features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in more detail, in which:

[0029] Figure 1 This is a perspective view illustrating one or more embodiments of the display device of this disclosure;

[0030] Figure 2 It is along Figure 1A cross-sectional view taken from line I-I';

[0031] Figure 3 It is shown Figure 2 Cross-sectional views of one or more embodiments of a display panel;

[0032] Figure 4 It is shown Figure 2 Cross-sectional views of one or more embodiments of the sensing panel;

[0033] Figure 5 It is shown Figure 1 A block diagram of one or more embodiments of a display device;

[0034] Figure 6 It is shown Figure 5 A block diagram of one or more embodiments of one of the sub-pixels;

[0035] Figure 7 It is shown Figure 1 A plan view of one or more embodiments of the display panel of a display device;

[0036] Figure 8 It is shown Figure 1 A plan view of one or more embodiments of the sensing panel of a display device;

[0037] Figure 9 It is shown Figure 8 Enlarged views of one or more embodiments of part A;

[0038] Figure 10 It is shown in Figure 1 In the display device Figure 8 Enlarged views of one or more embodiments of part A;

[0039] Figure 11 It is along Figure 10 A cross-sectional view taken from line II-II';

[0040] Figure 12 It is along Figure 10 A cross-sectional view taken from line III-III';

[0041] Figure 13 It is along Figure 10 A cross-sectional view taken from line IV-IV'; and

[0042] Figure 14 It is shown Figure 8 Enlarged view of one or more other embodiments of part A. Detailed Implementation

[0043] By referring to the detailed description and accompanying drawings of the embodiments, aspects of some embodiments of this disclosure and methods for implementing those aspects can be more readily understood. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey various aspects of this disclosure to those skilled in the art. Therefore, redundant processes / techniques, elements, and techniques that are irrelevant or unrelated to the description of the embodiments or that are not essential for a person of ordinary skill in the art to fully understand various aspects of this disclosure may be omitted. Unless otherwise indicated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated descriptions may be omitted.

[0044] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of “can,” “may,” or “may not” corresponds to one or more embodiments of this disclosure.

[0045] It will be appreciated by those skilled in the art that, in view of the entirety of this disclosure, unless otherwise stated or implied, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable manners, and each embodiment may be implemented independently of one another or in any suitable combination with one another.

[0046] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, this disclosure is not limited to the dimensions and thicknesses of elements shown in the drawings arbitrarily for ease of description. Furthermore, the use of crosshairs and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, proportion, commonalities among the elements shown, or any other characteristics, properties, or characteristics of the elements.

[0047] Various embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of examples and / or intervening structures. Thus, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to the concepts of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the elements, layers, or regions shown, but should include deviations in shape due to factors such as manufacturing.

[0048] For example, an injection zone shown as rectangular will typically have rounded or curved features and / or a gradient of injection concentration at its edges, rather than a binary change from the injection zone to the non-injection zone at the edges of the injection zone. Similarly, the buried zone formed by injection may result in some injection in the zone between the buried zone and the surface where the injection occurs.

[0049] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “overall,” “higher,” “upper side,” and “side” (e.g., as in “sidewall”) are used herein to describe the relationship between one element or feature and another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be positioned “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first component is described as being arranged "on" the second component, this indicates that the first component is arranged above or below the second component based on the direction of gravity, and is not limited to being arranged above the second component.

[0050] Furthermore, the phrase "in a plan view" refers to a portion of an object viewed from above, and the phrase "in a cross-sectional view" refers to a schematic cross-section obtained by vertically cutting a portion of an object, viewed from the side. The term "overlapping" means that the first object may be above or below the second object, or located to the side of the second object, and vice versa. Furthermore, the term "overlapping" can include stacking, facing or oriented towards, extending across, covering or partially covering, or any other suitable terminology as will be understood and appreciated by those skilled in the art. The expression "not overlapping" can include meanings such as "separated from," "separated from," or "offset from," and any other suitable equivalents as will be understood and appreciated by those skilled in the art. The terms "facing" and "oriented towards" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as being indirectly opposite each other, although still facing each other.

[0051] It will be understood that when an element, layer, area, or component is referred to as "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, area, or component," the element, layer, area, or component can be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, area, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, area, or component, such that one or more intermediary elements, layers, areas, or components may exist. Furthermore, this can be collectively referred to as direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, zone, or component is referred to as "electrically connected" or "electrically coupled" to another layer, zone, or component, the layer, zone, or component can be directly electrically connected or coupled to the other layer, zone, or component, or one or more intermediary layers, zones, or components may be present. One or more intermediary components may include switches, resistors, and / or capacitors, etc. In describing embodiments, unless explicitly described as a direct connection, the term "connection" indicates an electrical connection, and "directly connected / directly coupled" or "directly on" means that a component is directly connected or directly coupled to another component or directly on another component without an intermediary component.

[0052] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing relationships between components, such as "between," "directly between," "adjacent to," and "closely adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0053] For the purposes of this disclosure, expressions such as “at least one of…” or “any one of…” or “one or more of…” modify the entire list of elements, rather than individual elements in the list, when following a list of elements. For example, “at least one of X, Y, and Z”, “at least one selected from the group consisting of X, Y, and Z”, and “at least one selected from the group consisting of X, Y, or Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ or any variant thereof). Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when expressions such as "at least one of...", "multiple of...", "one of...", and other prepositional phrases follow a list of elements, they modify the entire list of elements, not individual elements within the list. Unless otherwise stated, when "C to D" is stated, it means C or more and D or fewer.

[0054] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, assembly, area, region, layer, segment, or part from another element, component, assembly, area, region, layer, segment, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first assembly, first area, first layer, or first segment described below may be referred to as a second element, second assembly, second area, second layer, or second segment. Describing an element as a first element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0055] In this example, the X-axis, Y-axis, and / or Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0056] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It will also be understood that when the terms “comprises,” “have,” and “includes,” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0057] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of ±5% of the corresponding value. Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), “about” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, in describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0058] In some embodiments, well-known structures and devices may be described in conjunction with one or more functional blocks (e.g., block diagrams), units, and / or modules in the accompanying drawings to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuits, individual components, microprocessors, hardwired circuits, memory elements, wiring connections, and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and optionally can be driven by firmware and / or software. Furthermore, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and a processor performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Additionally, in some embodiments, blocks, units, and / or modules may be physically divided into two or more interactive separate blocks, units, and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, without departing from the scope of this disclosure, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules.

[0059] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense.

[0060] Figure 1 This is a perspective view illustrating one or more embodiments of the display device of this disclosure.

[0061] Reference Figure 1 This disclosure can be applied to the display device DD when the display device DD is an electronic device in which a display surface is applied to a surface (such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, PDA, portable multimedia player (PMP), MP3 player, medical device, camera or wearable device).

[0062] The display device DD can be provided in various shapes, and for example, the display device DD can be provided in a rectangular planar shape with two pairs of sides parallel to each other, but this disclosure is not limited thereto. When the display device DD is provided in a rectangular planar shape, one pair of sides can be provided to be longer than the other pair of sides. In the drawings, the display device DD has angled corners formed by straight lines, but this disclosure is not limited thereto. According to one or more embodiments, the display device DD provided in a rectangular planar shape can have a rounded shape at the corner where one long side and one short side meet each other.

[0063] In one or more embodiments of this disclosure, for ease of description, the display device DD has a rectangular planar shape having a pair of long sides and a pair of short sides. In this case, the extending direction of the long side can be indicated as a second direction DR2, the extending direction of the short side can be indicated as a first direction DR1, and the direction perpendicular to the extending directions of the long and short sides can be indicated as a third direction DR3. The first direction DR1 to the third direction DR3 can respectively refer to the directions indicated by the first direction DR1 to the third direction DR3.

[0064] In one or more embodiments of this disclosure, at least a portion of the display device DD may be flexible, and the display device DD may be folded at the flexible portion.

[0065] The display device DD may include a display area DA for displaying an image and a non-display area NDA provided on at least one side of the display area DA. The non-display area NDA may be an area in which no image is displayed. However, this disclosure is not limited thereto. According to one or more embodiments, the shape of the display area DA and the shape of the non-display area NDA may be designed relative to each other.

[0066] Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0067] Reference Figure 2 The display device DD may include a display panel DP, a sensing panel TSP (or a touch sensor) and a window WD.

[0068] The display panel DP can be accessed through the display area DA (refer to...). Figure 1The display panel DP can be a self-emitting display panel, such as an organic light-emitting display panel (OLED panel) using organic light-emitting diodes as light-emitting elements, an ultra-small light-emitting diode display panel (nanoscale LED display panel) using ultra-small light-emitting diodes as light-emitting elements, and a quantum dot organic light-emitting display panel (QD OLED panel) using quantum dots and organic light-emitting diodes. Alternatively, non-emissive display panels such as liquid crystal display panels (LCD panels), electrophoretic display panels (EPD panels), and electrowetting display panels (EWD panels) can be used as the display panel DP. When a non-emissive display panel is used as the display panel DP, the display device DD may include a backlight unit that supplies light to the display panel DP.

[0069] The touch sensor panel (TSP) can be positioned on the display panel (DP) and can receive user touch input. The TSP can sense touch input using either mutual capacitance or self-capacitance methods.

[0070] Window WDs, used to protect exposed surfaces, can be provided on display panels (DP) and sensor panels (TSP). Window WDs protect the DP and TSP from external impacts and provide input and / or display surfaces to the user. Window WDs can be combined with display panels (DP) and TSP using optically clear adhesive (or bonding) components (OCA).

[0071] Window WD can have a multi-layered structure selected from glass substrates, plastic films, and plastic substrates. Such a multi-layered structure can be formed by a continuous process or by an adhesive process using adhesive layers. All or part of the window WD can be flexible.

[0072] Figure 3 It is shown Figure 2 A cross-sectional view of one or more embodiments of a display panel.

[0073] Reference Figure 3 The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a thin film encapsulation layer TFE.

[0074] The substrate SUB can be a rigid substrate or a flexible substrate. Here, when the substrate SUB is a rigid substrate, it can be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate. When the substrate SUB is a flexible substrate, it can be one of a membrane substrate including polymeric organic materials and a plastic substrate. Furthermore, the substrate SUB can include glass fiber reinforced plastic (GFRP).

[0075] The pixel circuit layer (PCL) can be positioned on the substrate (SUB). Multiple thin-film transistors (TFTs) and lines connected to the TFTs can be arranged within the PCL. For example, each TFT can have a structure in which a semiconductor layer, a gate electrode, and source / drain electrodes are sequentially stacked with an insulating layer interposed therebetween. The semiconductor layer can include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, and organic semiconductors. The gate electrode and source / drain electrodes can include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but this disclosure is not limited thereto. Furthermore, the PCL can include one or more insulating layers.

[0076] The display element layer (DPL) can be positioned on the pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements for emitting light. The light-emitting element may be, for example, an organic light-emitting diode (OLED), but this disclosure is not limited thereto. According to one or more embodiments, the light-emitting element may be an inorganic light-emitting element comprising inorganic light-emitting materials or a light-emitting element that emits light by changing the wavelength of light emitted using quantum dots (quantum dot display element).

[0077] A thin-film encapsulation layer (TFE) can be positioned on the display element layer (DPL). The TFE can be an encapsulation substrate or have a structure consisting of multiple layers. When the TFE has an encapsulation layer structure, it can include inorganic and / or organic layers. For example, the TFE can have a structure in which inorganic layers, organic layers, and inorganic layers are sequentially stacked. The TFE can reduce or prevent external air and moisture from penetrating into the display element layer (DPL) and the pixel circuit layer (PCL).

[0078] Figure 4 It is shown Figure 2 A cross-sectional view of one or more embodiments of the sensing panel.

[0079] Reference Figure 4 The sensing panel TSP (or touch sensor) can be directly positioned within the display panel DP (see reference). Figure 3 The image is displayed on the surface to receive touch input and / or hover input from the user. Here, "directly positioned on" can mean formed by a continuous process, excluding attachment using a separate adhesive layer (or bonding layer). The sensing panel TSP can sense touch capacitance through contact and / or proximity by a separate input method such as the user's hand or a similar conductor, to identify the display device DD (refer to...). Figure 2Touch input and / or hover input. Here, touch input may mean direct touch (or contact) by the user's hand or other input methods, and hover input may mean the user's hand or other input methods being near the display device DD, including the sensing panel TSP, but not touching the display device DD.

[0080] The sensing panel TSP can have a multi-layer structure. The sensing panel TSP may include at least one conductive layer and at least one insulating layer.

[0081] For example, a sensing panel TSP may include a substrate layer BSL, a first conductive layer CPL1, a first insulating layer TS_INS1, a second conductive layer CPL2, and a second insulating layer TS_INS2.

[0082] The first conductive layer CPL1 can be directly positioned on the thin-film encapsulation layer TFE of the display panel DP, but this disclosure is not limited thereto. According to one or more embodiments, another insulating layer, such as the substrate layer BSL, can be positioned between the first conductive layer CPL1 and the thin-film encapsulation layer TFE. In this case, the first conductive layer CPL1 can be directly positioned on the substrate layer BSL.

[0083] Each of the first conductive layer CPL1 and the second conductive layer CPL2 may have a single-layer structure or a multilayer structure stacked in the thickness direction. The single-layer conductive layer may include a conductive material. For example, the conductive material may include metals such as molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), or alloys thereof, or may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0084] The conductive layer of a multilayer structure may include multiple metal layers. These multiple metal layers may have a three-layer structure, such as titanium (Ti) / aluminum (Al) / titanium (Ti), but are not limited to this. The conductive layer of a multilayer structure may include multiple metal layers and a transparent conductive layer.

[0085] According to one or more embodiments, the first conductive layer CPL1 and the second conductive layer CPL2 may include Figure 8 The sensor electrode SEN and Figure 8 The sensing lines SL1 and SL2.

[0086] Each of the first insulating layer TS_INS1 and the second insulating layer TS_INS2 may comprise an inorganic or organic material. The inorganic material may comprise silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) xOrganic materials may include at least one of the following: acrylic resins, methacrylic resins, polyisoprene resins, ethylene resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0087] Figure 5 It is shown Figure 1 A block diagram of one or more embodiments of a display device.

[0088] Reference Figure 5 The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0089] The display panel DP may include sub-pixels SPX. Sub-pixels SPX can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SPX can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0090] Each of the sub-pixels SPX may include at least one light-emitting element configured to generate light. Therefore, each of the sub-pixels SPX may generate light of a corresponding color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels SPX may constitute one pixel (not shown). For example, three sub-pixels SPX may constitute one pixel.

[0091] Gate driver 120 can be connected to sub-pixels SPX arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In an embodiment, gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for timing-synchronizing the output of gate signals with applied data signals, etc.

[0092] In an embodiment, first emission control lines EL1 to m-th emission control lines ELm connected to the sub-pixels SPX in the row direction may also be provided. In this case, gate driver 120 may include emission control drivers configured to control the first emission control lines EL1 to m-th emission control lines ELm, and the emission control drivers may operate under the control of controller 150.

[0093] The gate driver 120 may be positioned on one side of the display panel DP. However, the embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and the drivers may be positioned on one side of the display panel DP and on the opposite side of the display panel DP, respectively. As described above, according to the embodiments, the gate driver 120 may be positioned around the display panel DP in various shapes.

[0094] Data driver 130 can be connected to sub-pixels SPX arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 can receive image data DATA and data control signal DCS from controller 150. Data driver 130 can operate in response to data control signal DCS. In an embodiment, data control signal DCS may include source start pulse, source shift clock, and source output enable signal, etc.

[0095] The data driver 130 can use the voltage from the voltage generator 140 to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the corresponding sub-pixel SPX can generate light corresponding to the data signal. Thus, an image can be displayed in the display panel DP.

[0096] In one embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0097] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can be configured to generate multiple voltages and provide the generated voltages to components of display device DD. For example, voltage generator 140 can be configured to generate multiple voltages by receiving an input voltage from outside display device DD, adjusting the received voltage, and regulating the adjusted voltage.

[0098] Voltage generator 140 can generate a first electrical voltage and a second electrical voltage. The first electrical voltage and the second electrical voltage can be provided to the sub-pixel SPX via a first electrical line VDDL and a second electrical line VSSL, respectively. The first electrical voltage can have a relatively high voltage level, and the second electrical voltage can have a voltage level lower than that of the first electrical voltage VDD. In other embodiments, the first electrical voltage or the second electrical voltage can be provided by an external device of the display device DD.

[0099] Furthermore, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to the sub-pixel SPX. For example, during sensing operation for sensing the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SPX, a reference voltage (e.g., a predetermined reference voltage) can be applied to the first data lines DL1 to the nth data lines DLn, and voltage generator 140 can generate the reference voltage.

[0100] The controller 150 can control the overall operation of the display device DD. The controller 150 can receive input image data IMG and control signal CTRL from an external source. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0101] The controller 150 can convert the input image data IMG to fit the display device DD or display panel DP, and can output image data DATA. In an embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to fit the sub-pixels of the row unit SPX.

[0102] Two or more of the data driver 130, voltage generator 140, and controller 150 may be housed in a single integrated circuit. For example, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit. In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separated components within a single driver integrated circuit. In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component distinct from the driver integrated circuit.

[0103] Figure 6 It is shown Figure 5 A block diagram of one or more embodiments of one of the sub-pixels.

[0104] exist Figure 6 In Figure 5 Among the sub-pixels SPX, the sub-pixel SPXij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0105] Reference Figure 6 Subpixel SPXij may include subpixel circuit SPC and light-emitting element LD.

[0106] The light-emitting element (LD) can be connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN can be connected to a first power line VDDL and can receive a first power voltage. The second power voltage node VSSN can be connected to a second power line VSSL and can receive a second power voltage. The first power voltage can have a higher voltage level than the second power voltage.

[0107] The light-emitting element (LD) has an anode electrode AE ​​and a cathode electrode CE. The anode electrode AE ​​can be connected to a first power voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to a second power voltage node VSSN. The light-emitting element LD can be configured to emit light according to the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0108] Sub-pixel circuits (SPCs) can be connected to Figure 5 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm and Figure 5 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. In response to a gate signal received via the i-th gate line GLi, the sub-pixel circuit SPC can control the light-emitting element LD to emit light based on the data signal received via the j-th data line DLj. The i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. In an embodiment, the sub-pixel circuit SPC may be further connected to... Figure 5 The first emission control line EL1 to the m-th emission control line ELm is the i-th emission control line ELi. In this case, the sub-pixel circuit SPC can further control the light-emitting element LD in response to the emission control signal received through the i-th emission control line ELi.

[0109] For such an operation, the subpixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0110] The transistors in the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors in the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, the transistors in the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, and oxide semiconductors, etc.

[0111] Figure 7 It is shown Figure 1 A plan view of one or more embodiments of the display panel of a display device.

[0112] Reference Figure 7 The display panel (DP) can include the display area (DA) and the non-display area (NDA).

[0113] The display area DA can be the area where an image is displayed. The display area DA can include multiple sub-pixels SPX, multiple power lines VL, and multiple signal lines SVL.

[0114] According to one or more embodiments, multiple power lines VL can be transmitted from voltage generator 140 (see reference 140). Figure 5 The received power voltage is supplied to multiple sub-pixels SPX. Here, the power voltage can be at least one of a first power voltage, a second power voltage, an initialization voltage, and a reference voltage. Multiple power lines VL can extend along a second direction DR2 and can be spaced apart from each other along a first direction DR1 that intersects the second direction DR2. Some of the multiple power lines VL can be reference voltages. Figure 6 The first power line VDDL and the second power line VSSL are described.

[0115] Multiple signal lines SVL can be used to switch from data driver 130 (reference) Figure 5 The received data signals are supplied to multiple sub-pixels SPX. Here, in addition to data lines DL1 to DLn (refer to...) Figure 5 In addition to the signal lines SVL, multiple signal lines may also include gate lines GL1 to GLm (see reference). Figure 5 ) and transmit control lines EL1 to ELm (refer to Figure 5 Multiple signal lines SVL can extend in the second direction DR2 and can be spaced apart from each other in the first direction DR1, which intersects with the second direction DR2.

[0116] The Display Pad Area (DPDA) can be located within the non-display area (NDA). The DPDA can be electrically connected to the sub-pixels (SPX) of the display area (DA) via multiple signal lines (SVL) and multiple power lines (VL). The DPDA may include the display pads (DPD).

[0117] Figure 8 It is shown Figure 1 A plan view of one or more embodiments of the sensing panel of a display device.

[0118] Reference Figure 8 The sensing panel TSP may include a sensor area SA (sensing area or active area) capable of sensing touch input and (e.g., in a plan view) a non-sensor area NSA (non-sensing area or inactive area) surrounding at least a portion of the sensor area SA.

[0119] The sensor area SA can be provided in the central area of ​​the sensing panel TSP to be in conjunction with the display area DA (refer to...). Figure 1 (Overlap). The sensor area SA may have a shape substantially the same as, but is not limited to, the shape of the display area DA. Sensor electrodes SEN for sensing touch input may be provided and / or formed in the sensor area SA.

[0120] The non-sensor area (NSA) can be provided in the peripheral area of ​​the sensing panel (TSP) to interact with the non-display area (NDA) (see reference). Figure 1 Overlap. Here, the peripheral region can be (e.g., in a plan view) the region surrounding the central region of the sensing panel TSP. Sensing lines electrically connected to the sensor electrodes SEN to receive and transmit sensing signals can be provided and / or formed in the non-sensor region NSA. Furthermore, a touch pad region TPDA connected to the sensing lines and electrically connected to the sensor electrodes SEN in the sensor region SA can be located in the non-sensor region NSA. The touch pad region TPDA can include a touch pad TPD. The sensing lines can include multiple first sensing lines SL1 and multiple second sensing lines SL2.

[0121] The sensor electrode SEN may include multiple sensor electrodes SE1 and SE2 as well as a connection electrode CTE (or referred to as the "sensor connection electrode").

[0122] The sensor electrode SEN may include a plurality of first sensor electrodes SE1 and a plurality of second sensor electrodes SE2 that are electrically insulated from the plurality of first sensor electrodes SE1.

[0123] The first sensor electrode SE1 can be arranged on the first direction DR1 and can be electrically connected to an adjacent first sensor electrode SE1 via a connecting electrode CTE to configure at least one sensor row. The second sensor electrode SE2 can be arranged on the second direction DR2, which intersects the first direction DR1, and can be electrically connected to an adjacent second sensor electrode SE2 to form at least one sensor column.

[0124] The first sensor electrode SE1 and the second sensor electrode SE2 can be electrically connected to the touch pad TPD via corresponding sensing lines. As an example, the first sensor electrode SE1 can be electrically connected to the touch pad TPD via the first sensing line SL1, and the second sensor electrode SE2 can be electrically connected to the touch pad TPD via the second sensing line SL2.

[0125] The first sensor electrode SE1 can be a driving electrode for receiving a driving signal for detecting a touch position in the sensor region SA, and the second sensor electrode SE2 can be a sensing electrode for outputting a sensing signal for detecting a touch position in the sensor region SA. However, this disclosure is not limited thereto, and the first sensor electrode SE1 can be a sensing electrode and the second sensor electrode SE2 can be a driving electrode.

[0126] According to one or more embodiments, the sensing panel TSP can identify a user's touch by sensing the change in mutual capacitance formed between the first sensor electrode SE1 and the second sensor electrode SE2.

[0127] Figure 9 It is shown Figure 8 Enlarged view of one or more embodiments of part A. Figure 10 It is shown in Figure 1 In the display device Figure 8 Enlarged views of one or more embodiments of part A. (Compared to) Figure 9 The difference lies in Figure 10 The transmission areas EMA1 to EMA6 are shown in the diagram.

[0128] Reference Figure 8 , Figure 9 and Figure 10 Each of the multiple sensor electrodes SE1 and SE2 can have a sensor pattern overlapping with the non-emitting region NEMA. In this case, the non-emitting region NEMA can refer to the area other than the emitting region EMA. For example, the non-emitting region NEMA can be associated with the pixel-defining layer (see reference). Figure 11 The pixel-defined layer (PDL) overlaps. The sensor pattern may include a first sensor pattern SPT1, a second sensor pattern SPT2, a bridging pattern BPT, and at least one dummy pattern DPT.

[0129] The first sensor pattern SPT1 and the second sensor pattern SPT2 can be positioned in the same layer and can be spaced apart from each other. The first sensor pattern SPT1 and the second sensor pattern SPT2 can be connected to each other at corresponding points. The first sensor pattern SPT1 and the second sensor pattern SPT2 can be included in the first conductive layer CPL1 (see reference). Figure 4 )middle.

[0130] A first sensor pattern SPT1 may extend along a first direction DR1 and may be spaced out along a second direction DR2 that intersects the first direction DR1. The first sensor pattern SPT1 may have a first width W1 along the second direction DR2. Furthermore, a second sensor pattern SPT2 may extend along the second direction DR2 and may be spaced out along the first direction DR1. The second sensor pattern SPT2 may have a fifth width W5 along the first direction DR1. In one or more embodiments, the fifth width W5 may be the same width as the first width W1.

[0131] A bridging pattern BPT can extend along a first direction DR1 and can electrically connect spaced-apart second sensor patterns SPT2 to each other. The bridging pattern BPT can be positioned in a different layer from the first sensor patterns SPT1 and the second sensor patterns SPT2. For example, the bridging pattern BPT can be connected to one of the second sensor patterns SPT2 through a first contact hole CTH1 and can extend partially in a direction opposite to a third direction DR3. The bridging pattern BPT can be bent at the overlapping portion with the first sensor patterns SPT1 and the second sensor patterns SPT2 and can extend along the first direction DR1. Furthermore, the bridging pattern BPT can extend partially along a third direction DR3 through a second contact hole CTH2 and can be connected to the other of the second sensor patterns SPT2. Therefore, the bridging pattern BPT can extend along the first direction DR1 and can connect the second sensor patterns SPT2.

[0132] At least one dummy pattern DPT can be positioned in a different layer from the first sensor pattern SPT1 and the second sensor pattern SPT2. Furthermore, at least one dummy pattern DPT can be positioned in the same layer as the bridging pattern BPT. At least one dummy pattern DPT and the bridging pattern BPT can be included in the second conductive layer CPL2 (see reference). Figure 4 )middle.

[0133] At least one dummy pattern DPT may have a second width W2 that is greater than the first width W1 in the second direction DR2, and may have a sixth width W6 that is greater than the fifth width W5 in the first direction DR1.

[0134] At least one dummy pattern DPT may overlap with at least one of the first sensor pattern SPT1 and the bridging pattern BPT in a planar view. In an embodiment, at least one dummy pattern DPT may be one of a first dummy pattern DPT1 overlapping with the connection electrode CPT, a second dummy pattern DPT2 connected to a portion of the bridging pattern BPT, and a third dummy pattern DPT3 overlapping with the first sensor pattern SPT1. According to one or more embodiments, the first dummy patterns DPT1 to the third dummy patterns DPT3 may have different widths. However, the embodiments are not limited thereto, and the first dummy patterns DPT1 to the third dummy patterns DPT3 may have the same width.

[0135] The first dummy pattern DPT1 can be positioned within the non-emitting region NEMA and can overlap with the connection electrode CPT configured to transmit electrical voltage. That is, the connection electrode CPT can be positioned between the second power line VSSL and the first dummy pattern DPT1. Furthermore, the third dummy pattern DPT3 can overlap with one of the first sensor patterns SPT1 extending in the first direction DR1. Both the first dummy pattern DPT1 and the third dummy pattern DPT3 can be electrically levitated.

[0136] The second dummy pattern DPT2 can be connected to a portion of the bridging pattern BPT. In this case, the second dummy pattern DPT2 may include a first portion DPT2_1 protruding from the bridging pattern BPT in the second direction DR2 and a second portion DPT2_2 protruding from the bridging pattern BPT in the opposite direction to the second direction DR2. The second dummy pattern DPT2 can be connected to a portion of the bridging pattern BPT to electrically connect the second sensor patterns SPT2 to each other.

[0137] Reference Figure 8 and Figure 10 The first sensor pattern SPT1 and the second sensor pattern SPT2 can be formed in a planar view in a mesh or network structure. The first sensor pattern SPT1 and the second sensor pattern SPT2 can surround the sub-pixels SPX that form pixel PXL in the planar view (see reference). Figure 5 The first sensor pattern SPT1 and the second sensor pattern SPT2 may not overlap with the emission area EMA. Furthermore, the bridging pattern BPT and at least one dummy pattern DPT may not overlap with the emission area EMA. Therefore, the display device DD (refer to...) Figure 1 This can reduce or prevent a decrease in the brightness of light emitted from the EMA emission area due to the sensor panel TSP.

[0138] According to one or more embodiments, the emission region EMA can be arranged in sub-pixel columns CLM1 to CLM8. Figure 10 In the diagram, the first subpixel columns CLM1 through the eighth subpixel columns CLM8 are shown as an example. However, this is for simplicity, and the display panel DP may include more subpixel columns. Each of the emitting areas EMA may include a light-emitting element.

[0139] The first sub-pixel columns CLM1 to the eighth sub-pixel columns CLM8 can be arranged on the first direction DR1. The emission region EMA of each of the first sub-pixel columns CLM1 to the eighth sub-pixel columns CLM8 can be arranged on the second direction DR2.

[0140] Emitting regions emitting the same color of light can be arranged in even-numbered sub-pixel columns CLM2, CLM4, CLM6, and CLM8. For example, emitting regions for emitting green light can be arranged in even-numbered sub-pixel columns CLM2, CLM4, CLM6, and CLM8. In this case, emitting regions for emitting light of a different color than that of the even-numbered sub-pixel columns CLM2, CLM4, CLM6, and CLM8 can be arranged in odd-numbered sub-pixel columns CLM1, CLM3, CLM5, and CLM7. For example, in odd-numbered sub-pixel columns CLM1, CLM3, CLM5, and CLM7, emitting regions for emitting red light and emitting regions for emitting blue light can be arranged alternately.

[0141] Reference Figure 10 In each of the even-numbered subpixel columns CLM2, CLM4, CLM6, and CLM8, the emitting regions EMA and the non-emitting regions NEMA between the emitting regions EMA can be alternately arranged with relatively narrow and wide distances. As an example, the second subpixel column CLM2 may include a first emitting region EMA1, a second emitting region EMA2, and a third emitting region EMA3 arranged along a second direction DR2. The second emitting region EMA2 may be spaced from the first emitting region EMA1 by a first distance D1 along the second direction DR2. Furthermore, the third emitting region EMA3 may be spaced from the second emitting region EMA2 by a second distance D2 greater than the first distance D1 along the second direction DR2.

[0142] Furthermore, the fourth sub-pixel column CLM4 may include a fourth emission region EMA4, a fifth emission region EMA5, and a sixth emission region EMA6 arranged along the second direction DR2. The fifth emission region EMA5 may be spaced from the fourth emission region EMA4 by a third distance D3 along the second direction DR2. Furthermore, the sixth emission region EMA6 may be spaced from the fifth emission region EMA5 by a fourth distance D4 along the second direction DR2 that is smaller than the third distance D3. Here, the third distance D3 may be the same as the second distance D2, and the fourth distance D4 may be the same as the first distance D1, but is not limited thereto.

[0143] At least one of the first sensor pattern SPT1 and the bridging pattern BPT can be positioned between the first transmitting region EMA1 and the second transmitting region EMA2, between the second transmitting region EMA2 and the third transmitting region EMA3, between the fourth transmitting region EMA4 and the fifth transmitting region EMA5, and between the fifth transmitting region EMA5 and the sixth transmitting region EMA6. For example, the first sensor pattern SPT1 can extend in the first direction DR1 across the first transmitting region EMA1 and the second transmitting region EMA2, across the second transmitting region EMA2 and the third transmitting region EMA3, and across the fifth transmitting region EMA5 and the sixth transmitting region EMA6. The bridging pattern BPT can extend in the first direction DR1 across the fourth transmitting region EMA4 and the fifth transmitting region EMA5.

[0144] At least one dummy pattern DPT can be positioned in the corresponding sub-pixel column between relatively far-distributed emission regions EMA. For example, at least one dummy pattern DPT can be positioned in the planar view between the second emission region EMA2 and the third emission region EMA3, and between the fourth emission region EMA4 and the fifth emission region EMA5. As described above, by positioning at least one dummy pattern DPT in the corresponding sub-pixel column within the non-emission regions NEMA between relatively far-distributed emission regions EMA, the reduction in optical visibility caused by identifying sensor patterns, etc., can be reduced or prevented.

[0145] In the above embodiments, as an example, the first sensor pattern SPT1 and the second sensor pattern SPT2 are included in the first conductive layer CPL1 (refer to...). Figure 4 In the second conductive layer CPL2, at least one dummy pattern DPT and / or bridging pattern BPT is included, and at least one dummy pattern DPT and / or bridging pattern BPT is included. Figure 4 However, this disclosure is not limited thereto. According to one or more embodiments, the first sensor pattern SPT1 and the second sensor pattern SPT2 may be included in the second conductive layer CPL2, and at least one dummy pattern DPT and / or bridging pattern BPT may be included in the first conductive layer CPL1.

[0146] Figure 11 It is along Figure 10 The cross-sectional view taken from line II-II'.

[0147] Reference Figure 10 and Figure 11 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SPX1 containing a light-emitting element that emits light of the same color.

[0148] The first sub-pixel SPX1 included in the first pixel PXL1 may include a second emitting region EMA2 that emits light and a non-emitting region NEMA that does not emit light. The first sub-pixel SPX1 included in the second pixel PXL2 may include a third emitting region EMA3 that emits light and a non-emitting region NEMA that does not emit light. Here, the second emitting region EMA2 and the third emitting region EMA3 may be emitting regions that emit light of the same color. In addition, the non-emitting region NEMA may be located between the second emitting region EMA2 and the third emitting region EMA3.

[0149] The display panel DP may include a substrate SUB, a pixel circuit layer PCL provided and / or formed on the substrate SUB, and a display element layer DPL provided and / or formed on the pixel circuit layer PCL (as used herein, "formed on", "provided on", or "positioned on" may mean "above").

[0150] A first sub-pixel SPX1, comprising each of the first pixel PXL1 and the second pixel PXL2, may be provided on a substrate SUB, and the first sub-pixel SPX1 may include a pixel circuit layer PCL, a display element layer DPL provided on the pixel circuit layer PCL, and a thin-film encapsulation layer TFE, wherein the pixel circuit layer PCL includes a sub-pixel circuit SPC (refer to) containing at least one transistor. Figure 6 ).

[0151] exist Figure 11 For convenience, in the pixel circuit layer PCL, the via layer VIA and the electrical connection of the transistor to the source / drain electrode SDL of the anode electrode ELT1 located in the second emitter region EMA2 are shown. However, the pixel circuit layer PCL may also include a transistor and at least one insulating layer. For example, the transistor may include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and may be formed of a thin-film transistor.

[0152] The display element layer (DPL) may include a light-emitting element, a connecting electrode (CPT), and a pixel-defining layer (PDL). The light-emitting element may include an anode electrode (ELT1), a light-emitting layer (EL), and a cathode electrode (ELT2).

[0153] The anode electrode ELT1 can be positioned within the second emission region EMA2 and the third emission region EMA3, respectively. The light-emitting layer EL can be positioned on the anode electrode ELT1. The second emission region EMA2 and the third emission region EMA3 can be emission regions for emitting green light. The second emission region EMA2 and the third emission region EMA3 can be defined as the area of ​​the anode electrode ELT1 exposed by the opening of the pixel defining layer PDL, or as the area where the light-emitting layer EL is positioned.

[0154] The connecting electrode CPT can be located in the non-emitting region NEMA and in the same layer as the anode electrode ELT1, and can be configured to transmit electrical voltage. The connecting electrode CPT can be located below the first dummy pattern DPT1 and can be electrically connected to the second power line VSSL that provides the electrical voltage. However, visibility may be reduced with the formation of the connecting electrode CPT. For example, visibility may be reduced as the connecting electrode CPT is formed in the non-emitting region NEMA with a relatively wide distance, and the pixel defining layer PDL is partially open.

[0155] Therefore, the first dummy pattern DPT1 can overlap with the connecting electrode CPT on the pixel-defining layer PDL. Thus, uniform visibility can be ensured regardless of whether the pixel-defining layer PDL is open, and visibility reduction caused by the connecting electrode CPT can be reduced or prevented.

[0156] The pixel-defining layer (PDL) can partially cover the anode electrode ELT1 and the connecting electrode CPT. However, the PDL overlapping the connecting electrode CPT can be partially opened. On the other hand, the PDL not overlapping the connecting electrode CPT can remain unopened. The first sensor pattern SPT1 and the second sensor pattern SPT2 can be positioned on the pixel-defining layer (PDL).

[0157] The cathode electrode ELT2 can be completely positioned on the pixel confinement layer PDL, the light-emitting layer EL, and the connection electrode CPT. The cathode electrode ELT2 can be electrically connected to the light-emitting layer EL and the connection electrode CPT.

[0158] A thin-film encapsulation layer (TFE) can be provided and / or formed on the display element layer (DPL). A sensing panel (TSP) can be provided and / or formed on the thin-film encapsulation layer (TFE).

[0159] The sensing panel TSP may include a first sensor pattern SPT1 and a second sensor pattern SPT2 positioned on the substrate layer BSL, a bridging pattern BPT, at least one dummy pattern DPT, and a first insulating layer TS_INS1 and a second insulating layer TS_INS2.

[0160] According to one or more embodiments, the first dummy pattern DPT1 can be positioned relative to the first sensor pattern SPT1_1 (i.e., Figure 10A portion of the first sensor pattern SPT1 is positioned between the first sensor pattern SPT1_1 and the display panel DP. A first dummy pattern DPT1 can be positioned between the first sensor pattern SPT1_1 and the connecting electrode CPT. Furthermore, the first dummy pattern DPT1 can overlap with the first sensor pattern SPT1_1 and the connecting electrode CPT. That is, the first dummy pattern DPT1 can be positioned together with the first sensor pattern SPT1_1 and the connecting electrode CPT in the non-emission region NEMA between the second emission region EMA2 and the third emission region EMA3.

[0161] Reference Figure 11 The first dummy pattern DPT1 can have a width different from the width of each of the first sensor pattern SPT1_1 and the connecting electrode CPT that overlap with it. As an example, the first sensor pattern SPT1_1 can have a first width W1 in the second direction DR2. The connecting electrode CPT can have a third width W3 in the second direction DR2 that is greater than the first width W1. In this case, the first dummy pattern DPT1 can have a second width W2 in the second direction DR2 that is greater than the first width W1 of the first sensor pattern SPT1_1. Furthermore, the second width W2 of the first dummy pattern DPT1 can be greater than the third width W3 of the connecting electrode CPT. However, the second width W2 of the first dummy pattern DPT1 can be set to a width between the second emission region EMA2 and the third emission region EMA3 within a range that does not obstruct the viewing angle of the first sub-pixel SPX1.

[0162] As described above, by forming a first dummy pattern DPT1 on the connecting electrode CPT with a width greater than that of the connecting electrode CPT, the amount of light reflection caused by the connecting electrode CPT can be reduced, thereby further improving the visibility of the screen / image.

[0163] Figure 12 It is along Figure 10 The cross-sectional view taken from line III-III'.

[0164] Display device DD (reference) Figure 1 Each of the components can be associated with the above. Figure 11 The embodiments are configured similarly.

[0165] Reference Figure 10 and Figure 12 The second dummy pattern DPT2 can be positioned on the pixel-defined layer PDL. In addition, the third pixel PXL3 and the fourth pixel PXL4 can have the same... Figure 11The configurations of the first pixel PXL1 and the second pixel PXL2 shown are substantially the same or similar. For example, the first sub-pixel SPX1 included in each of the third pixel PXL3 and the fourth pixel PXL4 can be provided on the substrate SUB, and the first sub-pixel SPX1 can include a pixel circuit layer PCL, a display element layer DPL provided on the pixel circuit layer PCL, and a thin film encapsulation layer TFE. In the following, with Figure 11 Repeated descriptions have been omitted.

[0166] Each of the third pixel PXL3 and the fourth pixel PXL4 may include a first sub-pixel SPX1 containing a light-emitting element that emits light of the same color.

[0167] The first sub-pixel SPX1 included in the third pixel PXL3 may include a fourth emitting region EMA4 that emits light and a non-emitting region NEMA that does not emit light. The first sub-pixel SPX1 included in the fourth pixel PXL4 may include a fifth emitting region EMA5 that emits light and a non-emitting region NEMA that does not emit light. Here, the fourth emitting region EMA4 and the fifth emitting region EMA5 may be emitting regions used to emit light of the same color.

[0168] According to one or more embodiments, the second dummy pattern DPT2 can be positioned on the pixel definition layer PDL. The second dummy pattern DPT2 can overlap with the pixel definition layer PDL but not with the light-emitting layer EL. The pixel definition layer PDL overlapping with the second dummy pattern DPT2 can be a pixel definition layer PDL located in a non-emitting region NEMA between the fourth emitting region EMA4 and the fifth emitting region EMA5. Furthermore, the second dummy pattern DPT2 can also overlap with the signal line SGL located below the pixel definition layer PDL.

[0169] The second dummy pattern DPT2 may be included on the second direction DR2 from the bridging pattern BPT (see reference). Figure 10 The first prominent part, DPT2_1 (refer to) Figure 9 ) and the second part DPT2_2 protruding in the direction opposite to the second direction DR2 (see reference) Figure 9The second dummy pattern DPT2 may have a width different from the width of the bridging pattern BPT connected to the second dummy pattern DPT2. For example, a portion of the bridging pattern BPT may be connected to the first portion DPT2_1 and the second portion DPT2_2 of the second dummy pattern DPT2. The second dummy pattern DPT2 may be connected to a portion of the bridging pattern BPT and may have a seventh width W7 in the second direction DR2. On the other hand, the remaining portion of the bridging pattern BPT that is not connected to the second dummy pattern DPT2 may have a fourth width W4 in the second direction DR2 that is smaller than the seventh width W7. However, the seventh width W7 of the second dummy pattern DPT2 may be set to a width between the fourth emission region EMA4 and the fifth emission region EMA5 within a range that does not obstruct the viewing angle of the first sub-pixel SPX1.

[0170] Reference Figure 11 and Figure 12 The seventh width W7 of the second dummy pattern DPT2 can be greater than the second width W2 of the first dummy pattern DPT1. As an example, the width of each of the first dummy pattern DPT1 and the second dummy pattern DPT2 can be set such that the first dummy pattern DPT1 and the second dummy pattern DPT2 have the same reflectivity in their respective non-emitting regions NEMA. For example, the first dummy pattern DPT1 can overlap with the first sensor pattern SPT1_1 and the connecting electrode CPT, and can be located in an area where a portion of the pixel defining layer PDL is open. On the other hand, the second dummy pattern DPT2 can be located in an area overlapping with the pixel defining layer PDL. The area where the second dummy pattern DPT2 is located can also overlap with the signal line SGL. Therefore, a difference in reflectivity may occur in the areas where the first dummy pattern DPT1 and the second dummy pattern DPT2 are located. Therefore, by forming the first dummy pattern DPT1 and the second dummy pattern DPT2 with different widths, the first dummy pattern DPT1 and the second dummy pattern DPT2 can be adjusted to have approximately the same reflectivity.

[0171] As described above, by forming a second dummy pattern DPT2 on the pixel-defining layer PDL with a width larger than that of the bridging pattern BPT, the amount of light reflection caused by the pixel-defining layer PDL (and the signal line SGL positioned below the pixel-defining layer PDL) can be reduced, thereby improving the visibility of the screen / image. Furthermore, because the second dummy pattern DPT2 can be connected to the bridging pattern BPT, the bridging pattern BPT can be enlarged.

[0172] Figure 13 It is along Figure 10 The cross-sectional view taken from line IV-IV'.

[0173] Display device DD (reference) Figure 1 Each of the components can be associated with the above. Figure 11 The embodiments are configured similarly.

[0174] Reference Figure 10 and Figure 13 The third dummy pattern DPT3 can be positioned on the pixel-limited layer PDL and can be aligned with the first sensor pattern SPT1_2 (i.e., Figure 10 The first sensor pattern SPT1 overlaps with another part of it. In addition, the fifth pixel PXL5 and the sixth pixel PXL6 can have the same... Figure 11 The configurations of the first pixel PXL1 and the second pixel PXL2 shown are substantially the same or similar. For example, the first sub-pixel SPX1 included in each of the fifth pixel PXL5 and the sixth pixel PXL6 can be provided on the substrate SUB, and the first sub-pixel SPX1 can include a pixel circuit layer PCL, a display element layer DPL provided on the pixel circuit layer PCL, and a thin film encapsulation layer TFE. In the following, with Figure 11 Overlapping descriptions have been omitted.

[0175] Each of the fifth pixel PXL5 and the sixth pixel PXL6 may include a first sub-pixel SPX1 containing a light-emitting element that emits light of the same color.

[0176] The first sub-pixel SPX1 included in the fifth pixel PXL5 may include a second emitting region EMA2' that emits light and a non-emitting region NEMA that does not emit light. The first sub-pixel SPX1 included in the sixth pixel PXL6 may include a third emitting region EMA3' that emits light and a non-emitting region NEMA that does not emit light. Here, the second emitting region EMA2' and the third emitting region EMA3' may be emitting regions used to emit light of the same color.

[0177] According to one or more embodiments, a third dummy pattern DPT3 may be positioned on a pixel-defining layer PDL. The third dummy pattern DPT3 may overlap with a first sensor pattern SPT1_2. The third dummy pattern DPT3 may overlap with the pixel-defining layer PDL but not with the light-emitting layer EL. The pixel-defining layer PDL overlapping with the third dummy pattern DPT3 may be a pixel-defining layer PDL located in a non-emitting region NEMA between the second emitting region EMA2' and the third emitting region EMA3'. Furthermore, the third dummy pattern DPT3 may also overlap with a signal line SGL located below the pixel-defining layer PDL.

[0178] The third dummy pattern DPT3 can be positioned between the first sensor pattern SPT1_2 and the display panel DP. The third dummy pattern DPT3 can be positioned between the first sensor pattern SPT1_2 and the signal line SGL. The third dummy pattern DPT3 can be positioned together with the first sensor pattern SPT1_2 and the signal line SGL in the non-emission area NEMA between the second emission area EMA2' and the third emission area EMA3'.

[0179] Reference Figure 13 The third dummy pattern DPT3 may have a width different from the width of the first sensor pattern SPT1_2 that overlaps with it. As an example, the first sensor pattern SPT1_2 may have a first width W1 in the second direction DR2. The third dummy pattern DPT3 may have an eighth width W8 in the second direction DR2, which is greater than the first width W1 of the first sensor pattern SPT1_2. Furthermore, the eighth width W8 of the third dummy pattern DPT3 may be greater than the width of the signal line SGL. However, the eighth width W8 of the third dummy pattern DPT3 may be set to a width between the second emission region EMA2' and the third emission region EMA3' within a range that does not obstruct the viewing angle of the first sub-pixel SPX1.

[0180] As described above, by forming a third dummy pattern DPT3 on the pixel-defining layer PDL with a width greater than that of the first sensor pattern SPT1_2, the amount of light reflection caused by the pixel-defining layer PDL and the signal line SGL positioned below the pixel-defining layer PDL can be reduced, thereby improving the visibility of the screen / image.

[0181] Reference Figure 11 , Figure 12 and Figure 13The eighth width W8 of the third dummy pattern DPT3 can be greater than the second width W2 of the first dummy pattern DPT1. Furthermore, the eighth width W8 of the third dummy pattern DPT3 can be smaller than the seventh width W7 of the second dummy pattern DPT2. As an example, the width of each of the first dummy patterns DPT1 to the third dummy pattern DPT3 can be set such that the first dummy patterns DPT1 to the third dummy pattern DPT3 have the same reflectivity in their respective non-emissive regions (NEMA). For example, the first dummy pattern DPT1 can overlap with the first sensor pattern SPT1_1 and the connecting electrode CPT, and can be located in an area where a portion of the pixel defining layer PDL is open. The second dummy pattern DPT2 can be located in an area that overlaps with the pixel defining layer PDL and the signal line SGL, but not with the first sensor pattern SPT1. Furthermore, the third dummy pattern DPT3 can be located in an area that overlaps with the first sensor pattern SPT1_2 and the signal line SGL. Therefore, a difference in reflectivity may occur in the areas where the first dummy patterns DPT1 to the third dummy pattern DPT3 are located.

[0182] As described above, the first dummy pattern DPT1 to the third dummy pattern DPT3 can be positioned with different widths. Therefore, consistent reflectivity can be achieved regardless of whether the connecting electrode CPT, signal line SGL, and sensor patterns SPT1_1 and SPT1_2 are positioned, and regardless of whether the pixel defining layer PDL is open. Thus, reductions in optical visibility due to differences in reflectivity can be reduced or prevented.

[0183] Figure 14 It is shown Figure 8 Enlarged views of one or more other embodiments of part A.

[0184] The first sensor pattern SPT1', the second sensor pattern SPT2', the bridging pattern BPT', at least one dummy pattern DPT', the connecting electrode CPT', and the contact hole CTH' can be combined with Figure 10 The embodiments are described similarly. Regarding Figure 10 Overlapping or repetitive descriptions of the embodiments are omitted, and the main description is as follows: Figure 14 The differences between this embodiment and the above embodiment.

[0185] Reference Figure 14 The first sensor pattern SPT1' can extend in the X-axis direction and can be spaced apart in the Y-axis direction, which intersects the X-axis direction. The second sensor pattern SPT2' can extend in the Y-axis direction and can be spaced apart in the X-axis direction. The second sensor pattern SPT2' can be positioned in the same layer as the first sensor pattern SPT1' and can be connected to the first sensor pattern SPT1'.

[0186] The bridging pattern BPT' can extend in the X-axis direction and can electrically connect the spaced-apart second sensor patterns SPT2' to each other. The bridging pattern BPT' can be positioned in a different layer from the first sensor pattern SPT1' and the second sensor pattern SPT2'. The bridging pattern BPT' can extend in the X-axis direction and can connect the second sensor patterns SPT2'.

[0187] The first sensor pattern SPT1' and the second sensor pattern SPT2' can be formed in a planar view as a mesh or network structure. The first sensor pattern SPT1' and the second sensor pattern SPT2' can be formed in a planar view around the sub-pixels SPX that form the pixels (see reference). Figure 5 Each of the subpixels in the SPX has an emission region EMA'. At this point, each of the subpixels in the SPX can be arranged in a diamond structure.

[0188] According to one or more embodiments, the emission region EMA' can be arranged in sub-pixel columns CLM1' to CLM6'. The first sub-pixel columns CLM1' to the sixth sub-pixel columns CLM6' can be arranged in a first direction DR1. Each of the first sub-pixel columns CLM1' to the sixth sub-pixel columns CLM6' can extend in a second direction DR2. In this case, the first direction DR1 can be a diagonal direction in which the X-axis direction intersects with a direction opposite to the Y-axis direction, and the second direction DR2 can be a diagonal direction in which the X-axis direction and the Y-axis direction intersect.

[0189] A third emission region EMA3' emitting light of the same color can be arranged in even-numbered sub-pixel columns CLM2', CLM4', and CLM6'. Conversely, emission regions emitting light of a different color than that of the even-numbered sub-pixel columns CLM2', CLM4', and CLM6' can be arranged in odd-numbered sub-pixel columns CLM1', CLM3', and CLM5'. For example, the first emission region EMA1' and the second emission region EMA2' can be arranged alternately in the odd-numbered sub-pixel columns CLM1', CLM3', and CLM5'. In this case, the third emission region EMA3' can be arranged to be spaced apart from each other in the first direction DR1 and the second direction DR2. The first emission region EMA1' or the second emission region EMA2' can be arranged adjacent to the third emission region EMA3' in the X-axis direction or the Y-axis direction.

[0190] Reference Figure 14At least one dummy pattern DPT' may be positioned between adjacent emission regions EMA' of each of the first sub-pixel columns CLM1' to the sixth sub-pixel columns CLM6'. In each of the first sub-pixel columns CLM1' to the sixth sub-pixel columns CLM6', at least one dummy pattern DPT' may be arranged in a non-emission region NEMA' located between the emission regions EMA'. For example, at least one dummy pattern DPT' may be arranged in each non-emission region NEMA' located between adjacent third emission regions EMA3'.

[0191] At least one dummy pattern DPT' may overlap with at least one of the points in the plan view where the first sensor pattern SPT1' and the second sensor pattern SPT2' intersect and where the bridging pattern BPT' and the second sensor pattern SPT2' intersect.

[0192] In an embodiment, at least one dummy pattern DPT' may be one of a first dummy pattern DPT1' overlapping with the connecting electrode CPT', a second dummy pattern DPT2' connected to a portion of the bridging pattern BPT', and a third dummy pattern DPT3' overlapping with the first sensor pattern SPT1'. The first dummy pattern DPT1' to the third dummy pattern DPT3' may be... Figures 11 to 13 The embodiments are described similarly. Regarding Figures 11 to 13 The overlapping descriptions of the embodiments are omitted.

[0193] In the display device according to embodiments of the present disclosure, by positioning at least one dummy pattern in a non-emission region between relatively far emission regions in a corresponding sub-pixel column, optical visibility reduction caused by identification sensor patterns, etc., can be reduced or prevented. For example, according to embodiments of the present disclosure, when at least one dummy pattern is positioned on a pixel defining layer to overlap with a connecting electrode, uniform visibility can be ensured regardless of whether the pixel defining layer is open, and visibility reduction caused by the connecting electrode can be reduced or prevented.

[0194] According to embodiments of this disclosure, a display device with improved reliability is provided.

[0195] Although specific embodiments and applications have been described herein, other embodiments and variations can be derived from the above description. Therefore, the spirit of this disclosure is not limited to these embodiments, but extends to the scope of the appended claims, various obvious modifications and equivalents.

[0196] The effects of the embodiments are not limited to those illustrated above, and further various effects are included in this specification.

Claims

1. A display device, wherein, The display device includes: A display panel, comprising multiple emitting areas and non-emitting areas between the multiple emitting areas; and A sensing panel, above the display panel and having a plurality of sensor patterns overlapping the non-emission area, wherein the plurality of sensor patterns include: A plurality of first sensor patterns extend in a first direction and are spaced apart in a second direction intersecting the first direction, and each of the plurality of first sensor patterns has a first width in the second direction; A plurality of second sensor patterns, located on the same layer as the plurality of first sensor patterns, connected to the plurality of first sensor patterns, extending in the second direction, and spaced apart in the first direction; and At least one dummy pattern is located on a different layer from the plurality of first sensor patterns and the plurality of second sensor patterns, and the at least one dummy pattern has a second width in the second direction that is greater than the first width.

2. The display device according to claim 1, wherein, The display panel includes: Anode electrode, in the emission region; and The connecting electrode, located in the non-emission region and on the same layer as the anode electrode, is configured to transmit electrical voltage and overlaps with the at least one dummy pattern.

3. The display device according to claim 2, wherein, The display panel further includes: power lines, below the connecting electrodes, configured to provide the power voltage and electrically connected to the connecting electrodes, and The connecting electrode is located between the electric field line and the at least one dummy pattern.

4. The display device according to claim 2, wherein, The connecting electrode has a third width in the second direction that is smaller than the second width, and The third width is greater than the first width.

5. The display device according to claim 1, wherein, The plurality of sensor patterns further include: a bridging pattern, which is on the same layer as the at least one dummy pattern, extends in the first direction, and electrically connects the plurality of second sensor patterns to each other.

6. The display device according to claim 5, wherein, The at least one dummy pattern includes a first portion protruding from the bridging pattern in the second direction and a second portion protruding in the opposite direction to the second direction. Wherein, the first portion, the second portion, and the portion of the bridging pattern connected to the first portion and the second portion have the second width in the second direction, and The bridging pattern has a fourth width in the second direction that is smaller than the second width.

7. The display device according to claim 5, wherein, The bridging pattern is located on a different layer than the layers where the plurality of second sensor patterns are located.

8. The display device according to claim 5, wherein, The multiple launch areas include: The first column of the plurality of emission regions is arranged along the second direction and includes: a first emission region; a second emission region spaced apart from the first emission region by a first distance in the second direction; and a third emission region spaced apart from the second emission region by a second distance greater than the first distance in the second direction; and The second column of the multiple emission regions is arranged along the second direction, and In the plan view, the at least one dummy pattern is located between the second emission region and the third emission region. The second column of the plurality of emission regions includes: a fourth emission region; a fifth emission region spaced apart from the fourth emission region by a third distance in the second direction; and a sixth emission region spaced apart from the fifth emission region by a fourth distance less than the third distance in the second direction. The bridging pattern extends in the first direction between the fourth and fifth emission regions, and the bridging pattern has the second width between the fourth and fifth emission regions. The emission regions of the first column and the emission regions of the second column of the plurality of emission regions are configured to emit light of the same color.

9. The display device according to claim 1, wherein, The at least one dummy pattern overlaps with one of the plurality of first sensor patterns.

10. The display device according to claim 1, wherein, Each of the plurality of second sensor patterns has a fifth width in the first direction. Wherein, the at least one dummy pattern has a sixth width in the first direction that is greater than the fifth width, and The fifth width is equal to the first width.

Images