A test structure and test method for a waveguide chip test fixture

Abstract

The application discloses a test structure and a test method for a waveguide chip test fixture, and belongs to the technical field of chip testing. The test structure comprises a first connecting unit connected with a first waveguide port outside the test fixture, and a second connecting unit connected with a test template through an adapter assembly. The test template is arranged on a chip contact surface, and the chip contact surface is arranged on the test fixture, so that the second connecting unit detects the scattering parameter of the test fixture. The adapter assembly is designed to connect the test template and the chip contact surface to test the test fixture, and a two-port test channel is formed by the first connecting unit and the second connecting unit, so that the performance of the test fixture can be accurately evaluated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a test structure and a test method for a waveguide chip test fixture. BACKGROUND

[0002] A microwave waveguide chip is a microwave assembly used for transmitting and controlling electromagnetic waves. Its basic principle is to use the propagation characteristics of electromagnetic waves at a specific frequency to limit the propagation of electromagnetic waves in a closed or semi-closed space through a waveguide structure, thereby achieving efficient energy transmission and precise signal control. Compared with traditional transmission line structures, waveguide systems have significant low-loss characteristics and excellent electromagnetic shielding performance, and are particularly suitable for high-power transmission and signal processing in complex electromagnetic environments.

[0003] In the performance testing of packaged chips, there are many test fixtures for BGA (Ball Grid Array Package, Ball Grid Array Package), QFN (Quad Flat No-leads Package, Quad Flat No-leads Package) and other packaging structures on the market, but there are relatively few test fixtures for microwave waveguide structure chips. The test fixture can only test the waveguide chip, and can only test the total performance index of the waveguide chip after placing the waveguide chip, and cannot evaluate the test fixture, nor can it perform subsequent de-embedding operations. SUMMARY

[0004] The purpose of the present application is to solve the problems existing in the prior art and provide a test structure and a test method for a waveguide chip test fixture.

[0005] To achieve the above purpose, the present application adopts the following technical scheme: a test structure for a waveguide chip test fixture, comprising:

[0006] A first connecting unit is connected to a first waveguide port on the outside of the test fixture.

[0007] A second connecting unit is connected to a test fixture through an adapter assembly. The test fixture is provided on a chip contact surface, and the chip contact surface is installed on the test fixture to enable the second connecting unit to detect the scattering parameters of the test fixture.

[0008] Further description of the above technical scheme: a plurality of second waveguide ports are provided on the chip contact surface.

[0009] Further description of the above technical scheme: the test fixture is installed on the test fixture and is in contact with the upper end surface of the chip contact surface.

[0010] As a further description of the above technical solution: a plurality of through holes are formed on the test template, and any of the through holes corresponds to the position of the second waveguide port.

[0011] As a further description of the above technical solution: the adapter assembly comprises a first test adapter and a second test adapter arranged in the middle of the first test adapter.

[0012] As a further description of the above technical solution: a first adapter port is arranged on the first test adapter, and a second adapter port is formed on the second test adapter, and the second adapter port extends to the outside of the first test adapter.

[0013] As a further description of the above technical solution: a pin shaft and a pin hole are arranged on the side of the first test adapter away from the second adapter port, and the second connecting unit is connected with the adapter assembly through the pin shaft and the pin hole.

[0014] As a further description of the above technical solution: two adapter assemblies are connected back-to-back and connected with the first connecting unit or the second connecting unit.

[0015] Further, a test method for a waveguide chip test fixture is also provided, which is applicable to any of the test structures of the above technical solutions, and the test method comprises:

[0016] The test template and the adapter assembly are installed on the chip contact surface of the test fixture, the connection position of the test template and the chip contact surface is adjusted, and the waveguide port is positioned;

[0017] The first connecting unit and the second connecting unit are installed, the preset waveguide signal is input through the first connecting unit, and the second connecting unit receives a corresponding waveguide signal;

[0018] The waveguide signal received by the second connecting unit is measured to obtain a first scattering parameter, which is used to evaluate the performance of the test fixture.

[0019] As a further description of the above technical solution: two adapter assemblies are connected back-to-back, the preset waveguide signal is input, and a second scattering parameter is obtained.

[0020] The second scattering parameter is processed to obtain a third scattering parameter of one of the adapter assemblies.

[0021] The fourth scattering parameter is obtained by processing the first scattering parameter and the third scattering parameter, which is used as the de-embedding data of the test fixture.

[0022] The above technical solution has the following advantages or beneficial effects:

[0023] By designing an adapter component to connect with the test template and chip contact surface, adjusting the connection position between the test template and chip contact surface, positioning the waveguide port, and testing the test fixture, a dual-port test channel is formed with the first connection unit and the second connection unit, which can accurately evaluate the performance of the test fixture.

[0024] During the testing process, due to the introduction of the adapter component, the scattering parameters of the adapter component are obtained by testing the two adapter components back-to-back. This allows for obtaining more accurate scattering parameters of the adapter component and the test fixture, which can be used for subsequent de-embedding processing. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a perspective view of the test fixture and test structure proposed in this invention;

[0027] Figure 2 This is an exploded view of the test structure proposed in this invention;

[0028] Figure 3 for Figure 2 A magnified view of a section at point A in the middle;

[0029] Figure 4 This is a perspective view of the test template used in this invention;

[0030] Figure 5 The three-dimensional form of the adapter component in this invention Figure 1 ;

[0031] Figure 6 The three-dimensional form of the adapter component in this invention Figure 2 ;

[0032] Figure 7 This is a cross-sectional view of the adapter component in this invention;

[0033] Figure 8 This is a schematic diagram of the structure of two adapter components connected back to back in this invention;

[0034] Figure 9 This is a schematic diagram of the structure for testing the back-to-back connection of the two adapter components in this invention;

[0035] Figure 10 The process of the test method proposed in this invention Figure 1 ;

[0036] Figure 11 Flow of the test method proposed in the present application Figure 2 .

[0037] Legend:

[0038] 1, first connecting unit; 2, test fixture; 3, first waveguide port; 4, second connecting unit; 5, adapter assembly; 51, first test adapter; 511, first adapter port; 512, pin shaft; 513, pin hole; 52, second test adapter; 521, second adapter port; 6, test template; 61, through hole; 7, chip contact surface; 71, second waveguide port. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0040] The existing microwave waveguide chip typically integrates power amplifiers (PAs), low noise amplifiers (LNAs), phase shifters, power dividers and other multifunctional modules, and realizes three-dimensional integration through substrate integrated waveguide (SIW), MEMS and other technologies. Compared with the traditional transmission line structure, the waveguide system has significant low-loss characteristics and excellent electromagnetic shielding performance, and is particularly suitable for high-power transmission and signal processing in complex electromagnetic environments, so it plays an irreplaceable role in chip signal transmission structure, especially in the millimeter wave band above 70 GHz. The conventional transmission line structure and coaxial-like packaging have been difficult to meet the working requirements. In the performance testing of packaged chips, there are many test fixtures of BGA (Ball Grid Array Package, ball grid array packaging), QFN (Quad Flat No-leads Package, square flat no-lead packaging) and other packaging structures on the market, but there are relatively few test fixtures for microwave waveguide structure chips, and only waveguide chips can be tested. The total performance index of the waveguide chip is directly tested after being placed into the waveguide chip, and the test fixture cannot be evaluated, and subsequent de-embedding operation cannot be performed.

[0041] Reference Figures 1-2In one embodiment of the present application, a test structure for a waveguide chip test fixture comprises: a first connecting unit 1 connected with a first waveguide port 3 on the outside of a test fixture 2; a second connecting unit 4 connected with a test template 6 through an adapter assembly 5, the test template 6 is arranged on a chip contact surface 7, and the chip contact surface 7 is installed on the test fixture 2, so that the second connecting unit 4 detects the scattering parameters of the test fixture 2.

[0042] In this embodiment, the first connecting unit 1 and the second connecting unit 4 have the same structure, which is a waveguide flange or a waveguide-coaxial adapter. The first connecting unit 1 and the second connecting unit 4 can be used for input and output of waveguide signals. The upper cover of the test fixture 2 is opened, and the test template 6, the adapter assembly 5 and the second connecting unit 4 are connected in sequence above the chip contact surface 7. The scattering parameters are output, and the test fixture 2 is tested by designing the adapter assembly 5 to connect the test template 6 and the chip contact surface 7. A double-port test channel is formed with the first connecting unit 1 and the second connecting unit 4, which can accurately evaluate the performance of the test fixture 2.

[0043] The test fixture 2 is a waveguide test fixture, and the inside is integrated with a waveguide transmission line. The first waveguide port 3 on the outside of the test fixture 2 transmits the preset waveguide signal to the chip contact surface 7 through the waveguide transmission line for output, and the adapter assembly 5 outputs to the second connecting unit 4 for testing.

[0044] Referring to Figure 3 A plurality of second waveguide ports 71 are arranged on the chip contact surface 7.

[0045] In this embodiment, a plurality of second waveguide ports 71 are arranged on the chip contact surface 7. The second waveguide ports 71 are arranged in a ring, an array or a multi-point distribution. The second waveguide ports 71 correspond to the test ports of the chip to be tested. Different second waveguide ports 71 can be connected to different test signals, and can simulate the waveguide layout of multiple chips. When testing, the chip to be tested does not need to be installed. The adapter assembly 5 is connected to the chip contact surface 7 through the test template 6. If it is necessary to adjust the position of the waveguide port, it is only necessary to adjust the corresponding position of the second waveguide port 71 on the test template 6 and the chip contact surface 7. This simplifies the test operation and reduces the test cost and time.

[0046] Referring to Figure 4 The test template 6 is installed on the test fixture 2 and in contact with the upper end surface of the chip contact surface 7.

[0047] In this embodiment, the test template 6 has a countersunk hole at each corner and is installed on the test fixture 2 through a screw. The test template 6 is located above the chip contact surface 7. After the chip contact surface 7 is placed inside the test fixture 2, the test template 6 is installed above the chip contact surface 7 and in contact with the upper end surface of the chip contact surface 7.

[0048] The test jigs 6 are provided with a plurality of through holes 61, and any through hole 61 corresponds to the position of the second waveguide port 71.

[0049] In the embodiment, the position of any through hole 61 corresponds to the position of the second waveguide port 71 on the chip contact surface 7, and coincides with the center position and direction of the second waveguide port 71, for calibrating the connection position of the adapter assembly 5 and the second waveguide port 71, providing clear mechanical positioning for the connection of the adapter assembly 5, avoiding the coupling loss caused by manual alignment error, if the positions of the second waveguide ports 71 to be tested on the chip contact surface 7 are different, only the position of the through hole 61 connected by the adapter assembly 5 needs to be adjusted, for the positions of the second waveguide ports 71 with close spacing, a plurality of test jigs 6 can be connected for calibration.

[0050] Referring to Figures 5-7 , the adapter assembly 5 includes a first test adapter 51 and a second test adapter 52 arranged in the middle of the first test adapter 51.

[0051] In the embodiment, the adapter assembly 5 is connected with the second waveguide port 71 of the chip contact surface 7, and then matched with the first waveguide port 3 of the test fixture 2, the middle of the first test adapter 51 is provided with a mounting hole, and the second test adapter 52 is arranged at the mounting hole and connected by bolts, and the first test adapter 51 and the second test adapter 52 are used to receive different waveguide signals.

[0052] The first test adapter 51 is provided with a first adapter port 511, and the second test adapter 52 is provided with a second adapter port 521, and the second adapter port 521 extends to the outside of the first test adapter 51.

[0053] In the embodiment, the first adapter port 511 is circumferentially arranged at the end face of the first test adapter 51, and the second adapter port 521 extends vertically to the outside of the first test adapter 51, and the shape is adapted to the through hole 61 and the second waveguide port 71, and connected with the through hole 61 and the second waveguide port 71. By designing the first test adapter 51 and the second test adapter 52 separately, two kinds of adaptive structures are formed, which is convenient for replacing the second adapter port 521 of different sizes, and is convenient for adapting to the second waveguide port 71 of different sizes, so that the first adapter port 511 is standardized, and the purpose of adapting the second waveguide port 71 is achieved by replacing the non-standard second adapter port 521 of different sizes.

[0054] The side of the first test adapter 51 opposite to the second adapter port 521 is provided with a pin shaft 512 and a pin hole 513, and the second connection unit 4 is connected with the adapter assembly 5 through the pin shaft 512 and the pin hole 513.

[0055] In the embodiment, the pin shaft 512 and the pin hole 513 are arranged on the end surface of the first test adapter 51 in the circumferential direction, used for connecting with the second connecting unit 4, and the network analyzer can be directly connected through the adapter assembly 5 or connected through the second connecting unit 4, and the time domain analysis, direct calibration, port extension and other functions of the network analyzer are used to obtain the scattering parameters.

[0056] With reference to Figures 8-9 , the two adapter assemblies 5 are connected back to back and connected with the first connecting unit 1 or the second connecting unit 4.

[0057] In the embodiment, in order to remove the influence of the adapter assembly 5, the two adapter assemblies 5 are connected back to back, and in order to ensure the alignment accuracy between the adapter assemblies 5, the through hole 61 of the test template 6 is used to connect from both sides, and the scattering parameters of a single adapter assembly 5 can be obtained through calculation and processing, and the scattering parameters received by the second connecting unit 4 are processed to obtain more accurate scattering parameters of the test fixture 2, which is used to evaluate the performance of the test fixture 2.

[0058] With reference to Figure 10 , the application also includes an embodiment of a test method for a waveguide chip test fixture, the test method is suitable for any test structure in the above technical solutions, and the test method comprises the following steps:

[0059] S1: installing a test template and an adapter assembly on the chip contact surface of the test fixture, adjusting the connection position of the test template and the chip contact surface, and positioning the waveguide port;

[0060] S2: installing a first connecting unit and a second connecting unit, inputting a preset waveguide signal through the first connecting unit, and receiving a corresponding waveguide signal through the second connecting unit;

[0061] S3: measuring the waveguide signal received by the second connecting unit to obtain a first scattering parameter, which is used to evaluate the performance of the test fixture.

[0062] In the embodiment, when the test fixture 2 is opened, the adapter assembly 5 can be directly connected with the chip contact surface 7 of the test fixture 2, the network analyzer can be directly used for measurement to obtain the scattering parameters, and the performance of the test fixture can be preliminarily judged.

[0063] Further, in order to improve the test accuracy, the test template 6 and the adapter assembly 5 are installed on the chip contact surface 7 of the test fixture 2, the position of the test template 6 is adjusted according to the test requirements to determine the position of the second waveguide port 71 to be tested, the waveguide port is positioned, and then the first connection unit 1 is inserted into the first waveguide port 3 outside the test fixture 2, the adapter assembly 5 is inserted into the second waveguide port 71, the second connection unit 4 is connected with the adapter assembly 5, the preset waveguide signal is input through the first connection unit 1, the corresponding waveguide signal is obtained by the second connection unit 4, and the corresponding first scattering parameter is obtained by connecting the network analyzer with the second connection unit 4 for measurement. The first scattering parameter is used for evaluating the performance of the test fixture 2.

[0064] With reference to Figure 11 By setting the test template 6 and the adapter assembly 5 on the test fixture 2, and forming a two-port scattering parameter test channel through the first connection unit 1 and the second connection unit 4, the performance of the test fixture 2 is evaluated. During the test process, due to the introduction of an adapter assembly 5, the loss and possible impedance mismatch are increased in the test link, and it is necessary to further remove the influence of the adapter assembly 5, especially the loss, during the test process.

[0065] A1: The two adapter assemblies are connected back-to-back, a preset waveguide signal is input, and a second scattering parameter is obtained;

[0066] A2: The second scattering parameter is split and processed to obtain a third scattering parameter of one adapter assembly;

[0067] A3: The fourth scattering parameter is obtained by processing the first scattering parameter and the third scattering parameter, which is used as the de-embedding data of the test fixture.

[0068] In this embodiment, the two adapter assemblies 5 are connected back-to-back to form a two-port, and the second scattering parameter is obtained by measuring the network analyzer;

[0069] The second scattering parameter is processed by using the 2X-Thru Split method, the second scattering parameter is split, and the third scattering parameter of a single adapter assembly 5 is obtained; the 2X-Thru Split can be realized by using Matlab or ADS or similar commercial software such as AFR.

[0070] According to the measured first scattering parameter, the fourth scattering parameter of the test fixture 2 is obtained by processing and removing the third scattering parameter, and the obtained fourth scattering parameter can be loaded on the network analyzer for subsequent de-embedding operation.

[0071] It is to be noted that, in the present text, terms such as first and second, and the like, merely refer to one entity or action being distinguished from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0072] Finally, it should be noted that the above-mentioned only constitutes preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications and / or equivalent substitutions of the technical solutions described in the foregoing embodiments can be made, or some technical features thereof can be replaced by equivalent features, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A test structure for a waveguide chip test fixture, characterized by, The utility model relates to a test structure and a test method thereof, comprising: a first connecting unit (1) connected with a first waveguide port (3) outside a test fixture (2); a second connecting unit (4) connected with a test template (6) through an adapter assembly (5), the test template (6) is arranged on a chip contact surface (7), and the chip contact surface (7) is installed on the test fixture (2) to enable the second connecting unit (4) to detect the scattering parameter of the test fixture (2); the adapter assembly (5) comprises a first test adapter (51) and a second test adapter (52) arranged in the middle of the first test adapter (51); a first adapter port (511) is arranged on the first test adapter (51), a second adapter port (521) is formed in the second test adapter (52), and the second adapter port (521) extends to the outside of the first test adapter (51); a pin shaft (512) and a pin hole (513) are arranged on the side of the first test adapter (51) away from the second adapter port (521), and the second connecting unit (4) is connected with the adapter assembly (5) through the pin shaft (512) and the pin hole (513).

2. The test structure of claim 1, wherein: Two adapter assemblies (5) are connected back to back and connected with the first connecting unit (1) or the second connecting unit (4).

3. The test structure of claim 1, wherein: A plurality of second waveguide ports (71) are formed in the chip contact surface (7).

4. The test structure of claim 1, wherein: The test template (6) is installed on the test fixture (2) and contacts the upper end surface of the chip contact surface (7).

5. The test structure of claim 3, wherein: A plurality of through holes (61) are formed in the test template (6), and any through hole (61) corresponds to the position of the second waveguide port (71).

6. A test method for a waveguide chip test fixture, characterized by, The test method is suitable for the test structure in any one of claims 1-5, comprising: installing a test template and an adapter assembly on the chip contact surface of a test fixture, adjusting the connection position of the test template and the chip contact surface, and positioning a waveguide port; installing a first connecting unit and a second connecting unit, inputting a preset waveguide signal through the first connecting unit, and receiving a corresponding waveguide signal through the second connecting unit; measuring the waveguide signal received by the second connecting unit to obtain a first scattering parameter, and using the first scattering parameter to evaluate the performance of the test fixture.

7. The test method according to claim 6, wherein: two adapter assemblies are connected back to back, a preset waveguide signal is inputted, and a second scattering parameter is obtained; the second scattering parameter is processed to obtain a third scattering parameter of one adapter assembly; a fourth scattering parameter is obtained by processing the first scattering parameter and the third scattering parameter, and the fourth scattering parameter is used as the de-embedding data of the test fixture.

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