Data processing method and electronic equipment

Abstract

The invention provides a data processing method, which is applied to a controller, and comprises the following steps: responding to the starting of electronic equipment, and obtaining first data; the first data comprises a signal output to a target port by a first system during operation, the electronic equipment is configured with the first system and a second system, and the first system is used for guiding the second system; responding to the condition that the obtained first data meets the target condition, and obtaining second data; the second data comprises a corresponding parameter value before the configuration parameter managed by the first system is modified, and if the target condition is met, the second system cannot operate normally; adjusting the third data based on the second data, so that the electronic equipment can normally operate the second system; the third data comprises corresponding parameter values after the configuration parameters managed by the first system are modified.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of electronic devices, and more particularly, to a data processing method and an electronic device. BACKGROUND

[0002] The booting of an operating system of an electronic device often relies on a basic input / output system (BIOS) to boot the loading of the operating system. However, during the booting process, a variety of situations that change the variable value in the NVRAM often occur, for example, a user enters the BIOS Setup interface to make start-up settings, password settings, hardware configuration adjustments, and the like. These settings and adjustments change the variable value in the NVRAM, and improper variable values can cause the device to malfunction at an early stage of booting and fail to complete the booting.

[0003] The related art generally performs a recovery operation by the BIOS itself during the booting process, but this recovery operation relies on the BIOS process to enter a subsequent stage such as distribution execution. Therefore, when the variable value is configured, the BIOS cannot enter the subsequent stage that can perform recovery, and thus cannot recover the abnormal configuration parameters, resulting in the system being in an unrepairable boot failure state. SUMMARY

[0004] Therefore, the present disclosure provides a data processing method and an electronic device.

[0005] One aspect of the present disclosure provides a data processing method, comprising: obtaining first data in response to booting of an electronic device; the first data comprising signals output by a first system to a target port during running of the first system, the electronic device being configured with the first system and a second system, the first system being configured to boot the second system; obtaining second data in response to the first data satisfying a target condition; the second data comprising parameter values corresponding to configuration parameters managed by the first system before the configuration parameters are modified, the target condition indicating that the second system cannot normally run; adjusting third data based on the second data to enable the electronic device to normally run the second system; the third data comprising parameter values corresponding to the configuration parameters managed by the first system after the configuration parameters are modified.

[0006] According to an embodiment of the present disclosure, the data processing method further comprises: in response to the process of the first system booting the second system, completing initialization of each hardware of the target electronic device, and backing up the parameter values corresponding to the configuration parameters managed by the first system to be used as the second data when the electronic device is next booted.

[0007] According to an embodiment of the present disclosure, the generation of the second data comprises at least one of the following: backing up the parameter values of the configuration parameters in response to entering a modification interface of the configuration parameters managed by the first system; backing up the parameter values of the configuration parameters in response to completing the initialization of each hardware of the target electronic device in a process in which the first system previously boots the second system; and backing up the parameter values of the configuration parameters in response to the parameter values of the configuration parameters managed by the first system being modified after the initialization of each hardware of the target electronic device is completed and the second system is normally running.

[0008] According to an embodiment of the present disclosure, the parameter values of the configuration parameters backed up comprise: backing up the parameter values of each configuration parameter; or backing up a first parameter value in each configuration parameter, the first parameter value being a parameter value of each configuration parameter that is modified.

[0009] According to an embodiment of the present disclosure, adjusting the third data based on the second data comprises: replacing the third data based on the parameter values of each configuration parameter backed up; or replacing a parameter value corresponding to the first parameter value in the third data based on the first parameter value.

[0010] According to an embodiment of the present disclosure, the response to obtaining the first data satisfying the target condition comprises: determining that the second system cannot normally run if the first data is not obtained for more than a target time; and the target time being a running time corresponding to a stage with the longest duration in a plurality of running stages of the second system.

[0011] According to an embodiment of the present disclosure, the data processing method further comprises: in response to the electronic device being started, starting a timer, and determining that the target condition is satisfied if the first data is not obtained twice in one timer period; and wherein the timer period is updated when the first data is obtained for the second time in one timer period.

[0012] According to an embodiment of the present disclosure, the data processing method further comprises: in response to the power-on self-test of the electronic device being completed or the electronic device being recovered from a low-power-consumption state to a wake-up running state, stopping obtaining the first data.

[0013] Another aspect of the present disclosure provides a data processing method applied to a first system, comprising: determining a target running stage from a plurality of running stages, the target running stage outputting a signal to a target port at a frequency lower than a threshold; and adjusting the signal output frequency of the target running stage to enable a controller to determine a running condition of a second system based on first data, the first data comprising signals output by each running stage to the target port; and the first system being used to boot the second system.

[0014] Another aspect of the present disclosure provides a data processing apparatus, comprising: a first obtaining module configured to obtain first data in response to a start of an electronic device; the first data comprising signals outputted by a first system to a target port during a running period of the first system; the electronic device being configured with the first system and a second system; the first system being configured to guide the second system; a second obtaining module configured to obtain second data in response to the first data satisfying a target condition; the second data comprising parameter values corresponding to configuration parameters managed by the first system before the configuration parameters are modified; the target condition indicating that the second system cannot run normally; a first adjusting module configured to adjust third data based on the second data, so that the electronic device can run the second system normally; the third data comprising parameter values corresponding to the configuration parameters managed by the first system after the configuration parameters are modified.

[0015] Another aspect of the present disclosure provides a data processing apparatus, comprising: a first determining module configured to determine a target running stage from a plurality of running stages; the target running stage outputting signals to a target port at a frequency lower than a threshold; a second adjusting module configured to adjust the frequency of signal output of the target running stage, so that a controller can determine a running condition of a second system based on first data; the first data comprising signals outputted by each running stage to the target port; the first system being configured to guide the second system.

[0016] Another aspect of the present disclosure provides an electronic device, comprising: a processor configured to run a first system or a second system; the first system being configured to guide the second system; the first system outputting signals to a target port during a running period of the first system; a controller; a memory connected to the controller; wherein the memory stores instructions executable by the controller; the instructions being executed by the controller to enable the controller to perform the following operations: obtaining first data in response to a start of the electronic device; the first data comprising signals outputted by the first system to the target port during the running period of the first system; obtaining second data in response to the first data satisfying a target condition; the second data comprising parameter values corresponding to configuration parameters managed by the first system before the configuration parameters are modified; the target condition indicating that the second system cannot run normally; adjusting third data based on the second data, so that the electronic device can run the second system normally; the third data comprising parameter values corresponding to the configuration parameters managed by the first system after the configuration parameters are modified.

[0017] Another aspect of the present disclosure provides a computer readable storage medium storing computer instructions, wherein the computer instructions are configured to enable a computer to perform the data processing method according to any one of the preceding embodiments.

[0018] Another aspect of the present disclosure provides a computer program product, comprising computer programs / instructions, wherein the computer programs / instructions are configured to enable a processor to perform the operations of the data processing method according to any one of the preceding embodiments when the computer programs / instructions are executed by the processor. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A flowchart of a data processing method applied to a controller according to an embodiment of the present disclosure is schematically shown;

[0021] Figure 2 Another flowchart of a data processing method applied to a controller according to an embodiment of the present disclosure is schematically shown;

[0022] Figure 3 Another flowchart of a data processing method applied to a controller according to an embodiment of the present disclosure is schematically shown;

[0023] Figure 4 A flowchart of a data processing method applied to a first system according to an embodiment of the present disclosure is schematically shown;

[0024] Figure 5 A system framework diagram according to an embodiment of the present disclosure is schematically shown;

[0025] Figure 6 A block diagram of a data processing apparatus for performing a data processing method applied to a controller according to an embodiment of the present disclosure is schematically shown;

[0026] Figure 7 A block diagram of a data processing apparatus for performing a data processing method applied to a first system according to an embodiment of the present disclosure is schematically shown; and

[0027] Figure 8 A block diagram of an electronic device suitable for implementing the above-described methods according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present disclosure, and is not intended to limit the scope of the present disclosure. In the following detailed description of the embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it would be apparent to one skilled in the art that the present disclosure can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the present disclosure.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the term "includes" and "comprising" and the like are meant to be inclusive in a manner that there are no exclusions of additional unrecited members excluding other non-recited members or any additional or other features in the described compositions, steps, operations, components, and / or portions thereof.

[0030] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the use of any terms herein should not be interpreted to limit the scope of the disclosure to only those embodiments described herein. Rather, the terms should be interpreted broadly to include any embodiment that falls within the scope of the present disclosure.

[0031] In the case of using expressions similar to "at least one of A, B, and C, etc.", it is generally intended to include any of the A, B, and C, etc. individually and also to include two or more of A, B, and C, etc. in combination (e.g., "a system having at least one of A, B, and C" is intended to include a system having A alone, a system having B alone, a system having C alone, a system having A and B together, a system having A and C together, a system having B and C together, and also a system having A, B, and C together, etc.).

[0032] In embodiments of the present disclosure, the collection, updating, analysis, processing, use, transmission, provision, disclosure, storage, etc. of data (e.g., including but not limited to user personal information) involved are in compliance with relevant laws and regulations, are used for legal purposes, and do not violate public order and good customs. In particular, necessary measures are taken for user personal information to prevent illegal access to user personal information data, and to maintain user personal information security, network security, and national security.

[0033] Embodiments of the present disclosure provide a data processing method applied to a controller, including: in response to an electronic device starting, obtaining first data; the first data includes signals output to a target port by a first system during a running period, the electronic device being configured with the first system and a second system, the first system being used to guide the second system; in response to the first data satisfying a target condition, obtaining second data; the second data includes parameter values corresponding to configuration parameters managed by the first system before the configuration parameters are modified, the target condition indicating that the second system cannot normally run; adjusting third data based on the second data to enable the electronic device to normally run the second system; the third data includes parameter values corresponding to the configuration parameters managed by the first system after the configuration parameters are modified.

[0034] Figure 1 A flowchart of a data processing method applied to a controller according to an embodiment of the present disclosure is schematically shown.

[0035] As shown in Figure 1 The data processing method applied to the controller can at least include operations S110-S130.

[0036] In operation S110, in response to the electronic device being powered on, first data is obtained; the first data comprises signals output by a first system to a target port during operation of the first system, the electronic device being configured with the first system and a second system, the first system being configured to boot the second system. The first system can be a basic input / output system (BIOS) or a unified extensible firmware interface (UEFI) firmware of the electronic device, and the second system can be a main operating system, such as Windows or Linux, installed on the electronic device. The target port is a preset interface for the first system to communicate with an external device, such as an 80h port on an industry standard architecture (ISA) bus. The first data is a status code or a debug code, also referred to as a POST code, output by the first system to the target port during each stage of a boot process, such as a power-on self-test (POST).

[0037] The controller starts monitoring the target port to capture any signals output by the first system to the port in real time after detecting a power-on or start-up signal of the electronic device. This monitoring is independent of the execution progress of the first system. For example, when a personal computer is powered on, the EC firmware is activated and starts listening to the 80h port. After the main CPU starts executing the BIOS code, the BIOS outputs different POST code values to the 80h port at key nodes of its initialization process, such as memory detection, graphics card initialization, etc. The EC continuously receives these POST code values and uses them as the first data to determine the running state of the first system.

[0038] In operation S120, in response to the first data satisfying a target condition, second data is obtained; the second data comprises parameter values of configuration parameters managed by the first system before the configuration parameters are modified, and the target condition indicates that the second system cannot run normally. The target condition refers to an abnormal state exhibited by the obtained first data, which indicates that the boot process of the first system has been interrupted or suspended, thereby failing to boot the second system. Specifically, the boot process of the first system being interrupted or suspended can be caused by abnormal (e.g., improper, incorrect, or damaged) configuration parameters managed by the first system; due to the abnormal (e.g., improper, incorrect, or damaged) configuration parameters, the first system fails to complete the initial stage of the system and cannot enter the subsequent recovery stage, thereby failing to boot the second system. The second data is a set of configuration parameters known to enable the electronic device to start normally, which is pre-stored in a storage area accessible to the controller.

[0039] An abnormality in the configuration parameters, e.g., improper user configuration, specifically, one or more parameters are manually adjusted through a setup interface (e.g., BIOS Setup) of the first system, thus causing the corresponding variable values to change, when improperly configured, can be incompatible with the current hardware configuration or logically inconsistent. For example, a user sets the running frequency or timing parameters of the memory to values beyond the physical specifications of the installed memory stick, causing the first system to hang during the memory initialization self-test phase due to hardware instability.

[0040] An abnormality in the configuration parameters, e.g., software or firmware update error, specifically, a software tool running in the second system (e.g., operating system) or a firmware update program of the first system itself, when attempting to modify the configuration parameters, fails, causing the parameter storage area to be corrupted. For example, a system management tool, when attempting to modify a configuration of the first system, writes incomplete or incorrectly formatted data into the non-volatile memory (NVRAM) due to program defects or permission issues.

[0041] An abnormality in the configuration parameters, e.g., a failure in the physical storage medium used to store the configuration parameters, e.g., a bad block in a flash memory chip storing the configuration parameters due to excessive read / write times.

[0042] An abnormality in the configuration parameters, e.g., incompatibility caused by hardware changes; a new hardware component is replaced or added, and the previously stored configuration parameters are incompatible with the new hardware. For example, a user replaces the central processing unit (CPU) with a new model, but the voltage, frequency, and other configuration parameters related to the CPU in the first system fail to automatically adapt and remain the old, incompatible settings, thus causing the system to fail to start during the CPU initialization phase

[0043] Specifically, the controller analyzes the obtained first data stream, and when it finds that the update behavior of the first data is abnormal, it determines that the target condition is met. Once it is determined that the target condition is met, the controller reads a pre-stored, correct configuration parameter from its own storage medium as the second data, which is prepared for recovery.

[0044] For example, the EC continuously monitors the POST code and, according to its internal determination rules, determines that the received POST code stream indicates that the BIOS boot process has failed. For example, the EC receives a POST code stream that does not conform to an expected normal boot sequence, or receives a specific POST code that characterizes an unrecoverable error, and the EC determines that the target condition is met based on this. Once it is determined that the target condition is met, the EC immediately locates and reads a previously saved BIOS NVRAM data backup in its internal flash memory (EC ROM), and the backup is the second data.

[0045] At operation S130, the third data is adjusted based on the second data so that the electronic device can normally run the second system; the third data includes the parameter value corresponding to the configuration parameter managed by the first system and modified after the modification. The third data is the configuration parameter currently stored in the first system dedicated non-volatile storage area (for example, the NVRAM area in the BIOS chip), which causes the failure of this start. The adjustment operation means that at least part of the third data in the region is modified and adjusted according to the second data. Specifically, the controller can directly perform a write operation on the physical storage medium storing the third data through the system bus access authority it has, and use the second data to overwrite or rewrite the third data, so as to restore the configuration of the first system to a known normal state. Alternatively, the controller can send an instruction to the first system so that the processor running the first system performs a write operation on the physical storage medium storing the third data, and uses the second data to overwrite or rewrite the third data, so as to restore the configuration of the first system to a known normal state.

[0046] For example, after determining that the system is down and obtaining the NVRAM backup (second data), the EC directly accesses the BIOS ROM chip on the motherboard through a bus such as a serial peripheral interface. The EC writes the read second data into the NVRAM area of the BIOS ROM chip storing the BIOS variable, thereby overwriting the original configuration parameter (third data) in the NVRAM area of the BIOS ROM chip that causes the start failure. After completing data recovery, the EC can further issue a system reset signal to make the electronic device restart using the restored correct configuration parameter.

[0047] According to an embodiment of the present disclosure, by transferring the monitoring of the system start state and the recovery function of the configuration data to a controller independent of the first system (BIOS), the technical problem that the BIOS cannot enter its own recovery stage due to the abnormal configuration parameter in the NVRAM, and thus cannot recover the parameter to cause the system to be down, is solved. It is ensured that no matter which stage of the start process the fault occurs, the external intervention and recovery of the error system configuration can be effectively performed, thereby significantly improving the start reliability and robustness of the electronic device, and avoiding the situation that the device cannot be started due to the abnormal configuration parameter.

[0048] Figure 2 Another flowchart of the data processing method applied to the controller according to an embodiment of the present disclosure is schematically shown.

[0049] As shown in the foregoing embodiment, the data processing method can further include operation S210. Figure 2

[0050] ​In operation S210, in response to the process of booting the second system by the first system, initialization of each hardware of the target electronic device is completed, and a parameter value corresponding to a configuration parameter managed by the first system is backed up to be used as the second data when the electronic device is started next time. The event point of "the initialization of each hardware of the target electronic device is completed" indicates that the first system has successfully completed the power-on self-test (POST) process using the currently stored configuration parameter, and confirms that the current configuration is valid and can make the system run normally. The backup operation is to save the current set of valid configuration parameters to a secure location independent of the first system storage area.

[0051] Specifically, before the first system confirms that all critical hardware has been successfully initialized, that is, before the first system hands over the control to the second system (operating system), the first system sends a specific instruction or signal to the controller to inform the controller that the current system state is normal and the configuration backup can be performed, or the controller can detect that the first system has completed the power-on self-test (POST) process and the configuration backup can be performed. After receiving the instruction, or the controller detects that the first system has completed the power-on self-test (POST) process, the controller actively reads the current configuration parameter from the non-volatile storage area (such as BIOS NVRAM) of the first system, and writes it into a storage space accessible to the controller for saving, for example, writes it into the non-volatile memory (such as EC ROM) of the controller.

[0052] Specifically, for example, in a normal booting process, the BIOS successfully completes the detection and initialization of all hardware such as memory, processor, storage device, etc. At the last moment before jumping to the operating system boot loader, the BIOS sends a predefined "backup configuration" command to the EC through the system management bus or the keyboard controller interface. After receiving the command, the EC accesses the BIOS chip on the motherboard through the serial peripheral interface to read the data in the NVRAM area of the BIOS chip, and then completely copies these data into a reserved area of the ROM of the EC. The copied data is used as the second data that may be needed next time.

[0053] According to embodiments of the present disclosure, by backing up the configuration parameter after successfully completing the hardware initialization each time, it is ensured that the second data used for recovery is always a "last correct configuration" verified by actual operation. The effectiveness and reliability of the recovery data are guaranteed, and the use of an outdated or insufficiently verified backup data for recovery is avoided, thereby improving the success rate of the entire system self-recovery scheme and ensuring that the system can reliably fall back to a known state that can work normally when a start-up failure occurs.

[0054] On the basis of the foregoing embodiments, the generation process of the second data can include at least one of the following operations.

[0055] In response to entering the modification interface of the configuration parameter managed by the first system, the parameter value corresponding to the backup configuration parameter is backed up. The "modification interface of the configuration parameter" can refer to the setup interface provided by the first system (such as BIOS). The trigger point of this operation is that the user has performed the operation of entering the interface, but before the user performs any actual parameter modification.

[0056] For example, the user presses the "Del" key during the computer startup process to enter the BIOS Setup. After receiving the key event, the BIOS firmware does not immediately display the Setup menu, but first sends a "backup current configuration" command to the EC through the KBC interface or the SMBus. After receiving the command, the EC reads and saves the data in the current NVRAM, and after completing the backup, the BIOS continues to execute and presents the Setup interface to the user for modification. Alternatively, the user modifies the configuration parameter in the modification interface, but before the BIOS firmware actually writes it to the corresponding storage space, it first sends a "backup current configuration" command to the EC. After receiving the command, the EC reads and saves the data in the current NVRAM, and after completing the backup, the BIOS firmware actually writes it to the corresponding storage space.

[0057] In response to the process of booting the second system by the first system last time, when the initialization of each hardware of the target electronic device is completed, the parameter value corresponding to the backup configuration parameter is backed up. This operation is the same as the backup operation (S210) described in the foregoing embodiment in terms of execution mode, and the difference is that the second data used in this scheme is generated in the last electronic device startup process, and the specific content is not described here.

[0058] In response to the process of booting the second system by the first system last time, when the initialization of each hardware of the target electronic device is completed, the parameter value corresponding to the backup configuration parameter is backed up. This operation is the same as the backup operation (S210) described in the foregoing embodiment in terms of execution mode, and the difference is that the second data used in this scheme is generated in the last electronic device startup process, and the specific content is not described here.

[0059] For example, a user enters BIOS Setup, changes the boot order from hard drive to USB drive, saves and exits. During the save process, the BIOS sets a "configuration modified" flag in memory. The system then restarts and successfully boots from the USB drive using the new configuration. Upon completion of POST (Power-On Self-Processing), the BIOS detects that the "configuration modified" flag is true and sends a backup command to the EC (Electronic Control Unit) to back up the NVRAM data containing the new boot order to the EC ROM. After the backup is complete, the BIOS clears the flag. If the user does not modify any settings on the next boot, the backup will not be triggered because the flag will be false.

[0060] According to embodiments of this disclosure, flexibility is improved by providing multiple different backup trigger times (before entering the modification interface, after each successful startup, or only after modification and successful startup). One or more backup strategies best suited to a specific application scenario can be selected based on considerations such as system reliability, recovery efficiency, and the write lifespan of the controller storage media. For example, selecting to back up only after modification and successful startup can reduce unnecessary backup operations and extend storage lifespan; while selecting to back up after each successful startup provides the most reliable fallback guarantee, ensuring the timeliness of data recovery.

[0061] Based on the foregoing embodiments, the parameter values ​​corresponding to the backup configuration parameters may include at least one of the following operations.

[0062] Back up the parameter values ​​corresponding to each configuration parameter. Specifically, perform a complete and indiscriminate backup of all configuration parameters managed by the first system. When the backup operation is triggered, the controller will access the entire physical storage area (e.g., the NVRAM data area in the BIOS chip) that stores the configuration parameters of the first system, read all the data content in that area, and then save this data as a complete data block to the corresponding storage medium intact.

[0063] For example, suppose the configuration parameters of the first system are stored in a 64KB NVRAM area within the BIOS chip. When the controller receives a backup command, it reads the complete 64KB of data via the SPI bus and writes it as a whole into a reserved 64KB backup area in the EC ROM. This process does not concern itself with which specific parameter is modified; rather, it performs a complete image backup.

[0064] The first parameter value is the modified parameter value in each configuration parameter. The first parameter value can be the configuration parameter whose content has actually changed. When the backup operation is triggered, the first system first determines which configuration parameters have changed compared with the last stable state. Then, the first system packs these changed parameters and their new values (i.e., the first parameter values) and sends them to the controller through the communication interface. The controller only needs to store the information of the parameters that have been explicitly identified as modified.

[0065] For example, the user only modifies the "Secure Boot" option from "disabled" to "enabled" in the BIOS Setup. When the backup is triggered, the BIOS identifies that only the value of the "Secure Boot" variable has changed. Therefore, the backup data sent by the BIOS to the EC only contains the identifier of this variable and its new value ("enabled"). After receiving the backup data, the EC only saves this change record, rather than the entire content of the NVRAM.

[0066] According to examples of the present disclosure, by providing both the whole backup and the incremental backup, the present scheme has higher flexibility in implementation. When the whole backup is used, the logic is simple, and when the data needs to be restored later, the processing flow is more direct and robust. When the incremental backup is used, the amount of data to be transmitted and the storage space occupied by the backup operation can be significantly reduced, especially when the storage resources of the controller are limited, the backup efficiency can be improved and the service life of the storage medium can be prolonged.

[0067] On the basis of the foregoing embodiments, operation S130 can include one of the following operations.

[0068] Replace the third data based on the parameter values corresponding to the configuration parameters in the backup. This operation is a recovery method corresponding to the whole backup method (S410) in the foregoing embodiments. Specifically, when the controller needs to perform a recovery operation, it reads the complete backup data containing all configuration parameters that has been stored, and then writes this complete data block to the non-volatile storage area of the first system (i.e., the area where the third data is located) at one time, thereby realizing the overall replacement of the original data.

[0069] For example, the controller reads the previously backed up complete 64KB NVRAM data block (i.e., the second data) from its EC ROM. Then, the controller writes this 64KB data directly to the corresponding NVRAM area in the BIOS chip through the SPI bus, completely covering the original 64KB data (i.e., the third data) in this area that caused the startup failure.

[0070] Alternatively, based on the first parameter value, the parameter value corresponding to the first parameter value in the third data is replaced. This operation is a recovery method corresponding to the incremental backup mode (S420) in the foregoing embodiment. When the controller needs to perform the recovery operation, it reads the backup that has been stored, which only contains the changed parameter information (i.e., the first parameter value). Subsequently, the controller locates each corresponding parameter in the configuration storage area of the first system according to the information, and only updates the value of the parameter to the value in the backup.

[0071] For example, the value of the "secure boot" variable recorded in the backup of the controller is changed (the changed value is the first parameter value). When the recovery is performed, the controller accesses the NVRAM area of the BIOS chip, accurately locates the storage position of the "secure boot" variable, and then only overwrites the data at the position with the correct value recorded in the backup, while other parameters in the NVRAM, such as the boot order and the memory frequency, remain unchanged.

[0072] According to the embodiments of the present disclosure, the whole replacement mode is adopted, the recovery logic is simple and direct, the reliability is high, and the internal structure of the data does not need to be parsed. The partial replacement mode is adopted, the recovery speed is faster, the amount of data written is less, and unintended covering of other configuration items that may be normally modified can be avoided, and the recovery operation is more accurate.

[0073] On the basis of the foregoing embodiment, in response to obtaining that the first data satisfies the target condition can include that the first data is not obtained within a target time, it is determined that the second system cannot normally operate; the target time is a running time corresponding to a stage with the longest duration in a plurality of running stages of the second system. The "target time" is a pre-set fixed time threshold, which refers to the maximum time interval that can occur between any two consecutive first data (signals) outputs in a normal boot process. The basis for setting the target time is that all stages of the first system (BIOS) in the normal boot process are analyzed, a stage with the longest execution time under all possible hardware configurations and running conditions is found, and the longest execution time is set as the reference. "The first data is not obtained within the target time" can mean that since the last signal is received, or since the electronic device is started, no new signal can be received within the pre-set "target time", which indicates that the execution flow of the first system has stalled.

[0074] Specifically, the controller starts a timer when the electronic device is powered on, and the timeout period of the timer is set as a "target time". The target time is determined according to the evaluation of the execution time of each execution module (such as the security stage SEC, the pre-EFI initialization stage PEI, etc.) of the first system in the worst case. If the first system fails to complete its boot process (for example, fails to send a clear "stop timing" or "indicate boot success" signal to the controller) before the timer times out, the timer will time out. The timeout event of the timer is determined by the controller as "satisfying the target condition", indicating that the first system has been suspended and cannot normally boot the second system.

[0075] For example, in a specific project, the BIOS developer confirms through analysis that, among all hardware initialization modules, "memory training" is the stage with the longest interval between two consecutive POST code outputs, and its longest time consumption is 30 seconds. Therefore, the "target time" of the timeout timer in the controller can be set to a value slightly larger than this, such as 35 seconds. After the electronic device is powered on, the controller starts monitoring the 80h port. If the system is suspended due to configuration errors during memory training, there will be no new POST code output. When the timer in the controller starts timing from T0 time, it will time out after 35 seconds without being reset by a new POST code. The controller captures the timeout event and determines that the system has crashed, and triggers the subsequent recovery operation.

[0076] On the basis of the foregoing embodiment, the data processing method can further include the following operations.

[0077] In response to the electronic device being powered on, a timer is started, and it is determined that a target condition is satisfied when the first data is not obtained twice within a timing period. Wherein, the timing period is updated when the first data is obtained for the second time within a timing period. Similar to the "target time" in the foregoing embodiment, the "timing period" refers to the timeout period set for a resettable timer in the controller. The setting of this period is based on the maximum time interval that can occur between any two consecutive signal outputs in the normal boot process of the first system (BIOS), which usually corresponds to the most time-consuming hardware initialization stage. "Updating the timing period" here can refer to the operation of resetting the timer, that is, whenever a new signal is received, the timer is reset to a full period and starts a new round of countdown. "The first data is not obtained twice within a timing period" can mean that after receiving the first data and resetting the timer, the timer fails to receive the next first data before the countdown ends, resulting in a timeout.

[0078] The controller activates an internal timeout timer when the electronic device is powered on. The timeout period of the timer is preset as a "timing period". The controller continuously monitors the target port, and whenever a first data is successfully obtained from the target port, the controller immediately performs a reset operation on the timeout timer. If the execution flow of the first system is suspended, no new first data can be outputted, and thus the timer in the controller cannot be reset. When the timer completes a full countdown period, a timeout interrupt or status flag is generated, based on which the controller determines that the target condition is met.

[0079] For example, the BIOS developer confirms that in each execution stage, the "memory initialization in PEI stage" module consumes the longest time, and thus sets the "timing period" of the timeout timer in the EC as 40 seconds. When the computer is powered on, the EC immediately starts the 40-second timer. In the early stage of startup, the BIOS outputs a POST code to the 80h port, and the EC receives the POST code and immediately resets the 40-second timer. Subsequently, the BIOS continues to execute and outputs the next POST code, and the EC receives and resets the timer again. When the BIOS enters the PEI stage to perform memory initialization and is suspended due to a configuration error, it will stop outputting any new POST code. At this time, the 40-second timer of the EC starts counting down after the last reset, and since there is no new POST code to reset it, the timer will timeout after 40 seconds. The EC captures the timeout event and determines that the system has crashed.

[0080] According to the embodiments of the present disclosure, by employing a timeout timer that is reset upon receiving a signal, a dynamic and reliable system suspension detection mechanism is provided, which can accurately monitor the "activity" of the first system boot flow. As long as the flow is normally advancing, the timer will be continuously reset, and as soon as the flow is stalled, the timeout can be triggered quickly, which can effectively distinguish between normal long startup and abnormal execution suspension, thereby greatly improving the reliability and response speed of fault detection.

[0081] Figure 3 Another flowchart of the data processing method applied to the controller according to the embodiments of the present disclosure is schematically shown.

[0082] As Figure 3 shown, on the basis of the foregoing embodiments, the data processing method can further include operation S310.

[0083] At operation S310, in response to the end of power-on self-test of the electronic device or the resumption from the low-power state to the wake-up running state, the obtaining of the first data is stopped. The "end of power-on self-test" means that the first system (BIOS) has successfully completed all necessary hardware initialization and self-test (POST) processes, and is about to hand over the system control to the second system (operating system). The "resumption from the low-power state to the wake-up running state" means that the electronic device is woken up from a low-power state such as suspension to memory, and the first system has performed necessary resumption procedures and is ready to resume the running context of the second system.

[0084] After the first system completes the critical task of its booting or wake-up process, before handing over the control, it actively sends an explicit instruction or signal to the controller to inform the controller that the current stage has been safely completed. Alternatively, the controller can detect the timing of the specific event, and the controller stops monitoring the target port and / or stops the internal timeout timer for fault detection after receiving the instruction or detecting the timing of the specific event.

[0085] For example, in a normal booting process, when the BIOS completes the POST and is about to jump to the operating system boot loader, the BIOS sends a predefined "stop monitoring" command to the EC through the system management bus (SMBus) or keyboard controller (KBC) interface. Similarly, when the computer is woken up from the sleep state, the BIOS executes a specific wake-up firmware path to restore the system state, and at the end of the path, before restoring the operating system context, the BIOS also sends the "stop monitoring" command to the EC. After receiving the command in either case, the EC stops its timeout timer and stops listening to the activities of the 80h port.

[0086] According to embodiments of the present disclosure, by explicitly stopping the monitoring and fault detection logic after the system successfully boots or wakes up, it is ensured that the resumption mechanism is only activated during the most critical and most prone-to-failure startup and wake-up stages. False positives and unnecessary resumption operations caused by different usage of the target port by the second system (operating system) or long periods of no signal output during the normal running of the system are avoided, the resource overhead of the system is significantly reduced, and the stability and accuracy of the entire scheme are improved, ensuring that the resumption function is accurately executed and stopped within the correct time window.

[0087] Figure 4 A flowchart of a data processing method applied to the first system according to an embodiment of the present disclosure is schematically shown.

[0088] As Figure 4 shown, on the basis of the foregoing embodiments, the data processing method applied to the first system can include operations S410-S420.

[0089] In operation S410, a target execution phase is determined from a plurality of execution phases, the target execution phase outputs signals to the target port at a frequency lower than a threshold value. The "plurality of execution phases" refers to various independent functional modules in the BIOS during the execution of the boot process, such as the security (SEC) phase, the memory initialization module in the pre-EFI initialization (PEI) phase, the PCI bus enumeration module in the driver execution environment (DXE) phase, and the like. The "target execution phase" refers to modules that have a relatively long execution time, but the interval of outputting signals (POST code) in the native code within the module exceeds the timeout period set by the controller side.

[0090] The execution time of each functional module of the firmware is evaluated and compared with the timeout period set by the controller side (for example, the "target time" or "timing period" in the foregoing embodiment). If the execution time of a certain module in the worst case exceeds the timeout period, and no signal is output within the execution time, the module is determined as the "target execution phase".

[0091] For example, it is assumed that the timeout timer period of the controller is set to 35 seconds. The BIOS developer analyzes and finds that the memory reference code (MRC) in the PEI phase has an execution time of up to 60 seconds when processing large-capacity memory, and the native MRC code may not output any POST code within the 60 seconds. Since 60 seconds is much longer than 35 seconds, this will cause the controller to misjudge that the system is down. Therefore, this "memory reference code" module is determined as the "target execution phase" that needs to be adjusted.

[0092] In operation S420, the signal output frequency of the target execution phase is adjusted so that the controller can determine the running state of the second system based on first data, the first data including signals output by each execution phase to the target port, and the first system being used to boot the second system. The signal output frequency of the target execution phase can be artificially increased in the source code of the determined target execution phase to output signals to the target port. Specifically, in the source code of the target execution phase, especially between the internal loops or time-consuming algorithm steps, additional instructions for outputting signals to the target port are inserted. These additional signals can be some reserved specific status codes indicating "processing in progress", which serve as a kind of "heartbeat" signal to reset the timeout timer of the controller.

[0093] For example, for the aforementioned "Memory Reference Code" module which takes 60 seconds, a modification is made in its source code. The module can contain a loop which initializes memory channels, and after each channel is initialized, an instruction is inserted to output a specific POST code (e.g. 0xBF, which stands for "Working Properly") to port 80h. With this modification, even though the entire module takes 60 seconds, a new POST code is output every 15 seconds, ensuring that the signal output interval is much smaller than the controller's 35-second timeout period, thus avoiding being misjudged as a system hang by the controller.

[0094] According to embodiments of the present disclosure, by actively cooperating with the first system (BIOS), the signal output is increased during the long-running phase inside the system, thus solving the misjudgment problem that can be caused by the controller's timeout judgment alone. The controller can accurately distinguish between "normal but long-time-consuming operation" and "real system hang", thus improving the accuracy of the entire mechanism for fault recovery based on the controller.

[0095] Figure 5 A system framework diagram according to embodiments of the present disclosure is schematically shown.

[0096] As shown in Figure 5 the system framework of embodiments of the present disclosure mainly includes a processor and a controller, which are connected through a communication bus. The processor is responsible for running the first system (e.g. BIOS or UEFI firmware) or the second system (e.g. operating system). The controller, for example, can be an embedded controller (EC), which runs its own EC program independently of the processor. When the processor runs the first system, it outputs a signal to the communication bus through an 80 port, which can be captured by the controller.

[0097] For example, at the start-up stage of the electronic device, the processor starts to execute the code of the first system. In this process, the first system outputs a series of POST codes as status signals (i.e., the first data) to the communication bus through the 80 port according to its execution steps, while the controller continuously monitors the output of the 80 port through its EC program via the communication bus. Each time a new POST code is received, the timeout timer in the controller is reset. If the first system is suspended at a certain stage due to incorrect configuration parameters or other reasons, the processor will stop outputting new POST codes. This will cause the timeout timer of the controller to timeout after a preset time, thereby determining that the system cannot operate normally (i.e., the target condition is met). After determining that the system is down, the controller obtains a pre-backup correct configuration parameter (i.e., the second data) from its internal storage, and writes the correct parameter to the storage area where the current incorrect configuration (i.e., the third data) of the first system is stored through the communication bus, thereby completing the repair. After the repair is completed, the system is restarted, and the processor executes the first system using the configuration parameter corrected by the controller, so that the second system can be successfully booted and run.

[0098] Figure 6 A block diagram of a data processing apparatus for performing the data processing method applied to the controller according to an embodiment of the present disclosure is shown schematically.

[0099] As shown in Figure 6 The data processing apparatus 600 can include a first obtaining module 610, a second obtaining module 620, and a first adjusting module 630.

[0100] The first obtaining module 610 is configured to obtain first data in response to the start-up of the electronic device. The first data includes signals output by the first system to the target port during the running of the first system. The electronic device is configured with the first system and the second system. The first system is used to boot the second system. In some embodiments, the first obtaining module 610 can be configured to perform operation S110 in the above data processing method, and details are not repeated here.

[0101] The second obtaining module 620 is configured to obtain second data in response to the first data meeting a target condition. The second data includes a parameter value corresponding to a configuration parameter managed by the first system before the configuration parameter is modified. The target condition indicates that the second system cannot operate normally. In some embodiments, the second obtaining module 620 can be configured to perform operation S120 in the above data processing method, and details are not repeated here.

[0102] The first adjustment module 630 is configured to adjust the third data based on the second data, so that the electronic device can normally run the second system; the third data includes a parameter value corresponding to a configuration parameter managed by the first system after the configuration parameter is modified. In some embodiments, the first adjustment module 630 can be configured to perform operation S130 in the data processing method, which will not be repeated here.

[0103] According to an embodiment of the present disclosure, the data processing apparatus 600 can further include a first backup module.

[0104] The first backup module is configured to, in response to that each hardware of the target electronic device is initialized in the process that the first system boots the second system, backup a parameter value corresponding to a configuration parameter managed by the first system, to be used as the second data when the electronic device is started next time. In some embodiments, the first backup module can be configured to perform operation S210 in the data processing method, which will not be repeated here.

[0105] According to an embodiment of the present disclosure, the data processing apparatus 600 can include at least one of a second backup module, a third backup module, and a fourth backup module. The second backup module, the third backup module, and the fourth backup module are configured to generate the second data.

[0106] The second backup module is configured to, in response to entering a modification interface of a configuration parameter managed by the first system, backup a parameter value corresponding to the configuration parameter. In some embodiments, the second backup module can be configured to perform the backup of the parameter value corresponding to the configuration parameter in the data processing method, which will not be repeated here.

[0107] The third backup module is configured to, in response to that each hardware of the target electronic device is initialized in the process that the first system boots the second system last time, backup a parameter value corresponding to the configuration parameter. In some embodiments, the third backup module can be configured to perform the backup of the parameter value corresponding to the configuration parameter in the data processing method, which will not be repeated here.

[0108] The fourth backup module is configured to, in response to that the parameter value of the configuration parameter managed by the first system is modified after each hardware of the target electronic device is initialized last time, and the second system is normally running, backup a parameter value corresponding to the configuration parameter. In some embodiments, the fourth backup module can be configured to perform the backup of the parameter value corresponding to the configuration parameter in the data processing method, which will not be repeated here.

[0109] According to an embodiment of the present disclosure, the data processing apparatus 600 can further include a first replacement module, or a second replacement module.

[0110] The first replacing module is configured to replace the third data based on the parameter values corresponding to the backup configuration parameters. In some embodiments, the first replacing module can be configured to perform the operation of "replacing the third data based on the parameter values corresponding to the backup configuration parameters" in the data processing method, which will not be repeated here.

[0111] The second replacing module is configured to replace the parameter values corresponding to the first parameter values in the third data based on the first parameter values. In some embodiments, the second replacing module can be configured to perform the operation of "replacing the parameter values corresponding to the first parameter values in the third data based on the first parameter values" in the data processing method, which will not be repeated here.

[0112] According to the embodiments of the present disclosure, the data processing apparatus 600 can further include a condition determining module and a resetting module.

[0113] The condition determining module is configured to start a timer in response to the start of the electronic device, and determine that the target condition is met when the first data is not obtained twice within one timer period. In some embodiments, the condition determining module can be configured to perform the operation of "starting a timer in response to the start of the electronic device, and determining that the target condition is met when the first data is not obtained twice within one timer period" in the data processing method, which will not be repeated here.

[0114] The resetting module is configured to update the timer period when the first data is obtained for the second time within one timer period. In some embodiments, the resetting module can be configured to perform the operation of "updating the timer period when the first data is obtained for the second time within one timer period" in the data processing method, which will not be repeated here.

[0115] Figure 7 A block diagram of a data processing apparatus for performing a data processing method applied to a first system is schematically shown according to an embodiment of the present disclosure.

[0116] As shown in Figure 7 The data processing apparatus 700 can include a first determining module 710 and a second adjusting module 720.

[0117] The first determining module 710 is configured to determine a target running stage from a plurality of running stages, and the target running stage outputs a signal to a target port with a frequency lower than a threshold. In some embodiments, the first determining module 710 can be configured to perform operation S410 in the data processing method, which will not be repeated here.

[0118] The second adjusting module 720 is configured to adjust the signal output frequency of the target running stage, so that the controller can determine the running condition of the second system based on the first data, and the first data comprises signals output by each running stage to the target port. In some embodiments, the second adjusting module 720 can be configured to perform operation S420 in the data processing method described above, and details are not described herein.

[0119] Any one or more of the modules, sub-modules, units, sub-units according to the embodiments of the present disclosure, or at least part of the functions of any one or more of the modules, sub-modules, units, sub-units, can be implemented in one module. Any one or more of the modules, sub-modules, units, sub-units according to the embodiments of the present disclosure can be split into multiple modules for implementation. Any one or more of the modules, sub-modules, units, sub-units according to the embodiments of the present disclosure can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or any other reasonable way of hardware or firmware that can be integrated or packaged with a circuit, or implemented in any one of software, hardware and firmware or in a proper combination of any of them. Alternatively, one or more of the modules, sub-modules, units, sub-units according to the embodiments of the present disclosure can be at least partially implemented as computer program modules that can perform corresponding functions when the computer program modules are run.

[0120] For example, any one or more of the first obtaining module 610, the second obtaining module 620, and the first adjusting module 630 can be combined in one module / unit / sub-unit for implementation, or any one of the modules / units / sub-units can be split into multiple modules / units / sub-units. Alternatively, at least part of the functions of one or more of the modules / units / sub-units can be combined with at least part of the functions of other modules / units / sub-units, and implemented in one module / unit / sub-unit. According to embodiments of the present disclosure, at least one of the first obtaining module 610, the second obtaining module 620, and the first adjusting module 630 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or any other reasonable way of hardware or firmware that can be integrated or packaged with a circuit, or implemented in any one of software, hardware and firmware or in a proper combination of any of them. Alternatively, at least one of the first obtaining module 610, the second obtaining module 620, and the first adjusting module 630 can be at least partially implemented as computer program modules that can perform corresponding functions when the computer program modules are run.

[0121] It should be noted that the data processing system part in the embodiments of this disclosure corresponds to the data processing method part in the embodiments of this disclosure. The specific description of the data processing system part is referred to in the data processing method part, and will not be repeated here.

[0122] Figure 8 A block diagram of an electronic device suitable for implementing the methods described above, according to embodiments of the present disclosure, is illustrated schematically. Figure 8 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0123] like Figure 8 As shown, an electronic device 800 according to an embodiment of this disclosure includes a processor 801 and a separate controller 812. The processor 801 can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage portion 808 into a random access memory (RAM) 803. The processor 801 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 801 may also include onboard memory for caching purposes. The processor 801 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of this disclosure.

[0124] RAM 803 stores various programs and data required for the operation of electronic device 800. Processor 801, ROM 802, and RAM 803 are interconnected via bus 804.

[0125] The controller 812, for example, can be an embedded controller (EC) which operates independently of the processor 801. The controller 812 is connected with a memory, which can be a storage unit integrated inside the controller 812, or a separate storage chip connected with the controller 812. The memory stores instructions executable by the controller 812, and when the controller 812 executes the instructions in its memory, it can implement the data processing method applied to the controller in any of the preceding embodiments. Specifically, the controller 812 can perform the following operations: in response to the electronic device being started, the controller 812 monitors the target port through the bus 804 to obtain the signal output by the processor 801 when running the first system as the first data. The controller 812 determines whether the obtained first data meets the target condition according to its internal instructions (for example, determines whether it has timed out through its internal timer). When the target condition is met, the controller 812 obtains the pre-stored correct configuration parameters from its own corresponding memory as the second data. Subsequently, the controller 812 accesses the ROM 802 storing the current configuration parameters of the first system through the bus 804 (for example, through the SPI interface), adjusts or replaces the configuration parameters (i.e. the third data) causing the startup failure in the ROM 802 based on the second data, so that the processor 801 can use the correct configuration parameters when starting next time, thereby enabling the electronic device to normally run the second system.

[0126] The processor 801 performs various operations of the method flow according to the embodiments of the present disclosure by executing the programs in the ROM 802 and / or the RAM 803. It should be noted that the programs can also be stored in one or more memories other than the ROM 802 and the RAM 803. The processor 801 can also perform various operations of the method flow according to the embodiments of the present disclosure by executing the programs stored in the one or more memories.

[0127] According to an embodiment of the present disclosure, the electronic device 800 can further include an input / output (I / O) interface 805 also connected to the bus 804. The electronic device 800 can further include one or more of the following components connected to the input / output (I / O) interface 805: an input part 806 including a keyboard, a mouse, etc.; an output part 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage part 808 including a hard disk, etc.; and a communication part 809 including a network interface card such as a LAN card, a modem, etc. The communication part 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the input / output (I / O) interface 805 as necessary. A removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the drive 810 as necessary, so that a computer program read therefrom is installed in the storage part 808 as necessary.

[0128] According to an embodiment of the present disclosure, the method flow according to the embodiment of the present disclosure can be implemented as a computer software program. For example, the embodiment of the present disclosure includes a computer program product including a computer program carried on a computer-readable storage medium, the computer program containing program codes for executing the method shown in the flow chart. In such an embodiment, the computer program can be downloaded and installed from a network by the communication part 809, and / or installed from the removable medium 811. When the computer program is executed by the processor 801 or the controller 812, the above-described functions defined in the system of the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the system, device, apparatus, module, unit, etc. described above can be implemented by computer program modules.

[0129] The present disclosure also provides a computer-readable storage medium, which can be included in the device / apparatus / system described in the above embodiments; or can exist separately without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, when the one or more programs are executed, the method according to the embodiment of the present disclosure is implemented.

[0130] According to an embodiment of the present disclosure, the computer readable storage medium can be a nonvolatile computer readable storage medium. For example, it can include, but is not limited to, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination thereof. In this disclosure, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0131] For example, according to an embodiment of the present disclosure, the computer readable storage medium can include one or more memories of the ROM 802 and / or the RAM 803 described above and / or one or more memories other than the ROM 802 and the RAM 803.

[0132] Embodiments of the present disclosure also include a computer program product, which includes a computer program containing program codes for executing the method provided by the embodiments of the present disclosure, and the program codes are used to make the electronic device implement the data processing method provided by the embodiments of the present disclosure when the computer program product is run on the electronic device.

[0133] When the computer program is executed by the processor 801 or the controller 812, the above-mentioned functions defined in the system / apparatus of the embodiments of the present disclosure are performed. According to an embodiment of the present disclosure, the system, apparatus, module, unit, etc. described above can be implemented by computer program modules.

[0134] In one embodiment, the computer program may rely on tangible storage media such as optical storage devices or magnetic storage devices. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via communication section 809, and / or installed from removable medium 811. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof. According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code may be executed entirely on a user computing device, partially on a user device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing devices can be connected to user computing devices via any type of network, including local area networks (LANs) or wide area networks (WANs), or they can be connected to external computing devices (e.g., via the Internet using an Internet service provider).

[0135] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of this disclosure may be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0136] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1.A data processing method applied to a controller, comprising: obtaining first data in response to a start of an electronic device; the first data comprising signals outputted by a first system to a target port during a running period, the electronic device being configured with the first system and a second system, the first system being used to guide the second system; obtaining second data in response to the first data satisfying a target condition; the second data comprising parameter values corresponding to configuration parameters managed by the first system before the configuration parameters are modified, the target condition indicating that the second system cannot run normally; adjusting third data based on the second data to enable the electronic device to run the second system normally; the third data comprising parameter values corresponding to the configuration parameters managed by the first system after the configuration parameters are modified. 2.The method of claim 1, further comprising: backing up the parameter values corresponding to the configuration parameters managed by the first system to be used as the second data when the electronic device is started next time in response to completion of initialization of each hardware of the target electronic device during the process of the first system guiding the second system. 3.The method of claim 1, the process of generating the second data comprising at least one of: backing up the parameter values corresponding to the configuration parameters in response to entering a modification interface of the configuration parameters managed by the first system; backing up the parameter values corresponding to the configuration parameters in response to completion of initialization of each hardware of the target electronic device during the process of the first system guiding the second system last time; backing up the parameter values corresponding to the configuration parameters managed by the first system in response to the parameter values of the configuration parameters being modified after completion of the initialization of each hardware of the target electronic device last time and the second system running normally. 4.The method of claim 2 or 3, the backing up of the parameter values corresponding to the configuration parameters comprising: backing up the parameter values corresponding to each of the configuration parameters; or, backing up a first parameter value in each of the configuration parameters, the first parameter value being a modified parameter value in each of the configuration parameters. 5.The method of claim 4, the adjusting of the third data based on the second data comprising: replacing the third data based on the backed up parameter values corresponding to each of the configuration parameters; or, replacing a parameter value corresponding to the first parameter value in the third data based on the first parameter value. 6.The method of claim 1, the obtaining of the first data satisfying the target condition comprising: determining that the second system cannot run normally in response to not obtaining the first data within a target time; the target time being a running time corresponding to a stage with the longest duration in a plurality of running stages of the second system. 7.The method of claim 1, further comprising: starting a timer in response to a start of the electronic device, and determining that the target condition is satisfied in response to not obtaining the first data twice within a timer period; wherein the timer period is updated when the first data is obtained for the second time within the timer period. 8.The method of claim 1, further comprising: In response to the end of power-on self-test or the resumption from a low-power state to a wake-up running state on the electronic device, the obtaining of the first data is stopped. 9.A data processing method applied to a first system, comprising: determining a target running phase from a plurality of running phases, the target running phase having a frequency of outputting signals to a target port lower than a threshold value; adjusting the frequency of outputting signals of the target running phase, so that a controller can determine a running condition of a second system based on first data, the first data comprising signals outputted by each running phase to the target port; the first system being configured to guide the second system. 10.An electronic device, comprising: a processor configured to run a first system or a second system, the first system being configured to guide the second system, the first system outputting signals to a target port during running; a controller; a memory connected to the controller; wherein the memory stores instructions executable by the controller, the instructions being executed by the controller to enable the controller to: in response to the start of the electronic device, obtain first data, the first data comprising signals outputted by the first system to the target port during running; in response to the first data satisfying a target condition, obtain second data, the second data comprising parameter values corresponding to configuration parameters managed by the first system before the configuration parameters are modified, the satisfying of the target condition indicating that the second system cannot run normally; adjust third data based on the second data, so that the electronic device can run the second system normally, the third data comprising parameter values corresponding to the configuration parameters managed by the first system after the configuration parameters are modified.

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