Task scheduling method, system and equipment of data stream processor and storage medium

Abstract

The invention relates to the technical field of task scheduling, and discloses a task scheduling method, system and device for a data stream processor and a storage medium, a host end uses a heterogeneous computing framework, the total computing resource amount of a device end does not need to be considered during compiling, resource allocation is automatically allocated by a stream control core of the data stream processor, and the task scheduling efficiency is improved. And the resource configuration of hardware does not restrict the scale of the calculation task. And the C flow control core can analyze the DAG task graph, and issues the calculation task to the calculation node in a time-sharing manner. The DAG task graphs of multiple calculation tasks can be processed at the same time, the parallel execution capacity of the data flow processor is improved, then the processing efficiency of the data flow processor is improved, and the problem that in an existing task scheduling scheme of the data flow processor, the overall calculation resource utilization rate of the data flow processor is low is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of task scheduling, for example, to a task scheduling method, system, device and storage medium of a data flow processor. BACKGROUND

[0002] The data flow processor refers to a processor designed with a data flow architecture, which is different from the processor with a von Neumann architecture. The processor with the data flow architecture drives the computing process through data flow instead of regular instruction flow.

[0003] When the processor with the data flow architecture executes a computing task, the computing sequence is dynamically driven by data dependency. Each computing unit executes its computing task immediately after the input data is ready, without the need for a central controller to schedule. This architecture connects computing modules through dedicated data channels, realizes "computing and data transmission overlap", and reduces idle waiting time. For example, after the computing unit where the Step1 computing task is executed, the output data of the Step1 computing task directly flows into the dedicated computing unit of the Step2 computing task.

[0004] Existing problems: The existing data flow processor needs to determine which processing node each computing task runs on in the compilation phase through the compiler, and the task is issued to the corresponding coordinate processing node through the driver program. The disadvantage is that in one task cycle, the computing node can only run one data flow computing task at a time. The computing node must be released after the entire computing task is executed. The binding relationship between the computing task and the computing node is determined in the compilation phase and cannot be changed during the execution of the data flow processor program.

[0005] A complex computing task has a long DAG task graph. During the execution of the front node, the back processing core is in an idle state. When the back core executes, the front core is in an idle state, and the utilization rate of the processing core is low. When there are multiple concurrent task requests to use the data flow processor in the operating system, the tasks can only be executed one by one in sequence. The host uses the data flow processor in sequence through the task queue, and the host will only issue the next computing task after the previous task is executed. The overall computing resource utilization rate of the data flow processor is not high.

[0006] In summary, in the existing task scheduling scheme of the data flow processor, there is a problem of low overall computing resource utilization rate of the data flow processor.

[0007] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application. SUMMARY

[0008] The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. The summary is not an extensive overview of the embodiments nor is it intended to identify key / critical elements of the embodiments or to delineate the scope of the embodiments but to present some concepts of the embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0009] The task scheduling method, system, device and storage medium of the data stream processor provided by the embodiments of the present disclosure can solve the problem of low overall computing resource utilization of the data stream processor in the existing task scheduling scheme of the data stream processor.

[0010] The embodiments of the present disclosure provide a task scheduling method of a data stream processor, which comprises: In the program design stage of the computing task, the computing task is separated from the node coordinates, and the node coordinates are configured as execution parameters; In the compilation stage, the compiler analyzes the dependency relationship and data flow conversion relationship of each computing task, generates a DAG task scheduling graph, each task node corresponds to an execution node in the data stream processor, and generates a virtual coordinate of the node; In the execution stage, the host writes the kernel function bin instruction of each computing node into the memory of the data stream processor, and writes the data structure of the DAG task scheduling graph into the memory of the data stream processor, and releases the PCIe bus, so that other application programs can write tasks into the data stream processor concurrently; The C stream control core of the data stream processor reads the DAG task scheduling graph in the memory of the data stream processor; The C stream control core creates a task scheduling program for each DAG task scheduling graph, and sequentially issues firmware and kernel function bin instructions to the actual computing core according to the coordinate mapping relationship, according to the grouped DAG task scheduling graph output by the corresponding analysis program; When the computing node completes the first segment of the first group of computing tasks, a completion signal is sent to the C stream control core, the analysis program allocates computing cores for the second group of tasks in the DAG task scheduling graph, and establishes a mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the second group of tasks in the DAG task scheduling graph; the C stream core scheduling program issues the corresponding DAG task scheduling graph in the second group of computing tasks to the actual computing core; the node that completes the computing task releases the resource in time and enters the idle node resource pool, and the same is true for the subsequent nodes, until all the computing tasks in the entire DAG task scheduling graph are completed.

[0011] The embodiments of the present disclosure provide a task scheduling system of a data stream processor, which comprises: The separation module is configured to separate the computing task from the node coordinates in the program design stage of the computing task, and configure the node coordinates as execution parameters; The compiler is configured to analyze dependency relationships and data flow relationships of each computing task in a compilation phase, generate a DAG task scheduling graph, each task node corresponds to an execution node in a data flow processor, and generate virtual coordinates of the nodes. The host is configured to write the kernel function bin instructions of each computing node into the data flow processor memory and write the data structure of the DAG task scheduling graph into the data flow processor memory in an execution phase, and release the PCIe bus so that other application programs can concurrently write tasks into the data flow processor. The data flow processor is configured to read the DAG task scheduling graph in the data flow processor memory based on the C stream control core. The data flow processor is further configured to create a task scheduler for each DAG task scheduling graph based on the C stream control core, sequentially issue firmware and kernel function bin instructions to actual computing cores according to the coordinate mapping relationship, and output the grouped DAG task scheduling graph from the parsing program. The data flow processor is further configured to send a completion signal to the C stream control core when the computing node completes the first segment of the first group of computing tasks, allocate computing cores for the second group of tasks in the DAG task scheduling graph, and establish a mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the second group of tasks in the DAG task scheduling graph.

[0012] The embodiments of the present disclosure provide an electronic device, which comprises at least one processor; and a memory connected in communication with the at least one processor; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the task scheduling method of the data flow processor.

[0013] The embodiments of the present disclosure provide a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the task scheduling method of the data flow processor.

[0014] The data flow processor task scheduling method, system, device and storage medium provided by the embodiments of the present disclosure can achieve the following technical effects: In the present disclosure, the host uses a heterogeneous computing framework, and does not need to consider the total amount of computing resources of the device end at the time of compilation. The resource allocation is automatically allocated by the flow control core of the data flow processor, and the resource configuration of the hardware does not restrict the scale of the computing task. The C flow control core can parse the DAG task graph and issue the computing task to the computing node in time. Multiple computing tasks of the DAG task graph can be processed at the same time, improving the parallel execution capability of the data flow processor. The processing efficiency of the data flow processor is improved. The computing task is not executed in sequence, and multiple computing tasks can be concurrently written into the data flow processor. The data flow processor automatically allocates resources for each computing task, improving the parallelism. The computing node coordinates are used as execution parameters, and are not compiled into static coordinates. The computing task and the computing node are no longer in a forced binding relationship. The flow control core maps the virtual coordinates to the physical coordinates, increasing the flexibility of program design. The problem of low utilization of the overall computing resources of the data flow processor existing in the task scheduling scheme of the existing data flow processor is solved.

[0015] The foregoing general description and the following description are only exemplary and explanatory, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are exemplarily illustrated by the corresponding drawings, which do not constitute a limitation on the embodiments, elements with the same reference numerals in the drawings are shown as similar elements, the drawings do not constitute a proportional limitation, and wherein: Figure 1 is a flow diagram of a task scheduling method of a data flow processor provided by an embodiment of the present disclosure; Figure 2 is a flow diagram of another task scheduling method of a data flow processor provided by an embodiment of the present disclosure; Figure 3 is a specific interaction diagram of a task scheduling method of a data flow processor provided by an embodiment of the present disclosure; Figure 4 is a flow diagram of a method for cyclically executing computing tasks in a DAG task scheduling graph provided by an embodiment of the present disclosure; Figure 5 is an architecture diagram of a task scheduling system of a data flow processor provided by an embodiment of the present disclosure; Figure 6 is an architecture diagram of another task scheduling system of a data flow processor provided by an embodiment of the present disclosure; Figure 7 is a structure diagram of a task scheduling device of a data flow processor provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] In order to enable more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below, and the attached drawings are only used for reference and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, through multiple details, a sufficient understanding of the disclosed embodiments is provided. However, one or more embodiments can still be implemented without these details. In other cases, in order to simplify the drawings, well-known structures and devices can be simplified.

[0018] The terms "first", "second", and the like in the embodiments of the present disclosure are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so as to implement the embodiments of the present disclosure described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0019] Unless otherwise specified, the term "multiple" means two or more.

[0020] In the embodiments of the present disclosure, the character " / " represents an "or" relationship between the objects before and after it. For example, A / B represents: A or B.

[0021] The term "and / or" is a description of the association between objects, which means that there can be three relationships. For example, A and / or B, which means: A or B, or, A and B, three relationships.

[0022] The term "corresponding" can refer to an association or binding relationship. A and B correspond to each other means that there is an association or binding relationship between A and B.

[0023] In order to solve the above problems, the present disclosure provides a task scheduling method, system, device and storage medium of a data stream processor.

[0024] The task scheduling method, system, device and storage medium of the data stream processor provided by the embodiments of the present disclosure are described below with reference to the drawings.

[0025] Figure 1 It is a flowchart of a task scheduling method of a data stream processor provided by the embodiments of the present disclosure.

[0026] In combination with Figure 1 As shown, the task scheduling method of the data stream processor can include: S101, in the programming stage of the computing task, separate the computing task from the node coordinates, and configure the node coordinates as execution parameters; S102, in the compilation phase, the compiler analyzes the dependency relationship of each computing task, the data flow conversion relationship, generates a directed acyclic graph (DAG) task scheduling graph, each task node corresponds to an execution node in the data flow processor, and generates the virtual coordinates of the node; S103, in the execution phase, the host writes the core function bin instructions of each computing node into the data flow processor memory, and writes the data structure of the DAG task scheduling graph into the memory of the data flow processor, and releases the PCIe bus, so that other application programs can write tasks into the data flow processor concurrently; S104, the C stream control core of the data flow processor reads the DAG task scheduling graph in the data flow processor memory; S105, the C stream control core creates a task scheduling program for each DAG task scheduling graph, and outputs the grouped DAG task scheduling graph of the corresponding parsing program to the actual computing core according to the coordinate mapping relationship; S106, when the computing node completes the first computing task in the first group, a completion signal is sent to the C stream control core, the parsing program allocates computing cores for the second group of tasks in the DAG task scheduling graph, and establishes the mapping relationship between the actual physical coordinates of the idle node and the virtual coordinates of the second group of tasks in the DAG task scheduling graph; the C stream core scheduling program issues the corresponding DAG task scheduling graph in the second group of computing tasks to the actual computing core; the node that completes the computing task releases the resource in time, enters the idle node resource pool, and the same is true for the subsequent groups, until all the computing tasks in the entire DAG task scheduling graph are completed.

[0027] In some embodiments, after the C stream control core of the data flow processor reads the DAG task scheduling graph in the data flow processor memory, Figure 1 The method in the above method can further include: A parsing program is allocated for each DAG task, the parsing program estimates the ratio of the computing time to the transmission time according to the computing data volume and the computing complexity of the computing task, and groups the DAG task scheduling graph according to the ratio, and each group has two task segments, wherein the ratio of the estimated computing time to the transmission time satisfies the formula , , the computing volume wi is determined by the task complexity, P k The processing capacity of the target computing node, DataSize(e ij ) is the data volume transmitted by the edge e ij BandWidth is the bandwidth of the inter-node noc network; The mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph is established, and the actual computing core is allocated to the computing task.

[0028] In some embodiments, the threshold decision rule can be specifically: CTR>10: compute-intensive task→preferentially independent grouping; CTR<0.1: communication-intensive task→forced grouping with dependent task; 0.1≤CTR≤10: balanced task→dynamic grouping according to global dependency.

[0029] In some embodiments, when there are three computing tasks TASK1, TASK2 and TASK3 requested at the current host end, corresponding to three different DAG task scheduling graphs, the C flow control core creates analysis programs including DAG analysis program 1, DAG analysis program 2 and DAG analysis program 3; The DAG analysis program analyzes the computing complexity, computing data volume and data transmission time information between adjacent nodes of the sub-nodes in the DAG task scheduling graph, estimates the computing time and transmission time of each sub-node, and groups the DAG task scheduling graph.

[0030] In some embodiments, the above mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph is established, and the actual computing core is allocated to the computing task, including: The flow control core searches for a computing core in the current idle resource pool and allocates an actual computing core to the computing sub-task corresponding to the virtual coordinates, wherein when searching for a computing core in the current idle resource pool, the flow control core considers the position of the idle node in the idle resource pool and the physical topology distance of the computing node where the parent task is located, the available bandwidth factor of the node NOC network path, defines the node matching degree Affinity(n k ,v i ), Dist(n k ,parent i ) is the physical distance of the node n k and the computing node where the parent task parent i is located, BW avail is the available network bandwidth, and a and β are weight factors, and then the idle node with the highest matching degree is selected, and the physical coordinates of the idle node are mapped to the virtual coordinates of the corresponding node in the DAG task graph.

[0031] In some embodiments, the kernel function bin instruction is a computing instruction that needs to be executed by the computing node in the data flow processor, and different computing nodes correspond to different computing sub-tasks. The data structure of the DAG task scheduling graph includes virtual coordinate information of each subtask node, input and output data information of the subnode, data dependency relationship information of each node in the DAG task scheduling graph, and position information of the kernel function bin instruction corresponding to the subtask in the DDR memory.

[0032] Figure 2 is a flowchart of another task scheduling method of a data flow processor provided by the embodiments of the present disclosure, Figure 3 is a specific interaction diagram of a task scheduling method of a data flow processor provided by the embodiments of the present disclosure, Figure 4 is a flowchart of a method for cyclically executing a computing task in a DAG task scheduling graph provided by the embodiments of the present disclosure, in combination with Figures 2 to 4 , the task scheduling method of the data flow processor in Figure 1 is further described.

[0033] As shown in Figure 3 , the host end has three computing tasks TASK1, TASK2 and TASK3, which need to call the data flow processor. For this scenario, the embodiments of the present disclosure include the following steps: Step 1: In the program design phase of the computing task, separate the computing task from the node coordinates, and configure the node coordinates as an execution parameter.

[0034] Step 2: In the compilation phase, the compiler analyzes the dependency relationship and data flow conversion relationship of each computing task, and generates a DAG task graph. As shown in Figure 3 , the three computing tasks TASK1, TASK2 and TASK3 correspond to different DAG task graphs. Each subtask node in the graph corresponds to an execution node in the data flow processor, and the compiler generates virtual node coordinates for it.

[0035] Step 3: In the execution phase, the CPU host communicates with the P core through the PCIe bus, writes the kernel function bin instruction of each computing node into the data flow processor memory, and writes the data structure of the DAG task scheduling graph into the memory of the data flow processor. And immediately release the PCIe bus, so that other application programs can write tasks into the data flow processor concurrently.

[0036] The kernel function bin instruction is a computing instruction that needs to be executed by the computing node in the data flow processor, and different computing nodes correspond to different computing subtasks. The data structure of the DAG task graph includes virtual coordinate information of each subtask node, input and output data information of the subnode, data dependency relationship information of each node in the DAG task graph, and position information of the kernel function bin instruction corresponding to the subtask in the DDR memory.

[0037] Step 4: The C flow control core of the data stream processor reads the DAG task graph data in the data stream processor memory. A parser is assigned to each DAG task, which estimates the computation time and transmission time according to the computation data volume and computation complexity of the computation task, and performs task segmentation and grouping on the DAG task graph, with two task segments in each group (adjustable). The mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the first group of tasks in the DAG graph is established, and the actual computation core is assigned to the computation subtask.

[0038] For example, there are three computation tasks TASK1, TASK2, and TASK3 requested by the current host, corresponding to three different DAG task graphs. The C flow control core creates three different parsers: DAG parser 1, DAG parser 2, and DAG parser 3.

[0039] The DAG parser analyzes the computation complexity, computation data volume, and data transmission time between adjacent nodes of the subnodes in the DAG task graph, estimates the computation time and transmission time of each subnode, and groups the DAG task graph, as shown in Tables 1-3.

[0040] Table 1

[0041] Table 2

[0042] Table 3

[0043] The mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the first group of tasks in the DAG graph is established, that is, the flow control core finds the computation core in the current idle resource pool and assigns the actual computation core to the computation subtask corresponding to the virtual coordinates, as shown in Tables 4-6.

[0044] Table 4

[0045] Table 5

[0046] Table 6

[0047] Step 5: The C flow control core creates a task scheduling program for each DAG task graph, and according to the coordinate mapping relationship, sequentially issues firmware and kernel function bin instructions to the actual computation core for the grouped DAG task graph output by each parser.

[0048] According to step 4, the current host has three computing tasks TASK1, TASK2, TASK3 requests, corresponding to three different DAG task graphs, and the C flow control core will create three different schedulers: DAG scheduler 1, DAG scheduler 2, and DAG scheduler 3.

[0049] According to the mapping relationship between the virtual coordinates of the first group of task nodes determined in step 4 and the actual computing core coordinates, the DAG scheduler will issue the firmware and core function bin instructions of the computing core to the actual computing core.

[0050] Step 6: As shown in Figure 4 When the computing node completes the first computing task in the first group, it sends a completion signal to the C flow control core, and the parser allocates computing cores for the second group of tasks in the DAG graph and establishes a mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the second group of tasks in the DAG graph. The C core scheduler issues the second group of computing tasks in the corresponding DAG task graph to the actual computing core. The node that completes the computing task releases the resource in time and enters the idle node resource pool. By analogy, until all computing tasks in the entire DAG task graph are completed.

[0051] The task scheduling method of the data stream processor in the present disclosure uses a heterogeneous computing framework on the host side, and does not need to consider the total amount of computing resources on the device side during compilation. The resource allocation is automatically allocated by the flow control core of the data stream processor, and the hardware resource configuration does not restrict the scale of the computing task. The C flow control core can parse the DAG task graph and issue the computing task to the computing node in time. Multiple computing task DAG task graphs can be processed at the same time, improving the parallel execution capability of the data stream processor and thus improving the processing efficiency of the data stream processor. The computing task is not executed in sequence, and multiple computing tasks can be written into the data stream processor concurrently. The data stream processor automatically allocates resources for each computing task, improving the parallelism. The computing node coordinates are used as execution parameters, and are not compiled into static coordinates. The computing task and the computing node are no longer in a forced binding relationship, and the flow control core maps the virtual coordinates to the physical coordinates, increasing the flexibility of program design.

[0052] Figure 5 is a schematic diagram of a task scheduling system of a data stream processor provided by an embodiment of the present disclosure. As shown in Figure 5 The system mainly includes a host CPU, a device data stream processor, and a device DDR memory.

[0053] The processing cores of the data stream processor are divided into multiple types of cores according to different functions, including a flow control core, a computing core, a memory access core, and a host communication core.

[0054] The computing core (T) is used to execute specific computing tasks.

[0055] Stream control core (C): The function is to monitor the state of the computing core through the on-chip NoC network of the data stream processor, identify and analyze the DAG task graph in the DDR, and issue the bin instructions corresponding to each task to the idle node. Responsible for the management and allocation of idle nodes.

[0056] Memory access core (M): The function is to receive the memory access request of other cores in the NoC network, and perform read and write access to the DDR memory.

[0057] Host communication core (P): The function is to communicate with the host through the PCIe bus, analyze the data read and write request of the host end, and forward it to the corresponding node in the NoC network.

[0058] With Figure 1 Corresponding to the flowchart of the task scheduling method of the data stream processor, the disclosure also provides a task scheduling system of a data stream processor, which combines Figure 5 , the task scheduling system of the data stream processor can include: Figure 6 As shown in the system, the task scheduling system of the data stream processor can include: Separation module 601, configured to separate the computing task from the node coordinates in the program design stage of the computing task, and configure the node coordinates as an execution parameter; Compiler 602, configured to analyze the dependency relationship and data flow relationship of each computing task in the compilation stage, generate a DAG task scheduling graph, each task node corresponds to an execution node in the data stream processor, and generate a virtual coordinate of the node; Host 603, configured to write the kernel function bin instructions of each computing node into the data stream processor memory in the execution stage, and write the data structure of the DAG task scheduling graph into the memory of the data stream processor, and release the PCIe bus, so that other application programs can write tasks into the data stream processor concurrently; Data stream processor 604, configured to read the DAG task scheduling graph in the data stream processor memory based on the C stream control core; Data stream processor 604, further configured to create a task scheduling program for each DAG task scheduling graph based on the C stream control core, output the grouped DAG task scheduling graph of the corresponding analysis program, and sequentially issue firmware and kernel function bin instructions to the actual computing core according to the coordinate mapping relationship; The data stream processor 604 is also used to send a completion signal to the C-flow control core when the computing node completes the first segment of the first group of computing tasks. The parser allocates computing cores to the second group of tasks in the DAG task scheduling graph and establishes a mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the second group of tasks in the DAG task scheduling graph. The C-flow core scheduler sends the corresponding second group of computing tasks in the DAG task scheduling graph to the actual computing cores. The node that has completed the computing task releases its resources in a timely manner and enters the idle node resource pool. This process continues until all computing tasks in the entire DAG task scheduling graph are completed.

[0059] In some embodiments, the data stream processor 604 is further configured to, after reading the DAG task scheduling graph in the data stream processor memory, allocate a parser to each DAG task. The parser estimates the ratio of computation time to transmission time based on the computational data volume and computational complexity of the task, and segments and groups the DAG task scheduling graph according to the ratio, with each group consisting of two task segments. The ratio of the estimated computation time to transmission time satisfies the formula... , computational load wi Determined by the complexity of the task. P k For the processing capacity of the target computing node, DataSize(e ij ) is edge e ij The amount of data transmitted; BandWidth is the network bandwidth between nodes (NOC). Establish a mapping relationship between the actual physical coordinates of idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and allocate actual computing cores to computing tasks.

[0060] In some embodiments, when there are three computing tasks TASK1, TASK2, and TASK3 requests on the current host, corresponding to three different DAG task scheduling graphs, the C-flow control core will create three different parsers: DAG parser 1, DAG parser 2, and DAG parser 3. The DAG parser analyzes information such as the computational complexity, computational data volume, and data transmission time between child nodes and adjacent nodes in the DAG task graph, estimates the computation time and transmission time of each child node, and groups the DAG task scheduling graph.

[0061] In some embodiments, the mapping relationship between the actual physical coordinates of the idle nodes and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and the allocation of actual computing cores to the computing tasks, includes: The flow control core searches for a computing core in the current idle resource pool and allocates an actual computing core to the computing subtask corresponding to the virtual coordinate pair. When searching for a computing core in the current idle resource pool, the flow control core considers the physical topology distance between the location of the idle node in the idle resource pool and the computing node where the parent task is located, and the available bandwidth factor of the node NOC network path, defines the node matching degree Affinity(n k , i , Dist(n k , parent i ) is the physical distance between the node n k and the computing node where the parent task parent i is located, BW avail is the available network bandwidth, and a and β are weight factors. Then, the idle node with the highest matching degree is selected, and the physical coordinates of the idle node are mapped to the virtual coordinates of the corresponding node in the DAG task graph.

[0062] In some embodiments, the kernel function bin instruction is a computing instruction required to be executed by the computing node in the data flow processor, and different computing nodes correspond to different computing subtasks. The data structure of the DAG task scheduling graph includes virtual coordinate information of each subtask node, input and output data information of the subnode, data dependency relationship information of each node in the DAG task scheduling graph, and position information of the kernel function bin instruction corresponding to the subtask in the DDR memory.

[0063] As shown in Figure 7 , the embodiments of the present disclosure also provide a task scheduling device 700 of a data flow processor, which includes a processor 704 and a memory 701. Optionally, the system can also include a communication interface 702 and a bus 703. The processor 704, the communication interface 702, and the memory 701 can complete mutual communication through the bus 703. The communication interface 702 can be used for information transmission. The processor 704 can call the logical instructions in the memory 701 to execute the task scheduling method of the data flow processor in the above-described embodiments.

[0064] In addition, the logical instructions in the memory 701 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer readable storage medium.

[0065] The memory 701 can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiments of the present disclosure, as a computer readable storage medium. The processor 704 executes the program instructions / modules stored in the memory 701, thereby performing functional applications and data processing, that is, implementing the task scheduling method of the data flow processor in the above embodiments.

[0066] The memory 701 can include a program storage area and a data storage area, where the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 701 can include a high-speed random access memory, and can also include a non-volatile memory.

[0067] The embodiments of the present disclosure provide a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are set as the task scheduling method of the data flow processor.

[0068] The computer readable storage medium described above can be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

[0069] The technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes one or more instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method of the embodiments of the present disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, etc. various media that can store program codes, or can be a transitory storage medium.

[0070] The above description and drawings are illustrative of embodiments of the present disclosure and are not intended to be limiting. Other embodiments can include structural, logical, electrical, process, and other changes. Embodiments are illustrative of the many possible variations that are readily undertaken. Individual components and functions are optional unless explicitly required, and the order of operations can be varied. Portions and features of some embodiments can be included in, or substituted for, those of other embodiments. As used in the description of the embodiments, the article "a" is intended to include one or more items unless the context clearly indicates otherwise. Likewise, the term "and / or" as used in the application refers to any and all possible combinations of one or more of the associated listed items. Additionally, as used in this application, the term "comprises" and variations thereof do not intend to preclude the presence or addition of one or more other features, integers, steps, operations, elements, and / or groups thereof, but rather to encompass them. An element procured under the recitation "a" does not, without additional recitation, preclude the existence of additional identical elements in the process, method, or apparatus. Each embodiment is intended to cover its variations and alternatives. For the methods, products, etc. disclosed by the embodiments, if they correspond to the method part of the embodiments, the relevant parts can be referred to the description of the method part.

[0071] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present disclosure. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0072] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to apparatuses, devices, etc.), can be implemented in other manners. For example, the apparatus embodiments described above are merely schematic. For example, the division of the units is merely logical function division. There can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, or among the different units, can be indirect couplings or communication connections through some interfaces, devices, or units, and can be in electric, mechanical, or other forms.

[0073] The flowcharts and block diagrams in the drawings show the possible implementation architectures, functions, and operations of the systems, methods, and computer program products according to the embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks can occur in different orders than those noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the drawings, the operations or steps corresponding to different blocks can also occur in different orders than those disclosed in the descriptions, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. Each block in the block diagrams and / or flowcharts, and the combination of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0074] The various embodiments of the systems and techniques described above can be implemented in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a load programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0075] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, or entirely on a remote machine or server.

[0076] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0077] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0078] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0079] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server is generally established by computer programs running on the respective computers and having a client-server relationship to each other. The servers can be cloud servers, servers of a distributed system, or servers combined with a blockchain.

[0080] It should be understood that various forms of flow shown above can be used, with steps reordered, added, or removed. For example, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, without limitation herein, so long as the desired results of the technical solutions of the present disclosure are achieved.

[0081] The specific embodiments described above are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that various modifications, combinations, sub-combinations, and alternatives can be made to the specific embodiments without departing from the spirit and principles of the present disclosure. Any further modifications, equivalent substitutions, improvements, and the like, which are within the spirit and principles of the present disclosure are to be encompassed by the present disclosure.

Claims

1. A method of task scheduling for a dataflow processor, the method comprising: The method comprises: In the programming stage of the computing task, the computing task is separated from the node coordinates, and the node coordinates are configured as execution parameters; In the compilation stage, the compiler analyzes the dependency relationship and data flow relationship of each computing task, generates a DAG task scheduling graph, each task node corresponds to an execution node in a data flow processor, and generates a virtual coordinate of the node; In the execution stage, the host writes the kernel function bin instructions of each computing node into the data flow processor memory, and writes the data structure of the DAG task scheduling graph into the data flow processor memory, and releases the PCIe bus, so that other application programs can write tasks into the data flow processor concurrently; The C stream control core of the data flow processor reads the DAG task scheduling graph in the data flow processor memory; The C stream control core creates a task scheduling program for each DAG task scheduling graph, and outputs the grouped DAG task scheduling graph parsed by the corresponding parser to the actual computing core in sequence according to the coordinate mapping relationship; When the computing node completes the first computing task in the first group, a completion signal is sent to the C stream control core, the parser allocates computing cores for the second group of tasks in the DAG task scheduling graph, and establishes a mapping relationship between the actual physical coordinates of the idle node and the virtual coordinates of the second group of tasks in the DAG task scheduling graph; The C stream kernel scheduling program issues the corresponding DAG task scheduling graph in the second group of computing tasks to the actual computing core; the node that completes the computing task releases the resource in time and enters the idle node resource pool, and the same is true for the subsequent computing tasks, until all the computing tasks in the entire DAG task scheduling graph are completed.

2. The method of claim 1, wherein, After the C stream control core of the data flow processor reads the DAG task scheduling graph in the data flow processor memory, the method further comprises: A resolver is assigned to each DAG task, the resolver estimates the ratio of the computation time and the transmission time according to the computation data volume and the computation complexity of the computation task, and performs task segmentation and grouping on the DAG task scheduling graph according to the ratio, and each group has two segments of tasks, wherein the ratio of the estimated computation time and the transmission time satisfies the formula , , the computation volume wi is determined by the task complexity, P k is the processing capacity of the target computing node, DataSize(e ij ) is the data volume transmitted by the edge e ij , and BandWidth is the bandwidth of the inter-node noc network. Establishing a mapping relationship between the actual physical coordinates of the idle node and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and allocating actual computing cores for the computing tasks.

3. The method of claim 2, wherein, When the current host has three computing task requests TASK1, TASK2 and TASK3, corresponding to three different DAG task scheduling graphs, the C stream control core creates parsers including DAG parser 1, DAG parser 2 and DAG parser 3; The DAG parser analyzes the computing complexity, computing data volume and data transmission time information between adjacent nodes of the subnodes in the DAG task scheduling graph, estimates the computing time and transmission time of each subnode, and groups the DAG task scheduling graph.

4. The method of claim 2, wherein, The method for establishing a mapping relationship between the actual physical coordinates of the idle node and the virtual coordinates of the first group of tasks in the DAG task scheduling graph, and allocating actual computing cores for the computing tasks, comprises: The flow control core searches for a computing core in the current idle resource pool, and allocates an actual computing core to the computing subtask corresponding to the virtual coordinate pair. When searching for the computing core in the current idle resource pool, the flow control core considers the physical topology distance between the position of the idle node in the idle resource pool and the computing node where the parent task is located, and the available bandwidth factor of the node NOC network passage, defines the node matching degree Affinity(n k , i , Dist(n k , parent i ) is the physical distance between the node n k and the computing node where the parent task parent i is located, BW avail is the available network bandwidth, and α and β are weight factors. Then, the idle node with the highest matching degree is selected, and the physical coordinates of the idle node are mapped to the virtual coordinates of the corresponding node in the DAG task graph.

5. The method of claim 1, wherein, The kernel function bin instruction is a computing instruction that needs to be executed by the computing node in the data flow processor, and different computing nodes correspond to different computing subtasks; The data structure of the DAG task scheduling graph includes virtual coordinate information of each subtask node, input and output data information of the subnode, data dependency relationship information of each node in the DAG task scheduling graph, and position information of a kernel function bin instruction corresponding to the subtask in the DDR memory.

6. A task scheduling system of a dataflow processor, characterized by The system comprises; a separation module, configured to separate the computing task from the node coordinates in a programming stage of the computing task, and configure the node coordinates as an execution parameter; a compiler, configured to analyze dependency relationship and data flow relationship of each computing task, generate a DAG task scheduling graph, and generate a virtual coordinate of a node in a compiling stage; a host, configured to write kernel function bin instructions of each computing node into a data stream processor memory, write a data structure of the DAG task scheduling graph into the data stream processor memory, and release a PCIe bus so that other application programs can concurrently write tasks into the data stream processor; a data stream processor, configured to read the DAG task scheduling graph in the data stream processor memory based on a C stream control core; the data stream processor is further configured to create a task scheduling program for each DAG task scheduling graph based on the C stream control core, output a grouped DAG task scheduling graph by a parsing program corresponding to the DAG task scheduling graph, and sequentially issue firmware and kernel function bin instructions to actual computing cores according to a coordinate mapping relationship; the data stream processor is further configured to send a completion signal to the C stream control core when a first computing task in a first group is completed, allocate a computing core for a second group of tasks in the DAG task scheduling graph by the parsing program, and establish a mapping relationship between actual physical coordinates of an idle node and virtual coordinates of the second group of tasks in the DAG task scheduling graph; the C stream core scheduling program issues the second group of computing tasks in the DAG task scheduling graph to the actual computing cores, and the node that completes the computing task releases resources in time and enters an idle node resource pool, and the same is repeated until all computing tasks in the entire DAG task scheduling graph are completed.

7. The system of claim 6, wherein, The data flow processor is further configured to, after reading the DAG task scheduling diagram in the data flow processor memory, assign a parsing program to each DAG task, the parsing program estimating a ratio of a calculation time to a transmission time according to a calculation data volume and a calculation complexity of the calculation task, and performing task segmentation and grouping on the DAG task scheduling diagram according to the ratio, each group having two segments of tasks, wherein the ratio of the calculation time to the transmission time satisfies the formula , , the calculation volume wi being determined by the task complexity, P k a processing capacity of a target computing node, DataSize(e ij ) is a data volume transmitted by an edge e ij , and BandWidth is a bandwidth of an inter-node noc network. a mapping relationship between actual physical coordinates of an idle node and virtual coordinates of the first group of tasks in the DAG task scheduling graph is established, and an actual computing core is allocated for the computing task.

8. The system of claim 7, wherein, When there are three computing tasks TASK1, TASK2 and TASK3 in the current host, three different DAG task scheduling graphs are correspondingly created, and three different parsing programs, namely, a DAG parsing program 1, a DAG parsing program 2 and a DAG parsing program 3, are created by the C stream control core. The DAG parsing program analyzes computing complexity, computing data volume and data transmission time information between adjacent nodes of the subnode in the DAG task graph, estimates computing time and transmission time of each subnode, and groups the DAG task scheduling graph.

9. An electronic device, comprising: comprises: at least one processor; and a memory in communication connection with the at least one processor; The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

10. A non-transitory computer-readable storage medium storing computer instructions, the computer instructions being for causing a computer to perform the method of any one of claims 1-5. The computer instructions are for causing the computer to perform the method of any one of claims 1-5.

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