SPI (Serial Peripheral Interface) communication method and communication system

Abstract

The invention provides an SPI (Serial Peripheral Interface) communication method and system. The system comprises an SPI host and at least one SPI slave; the method comprises the following steps: an SPI host switches a first pin of a data signal line into an external interrupt input signal mode, and pulls down a chip selection signal of a target SPI slave in at least one SPI slave; when the target SPI slave detects that the chip selection signal is low level and the data is prepared, the second pin of the data signal line is switched to a common output mode, and an interrupt signal is sent to the SPI host through the data signal line; after the interrupt signal is sent, the second pin of the data signal line is switched to a data transmission signal mode; and when the SPI host detects interrupt signal input, switching the first pin of the data signal line into a data transmission signal mode, starting SPI communication with the target SPI slave, and receiving target data sent by the target SPI slave. Therefore, the data signal line is multiplexed into different signal modes, and the interrupt notification mechanism of the SPI slave is combined, so that the efficient communication between the SPI master and slave is realized on the basis of not adding a new signal line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a SPI communication method and a communication system. BACKGROUND

[0002] In embedded systems, SPI (Serial Peripheral Interface) is a commonly used communication protocol, which is widely used to connect microcontrollers and external devices, providing a high-speed, full-duplex, serial communication interface. SPI has shown strong application ability in different scenarios, including sensor interface, memory device connection, and embedded communication module. Sensors play an important role in embedded systems, and SPI, as an efficient communication protocol, can well meet the needs of sensor data acquisition and control. Currently, SPI has four signal lines: MOSI, MISO, CLK, and CS. MOSI is the signal line for the host to send data to the slave; MISO is the signal line for the slave to send data to the host; CLK is the clock signal provided by the host; and CS is the chip selection signal line, used to select the slave participating in communication.

[0003] For SPI master-slave communication, the existing communication methods include: first, based on the existing four lines, an additional signal line Data Ready is added, which is used for the SPI slave to notify the SPI master that the data is ready, and then the SPI master initiates communication. However, this method increases hardware resource overhead. Second, based on the traditional SPI communication 4-line system, a polling method is used, and the SPI master continuously checks the SPI slave data ready signal within a certain time interval. If the signal is detected to be high, it means that the data is ready, and the host can start SPI communication to read data. However, this method will occupy a certain processing resource of the host for continuously checking the signal. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a SPI communication method and a communication system, which realizes efficient communication between SPI master and slave by time-multiplexing the data signal line into different signal modes and combining the interrupt notification mechanism of the SPI slave, without the need to add new signal lines.

[0005] The present application provides a SPI communication method, which is applied to a SPI communication system including a SPI master and at least one SPI slave. The method includes: The SPI master switches the first pin of the data signal line to an external interrupt input signal mode and pulls down the chip selection signal of the target SPI slave in the at least one SPI slave. The target SPI slave switches the second pin of the data signal line to a normal output mode when detecting that the chip select signal is low and the data is ready, sends an interrupt signal to the SPI master through the data signal line, and switches the second pin of the data signal line to a data transmission signal mode after the interrupt signal is sent. The SPI master switches the first pin of the data signal line to a data transmission signal mode and starts SPI communication with the target SPI slave when detecting the interrupt signal input, and receives target data sent by the target SPI slave.

[0006] Further, the data signal line is a MOSI signal line, and the data transmission signal mode is an SPI MOSI signal mode.

[0007] Further, the method further comprises: If the system only includes one SPI slave, the SPI master continues to execute the original business logic until the interrupt signal is detected within a preset time period.

[0008] Further, the method further comprises: If the system includes multiple SPI slaves, the SPI master pulls up the chip select signal of the target SPI slave, reselects the target SPI slave, and pulls down the chip select signal of the new target SPI slave to communicate with the new target SPI slave if the interrupt signal is not detected within a preset time period.

[0009] Further, the SPI master starts SPI communication with the target SPI slave to receive target data sent by the target SPI slave, comprising: The SPI master starts SPI communication with the target SPI slave to send instruction data to the target SPI slave; wherein the instruction data includes register address and read-write information. The target SPI slave receives the instruction data, reads the target data according to the instruction data, and sends the target data to the SPI master; When the target data is sent, the SPI master pulls up the chip select signal of the target SPI slave.

[0010] Further, sending an interrupt signal to the SPI master through the data signal line, comprising: The target SPI slave pulls up the level of the data signal line, delays for a predetermined time, and then pulls down the level of the data signal line to send a falling edge interrupt signal to the SPI master.

[0011] Further, the SPI host detects the interrupt signal, including: The SPI host releases the data signal line to a high impedance state or a high level in an idle period without data transmission. The SPI host determines that the interrupt signal is detected when a falling edge level change is detected through an independent GPIO interrupt controller.

[0012] Embodiments of the present application also provide an SPI communication system, including an SPI host and at least one SPI slave. The SPI host is configured to switch a first pin of a data signal line to an external interrupt input signal mode, and pull a chip select signal of a target SPI slave in the at least one SPI slave to a low level. The target SPI slave is configured to switch a second pin of the data signal line to a normal output mode when the chip select signal is detected to be at a low level and data is ready, send an interrupt signal to the SPI host through the data signal line, and switch the second pin of the data signal line to a data transmission signal mode after the interrupt signal is sent. The SPI host is further configured to switch the first pin of the data signal line to a data transmission signal mode when the interrupt signal is detected, start SPI communication between the SPI host and the target SPI slave, and receive target data sent by the target SPI slave.

[0013] Embodiments of the present application also provide an electronic device, including a processor, a memory and a bus, the memory stores machine readable instructions executable by the processor, the processor and the memory communicate through the bus when the electronic device is running, and the machine readable instructions are executed by the processor to perform steps of the SPI communication method.

[0014] Embodiments of the present application also provide a computer readable storage medium, the computer readable storage medium stores a computer program, and the computer program is executed by the processor to perform steps of the SPI communication method.

[0015] The embodiment of the present application provides a kind of SPI communication method and communication system, system includes SPI host and at least one SPI slave;The method comprises: the first pin of the data signal line is switched to external interrupt input signal mode by the SPI host, and the chip selection signal of target SPI slave in the at least one SPI slave is pulled low;When detecting that chip selection signal is low level and data is ready, the second pin of the data signal line is switched to normal output mode by the target SPI slave, and interrupt signal is sent to the SPI host by the data signal line;And after the interrupt signal is sent, the second pin of the data signal line is switched to data transmission signal mode;When detecting the interrupt signal input, the first pin of the data signal line is switched to data transmission signal mode by the SPI host, and the SPI communication between the target SPI slave is started, and target data sent by the target SPI slave is received.

[0016] In this way, by multiplexing the data signal line into different signal modes, in combination with the interrupt notification mechanism of the SPI slave, efficient communication between the SPI master and slave is realized without adding new signal lines.

[0017] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, it should be understood that the following drawings only show some embodiments of the present application, therefore should not be regarded as the limitation to the scope, for the ordinary skilled in the art, without paying the creative labor, other related drawings can also be obtained according to these drawings.

[0019] Figure 1 One of the flowcharts of the SPI communication method provided by the embodiment of the present application is shown; Figure 2 The structural schematic diagram of the SPI communication system provided by the embodiment of the present application is shown; Figure 3 The second flowchart of the SPI communication method provided by the embodiment of the present application is shown; Figure 4 The structural schematic diagram of the electronic device provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] In order to make the purposes, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, every other embodiment obtained by a person skilled in the art without creative work falls within the scope of protection of the present application.

[0021] It is found through research that, for the master-slave communication of SPI, the existing communication modes include: first, on the basis of the existing four lines, an additional signal line Data Ready is added, which is used for the SPI slave to notify the SPI master that data has been prepared, and then the SPI master initiates the communication mode. However, this mode increases the hardware resource overhead. Second, on the basis of the traditional SPI communication four-line system, a polling mode is adopted, and the SPI master constantly checks the SPI slave data preparation signal within a certain time interval. If the signal is detected to be high level, it indicates that the data has been prepared, and the host can start the SPI communication to read the data. However, this mode will occupy a certain processing resource of the host for constantly checking the signal.

[0022] Based on this, the embodiments of the present application provide an SPI communication method to realize efficient communication between SPI master and slave on the basis of not adding a new signal line.

[0023] Please refer to Figure 1 and Figure 2 , Figure 1 for one of the flowcharts of the SPI communication method provided by the embodiments of the present application, Figure 2 for a structural schematic diagram of a communication system provided by the embodiments of the present application.

[0024] The method is applied to an SPI communication system, and the system includes an SPI master and at least one SPI slave. Exemplarily, Figure 2 The SPI communication system in the embodiment includes an SPI master and two SPI slaves, namely, an SPI slave 1 and an SPI slave 2. As shown in Figure 2As shown in the figure, the SPI host and the SPI slave are connected through four signal lines of MOSI, MISO, CLK and CS. Among them, MOSI is Master Output Slave Input, that is, the signal line for the host to send data to the slave; MISO is Master Input Slave Output, that is, the signal line for the slave to send data to the host; CLK is Serial Clock, that is, the clock signal provided by the host; and CS is ChipSelect, that is, the chip selection signal line for sending the slave enable signal and selecting the slave participating in communication.

[0025] As shown in the figure, Figure 1 The SPI communication method provided by the embodiment of the application comprises: S101, the SPI host switches a first pin of a data signal line to an external interrupt input signal mode, and pulls down a chip selection signal of a target SPI slave in the at least one SPI slave.

[0026] Here, in the external interrupt input signal mode, the SPI host can detect the externally input interrupt signal, and the interrupt type can be set to edge trigger, for example. At the same time, the SPI host enables one of the SPI slaves to communicate with the SPI host by controlling the chip selection signal. Specifically, the chip selection signal of only one SPI slave is pulled down each time, and the chip selection signals of all other SPI slaves are pulled up, so that only one target SPI slave is enabled to communicate with the SPI host. Pulling up the chip selection signal indicates that the host does not communicate with the slave. The following takes SPI slave 1 as the target SPI slave as an example for description.

[0027] Among them, the data signal line refers to the signal line for transmitting data between the host and the slave, and the existing data signal lines in the SPI communication include MOSI and MISO signal lines. Preferably, the data signal line in the embodiment of the application is the MOSI signal line, and correspondingly, the data transmission signal mode is the SPI MOSI signal mode.

[0028] This is because: by multiplexing MOSI as an interrupt signal input and not multiplexing MISO as an interrupt signal input, the conflict risk is low, and the host detection complexity is low. By multiplexing MOSI as an interrupt signal input, the SPI host can distinguish between actively sending data by itself and interrupting by the slave, use independent GPIO interrupt, and do not need to parse data. The SPI slave usually needs to be enabled when the chip selection CS is pulled down, so as to drive the MISO line. The MOSI line can be handed over to the slave when the host is idle, and does not depend on the chip selection CS. The chip selection CS is only used to support multiple slaves to communicate with the host.

[0029] More specific reasons are as follows: MISO is originally used for slave to master transmission of data (such as responding to the host's read instruction), if it is simultaneously multiplexed as an interrupt signal transmission, when the slave needs to send data and interrupts, there will be "normal data" and "interrupt signal" on the MISO line at the same time. The default direction of MOSI is that the host sends data to the slave (host driving, slave receiving). When the slave needs to send an interrupt signal, the MOSI line can be driven to generate a level change (such as rising edge / falling edge) in the idle period when the host does not send data (at this time the MOSI line is released by the host, usually in a high impedance state or a fixed level), and the host can recognize it as an interrupt by detecting this "unexpected" level change. And according to the detection of MISO interrupt, the host needs to read bit by bit through the shift register of the SPI controller when receiving MISO data, and the interrupt signal needs to be embedded in the data frame (such as the preamble "11110000") if it is mixed into MISO. The host needs to parse the data frame to recognize the interrupt, which increases the protocol complexity and CPU overhead.

[0030] The detection of MOSI interrupt can be independent of the SPI controller, and the host can configure the MOSI pin as a "GPIO input" mode (idle time), and directly monitor the level change through an independent GPIO interrupt controller (such as an edge detection circuit) without going through the data receiving logic of the SPI.

[0031] S102, when the target SPI slave detects that the chip select signal is low and the data is ready, the second pin of the data signal line is switched to a normal output mode, and an interrupt signal is sent to the SPI host through the data signal line; and after the interrupt signal is sent, the second pin of the data signal line is switched to a data transmission signal mode.

[0032] In this step, when the SPI slave 1 detects that the chip select signal line CS1 is low and the SPI slave 1 data is ready, the SPI slave 1 switches the SPI MOSI special pin to a normal GPIO output mode without increasing the GPIO pin. For example, when the SPI slave 1 buffer update flag is 1, it indicates that the SPI slave data is ready.

[0033] In one possible implementation, the target SPI slave pulls up the level of the data signal line, delays for a predetermined time, and then pulls down the level of the data signal line to send a falling edge interrupt signal to the SPI host. For example, the SPI slave 1 first pulls up the level, delays for 10 microseconds, and then pulls down the level to generate a falling edge interrupt signal to the SPI host, notifying the SPI host to start communication.

[0034] In this way, the host sets the MOSI pin as an external interrupt input, and the slave sets the MOSI pin as a GPIO output. When the MOSI pin is used as a data line, the slave can send a falling edge interrupt signal to the host to inform the host to start communication, and then the SPI slave switches the interrupt signal pin to the MOSI signal mode of the SPI slave.

[0035] In addition, when the SPI slave 1 detects that the chip select signal line CS1 is low, but the SPI slave 1 data is not ready, at this time, the SPI slave 1 does not need to switch the interrupt mode, continues to prepare data, and does not feedback to the host, so as to reduce the occupation of communication resources.

[0036] S103、the SPI host switches the first pin of the data signal line to a data transmission signal mode and starts SPI communication with the target SPI slave when detecting the interrupt signal input, and receives target data sent by the target SPI slave.

[0037] Here, the SPI host detects the interrupt signal, including: The SPI host releases the data signal line to a high impedance state or a high level during an idle period without transmitting data; and the SPI host determines that the interrupt signal is detected when detecting a falling edge level change through an independent GPIO interrupt controller.

[0038] The SPI host receives one interrupt signal sent by the SPI slave 1 and the trigger edge is a falling edge. The SPI host pulls up the chip select CS1 first, and then switches the GPIO of the interrupt signal to the SPI MOSI signal mode, and starts SPI communication at the same time.

[0039] In a specific implementation, after the SPI host starts SPI communication with the target SPI slave, the SPI host receives target data sent by the target SPI slave, including: The SPI host starts SPI communication with the target SPI slave, and sends instruction data to the target SPI slave; wherein the instruction data includes a register address and read-write information; the target SPI slave receives the instruction data, reads the target data according to the instruction data, and sends the target data to the SPI host; and when the target data is sent, the SPI host pulls up the chip select signal of the target SPI slave.

[0040] Here, the SPI host pulls down the chip select CS1 to send instruction data; the SPI slave 1 receives the instruction data sent by the SPI host, first buffers the instruction data locally, parses the received instruction data, then reads and sends the existing target data in the buffer to the SPI host. The SPI host waits for the SPI slave 1 data sending to complete in a loop. When the target data is sent, the SPI host pulls up the chip select signal of the target SPI slave, the SPI slave 1 communication with the SPI host ends, the host can parse the data and perform corresponding operations, and the SPI communication between the host and a new slave begins. For example, when the SPI slave 2 needs to communicate with the SPI host, the above steps are repeated, and only the chip select CS1 in the steps is changed to the chip select CS2, and the slave 1 is changed to the slave 2.

[0041] Further, if the system only includes one SPI slave, the SPI host does not detect the interrupt signal input within a preset time length, and continues to execute the original business logic until the interrupt signal is detected.

[0042] Alternatively, if the system includes multiple SPI slaves, the SPI host does not detect the interrupt signal input within a preset time length, pulls up the chip select signal of the target SPI slave, reselects the target SPI slave, and pulls down the chip select signal of the new target SPI slave to communicate with the new target SPI slave.

[0043] For example, after the SPI host pulls down the chip select CS1, it waits for 20 microseconds, and if the host does not receive a falling edge interrupt signal sent by the slave and there is another slave, for example, the slave 2, only the chip select CS2 is pulled down and all other slave chip selects are pulled up, that is, the host tries to communicate with the slave 2; if the host does not receive a falling edge interrupt signal sent by the slave within a preset time and there is only one SPI slave 1, the SPI host can continue to do other things until the next interrupt signal arrives.

[0044] Please refer to Figure 3 , Figure 3 The flowchart of the SPI communication method provided by another embodiment of the application is shown in FIG. 2. As shown in FIG. 2, the SPI communication method provided by the embodiment of the application includes the following steps. Figure 3 Step 1, the SPI host sets the pin of the MOSI signal line to an external interrupt input signal mode, pulls down the chip select signal CS1, and enables the communication with the slave 1.

[0045] Step 2, the SPI slave 1 judges whether the chip select CS1 is low and whether the data is ready.

[0046] ​Step 3, if no, SPI slave 1 continues to prepare data until timeout, no interrupt signal is sent, SPI master pulls down chip select CS2 and pulls up other chip selects, and tries to communicate with SPI slave 2.

[0047] Step 4, if yes, SPI slave 1 switches the pin of MOSI signal line to normal GPIO mode, and generates a falling edge interrupt signal.

[0048] Step 5, SPI slave 1 switches the pin of the interrupt signal to SPI MOSI signal mode.

[0049] Step 6, SPI master receives the falling edge interrupt signal of SPI slave 1, switches the pin of MOSI signal line to external interrupt input signal mode, writes register address and read-write information into cache, and starts SPI communication.

[0050] Step 7, SPI master pulls down chip select CS1.

[0051] Step 8, SPI master sends instruction data.

[0052] Step 9, SPI slave 1 receives the instruction data, analyzes and returns target data to the SPI master.

[0053] Step 10, SPI master judges whether the agreed target data is sent, if no, returns to step 8; if yes, enters step 11.

[0054] Step 11, SPI master pulls up chip select CS1.

[0055] The embodiment of the application provides a kind of SPI communication method, SPI host will MOSI signal line's pin be set as external interrupt input signal mode, simultaneously by pulling down chip selection signal, select corresponding slave machine to carry out communication;SPI slave machine multiplexes as normal GPIO, SPI slave machine generates 1 falling edge interrupt signal to host, then switch to SPI MOSI signal line.When host receives the interrupt signal sent by slave machine, SPI host will MOSI signal line's pin be switched from external interrupt input signal mode to MOSI mode, host will register address and read-write information be placed in cache, host pulls down chip selection signal, then sends instruction data, slave machine accepts instruction data, parses, and by this, target data pre-stored in cache is sent to host, realizes the full-duplex transmission of data, chip selection signal is pulled high when communication ends.The data sent by slave machine has been pre-stored in cache by slave machine, slave machine notifies host to start data transmission by multiplexing MOSI pin as normal GPIO method and generating rising and falling edge signals, without increasing a signal line, reduce hardware resource overhead;At the same time, when SPI slave machine detects that corresponding chip selection signal line is low and data is ready, interrupt signal is directly generated, SPI host responds quickly and can continue to do other tasks when idle, reduce waiting time, improve MCU resource utilization.In addition, the SPI slave machine interrupt and mode switching method can also realize the communication of 1 host to multiple slaves, host time multiplexing can read the latest data.

[0056] In addition, in the embodiment of the application, the MOSI is used for multiplexing transmission of interrupt signals, instead of MISO, so that the risk of conflict is low, and the detection complexity of the host is low.The MOSI is multiplexed as an interrupt mode, so that the SPI host can distinguish between its own transmission and slave interrupt, independent GPIO interrupt, without the need to parse data.The SPI slave machine can drive the MISO line only when the chip selection CS is pulled low, while the MOSI line can be handed over to the slave machine when the host is idle, and does not depend on the chip selection CS.The chip selection CS is only used to support the communication of multiple slaves and the host. Based on the same inventive concept, the embodiment of the application also provides an SPI communication system.The system includes an SPI host and at least one SPI slave machine; The SPI host is configured to switch a first pin of a data signal line to an external interrupt input signal mode, and pull down a chip selection signal of a target SPI slave machine in the at least one SPI slave machine; The target SPI slave machine is configured to switch a second pin of the data signal line to a normal output mode when detecting that the chip selection signal is low and data is ready, send an interrupt signal to the SPI host through the data signal line, and switch the second pin of the data signal line to a data transmission signal mode after the interrupt signal is sent; The SPI host is further configured to switch the first pin of the data signal line to a data transmission signal mode and start SPI communication with the target SPI slave when the interrupt signal input is detected, and receive target data sent by the target SPI slave.

[0057] Further, the data signal line is a MOSI signal line, and the data transmission signal mode is an SPI MOSI signal mode.

[0058] Further, if the system includes only one SPI slave, the SPI host is further configured to continue to execute original business logic until the interrupt signal is detected, if the interrupt signal input is not detected within a preset time length.

[0059] Further, if the system includes multiple SPI slaves, the SPI host is further configured to pull up a chip select signal of the target SPI slave, reselect the target SPI slave, and pull down a chip select signal of a new target SPI slave, and perform communication with the new target SPI slave, if the interrupt signal input is not detected within a preset time length.

[0060] Further, the SPI host, when starting SPI communication with the target SPI slave and receiving target data sent by the target SPI slave, is specifically configured to: the SPI host starts SPI communication with the target SPI slave, and sends instruction data to the target SPI slave; the instruction data includes a register address and read-write information; the target SPI slave receives the instruction data, reads the target data according to the instruction data, and sends the target data to the SPI host; after the target data is sent, the SPI host pulls up the chip select signal of the target SPI slave.

[0061] Further, the target SPI slave, when sending an interrupt signal to the SPI host through the data signal line, is specifically configured to: the target SPI slave pulls up a level of the data signal line, delays for a predetermined time length, and then pulls down the level of the data signal line, to send a falling edge interrupt signal to the SPI host.

[0062] Further, the SPI host, when detecting the interrupt signal, is specifically configured to: the SPI host releases the data signal line to a high resistance state or a high level in an idle period without data transmission; the SPI host determines that the interrupt signal is detected when a falling edge level change is detected through an independent GPIO interrupt controller.

[0063] Please refer to Figure 4 , Figure 4 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, the electronic device 400 includes a processor 410, a memory 420 and a bus 430. Figure 4

[0064] The memory 420 stores machine readable instructions executable by the processor 410. When the electronic device 400 is running, the processor 410 communicates with the memory 420 through the bus 430. The machine readable instructions, when executed by the processor 410, can perform the steps of the SPI communication method in the method embodiment shown in FIG. 3. For specific implementation, please refer to the method embodiment, which will not be described here again. Figure 1

[0065] The present application also provides a computer readable storage medium, which stores a computer program. When the computer program is run by a processor, the steps of the SPI communication method in the method embodiment shown in FIG. 3 can be performed. For specific implementation, please refer to the method embodiment, which will not be described here again. Figure 1

[0066] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiment, which will not be described here again.

[0067] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented by other ways. The device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, devices or units, which can be electrical, mechanical or other forms.

[0068] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, some or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0069] ​​​In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0070] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0071] Finally, it should be noted that the above-described embodiments are merely specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit the same. The protection scope of the present application is not limited thereto, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily think of changes to the technical solutions recorded in the foregoing embodiments within the technical range disclosed by the present application, or replace some technical features with equivalent replacements; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of SPI communication, the method comprising: The method is applied to an SPI communication system, the system comprising an SPI host and at least one SPI slave; the method comprising: the SPI host switching a first pin of a data signal line into an external interrupt input signal mode and pulling a chip select signal of a target SPI slave in the at least one SPI slave low; the target SPI slave switching a second pin of the data signal line into a normal output mode upon detecting that the chip select signal is low and data is ready, sending an interrupt signal to the SPI host through the data signal line, and switching the second pin of the data signal line into a data transmission signal mode after the interrupt signal is sent; the SPI host switching the first pin of the data signal line into the data transmission signal mode upon detecting the interrupt signal input, and starting SPI communication between the SPI host and the target SPI slave to receive target data sent by the target SPI slave.

2. The method of claim 1, wherein, The data signal line is a MOSI signal line, and the data transmission signal mode is an SPI MOSI signal mode.

3. The method of claim 1, wherein, The method further comprises: if the system comprises only one SPI slave, the SPI host continuing to execute original business logic until detecting the interrupt signal if the interrupt signal is not detected within a preset time length.

4. The method of claim 1, wherein, The method further comprises: if the system comprises multiple SPI slaves, the SPI host pulling the chip select signal of the target SPI slave high, reselecting a target SPI slave, and pulling the chip select signal of the new target SPI slave low to communicate with the new target SPI slave if the interrupt signal is not detected within a preset time length.

5. The method of claim 1, wherein, The SPI host starting SPI communication between the SPI host and the target SPI slave to receive target data sent by the target SPI slave, comprising: the SPI host starting SPI communication between the SPI host and the target SPI slave to send instruction data to the target SPI slave; wherein the instruction data comprises a register address and read-write information; the target SPI slave receiving the instruction data, reading the target data according to the instruction data, and sending the target data to the SPI host; the SPI host pulling the chip select signal of the target SPI slave high after the target data is sent.

6. The method of claim 1, wherein, The target SPI slave sending an interrupt signal to the SPI host through the data signal line, comprising: the target SPI slave pulling the level of the data signal line high, delaying for a predetermined time length, and then pulling the level of the data signal line low to send a falling edge interrupt signal to the SPI host.

7. The method of claim 6, wherein, The SPI host detecting the interrupt signal, comprising: the SPI host releasing the data signal line into a high impedance state or a high level during an idle period when no data is transmitted; the SPI host determining that the interrupt signal is detected upon detecting a falling edge level change through an independent GPIO interrupt controller.

8. An SPI communication system, characterized by The system comprises an SPI host and at least one SPI slave; The SPI host is configured to switch the first pin of the data signal line into an external interrupt input signal mode and pull down a chip select signal of a target SPI slave in the at least one SPI slave; The target SPI slave is configured to switch the second pin of the data signal line into a normal output mode when detecting that the chip select signal is low and data is ready, send an interrupt signal to the SPI host through the data signal line, and switch the second pin of the data signal line into a data transmission signal mode after the interrupt signal is sent. The SPI host is further configured to switch the first pin of the data signal line into a data transmission signal mode and start SPI communication between the SPI host and the target SPI slave when detecting that the interrupt signal is input, and receive target data sent by the target SPI slave.

9. An electronic device, comprising: Comprise: A processor, a memory and a bus, the memory stores machine readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, the machine readable instructions are executed by the processor to perform the steps of the SPI communication method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, the computer program is executed by the processor to perform the steps of the SPI communication method as claimed in any one of claims 1 to 7.

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