Gpu chip yield prediction method and system based on multi-dimensional data fusion

Abstract

The present application relates to the technical field of chip yield prediction, in particular to a GPU chip yield prediction method and system based on multi-dimensional data fusion, comprising: first, obtaining multi-dimensional data in the manufacturing process of the GPU chip; then, based on the process flow, performing time sequence calibration and alignment on the multi-dimensional data, and generating high-order interaction features by using implicit feature interaction technology; then, generating a multi-dimensional abnormal correlation vector by yield bottleneck projection; subsequently, generating a local risk value based on the multi-dimensional abnormal correlation vector and the manufacturing process node, and constructing a global yield map; finally, constructing an abnormal propagation and accumulation calculation framework, calculating the cumulative risk value along the manufacturing process node, and obtaining the final GPU chip yield prediction value through global damage projection. The present application realizes GPU chip yield prediction by performing time sequence fusion and feature cross on multi-dimensional manufacturing data, and constructing a global yield map and calculating the propagation and accumulation risk of abnormalities.

Description

Technical Field

[0001] This invention relates to the field of chip yield prediction technology, specifically to a GPU chip yield prediction method and system based on multi-dimensional data fusion. Background Technology

[0002] With the rapid development of information technology, GPU chips are increasingly being used in high-value fields such as artificial intelligence and data centers. The manufacturing process of GPU chips is extremely precise and complex, and production costs are high. Therefore, how to accurately and efficiently predict yield has become a technical challenge for the semiconductor industry.

[0003] However, existing data analytics techniques have significant shortcomings in addressing the yield prediction challenges of complex chips like GPUs. Specifically, the data fusion level is shallow, exhibiting a "silo effect." While existing data platforms can display data from multiple dimensions, they essentially present data in segments and perform post-hoc statistics. Data from different testing phases fails to achieve deep correlation and integrated modeling. Although some technologies can perform correlation analysis on data from wafer testing and finished product testing, this remains at a superficial statistical analysis level, failing to reveal deep causal relationships across stages and dimensions. Therefore, the technical problem faced by existing technologies in GPU chip yield prediction lies in the lack of a method and system capable of breaking through data silos, deeply integrating production data from different manufacturing processes and dimensions, and establishing a forward-looking predictive model that can adapt to dynamic changes in the production environment in real time.

[0004] To address this, a method and system for predicting GPU chip yield based on multi-dimensional data fusion are proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a GPU chip yield prediction method and system based on multi-dimensional data fusion. This method involves: collecting and integrating multi-dimensional data from the GPU manufacturing process, analyzing the complex relationships between the data and constructing a global yield map, calculating a cumulative risk value based on propagation and cumulative effects, and thereby predicting the GPU chip yield.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] GPU chip yield prediction methods based on multi-dimensional data fusion include:

[0008] Acquire multi-dimensional data during the GPU chip manufacturing process, including batch data, test machine data, workstation data, fail-bin data, and electrical parameter data; perform timing calibration and alignment on the multi-dimensional data based on the process flow to generate a multi-dimensional timing matrix;

[0009] Based on implicit feature interaction, multidimensional feature cross-validation is performed on a multidimensional time series matrix to generate high-order interactive features. Specifically, a deep factorization machine network model is constructed, including a time series matrix input unit, a feature embedding unit, a factorization unit, a deep neural network unit, and an interactive feature output unit. The time series matrix input unit receives the multidimensional time series matrix. The feature embedding unit performs unified vectorization representation of the input discrete and continuous features, transforming the discrete and continuous features in the multidimensional time series matrix into numerical vectors, which are then mapped to a low-dimensional real vector space through the embedding layer. Discrete features include batch number, test machine number, workstation number, and the failure category with the highest proportion. Continuous features include electrical parameter values. The factorization unit extracts second-order interactive features by calculating the inner product of discrete and continuous features. The deep neural network unit couples multiple discrete and continuous features to extract high-order nonlinear complex interactive features. The interactive feature output unit concatenates the second-order interactive features and complex interactive features to generate high-order interactive features.

[0010] Dimensionality reduction of high-order interaction features is achieved by projecting yield bottlenecks to generate multidimensional anomaly correlation vectors; local risk values ​​are generated based on the multidimensional anomaly correlation vectors and GPU chip manufacturing process nodes, and a global yield map is constructed.

[0011] An anomaly propagation and accumulation calculation framework is constructed based on the global yield map. Based on the anomaly propagation and accumulation calculation framework, the superposition value of local risk values ​​is calculated along the GPU chip manufacturing process nodes, and finally the cumulative risk value is obtained. By performing global damage projection on the cumulative risk value, the GPU chip yield prediction value is obtained.

[0012] Preferably, the multi-dimensional data in the GPU chip manufacturing process includes: batch data obtained from the manufacturing execution system, and test machine data, workstation data, fail-bin data, and electrical parameter data extracted from automated testing equipment; the electrical parameter data includes threshold voltage, saturation current, leakage current, capacitance value, dynamic power consumption, and interface bandwidth.

[0013] Preferably, the step of performing time-series calibration and alignment on multi-dimensional data based on the process flow to generate a multi-dimensional time-series matrix includes: using the electronic identifier of the GPU chip as an index and generating a multi-dimensional time-series matrix based on the timestamps of the process nodes recorded by the manufacturing execution system.

[0014] Preferably, the step of reducing the dimensionality of high-order interaction features by projecting the yield bottleneck includes: analyzing the high-order interaction features based on principal component analysis and identifying the failure category combinations and electrical parameter anomalies that have the greatest impact on the yield of GPU chips; projecting the high-order interaction features onto a low-dimensional anomaly correlation vector space that characterizes the yield loss factors to generate a multi-dimensional anomaly correlation vector.

[0015] Preferably, the step of generating local risk values ​​based on multidimensional anomaly correlation vectors and manufacturing process nodes includes: for each GPU chip manufacturing process node, using the multidimensional anomaly correlation vector of historical chip batches at a single manufacturing process node as input features, and the final pass and failure results of historical chip batches as training labels, to train a local risk prediction model; inputting the multidimensional anomaly correlation vector generated by the current chip batch to be predicted at a single GPU chip manufacturing process node into the corresponding pre-trained local risk prediction model, and outputting a local risk value; the GPU chip manufacturing process nodes include: lithography and etching nodes, thin film and implantation nodes, chemical mechanical polishing nodes, multilayer metal interconnect nodes, via and contact hole nodes, wafer acceptance test nodes, wafer probing nodes, packaging nodes, and final test nodes.

[0016] Preferably, the construction of the global yield graph and the construction of the anomaly propagation and accumulation calculation framework include: constructing a Bayesian network model based on the global yield graph; constructing a directed acyclic graph with each manufacturing process node as a vertex and the manufacturing order as directed edges based on the manufacturing process of the GPU chip, wherein the attributes of the vertices include the local risk value of the manufacturing process node; and obtaining the conditional probability between any two connected nodes based on the local risk value.

[0017] Preferably, the calculation of the sum of the local risk values ​​to obtain the cumulative risk value includes: based on the anomaly propagation and cumulative calculation framework, using confidence propagation, along the direction of the directed acyclic graph, starting from the starting node, passing all confidence values ​​to the next node along the direction of the directed edges, the next node updates its confidence value based on the passed confidence values, and combines the conditional probability between any two connected nodes to calculate the intermediate cumulative risk value up to the current node, repeating the propagation and calculation step by step until the final test node, to obtain the cumulative risk value characterizing the cumulative failure risk of the entire process.

[0018] Preferably, the step of performing global damage projection on the cumulative risk value includes: using the cumulative risk value as input feature and historical yield data as training labels, training and constructing a gradient boosting decision tree regression model based on historical yield data and cumulative risk value through iterative construction of new trees and model updates, establishing a nonlinear mapping relationship between the cumulative risk value and the actual chip yield; and obtaining the GPU chip yield prediction value based on the nonlinear mapping relationship and the current cumulative risk value.

[0019] A GPU chip yield prediction system based on multi-dimensional data fusion includes:

[0020] Acquisition and Processing Module: Acquires multi-dimensional data during the GPU chip manufacturing process, including batch data, test machine data, workstation data, fail-bin data, and electrical parameter data; performs timing calibration and alignment on the multi-dimensional data based on the process flow to generate a multi-dimensional timing matrix;

[0021] Feature Engineering Module: Based on implicit feature interaction, this module performs multi-dimensional feature cross-validation on a multi-dimensional time series matrix to generate higher-order interactive features. Specifically, it constructs a deep factorization machine network model, including a time series matrix input unit, a feature embedding unit, a factorization unit, a deep neural network unit, and an interactive feature output unit. The time series matrix input unit receives the multi-dimensional time series matrix. The feature embedding unit performs unified vectorization representation of the input discrete and continuous features, transforming them into numerical vectors and mapping them to a low-dimensional real vector space through the embedding layer. Discrete features include batch number, test machine number, workstation number, and the failure category with the highest percentage. Continuous features include electrical parameter values. The factorization unit extracts second-order interactive features by calculating the inner product of discrete and continuous features. The deep neural network unit couples multiple discrete and continuous features to extract higher-order nonlinear complex interactive features. The interactive feature output unit concatenates the second-order interactive features and complex interactive features to generate higher-order interactive features.

[0022] Dimensionality reduction of high-order interaction features is achieved by projecting yield bottlenecks to generate multidimensional anomaly correlation vectors; local risk values ​​are generated based on the multidimensional anomaly correlation vectors and GPU chip manufacturing process nodes, and a global yield map is constructed.

[0023] Yield prediction module: Construct an anomaly propagation and accumulation calculation framework based on the global yield map; Based on the anomaly propagation and accumulation calculation framework, calculate the superposition value of local risk values ​​along the GPU chip manufacturing process nodes, and finally obtain the cumulative risk value; By performing global damage projection on the cumulative risk value, obtain the GPU chip yield prediction value.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] 1. This invention uses the electronic identifier of the GPU chip as an index and performs rigorous timing calibration and alignment on batch data, test machine data, workstation data, fail-bin data, and electrical parameter data based on the timestamps of the process flow, generating a multi-dimensional timing matrix. This method integrates data scattered across different manufacturing stages into a multi-dimensional timing matrix with time-series relationships, based on the lifecycle of a single chip. This not only solves the problem of the temporal and spatial fragmentation of multi-dimensional data but also provides data support for subsequent data processing and yield prediction.

[0026] 2. This invention utilizes a deep factorization machine network model to perform implicit feature interactions on a multidimensional time-series matrix, thereby uncovering second-order and higher-order nonlinear relationships between features. Subsequently, based on principal component analysis, yield bottleneck projection is performed, reducing the dimensionality of high-order interactive features to a low-dimensional anomaly correlation vector space representing key failure modes. This enables the localization of GPU yield-influencing factors among massive production parameters, thus avoiding the reliance of traditional analysis on single dimensions or shallow correlations. The deep factorization machine network model can identify and quantify complex, cross-dimensional, nonlinear combinations such as "anomalies in leakage current parameters of a specific lithography machine and a certain batch," thereby improving the depth and accuracy of yield bottleneck diagnosis and providing a data foundation for subsequent risk assessment.

[0027] 3. This invention constructs a global yield graph with manufacturing process nodes as vertices and local risk values ​​as attributes, and establishes a Bayesian network model to form an anomaly propagation and accumulation calculation framework. Finally, it calculates the cumulative risk value representing the overall process risk along the manufacturing flow using the confidence propagation method. This method simulates the dynamic propagation and accumulation effects of potential risks in long-cycle, multi-process GPU manufacturing scenarios. This invention transforms the abstract process flow into a quantifiable probabilistic graphical model, not only assessing the risk of individual nodes but also revealing how anomalies gradually propagate and amplify from upstream processes to downstream. The resulting cumulative risk value is a comprehensive assessment of the chip's overall lifecycle health, thereby improving the comprehensiveness and accuracy of risk identification.

[0028] 4. This invention employs an end-to-end prediction method that uses the cumulative risk value throughout the entire process as input features and historical yield data as training labels. It utilizes a gradient boosting decision tree regression model to establish a nonlinear mapping relationship between the cumulative risk value and the final yield. This method enables the prediction of the final yield of GPU chips in a dynamically changing production environment. It ultimately converges the complex production process risks into a cumulative risk value and leverages the powerful fitting ability of gradient boosting decision trees to establish a prediction path from underlying process data to top-level yield results. This allows the system to predict the final outcome in real time based on intermediate cumulative risks, providing forward-looking guidance for production decisions, thereby reducing production costs and improving overall efficiency. Attached Figure Description

[0029] Figure 1 This is a flowchart of a GPU chip yield prediction method based on multi-dimensional data fusion proposed in an embodiment of this invention.

[0030] Figure 2 This is a structural diagram of the GPU chip yield prediction system based on multi-dimensional data fusion proposed in an embodiment of this invention application;

[0031] Figure 3 This is a structural diagram of the implicit feature interaction proposed in an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Example 1

[0034] Please see Figure 1 This invention provides a GPU chip yield prediction method based on multi-dimensional data fusion, and the technical solution is as follows:

[0035] Acquire multi-dimensional data during the GPU chip manufacturing process, including batch data, test machine data, workstation data, fail-bin data, and electrical parameter data; perform timing calibration and alignment on the multi-dimensional data based on the process flow to generate a multi-dimensional timing matrix;

[0036] Multidimensional feature cross-polling is performed on the multidimensional time series matrix based on implicit feature interaction to generate high-order interaction features; the dimensionality of the high-order interaction features is reduced by the yield bottleneck projection to generate multidimensional anomaly correlation vectors; local risk values ​​are generated based on the multidimensional anomaly correlation vectors and manufacturing process nodes, and a global yield map is constructed.

[0037] An anomaly propagation and accumulation calculation framework is constructed based on the global yield map. Based on the anomaly propagation and accumulation calculation framework, the superposition value of local risk values ​​is calculated along the GPU chip manufacturing process nodes, and finally the cumulative risk value is obtained. By performing global damage projection on the cumulative risk value, the GPU chip yield prediction value is obtained.

[0038] Furthermore, the multi-dimensional data in the GPU chip manufacturing process includes: batch data obtained from the manufacturing execution system, and test machine data, workstation data, fail-bin data, and electrical parameter data extracted from automated testing equipment; the electrical parameter data includes threshold voltage, saturation current, leakage current, capacitance value, dynamic power consumption, and interface bandwidth.

[0039] Specifically, obtaining batch data from the manufacturing execution system includes: for each batch of GPU chips entering the production line, extracting the batch identifier and wafer number from the manufacturing execution system, obtaining the process flow followed by the chips in that batch, and the entry and exit timestamps at each GPU chip manufacturing node.

[0040] Specifically, Fail Bin data, also known as failure classification data, records the reasons why a semiconductor chip fails during the final testing process, and categorizes and numbers the reasons for failure. For example, when testing a batch of GPU chips, different Fail Bin numbers are assigned to different reasons for failure; Bin 1 indicates a short circuit in an I / O pin, and Bin 2 indicates that the core frequency is not up to standard.

[0041] This invention acquires multi-dimensional data covering process history, testing environment, failure modes, and electrical parameters from manufacturing execution systems and automated testing equipment, enabling quantitative characterization of factors affecting GPU chip yield. It constructs a complete data link from microscopic process deviations to macroscopic electrical failures, thereby providing data-driven support for yield prediction.

[0042] Furthermore, to address the impact of data drift and noise interference on model stability in real-world production environments, a dynamic data cleaning and adaptive normalization unit is included before the process flow-based temporal calibration and alignment of multi-dimensional data to generate a multi-dimensional time series matrix. This unit first utilizes a sliding window-based statistical process control method to monitor the distribution changes of electrical parameters in real time, automatically identifying and marking progressive data drift caused by equipment aging, environmental changes, and consumable replacement. Subsequently, the unit employs a Kalman filter-based adaptive normalization method, dynamically adjusting the normalization parameters according to the monitored drift trend to ensure that the data input to the subsequent feature engineering module is consistent and comparable across time scales. To address the cold start problem in the early stages of new product introduction, the dynamic data cleaning and adaptive normalization unit also introduces a transfer learning mechanism based on domain adversarial networks. This mechanism transfers some weights of the feature extraction network that has been trained on mature product lines to the model of the new product. By using domain adversarial training, the model learns the common features between the data of the old and new products, thereby shortening the model convergence time and improving the accuracy of initial predictions when the training data is sparse.

[0043] Furthermore, based on the process flow, multi-dimensional data is time-calibrated and aligned to generate a multi-dimensional timing matrix, including: using the electronic identifier of the GPU chip as an index and based on the timestamps of the process nodes recorded by the manufacturing execution system to generate a multi-dimensional timing matrix.

[0044] Specifically, using the electronic identifier of the GPU chip as an index and based on the timestamps of the process nodes recorded by the manufacturing execution system (MES), a multi-dimensional timing matrix is ​​generated. This includes: using the batch identifier and wafer number of the GPU chip as indexes, matching the data in the MES with the data in the automated testing equipment based on the timestamps of the process nodes recorded by the MES, and generating a structured multi-dimensional timing matrix. Each row of the multi-dimensional timing matrix represents an independent GPU chip die, indexed by its batch identifier and wafer number. Each column represents a feature, which are strictly arranged according to the chronological order of their occurrence in the manufacturing process. The multi-dimensional timing matrix is ​​a high-dimensional sparse vector containing all discrete and continuous features of the chip from wafer fabrication to final testing.

[0045] This invention uses the unique electronic identifier of the GPU chip as an index and strictly follows the process node timestamps recorded by the manufacturing execution system as an alignment benchmark. It maps and aligns batch-to-batch process data scattered over several weeks or even months of GPU chip manufacturing cycle with millisecond-level electrical parameter data and failure data in the final wafer testing stage onto each individual chip die. This ultimately constructs a multi-dimensional time series matrix, providing a data foundation for subsequent high-order feature cross-analysis, anomaly propagation accumulation analysis, and yield prediction.

[0046] Further, see Figure 3 The implicit feature interaction structure diagram is used to perform multi-dimensional feature cross-processing on a multi-dimensional time series matrix based on implicit feature interactions to generate high-order interactive features. This includes: constructing a deep factorization machine network model, comprising a time series matrix input unit, a feature embedding unit, a factorization unit, a deep neural network unit, and an interactive feature output unit; the time series matrix input unit receives the multi-dimensional time series matrix; the feature embedding unit performs unified vectorization representation of the input discrete and continuous features, transforming the discrete and continuous features in the multi-dimensional time series matrix into numerical vectors, which are then mapped to a low-dimensional real vector space through the embedding layer; discrete features include batch numbering, test machine numbering, workstation numbering, and the failure category with the highest proportion; continuous features include electrical parameter values; the factorization unit extracts second-order interactive features by calculating the inner product of discrete and continuous features; the deep neural network unit couples multiple discrete and continuous features to extract high-order nonlinear complex interactive features; and the interactive feature output unit concatenates the second-order interactive features and complex interactive features to generate high-order interactive features.

[0047] Specifically, the time series matrix input unit serves as the entry point for the model, receiving and processing the generated multidimensional time series matrix.

[0048] Specifically, the feature embedding unit addresses the problem of different types of features being unable to directly interact and compute, mapping all features to the same low-dimensional dense vector space, including:

[0049] For discrete features: For discrete features such as batch number, test machine number, workstation number, and the most prevalent failure category identified from FailBin data, an embedding matrix is ​​created for each feature. For example, if there are 100 test machines, a 100×K matrix is ​​created for the test machine number feature, where K is the preset embedding dimension, e.g., K=16. When a test machine with number i is input, the model extracts the i-th row vector of the embedding matrix as its vectorized representation.

[0050] For continuous features: For continuous features such as electrical parameter values, although they are numerical values, in order to interact with discrete features in the same space, each continuous feature is assigned a single embedding vector with a size of K. When inputting, the numerical value of the continuous feature is multiplied by this embedding vector to achieve its vectorization.

[0051] The original high-dimensional sparse vector input is vectorized and then transformed into a set of low-dimensional dense embedding vectors of dimension K.

[0052] Specifically, the factorization unit is used to capture second-order interactions between any two features. This involves: receiving the embedding vectors of all features; and for any two different feature embedding vectors, quantifying the impact of their combined effect on yield by calculating the inner product between the embedding vectors. Repeating these steps, the inner product results of all possible feature pairs are summed to obtain a scalar value, which is the sum of all second-order interaction effects.

[0053] Specifically, deep neural network units are used to automatically learn the implicit, highly nonlinear, complex interactions between three or more features. This involves: receiving the embedding vectors of all features; concatenating all embedding vectors into a single long vector, which is then used as the input to the deep neural network. The deep neural network contains three hidden layers with 128, 64, and 32 neurons respectively, using ReLU as the activation function. Through multiple layers of nonlinear transformations, the deep neural network can automatically combine input features to learn third-order and higher-order complex interaction features.

[0054] Specifically, the interaction feature output unit integrates low-order and high-order interaction information to generate the final high-order interaction features. This includes concatenating the scalar value representing the sum of second-order interaction effects output by the factorization unit with the complex interaction features representing high-order interactions output by the deep neural network unit. The resulting concatenated vector is the high-order interaction feature vector. The high-order interaction feature is a numerical vector that contains the interaction information in the original multidimensional time series matrix that has a decisive impact on yield.

[0055] By constructing a deep factorization machine network model integrating a factorization unit and a deep neural network unit, the present invention can not only explicitly calculate the second-order interaction between any two features, but also implicitly learn the coupled non-linear associations between three or more features through the deep network. Finally, the model generates a high-order interaction feature vector that can characterize how complex process fluctuations act together on the chip performance, thereby enhancing the insight into the causes of the yield problem.

[0056] Furthermore, dimensionality reduction of the high-order interaction features is performed through yield bottleneck projection, including: analyzing the high-order interaction features based on the principal component analysis method and identifying the combination of failure categories and electrical parameter anomalies that have the greatest impact on the yield of GPU chips; projecting the high-order interaction features into a low-dimensional abnormal association vector space representing the yield loss factor to generate a multi-dimensional abnormal association vector.

[0057] Specifically, analyzing the high-order interaction features based on the principal component analysis method and identifying the combination of failure categories and electrical parameter anomalies that have the greatest impact on the yield of GPU chips includes:

[0058] Data preparation: Taking a single chip die as a sample, pooling the high-order interaction feature vectors of all training samples to form an N×M matrix, where N is the number of samples and M is the dimension of the high-order interaction features; performing column-wise normalization on the matrix to make the mean of each feature dimension 0 and the variance 1; calculating the column-wise covariance matrix of the normalized matrix and performing eigenvalue decomposition on the covariance matrix to obtain a set of eigenvalues and their corresponding eigenvectors;

[0059] Principal component analysis and identification: Each eigenvector represents a principal component, which is also a new orthogonal dimension linearly combined by the original high-order interaction features; the magnitude of each eigenvalue represents the proportion of the total variance of the original data that the corresponding principal component can explain; sorting the eigenvalues from largest to smallest, the principal component ranked at the forefront is the combination of failure categories and electrical parameter anomalies that have the greatest impact on the yield fluctuation.

[0060] Specifically, projecting the high-order interaction features into a low-dimensional abnormal association vector space representing the yield loss factor to generate a multi-dimensional abnormal association vector includes: selecting the first d principal components whose cumulative variance contribution rate exceeds a certain threshold, for example, the threshold is 90%, where d << M, and these d eigenvectors form a new coordinate system basis, and this low-dimensional space is the low-dimensional abnormal association vector space representing the yield loss factor; for each GPU chip die, performing dot product operations on its original M-dimensional high-order interaction feature vector with these d selected principal components respectively; after calculation, each GPU chip die will obtain a d-dimensional new vector Z, and this vector Z is the final multi-dimensional abnormal association vector; the numerical magnitude of each dimension of the multi-dimensional abnormal association vector represents the risk degree of the chip die in that dimension.

[0061] This invention uses principal component analysis to mathematically decompose and project the high-order interactive features generated by the deep learning model, thereby reducing the dimensionality of the original high-dimensional feature vectors and mapping them to a low-dimensional anomaly correlation space. This not only reduces the complexity of subsequent calculations but also provides an engineering-interpretable diagnostic profile for the potential defects of each chip, improving the practical value and credibility of the yield prediction model.

[0062] Furthermore, local risk values ​​are generated based on multidimensional anomaly correlation vectors and manufacturing process nodes, including: for each GPU chip manufacturing process node, using the multidimensional anomaly correlation vector of historical chip batches at a single manufacturing process node as input features, and the final pass and failure results of historical chip batches as training labels, to train a local risk prediction model; inputting the multidimensional anomaly correlation vector generated by the current chip batch to be predicted at a single GPU chip manufacturing process node into the corresponding pre-trained local risk prediction model, and outputting the local risk value; the GPU chip manufacturing process nodes include: lithography and etching nodes, thin film and implantation nodes, chemical mechanical polishing nodes, multilayer metal interconnect nodes, via and contact hole nodes, wafer acceptance test nodes, wafer probing nodes, packaging nodes, and final test nodes.

[0063] Specifically, the generation of local risk values ​​based on multidimensional anomaly correlation vectors and manufacturing process nodes includes:

[0064] Training data preparation: For each historical chip sample and each GPU chip manufacturing process node I, only all process and measurement data up to the completion of GPU chip manufacturing process node I are extracted from the multi-dimensional time series matrix. The truncated time series sub-matrix is ​​input into the pre-trained deep factorization machine network model to generate node high-order interaction features specific to the GPU chip manufacturing process node. Using yield bottleneck projection, a node multi-dimensional anomaly correlation vector specific to the current GPU chip manufacturing process node is generated. The node multi-dimensional anomaly correlation vector objectively represents the cumulative anomaly risk of the chip after completing GPU chip manufacturing process node I. The training set of GPU chip manufacturing process node I is constructed using the set of node multi-dimensional anomaly correlation vectors generated by historical chip batches at GPU chip manufacturing process node I as input features and the binary results of the final pass and failure of historical chip batches as training labels.

[0065] Local risk prediction model training: Using the training set built on GPU chip manufacturing process node I, a local risk prediction model is trained based on gradient boosting decision trees and cross-entropy loss. The learning rate is 0.05, the number of trees is 100, and the maximum depth of each tree is 5. This process is repeated for all other GPU chip manufacturing process nodes to obtain a pre-trained local risk prediction model library.

[0066] Local risk value calculation: Select the corresponding local risk prediction model for the current GPU chip manufacturing process node from the local risk prediction model library, and input the node multidimensional anomaly correlation vector of each chip die in the current GPU chip batch to be predicted; the local risk prediction model outputs a value between [0, 1], which is the local risk value of the current GPU chip batch to be predicted at the current GPU chip manufacturing process node.

[0067] This invention trains a dedicated local risk prediction model for each GPU chip manufacturing process node based on historical data. The model takes the cumulative abnormal state vector up to the current node as input and the final chip yield result as the training target. This transforms the current cumulative abnormal state vector into the local risk value of the node, thereby upgrading the yield analysis mode from post-failure analysis to proactive risk warning. It also lays the data foundation for building subsequent risk accumulation and propagation models, thus improving the efficiency and accuracy of yield control.

[0068] Furthermore, the construction of the global yield graph and the construction of the anomaly propagation and accumulation calculation framework include: constructing a Bayesian network model based on the global yield graph; constructing a directed acyclic graph with each manufacturing process node as a vertex and the manufacturing order as directed edges based on the GPU chip manufacturing process, wherein the attributes of the vertices include the local risk value of the manufacturing process node; and obtaining the conditional probability between any two connected nodes based on the local risk value.

[0069] Specifically, a directed acyclic graph is constructed based on the GPU chip manufacturing process, including: treating each GPU chip manufacturing process node as a vertex of the graph; establishing directed edges between adjacent vertices according to the order of GPU chip manufacturing, with the direction from the previous node to the next node, forming an acyclic path from the start node to the end node; using the local risk value calculated for each chip at each node as the attribute of the vertex; the vertex attribute represents the prior probability that the GPU chip will ultimately fail in testing after completing the process at node I.

[0070] Specifically, a Bayesian network model is constructed based on the global yield graph, including: using the directed acyclic graph of the GPU chip manufacturing process as the topology to construct a Bayesian network; discretizing continuous local risk values ​​into several states. For example, based on the distribution of risk values, a threshold can be used to divide them into three states: low risk: local risk value less than or equal to 0.05; medium risk: local risk value greater than 0.05 and less than or equal to 0.2; high risk: local risk value greater than 0.2.

[0071] Specifically, based on local risk values, the conditional probability between any two connected nodes is obtained, including: for each chip, there is a complete risk sequence; for any node v in the network... j and its parent node v i Calculate P (node ​​v) j State = High Risk | Node v i The probability value of state = low risk, taking the calculation of P(v2=high risk|v1=low risk) as an example:

[0072] Select all chip samples with low risk status at node v1, and denote the number as a; count how many chips change to high risk status at node v2, and denote the number as b; divide b by a to obtain the maximum likelihood estimate of the conditional probability.

[0073] Repeat the above process for all possible combinations of states of all nodes and their parent nodes, and construct a complete conditional probability table based on all the maximum likelihood estimates obtained; the conditional probability table contains the conditional probabilities between any two connected nodes.

[0074] Furthermore, to enhance the adaptability of the global yield map to dynamic changes in the process flow, the anomaly propagation and cumulative calculation framework also includes a risk backpropagation and parameter self-correction mechanism based on the final test results. Specifically, after each chip batch completes final testing, the risk backpropagation and parameter self-correction mechanism compares the actual failure results with the cumulative risk value predicted by the model. For samples with large prediction deviations, the system triggers a backpropagation calculation: first, through association rule mining, the final failure mode is attributed to one or more upstream manufacturing process nodes; then, the attribution result is used as the true risk label, and backpropagation is performed along the directed acyclic graph, with minor weight adjustments made to the conditional probability tables between the nodes along the path according to the Bayesian update rule. This closed-loop feedback correction mechanism enables the anomaly propagation model to continuously learn and optimize from the latest production data. When a new, unseen failure propagation path appears, the model can automatically adjust its internal parameters to capture this new pattern, thereby ensuring the long-term effectiveness and robustness of the yield prediction system in the face of process changes or sudden anomalies.

[0075] This invention trains a dedicated local risk prediction model independently for each GPU chip manufacturing process node based on historical data. Using the multidimensional anomaly correlation vector up to the current GPU chip manufacturing node as input and the final chip yield result as the training target, it successfully decomposes and attributes the single, lagging final yield problem that runs through the entire manufacturing process to each specific stage in the process. Ultimately, this enables yield analysis to locate the process bottleneck that causes the greatest damage to yield, thereby improving the efficiency and accuracy of yield control.

[0076] This invention constructs a Bayesian network model based on a global yield graph, using manufacturing process nodes as random variables and manufacturing order as the causal dependency. This model integrates the local risk predictions of isolated nodes into a global dynamic model describing how risks probabilistically propagate, evolve, and accumulate throughout the entire process. Ultimately, it not only visualizes complex yield issues using a global yield graph but also establishes a framework for anomaly propagation and accumulation calculation. This framework quantifies the cascading impact of small early process deviations on subsequent steps and ultimately, the yield, thus elevating yield management from passive point-to-point monitoring to a systemic optimization of the entire process chain.

[0077] Further, the sum of the local risk values ​​is calculated to obtain the cumulative risk value, including: based on the anomaly propagation and cumulative calculation framework, confidence propagation is adopted. Starting from the starting node, all confidence values ​​are passed along the direction of the directed acyclic graph to the next node along the direction of the directed edges. The next node updates its confidence value based on the passed confidence values ​​and combines the conditional probability between any two connected nodes to calculate the intermediate cumulative risk value up to the current node. This process is repeated and calculated level by level until the final test node to obtain the cumulative risk value that represents the cumulative failure risk of the entire process.

[0078] Specifically, step-by-step risk updates based on confidence propagation include:

[0079] The propagation of confidence from parent node to child node, taking the propagation from node v1 to child node v2 as an example, first discretizes the risk states into {low risk, medium risk, high risk}: Node v1 sends its current confidence distribution, i.e., its assessment of its own risk state, as a message to v2; after receiving the message from node v1, child node v2 iterates through the probabilities of all risk states of v1, multiplies the probability of each risk state by the conditional probability of reaching the low-risk, medium-risk, and high-risk state under that state, and then sums them to obtain the prior confidence; multiplying the prior confidence by the conditional probability between the current node v1 and node v2, the posterior confidence of the low-risk, medium-risk, and high-risk states, i.e., the intermediate cumulative risk value, is obtained;

[0080] Repeat the above steps along the direction of the directed acyclic graph (DAG) until the last node of the DAG, at which point the iterative calculation terminates. The final confidence distribution calculated at the termination node represents the overall failure risk of the chip after undergoing all manufacturing processes. In the actual manufacturing process, the probability of the final high-risk confidence state can be taken as the cumulative risk value representing the cumulative failure risk throughout the entire process.

[0081] This invention, based on an anomaly propagation and cumulative calculation framework, employs a confidence propagation algorithm to perform step-by-step risk calculation along the directed acyclic graph of the manufacturing process. It integrates and updates the local risk value of each manufacturing node with the cumulative risk transmitted from upstream nodes based on the conditional probabilities between nodes. Ultimately, it transforms a series of discrete, static local risk predictions into a cumulative risk value that comprehensively reflects the cumulative effect of risks throughout the entire process. This cumulative risk value serves as the basis for final yield prediction, not only improving the accuracy and robustness of the prediction but also revealing the systemic causes of yield losses, providing a quantitative basis and perspective for global process optimization.

[0082] Furthermore, by performing global damage projection on the cumulative risk value, including: using the cumulative risk value as input feature and historical yield data as training labels, training and constructing a gradient boosting decision tree regression model based on historical yield data and cumulative risk value through iterative construction of new trees and model updates, establishing a nonlinear mapping relationship between the cumulative risk value and the actual chip yield; and obtaining the GPU chip yield prediction value based on the nonlinear mapping relationship and the current cumulative risk value.

[0083] Specifically, a gradient boosting decision tree regression model based on historical yield data and cumulative risk values ​​is trained and constructed, including:

[0084] Training data preparation: The input feature is the cumulative risk value of each historical chip die sample used for training; the training label is the historical yield data of the historical chip die samples, including: pass results and failure results;

[0085] The process involves training and building an improved decision tree regression model: Initializing the predicted values ​​for all historical chip die samples as the average yield of all chips in the training data (total number of good products / total number of samples); For each iteration: For each chip sample, calculating the mean squared error between the predicted value of the current gradient boosting decision tree regression model and its actual yield label, which is the negative gradient of the predicted value; constructing a new decision tree, multiplying it by a learning rate of 0.05, and then adding it to the existing gradient boosting decision tree regression model; repeating the iteration steps until performance no longer improves, resulting in the trained gradient boosting decision tree regression model. The trained gradient boosting decision tree regression model represents the non-linear mapping relationship between the cumulative risk value and the final yield. For example, when the cumulative risk value increases from 0.05 to 0.1, the yield probability drops sharply by 80%; however, when the cumulative risk value is already high, increasing from 0.8 to 0.85, because the cumulative risk value itself has already reached 0.8, the chip failure probability is extremely high, and the increase of 0.05 in the cumulative risk value will not significantly affect the chip failure probability, and the decrease in the yield probability is very gradual.

[0086] Specifically, based on the nonlinear mapping relationship and the current cumulative risk value, the predicted yield value of the GPU chip is obtained, including:

[0087] The cumulative risk value of a chip to be predicted is used as input to the pre-trained gradient boosting decision tree regression model. The gradient boosting decision tree regression model will output a continuous value between [0, 1], which is the final predicted value of the GPU chip yield.

[0088] Furthermore, to ensure that yield prediction results not only remain at the numerical level but also guide actual process optimization, the gradient boosting decision tree regression model integrates a root cause interpretability analysis unit based on multi-task learning while outputting the GPU chip yield prediction value. The root cause interpretability analysis unit extends the original single-task regression model into a multi-task learning framework. Under this framework, the primary task of the gradient boosting decision tree regression model remains predicting the final yield value; simultaneously, it also sets up multiple auxiliary classification tasks in parallel. These tasks utilize the local risk value and multi-dimensional anomaly correlation vector of each manufacturing process node to predict the most likely specific failure mode, such as excessive leakage current, timing violations, or memory cell damage. When the predicted yield of a chip batch is low, the root cause interpretability analysis unit not only provides a low yield warning but also highlights the manufacturing process node with the highest risk and the most likely underlying physical mechanism of failure based on the output probabilities of each auxiliary task, using a contribution score. This design transforms the black-box predictive model into a transparent diagnostic tool, providing engineers with a basis for decision-making to quickly locate yield bottlenecks and take targeted corrective and preventive measures.

[0089] This invention employs a gradient boosting decision tree regression model that iteratively builds new trees and updates the model, and uses historical yield data and the gradient of accumulated risk values ​​for training. This establishes a nonlinear mapping relationship between accumulated risk values ​​and the final chip yield result, ultimately projecting complex and abstract process risk measures into quantified yield prediction probabilities, thereby providing prediction results for capacity planning.

[0090] This invention first performs time-series alignment and fusion of multi-dimensional data to generate a multi-dimensional time-series matrix. Then, it mines high-order implicit features and quantifies the local risks at each manufacturing node. Finally, it establishes a full-process anomaly propagation and accumulation calculation framework. Based on this framework, it tracks, quantifies, and simulates the transmission and evolution of failure risks across process nodes, thereby enabling chip yield prediction. This invention not only achieves GPU chip yield prediction based on multi-dimensional fused data but also reveals the systemic causes of yield loss from a global perspective, thus providing data support for production decisions.

[0091] Example 2

[0092] Please see Figure 2 This invention provides a GPU chip yield prediction system based on multi-dimensional data fusion, comprising:

[0093] Acquisition and Processing Module: Acquires multi-dimensional data during the GPU chip manufacturing process, including batch data, test machine data, workstation data, fail-bin data, and electrical parameter data; performs timing calibration and alignment on the multi-dimensional data based on the process flow to generate a multi-dimensional timing matrix;

[0094] Feature engineering module: Based on implicit feature interaction, multidimensional feature cross is performed on the multidimensional time series matrix to generate high-order interaction features; the high-order interaction features are reduced in dimensionality by yield bottleneck projection to generate multidimensional anomaly correlation vectors; local risk values ​​are generated based on multidimensional anomaly correlation vectors and manufacturing process nodes, and a global yield map is constructed.

[0095] Yield prediction module: Construct an anomaly propagation and accumulation calculation framework based on the global yield map; Based on the anomaly propagation and accumulation calculation framework, calculate the superposition value of local risk values ​​along the GPU chip manufacturing process nodes, and finally obtain the cumulative risk value; By performing global damage projection on the cumulative risk value, obtain the GPU chip yield prediction value.

[0096] The following example uses a GPU chip manufactured with batch number LOT-XXXXXXXX to demonstrate the specific steps of a GPU chip yield prediction system based on multi-dimensional data fusion, including:

[0097] Acquisition and Processing Module: The acquisition and processing module automatically obtains data for batch number LOT-XXXXXXXX from the Manufacturing Execution System (MAS) and extracts batch-to-batch data, tester data, workstation data, Fail Bin data, and electrical parameter data for that batch of chips from the database of its automated testing equipment. For example, for a wafer with electronic identification D-1A3F in batch number LOT-XXXXXXXX, the system acquires data showing that the wafer used the IMPLANTER-07 device at the thin film and implantation nodes, the saturation current of the P-type metal-oxide-semiconductor field-effect transistor in the wafer acceptance test was 1.25 mA / um, and the number of failures attributed to failure category 5 (i.e., cache errors) in the wafer probing test was 2. Using D-1A3F as an index, the system aligns all multi-dimensional data according to the timestamps recorded by the MAS to generate a row in a multi-dimensional timing matrix. This process is repeated until a complete multi-dimensional timing matrix is ​​generated.

[0098] Feature engineering module:

[0099] Generation and quantization of high-order interaction features:

[0100] The feature embedding unit maps discrete feature vectors into low-dimensional dense real vectors, which are called embedding vectors.

[0101] The factorization unit quantifies the second-order interaction between different feature embedding vectors by calculating the inner product of the embedding vectors. For example, the system calculates the inner product of the embedding vector of IMPLANTER-07 and the vector of saturation current 1.25, which characterizes the correlation strength between device IMPLANTER-07 and saturation current 1.25 mA / um.

[0102] The embedding vectors of all features are concatenated and input into a deep neural network unit. The deep neural network unit learns deeper nonlinear relationships that cannot be discovered through simple pairwise combinations through a fully connected network and the ReLU nonlinear activation function. For example, the deep neural network unit discovers a hidden rule: if and only if the IMPLANTER-07 device is used, and the saturation current is in the range of 1.24 mA / um to 1.26 mA / um, and the wafer probing tester downstream of the manufacturing process is T-32 instead of T-33, the final failure probability of the chip will increase disproportionately. This is a high-order interactive feature.

[0103] Finally, the second-order and higher-order interaction features were concatenated to generate a higher-order interaction feature vector for the D-1A3F chip;

[0104] Dimensionality reduction and calculation of local risk values:

[0105] The high-order interaction feature vectors generated from historical chips are used to construct a matrix, and principal component analysis is applied to the matrix. The analysis results identify the top 10 principal components that have the greatest impact on the final yield. For example, the analysis report points out that the first principal component is mainly composed of interaction features related to injection uniformity and interaction features related to gate leakage current, pointing to the physical root cause of yield loss. Subsequently, the high-dimensional vectors of each chip in the LOT-XXXXXXXX batch are projected into the low-dimensional space composed of these 10 principal components to generate a 10-dimensional multidimensional anomaly correlation vector.

[0106] A local risk prediction model is pre-trained for each manufacturing process node;

[0107] The average of the 10-dimensional anomaly correlation vectors of all chips at the thin film and injection nodes for batch LOT-XXXXXXXX is taken and then input into the local risk prediction model of the thin film and injection nodes. The local risk prediction model determines the probability of the state represented by the current input vector leading to the final failure based on historical data and outputs a specific probability value. In this case, the probability value is 0.18.

[0108] Similarly, when the batch is transferred to the wafer probing node, a new anomaly correlation vector is generated based on the test data of the wafer probing node and input into the local risk model of the wafer probing node; since functional errors are directly discovered during the probing stage, the risk prediction of the wafer probing node is more severe, and the local risk value output by the model is 0.25.

[0109] Yield prediction module:

[0110] Calculation of abnormal propagation and cumulative risk:

[0111] A Bayesian network-based directed acyclic graph (DAG) is constructed as a computational framework for anomaly propagation and cumulative risk. Nodes in the DAG represent manufacturing nodes, and directed edges represent the process flow sequence. The weight of each edge is the conditional probability P(risk value of manufacturing node B | risk value of manufacturing node A). For example, in a batch with a risk value of 0.18 at the upstream injection node, 30% of the batches will have a risk exceeding 0.20 at the downstream wafer probing node.

[0112] Perform confidence propagation:

[0113] Assuming the accumulated risk value is 0.08 before the thin film and implantation nodes, upon reaching the thin film and implantation nodes, the local risk value of 0.1 at these nodes is merged with the accumulated risk of 0.08 from upstream. This fusion calculation follows a Bayesian inference formula, incorporating conditional probabilities between nodes to update the confidence level. After the update, the intermediate accumulated risk value up to the thin film and implantation nodes is 0.22. This intermediate accumulated risk value of 0.22 is passed as a confidence message to the next node, wafer acceptance testing. The wafer acceptance testing node itself has a low local risk of 0.05; after fusion calculation, the accumulated risk value slightly increases to 0.23. Next, the message is passed to the wafer probing node. At the wafer probing node, the accumulated risk of 0.23 from upstream is received and merged with the higher local risk value of 0.25. The wafer probing node has a higher local risk, and the merged intermediate accumulated risk value jumps significantly to 0.31. Through subsequent manufacturing process nodes, the risk value continues to accumulate, ultimately resulting in a cumulative risk value of 0.41, representing the total cumulative failure risk throughout the process.

[0114] Global damage projection and final yield prediction:

[0115] The final cumulative risk value of 0.41 is an internal evaluation metric, which is converted into a yield prediction value using a pre-trained gradient boosting decision tree regression model. The training data for the gradient boosting decision tree regression model consists of paired data of the final cumulative risk values ​​of historical batches and the actual final yields after final testing, such as (0.25, 94.5%) and (0.55, 82.1%). The cumulative risk value of 0.41 for the current batch is input into the gradient boosting decision tree regression model, and the model is calculated through a complex nonlinear mapping function. The final output GPU chip yield prediction value is 88.2%.

[0116] This invention deeply mines multi-dimensional fusion data from the entire GPU chip manufacturing process and automatically extracts high-order interaction features that have a key impact on yield using a deep factorization network. It also constructs an anomaly propagation and accumulation calculation framework based on Bayesian networks, thereby quantifying and simulating the transmission and superposition effects of risks between various process nodes. This enables the prediction of the final chip yield and the early location of potential yield bottlenecks, thereby improving the efficiency and intelligence level of production management.

[0117] Example 3

[0118] This embodiment includes: acquiring multi-dimensional data and generating a multi-dimensional time series matrix, generating high-order interaction features based on a deep factorization machine network model, generating multi-dimensional anomaly correlation vectors through yield bottleneck projection, and generating local risk values ​​based on multi-dimensional anomaly correlation vectors and manufacturing process nodes.

[0119] This embodiment employs an end-to-end risk accumulation and yield prediction model based on Long Short-Term Memory (LSTM) networks. The specific technical solution is as follows:

[0120] Furthermore, the local risk values ​​generated sequentially during the manufacturing process for each chip are used to generate a risk time series; a recurrent neural network model based on a long short-term memory network is trained and constructed, and the final GPU chip yield prediction value is directly output with the risk time series as input.

[0121] Specifically, recurrent neural network models that construct long short-term memory networks based on risk time series include:

[0122] Training data preparation: For each historical chip die sample, calculate its local risk value at each manufacturing process node according to the method in Example 1; arrange the local risk values ​​of the manufacturing process nodes in the order of the manufacturing process to form a one-dimensional time series vector; the input feature is the set of risk time series of all historical chip samples; the training label is the final binary yield result of the historical chip sample, including pass result and failure result.

[0123] Construct and train a long short-term memory network model:

[0124] Model building:

[0125] Input layer: Receives a tensor with dimension (m, n, 1), where m is the batch size, n is the time step size corresponding to n manufacturing nodes, and 1 is the number of features at each time step, i.e., the local risk value.

[0126] Long Short-Term Memory (LSTM) Layer: Contains multiple LSM layers, for example, with 64 hidden units. LSM units, through internal forget gates, input gates, and output gates, can learn long-term dependencies in the risk sequence, i.e., how the risk value of early nodes affects the risk state of later nodes.

[0127] Fully connected layer: The output of the last time step of the long short-term memory layer is non-linearly transformed through multiple fully connected layers;

[0128] Output layer: Uses a neuron with a Sigmoid activation function to output a continuous value between [0, 1], which is the yield prediction value of the GPU chip;

[0129] Model training:

[0130] The long short-term memory model is trained using the prepared training data; binary cross-entropy is selected as the loss function, and gradient descent is performed using the Adam optimizer; the model is trained through multiple rounds of iteration until its performance on the validation set converges.

[0131] Predict yield based on a trained model:

[0132] For a batch of chips to be predicted, the local risk value of each chip die at each manufacturing node is first calculated to form a risk time series. The risk time series is then input into a long short-term memory model that has been trained. The model will directly output a predicted value between [0, 1], which is the final predicted value of the GPU chip yield.

[0133] This embodiment achieves the mapping from risk time series input to yield prediction output through an end-to-end cumulative yield prediction model based on long short-term memory networks. It not only captures the dependency between early process deviations and later yield results, but also models the superposition effect between multiple risk factors by leveraging the powerful nonlinear fitting capability of deep neural networks, thereby simplifying the complexity of model construction and improving automation efficiency.

[0134] Example 4

[0135] This embodiment includes: acquiring multi-dimensional data and generating a multi-dimensional time series matrix, generating high-order interaction features based on a deep factorization machine network model, generating local risk values ​​based on multi-dimensional anomaly correlation vectors and manufacturing process nodes, constructing a global yield map and anomaly propagation accumulation framework, and calculating cumulative risk values ​​and global damage projection steps.

[0136] The difference in this embodiment lies in the use of a nonlinear dimensionality reduction method based on a deep autoencoder. The specific technical solution is as follows:

[0137] Furthermore, dimensionality reduction of high-order interaction features is achieved through yield bottleneck projection, generating a multi-dimensional anomaly correlation vector, including:

[0138] A nonlinear dimensionality reduction model based on a deep autoencoder is constructed to train high-order interaction features. The trained encoder is then used to project the high-order interaction features into a low-dimensional nonlinear latent space to generate multidimensional anomaly correlation vectors.

[0139] Specifically, building and training a deep autoencoder model includes:

[0140] Model architecture: Construct a deep autoencoder network, consisting of two parts:

[0141] The encoder consists of multiple fully connected layers and is responsible for progressively compressing the high-dimensional features of the input. For example, if the high-order interaction features are X-dimensional, such as X=256, the encoder network structure can be designed as [256->128->64->D], where D is the dimension of the target low-dimensional space, for example, D=10. Each layer uses the ReLU non-linear activation function;

[0142] Decoder: Its structure is the opposite of the encoder; it is responsible for progressively decompressing the low-dimensional latent vector and attempting to reconstruct the original input. For example, the network structure can be designed as [D->64->128->256];

[0143] The middle layer of the model is the bottleneck layer, and the output is the dimensionality-reduced latent space representation.

[0144] Model training:

[0145] Data preparation: The high-order interaction feature matrix generated in Example 1 was used as the training data;

[0146] Training objective: To minimize the reconstruction error, specifically the mean square error between the high-order interactive feature vector of the original input and the reconstructed vector after encoding and decoding; to iteratively train the network weights through backpropagation and the Adam optimizer until the reconstruction error converges.

[0147] Generating a multidimensional anomaly correlation vector: After training, the decoder is discarded, and only the trained encoder is retained. For each GPU chip die, its original high-order interaction feature vector is input into the trained encoder. The D-dimensional vector output by the encoder is the chip's multidimensional anomaly correlation vector. This multidimensional anomaly correlation vector is an abstract representation of the original high-order features in a nonlinear low-dimensional space. This D-dimensional vector will be used as input for the subsequent generation of local risk values.

[0148] This embodiment employs a nonlinear dimensionality reduction model based on a deep autoencoder to perform bottleneck projection on high-order interactive features, achieving a deep abstraction from linear projection to a nonlinear manifold space. This enables the learning and characterization of complex, nonlinear failure modes and provides data support for subsequent local risk assessment and full-process cumulative risk calculation, thereby improving the accuracy and reliability of the entire yield prediction framework.

[0149] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A GPU chip yield prediction method based on multi-dimensional data fusion, characterized in that, include: Acquire multi-dimensional data during the GPU chip manufacturing process, including batch data, test machine data, workstation data, FailBin data, and electrical parameter data; Based on the process flow, time series calibration and alignment of multi-dimensional data are performed to generate a multi-dimensional time series matrix; Based on implicit feature interaction, multidimensional feature cross-validation is performed on a multidimensional time series matrix to generate high-order interactive features. Specifically, a deep factorization machine network model is constructed, including a time series matrix input unit, a feature embedding unit, a factorization unit, a deep neural network unit, and an interactive feature output unit. The time series matrix input unit receives the multidimensional time series matrix. The feature embedding unit performs unified vectorization representation of the input discrete and continuous features, transforming the discrete and continuous features in the multidimensional time series matrix into numerical vectors, which are then mapped to a low-dimensional real vector space through the embedding layer. Discrete features include batch number, test machine number, workstation number, and the failure category with the highest proportion. Continuous features include electrical parameter values. The factorization unit extracts second-order interactive features by calculating the inner product of discrete and continuous features. The deep neural network unit couples multiple discrete and continuous features to extract high-order nonlinear complex interactive features. The interactive feature output unit concatenates the second-order interactive features and complex interactive features to generate high-order interactive features. The high-order interaction features are reduced in dimensionality by projecting the yield bottleneck. The high-order interaction features are analyzed and identified by principal component analysis to identify the failure category combinations and electrical parameter anomalies that have the greatest impact on the yield of GPU chips. The high-order interaction features are then projected onto a low-dimensional anomaly correlation vector space that represents the yield loss factors to generate a multi-dimensional anomaly correlation vector. Local risk values ​​are generated based on multidimensional anomaly correlation vectors and GPU chip manufacturing process nodes, and a global yield map is constructed. An anomaly propagation and accumulation calculation framework is constructed based on the global yield map; based on the anomaly propagation and accumulation calculation framework, the superposition value of local risk values ​​is calculated along the GPU chip manufacturing process nodes, and finally the cumulative risk value is obtained; By performing global damage projection on the cumulative risk value, the predicted yield value of the GPU chip is obtained.

2. The GPU chip yield prediction method based on multi-dimensional data fusion according to claim 1, characterized in that, The multi-dimensional data in the GPU chip manufacturing process includes: batch data obtained from the manufacturing execution system, and test machine data, workstation data, fail-bin data, and electrical parameter data extracted from automated testing equipment; the electrical parameter data includes threshold voltage, saturation current, leakage current, capacitance value, dynamic power consumption, and interface bandwidth.

3. The GPU chip yield prediction method based on multi-dimensional data fusion according to claim 1, characterized in that, The step of performing time-series calibration and alignment of multi-dimensional data based on process flow to generate a multi-dimensional time-series matrix includes: using the electronic identifier of the GPU chip as an index and generating a multi-dimensional time-series matrix based on the timestamps of process nodes recorded by the manufacturing execution system.

4. The GPU chip yield prediction method based on multi-dimensional data fusion according to claim 1, characterized in that, The method of generating local risk values ​​based on multidimensional anomaly correlation vectors and manufacturing process nodes includes: for each GPU chip manufacturing process node, using the multidimensional anomaly correlation vector of historical chip batches at a single manufacturing process node as input features, and the final pass and failure results of historical chip batches as training labels, to train a local risk prediction model; inputting the multidimensional anomaly correlation vector generated by the current chip batch to be predicted at a single GPU chip manufacturing process node into the corresponding pre-trained local risk prediction model, and outputting a local risk value; the GPU chip manufacturing process nodes include: lithography and etching nodes, thin film and implantation nodes, chemical mechanical polishing nodes, multilayer metal interconnect nodes, via and contact hole nodes, wafer acceptance test nodes, wafer probing nodes, packaging nodes, and final test nodes.

5. The GPU chip yield prediction method based on multi-dimensional data fusion according to claim 1, characterized in that, The construction of the global yield graph and the construction of the anomaly propagation and accumulation calculation framework include: constructing a Bayesian network model based on the global yield graph; constructing a directed acyclic graph with each manufacturing process node as a vertex and the manufacturing order as directed edges based on the manufacturing process of GPU chips, where the attributes of the vertices include the local risk value of the manufacturing process node; and obtaining the conditional probability between any two connected nodes based on the local risk value.

6. The GPU chip yield prediction method based on multi-dimensional data fusion according to claim 1, characterized in that, The cumulative risk value is calculated by summing the local risk values, which includes: based on the anomaly propagation and cumulative calculation framework, confidence propagation is adopted. Starting from the starting node, all confidence values ​​are passed along the direction of the directed acyclic graph to the next node along the direction of the directed edges. The next node updates its confidence value based on the passed confidence values ​​and combines the conditional probability between any two connected nodes to calculate the intermediate cumulative risk value up to the current node. This process is repeated and calculated level by level until the final test node, to obtain the cumulative risk value that represents the cumulative failure risk of the entire process.

7. The GPU chip yield prediction method based on multi-dimensional data fusion according to claim 1, characterized in that, The process of global damage projection on the cumulative risk value includes: using the cumulative risk value as input feature and historical yield data as training labels, training and constructing a gradient boosting decision tree regression model based on historical yield data and cumulative risk value through iterative construction of new trees and model updates, establishing a nonlinear mapping relationship between the cumulative risk value and the actual chip yield; and obtaining the GPU chip yield prediction value based on the nonlinear mapping relationship and the current cumulative risk value.

8. A GPU chip yield prediction system based on multi-dimensional data fusion, characterized in that, include: Acquisition and processing module: Acquires multi-dimensional data during the GPU chip manufacturing process, including batch data, test machine data, workstation data, fail-bin data, and electrical parameter data; Based on the process flow, time series calibration and alignment of multi-dimensional data are performed to generate a multi-dimensional time series matrix; Feature Engineering Module: Based on implicit feature interaction, this module performs multi-dimensional feature cross-validation on a multi-dimensional time series matrix to generate higher-order interactive features. Specifically, it constructs a deep factorization machine network model, including a time series matrix input unit, a feature embedding unit, a factorization unit, a deep neural network unit, and an interactive feature output unit. The time series matrix input unit receives the multi-dimensional time series matrix. The feature embedding unit performs unified vectorization representation of the input discrete and continuous features, transforming them into numerical vectors and mapping them to a low-dimensional real vector space through the embedding layer. Discrete features include batch number, test machine number, workstation number, and the failure category with the highest percentage. Continuous features include electrical parameter values. The factorization unit extracts second-order interactive features by calculating the inner product of discrete and continuous features. The deep neural network unit couples multiple discrete and continuous features to extract higher-order nonlinear complex interactive features. The interactive feature output unit concatenates the second-order interactive features and complex interactive features to generate higher-order interactive features. The high-order interaction features are reduced in dimensionality by projecting the yield bottleneck. The high-order interaction features are analyzed and identified by principal component analysis to identify the failure category combinations and electrical parameter anomalies that have the greatest impact on the yield of GPU chips. The high-order interaction features are then projected onto a low-dimensional anomaly correlation vector space that represents the yield loss factors to generate a multi-dimensional anomaly correlation vector. Local risk values ​​are generated based on multidimensional anomaly correlation vectors and GPU chip manufacturing process nodes, and a global yield map is constructed. Yield prediction module: Constructs an anomaly propagation and accumulation calculation framework based on the global yield map; Based on the anomaly propagation and accumulation calculation framework, calculates the superposition value of local risk values ​​along the GPU chip manufacturing process nodes, and finally obtains the cumulative risk value; By performing global damage projection on the cumulative risk value, the predicted yield value of the GPU chip is obtained.

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