Analog calculation circuit for solving quadratic unconstrained binary optimization problem

Abstract

The invention provides an analog calculation circuit for solving a quadratic unconstrained binary optimization (QUBO) problem, and belongs to the technical field of integrated circuits. A weight matrix and a bias vector in a QUBO problem are respectively mapped into a conductance value of a 1T1R array variable resistive memory and a voltage gain coefficient of a voltage gain module, and a feedback signal output by a threshold function module is connected to a grid electrode of a 1T1R array transistor to form a closed-loop feedback structure. The grid voltage is used as a QUBO problem solving state variable result, natural evolution minimization of an energy function is achieved, and solving of the QUBO problem is completed in one step. According to the structure of feeding back the signal to the grid electrode, the isolation of the signal is enhanced, and the power consumption of the circuit is reduced; the circuit is a continuous-time analog calculation circuit, no digital circuit participates in the circuit, the calculation cost is reduced, the calculation time is shortened, and the system power consumption and the chip area are reduced. The circuit has an important value and a wide development prospect in combination optimization application based on a Hopfield network and an Ising model.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, analog computing and integrated circuit, and relates to an analog computing circuit for solving quadratic unconstrained binary optimization problem in one step, in particular to a design of analog computing circuit based on transistors and variable resistance devices (such as resistive random access memory, phase change memory, magnetic memory, ferroelectric memory, etc.), covering its working principle and the design method of key parameters. BACKGROUND

[0002] Combinatorial optimization problem is a kind of optimization problem that seeks the optimal solution in a finite feasible solution set, which is an important research direction of operations research. Combinatorial optimization problems can be generally divided into two categories: one involves continuous variables, and the other involves discrete variables. The former aims to find a set of real number or function solutions, while the latter selects the optimal object from a finite set or countable infinite set. Due to the discreteness of variables, discrete combinatorial optimization problems have different characteristics from continuous optimization problems in terms of solution space structure and search strategy, and thus their solving methods are essentially different. Quadratic unconstrained binary optimization (QUBO) problem is a typical discrete combinatorial optimization problem, which is NP-hard, i.e., the time complexity of its solving process increases exponentially on traditional digital computers, making it difficult to obtain an accurate solution for large-scale problems within an acceptable time.

[0003] In recent years, in-memory computing cross-point array (CPA) based on transistors and variable resistance memory (collectively referred to as 1T1R structure) has been widely used to accelerate various matrix operations, significantly reducing the computational complexity of matrix operations. The analog computing circuits based on variable resistance memory cross-point array that have been implemented, such as the attached Figure 1As shown, a 0T1R structure is adopted to realize a circuit solution for a special case of QUBO problem with a zero bias vector, however, there is no general in-memory computing cross-point array structure for direct solution of QUBO problem. If a general analog computing circuit for one-step solution of QUBO problem can be constructed, it is expected to break through the bottleneck of traditional digital methods in time complexity and energy consumption. Especially in the combination optimization framework of Hopfield network, Ising model and the like with energy minimization as the core, the related problems can be equivalent to QUBO problem. Through appropriate mathematical mapping, the QUBO problem solving circuit can also be used for optimal solution search of such models, thereby having wider adaptability. Therefore, a general QUBO problem solving circuit based on analog computing mechanism is proposed, which has important theoretical value and engineering application significance. SUMMARY

[0004] In view of the problems in the prior art, the present application provides an analog computing circuit for solving a quadratic unconstrained binary optimization (QUBO) problem. The circuit is based on a 1T1R cross-point array, maps the weight matrix in the QUBO problem to the analog conductance value of the variable resistance memory in the 1T1R cross-point array, maps the bias vector to the gain coefficient of the voltage gain module, and takes the gate voltage of the transistor in each column of the 1T1R cross-point array in the feedback loop under steady state as the output of the QUBO problem solving state variable result. The updating mechanism constructed by the circuit ensures that the target energy function monotonically decreases and converges to a stable solution, thereby realizing one-step solution of the QUBO problem by relying on the natural evolution process of the circuit.

[0005] The QUBO problem solved by the present application can be described as follows:

[0006] For a given n-dimensional weight matrix W=(w ij ) and bias vector λ=(λ1, λ2,..., λ n ) T , the target is to find one or more states in all binary vectors X=(x1, x2,..., x n ) T ∈{0, 1} n that minimize the following energy function:

[0007]

[0008] In this invention, "solving the QUBO problem" refers to finding the solution that minimizes the energy function E among all possible states of X. By constructing an analog computing circuit corresponding to the structure of this QUBO problem, this invention achieves a one-step solution process without the iterative steps required by traditional digital computers, and has wide applicability in typical combinatorial optimization problems such as Hopfield networks and Ising models.

[0009] The technical solution provided by this invention is as follows:

[0010] A simulation circuit based on a 1T1R crosspoint array is proposed for solving positive weight QUBO problems. This circuit is suitable for solving problems with n state variables (x1, x2, ..., xn). n The positive weighted QUBO problem is characterized by using an n-dimensional weight matrix W = (w ij )∈R n×n And bias vector λ=(λ1,λ2,…,λ n ) T ∈R n×1 The analog conductance of the variable resistive memory mapped to a 1T1R crosspoint array and the gain coefficient of the voltage gain circuit are respectively given by the state vector X = (x1, x2, ..., x...). n ) T ∈{0,1} n Each time the feedback loop in the circuit naturally evolves and updates, the system energy function E monotonically remains constant and tends to stabilize. The voltage measured at the gates of the transistors in each column of the 1T1R crosspoint array is used as the output state X, which is a solution that minimizes the energy function E. The circuit structure includes an n×n 1T1R crosspoint array. In this array, the gates of all transistors in the same column are connected. The non-transistor ends of all variable resistive memories in the same row are connected together and connected to an external voltage. The sources of all transistors in the same row are connected together and connected to the negative input of the corresponding transimpedance amplifier. The positive input of the transimpedance amplifier in each row is grounded, and its output is connected to the voltage gain circuit corresponding to that row. A feedback resistor is connected between the inverting input and output of the transimpedance amplifier. The output of the voltage gain circuit in each row is connected to the threshold function module corresponding to that row. The output of the threshold function module in each row is connected to the gate of the transistor in the corresponding column of the crosspoint array, forming n feedback loops. The transistor gates serve as control terminals for closed-loop control of the feedback paths.

[0011] The n-dimensional weight matrix W = (w ij )∈R n×n The mapping is to the analog conductance value of the variable resistive memory in the 1T1R crosspoint array, and the mapping rule satisfies... Among them G ij and wij These represent the conductance of the variable resistive memory in the i-th row and j-th column of the 1T1R cross-point array and the W matrix element, respectively. i and R i These are the external voltage connected to the variable resistive memory in the i-th row of the 1T1R crosspoint array and the feedback resistor value on the transimpedance amplifier, respectively.

[0012] The voltage gain circuit is used to amplify the input voltage. The gain coefficient is mapped by the bias vector λ, and the mapping rule satisfies... in and λ i V represents the gain coefficient of the voltage gain circuit in the i-th row of the 1T1R cross-point array and the i-th component of the bias vector λ, respectively. DD is the supply voltage of the threshold function module, and k is the ratio of its threshold voltage to the supply voltage;

[0013] The analog computing circuit as described in claim 1, characterized in that the threshold function module is used to perform nonlinear mapping on the input voltage, when the input voltage is higher than or equal to a threshold voltage kV. DD At that time, its output voltage is V DD If the output voltage is 1, it represents a logic level of 1; otherwise, the output voltage is 0, representing a logic level of 0.

[0014] On the n feedback loops, the system's state vector X = (x1, x2, ..., xn) n ) T Each update is achieved through natural evolution from the feedback loop, and the update rule is: if the i-th row satisfies ∑ j w ij x j ≥λ i Then x i =1; otherwise x i =0.

[0015] Furthermore, in the voltage gain circuit, the input terminal is connected to the inverting input terminal of the operational amplifier through a variable resistive memory, the non-inverting input terminal of the operational amplifier is grounded, and the inverting input terminal and the output terminal are connected through another variable resistive memory.

[0016] Furthermore, the threshold function module consists of two CMOS inverters connected in series. The input terminal is the gate of the first CMOS inverter, and the output terminal is the drain of the second CMOS inverter, with the output being the output voltage of the second CMOS inverter. The two NMOS sources constituting the inverter are grounded, and the PMOS sources are connected to the power supply voltage V. DD By adjusting the threshold voltages of NMOS and PMOS and and V DDThe matching is realized, and the input voltage is higher than or equal to a threshold voltage kV DD When the input voltage is lower than the threshold voltage, the output voltage is 0. DD When the input voltage is lower than the threshold voltage, the output voltage is 0.

[0017] Further, the external voltage applied to the variable resistance memory on each row of the 1T1R cross-point array is a constant voltage, and the polarity of the constant voltage V i on the i-th row is related to the bias vector λ i , that is, V i = |V i | * sign (λ i ).

[0018] On the basis of the simulation calculation circuit for solving the positive weight QUBO problem, an n*n 1T1R cross-point array with the same structure is added to solve the real weight QUBO problem with n state variables (x1, x2,..., x n ), the added 1T1R cross-point array is connected with the original 1T1R cross-point array at all transistor sources on the corresponding rows and all transistor gates on the corresponding columns; the real weight matrix W=(w ij ) is split into two positive weight matrices and that satisfy W=W + -W - , so that the difference of the real weight is realized by the opposite polarity of the external voltage applied to the variable resistance memories of the two 1T1R cross-point arrays, the external voltage applied to the variable resistance memory on the i-th row of one 1T1R cross-point array is , and the simulation conductance value of the variable resistance memory on the j-th column thereof is , the external voltage applied to the variable resistance memory on the i-th row of the other 1T1R cross-point array is , and the simulation conductance value of the variable resistance memory on the j-th column thereof is In the circuit, the state vector X=(x1, x2,..., x n ) T is also updated by the feedback loop naturally each time.

[0019] The beneficial effects of the present application are as follows:

[0020] The application adopts a 1T1R cross-point array, a transimpedance amplifier, a voltage gain circuit and a threshold function module, constructs a closed-loop feedback structure, realizes one-step solution of a QUBO problem, and has good universality. In the circuit, the threshold function module output is connected to the gate of the transistor connected to each column gate of the 1T1R cross-point array, only part of the units in the array are activated in the working state, and the overall power consumption is effectively reduced; at the same time, the gate is a high-impedance node, has excellent signal isolation capability, and is not sensitive to the change of the source-drain voltage, so it is not easily affected by the array read-write disturbance. The whole system constitutes a continuous-time analog computing circuit, and the whole solving process does not need the participation of external digital circuits and does not depend on discrete-time iteration operation. Compared with the traditional method of solving the QUBO problem based on the iteration algorithm on the digital computer, the application has the advantages of high calculation efficiency, low energy consumption, saving of hardware resources and strong parallelism, and is suitable for the QUBO problem solving scene of low power consumption and high speed solution. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a schematic diagram of an existing analog computing circuit for solving a special case QUBO problem.

[0022] Figure 2 It is a schematic diagram of an analog computing circuit structure for solving a positive weight QUBO problem proposed by the application.

[0023] Figure 3 It is Figure 2 a circuit schematic diagram of a specific implementation of the voltage gain circuit in

[0024] Figure 4 It is Figure 2 a circuit schematic diagram of a specific implementation of the threshold function module in

[0025] Figure 5 It is a schematic diagram of an analog computing circuit structure for solving a real weight QUBO problem proposed by the application. DETAILED DESCRIPTION

[0026] In order to more clearly illustrate the purpose, technical scheme and advantages of the application, further detailed description will be made below in combination with the drawings. The description here is only used to explain the application and not to limit the application.

[0027] The application constructs a closed-loop feedback loop based on a 1T1R cross-point array and other analog circuit modules, and realizes an analog computing circuit for one-step solution of a QUBO problem. Specifically, a known weight matrix W=(w ij )∈R n×n and a bias vector λ=(λ1, λ2, …, λ n ) T ∈Rn×1 The analog conductance value of the variable resistance memory of the 1T1R cross-point array and the gain coefficient of the voltage gain circuit are mapped respectively, and the circuit naturally evolves, so that the voltage of each column gate is measured as the output state X∈{0,1} n , and the solution of the QUBO problem is realized.

[0028] Figure 2 A simulation calculation circuit structure diagram for solving a positive weight QUBO problem is provided for the present application. The circuit is composed of a 1T1R cross-point array with a size of n×n, n transimpedance amplifiers, n voltage gain circuits and n threshold function modules, and is used for solving the QUBO problem

[0029]

[0030] In the circuit, the two ends of each row of 1T1R units except the gate end are connected, wherein the end close to the variable resistance memory is connected to a constant external voltage V i (V i The polarity is related to λ i , that is, V i =|V i |*sign(λ i )), the transistor source end is connected to the input end of the corresponding row of transimpedance amplifiers, the transimpedance amplifier output end is connected to the input end of the voltage gain circuit, the voltage gain circuit output end is connected to the input end of the threshold function module, and the threshold function module output end is connected to the gate of the corresponding column of 1T1R units, forming a closed-loop feedback structure. The elements of the weight matrix W are mapped to the analog conductance value G ij of the variable resistance memory in the 1T1R cross-point array, and the mapping rule is

[0031]

[0032] , wherein R i is the feedback resistance value of the i-th row of transimpedance amplifiers; assuming that the supply voltage of the threshold function module is V DD , the threshold voltage is kV DD (0<k<1), when the input end voltage is greater than or equal to kV DD , the output end voltage is V DD ; otherwise, the output is 0, and the gain of the voltage gain circuit is adjusted according to the bias vector λ, so that the gain coefficient of the i-th row of voltage gain circuits is

[0033]

[0034] When the output voltage of the i-th column is V DD , it is considered that x i =1, otherwise it is considered that x i=0. For the current I at the input of the transimpedance amplifier in the i-th row... i If we consider the transistor as an ideal switch and the operational amplifier has virtual short and virtual open characteristics, then...

[0035]

[0036] Where, x j =1 The j-th column transistor is turned on, x j =0 indicates cutoff. The output voltage of the transimpedance amplifier is

[0037]

[0038] The output after voltage gain circuit is

[0039]

[0040] Then we have: When

[0041]

[0042] hour,

[0043]

[0044] otherwise

[0045]

[0046] Based on the circuit structure described above, the system's state vector X = (x1, x2, ..., x...). n ) T Each update is achieved through natural evolution from the feedback loop, and the update rule is: if the i-th row satisfies ∑ j w ij x j ≥λ i Then x i =1; otherwise x i =0. The above rule is equivalent to choosing a variable x at each time step. i And based on the current other variables x j (j≠i) state update x i Make the system energy function:

[0047]

[0048] The state can either decrease or remain unchanged. Specifically, let the current state be X, and if x is changed... i →x′ i Let the new state be X′, then we have:

[0049]

[0050] Since only one component x is changedi Therefore, the difference is completely determined by the weight of the ith row and the component. It can be derived that:

[0051]

[0052] The circuit update rule is to select x that makes the expression non-positive (≤0) i Thus, the energy function is non-increasing. Therefore, in the natural evolution of the physical circuit, the energy function E is always monotonically non-increasing and tends to be stable, thus ensuring convergence to a local optimal state. Considering the noise and other factors in the circuit, it will gradually approach the global optimal state.

[0053] Figure 3 is Figure 2 A circuit schematic diagram of a specific implementation of a voltage gain circuit in the threshold function module, the input end is connected to the variable resistance memory R ′ 1 connected to the inverting input end of the operational amplifier, the non-inverting input end of the operational amplifier is grounded, and the inverting input end and the output end are connected through another variable resistance memory R ′ 2. According to the virtual short and virtual open characteristics of the operational amplifier, there is

[0054]

[0055] That is, the voltage gain coefficient is

[0056]

[0057] By adjusting the resistance values of R ′ 1 and R ′ 2, the programmable configuration of the gain coefficient is realized, which adapts to the needs of different QUBO problems.

[0058] Figure 4 is Figure 2 A circuit schematic diagram of a specific implementation of a threshold function module, which is composed of two CMOS inverters in series. The input end is the gate of the first inverter, the output end is the drain of the second CMOS inverter, and the output is the output voltage of the second inverter. The two NMOS sources are grounded, and the PMOS source is connected to the supply voltage V DD . By adjusting the matching of the NMOS and PMOS threshold voltages and and V DD , the output voltage is V DD when the input voltage is higher than or equal to the threshold voltage kV DD , and the output is 0 when the input is lower than the voltage.

[0059] Figure 5The application discloses a simulation calculation circuit structure schematic diagram for solving a real weight QUBO problem. ij ) can be expressed as the difference of two positive weight matrices and , that is, W=W + -W - . The difference expression of the weight is realized by the opposite polarity of the voltage applied to the variable resistance memory. The applied voltage of the first array is , and the simulation conductance value of the variable resistance memory in the jth column is The applied voltage of the second array is , and the simulation conductance value of the variable resistance memory in the jth column is Because the transistors in the same row of the two arrays are connected to the source, the input current of the transimpedance amplifier is

[0060]

[0061] The output voltage of the transimpedance amplifier is

[0062]

[0063] After the voltage gain circuit, the output is

[0064]

[0065] When

[0066]

[0067] ,

[0068]

[0069] otherwise

[0070]

[0071] According to the above circuit structure, the state vector X=(x1, x2,..., x n ) T is updated by the feedback loop every time, and the update rule is that if the ith row satisfies j w ij x j ≥λ i , x i =1; otherwise x i =0. The update rule is the same as that in the same Figure 2 , so that the QUBO problem of the real weight matrix W is solved.

[0072] The embodiments described above are not intended to define the limits of the present application, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present application, and the scope of protection of the present application is defined by the scope of the claims.

Claims

1. A simulation circuit based on a 1T1R crosspoint array for solving positive-weighted quadratic unconstrained binary optimization (QUBO) problems. This circuit is suitable for solving problems with n state variables (x1, x2, ..., xn). n The positive-weighted QUBO problem, characterized in that, An n-dimensional weight matrix W=(w ij )∈R n×n and a bias vector λ=(λ1, λ2,..., λ n ) T ∈R n×1 are mapped to the analog conductance values of the variable resistance memory of the 1T1R cross-point array and the gain coefficients of the voltage gain circuit, respectively, and the state vector X=(x1, x2,..., x n ) T ∈{0, 1} n The system energy function E is monotonically non-increasing each time the feedback loop in the circuit is naturally evolved and updated, and tends to be stable. After that, the voltage at the gate of each transistor in the 1T1R cross-point array is measured as the output state X, which is a solution that minimizes the energy function E. The circuit structure includes a 1T1R cross-point array of n x n. In the 1T1R cross-point array, all transistor gates in the same column are connected together, all variable resistance memories in the same row are connected together at the end not connected to the transistor, and are connected to an external voltage. The sources of all transistors in the same row are connected together and connected to the negative input end of the transimpedance amplifier corresponding to the row. The positive input end of the transimpedance amplifier on each row is grounded, and the output end is connected to the voltage gain circuit corresponding to the row. A feedback resistor is connected between the inverting input end and the output end of the transimpedance amplifier. The output end of the voltage gain circuit on each row is connected to the threshold function module corresponding to the row. The output end of the threshold function module on each row is connected to the gate of the transistor corresponding to the column of the cross-point array, forming n feedback loops. The transistor gate serves as a control end for closed-loop control of the feedback path. said n-dimensional weight matrix W=(w ij )∈R n×n is mapped to the analog conductance value of the variable resistive memory in said 1T1R cross-point array, and the mapping rule satisfies where G ij and w ij are the conductance value of the variable resistive memory in the i-th row and j-th column of the 1T1R cross-point array and the element of the W matrix, V i and R i are the external voltage connected to the variable resistive memory in the i-th row of the 1T1R cross-point array and the feedback resistance value on the transimpedance amplifier, respectively; The voltage gain circuit is configured to amplify an input voltage, and a gain coefficient is mapped by a bias vector λ, and a mapping rule of the bias vector λ satisfies wherein and λ i respectively represent the gain coefficient of the voltage gain circuit on the i-th row of the 1T1R cross-point array and the i-th component of the bias vector λ, V DD is a supply voltage of the threshold function module, and k is a ratio of a threshold voltage of the threshold function module to the supply voltage. The threshold function module is configured to perform nonlinear mapping on the input voltage, and when the input voltage is higher than or equal to a threshold voltage kV DD , the output voltage is V DD , representing a logic level 1, otherwise the output voltage is 0, representing a logic level 0. On the n feedback loops, the system's state vector X = (x1, x2, ..., xn) n ) T Each update is achieved through natural evolution from the feedback loop, and the update rule is: if the i-th row satisfies ∑ j w ij x j ≥λ i Then x i =1; otherwise x i =0.

2. The analog computing circuit of claim 1, wherein, The voltage gain circuit, the input end is connected to the inverting input end of the operational amplifier through a variable resistance memory, the non-inverting input end of the operational amplifier is grounded, and the inverting input end is connected to the output end through another variable resistance memory.

3. The analog computing circuit of claim 1, wherein, The threshold function module is composed of two CMOS inverters in series, the input end is the gate of the first CMOS inverter, the output end is the drain of the second CMOS inverter, and the output is the output voltage of the second CMOS inverter; the two NMOS sources of the inverter are grounded, and the PMOS source is connected to the power supply voltage V DD ; by adjusting the matching of the threshold voltages of the NMOS and PMOS and and V DD , the output voltage is V DD when the input voltage is higher than or equal to the threshold voltage kV DD , and the output is 0 when the input is lower than the voltage.

4. The analog computing circuit of claim 1, wherein, The external voltage to the variable resistive memory on each row of the 1T1R cross-point array is a constant voltage, V i , whose polarity is related to the bias vector λ i , i.e., V i = |V i | * sign(λ i ).

5. A circuit for solving real-weighted QUBO problems using the analog computing circuit of claim 1, wherein, On the basis of the simulation computing circuit for solving the positive weight QUBO problem, an n×n 1T1R cross-point array with the same structure is added to solve the real weight QUBO problem with n state variables (x1, x2, …, xn). n ) and the original 1T1R cross-point array are connected on the corresponding row of all transistor sources and on the corresponding column of all transistor gates; by splitting the real weight matrix W=(w ij ) into two positive weight matrices and satisfying W=W + -W - The opposite polarity of the external voltage applied to the two 1T1R cross-point arrays realizes the differential representation of the real weight, wherein the external voltage applied to the i-th row of the variable resistive memory of one 1T1R cross-point array is and the analog conductance value of the j-th column of the variable resistive memory thereof is The external voltage applied to the i-th row of the variable resistive memory of the other 1T1R cross-point array is and the analog conductance value of the j-th column of the variable resistive memory thereof is In this circuit, the state vector X=(x1, x2, …, xn) of the system is n T which is also updated by the feedback loop naturally each time.​

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