A triple-junction solar cell capable of stress adjustment and a method for manufacturing the same

Abstract

The present application relates to the technical field of solar cells, in particular to a three-junction solar cell capable of adjusting stress and a preparation method thereof, the three-junction solar cell comprises, from bottom to top, a GaAs substrate, an etching stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell, a second tunnel junction, a strain buffer layer, a bottom cell, a stress adjustment layer and an ohmic contact layer. By growing the stress adjustment layer on the bottom cell layer, the present application can not only compensate the compressive stress generated by the bottom cell layer on the front two junction cell layers and the substrate, but also freely adjust the lattice constant and thickness of the functional layer structure to compensate the stress generated by mismatch, adjust the warping of the epitaxial wafer, and help to improve the production yield and device reliability of the flip-chip.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a stress-adjustable triple-junction solar cell and its fabrication method. Background Technology

[0002] Gallium arsenide triple-junction solar cells, with their superior photoelectric conversion efficiency and reliability, have become the core physical power source for space applications such as satellites, spacecraft, and space stations. However, traditional GaInP / GaInAs / Ge triple-junction cells have significant performance bottlenecks: the bandgap design of the top, middle, and bottom junctions (such as GaInP / GaInAs / Ge) must meet lattice matching, which limits the optimized absorption of the solar spectrum by each sub-cell, resulting in wasted current; the bottom cell uses a germanium (Ge) sub-cell with a bandgap of only 0.67 eV, and its contribution to voltage is significantly lower than that of the other two junctions (GaInP and GaInAs). NREL's proposed GaInP / GaAs / InGaAs flip-chip structure, through bandgap optimization and process innovation, breaks through the efficiency bottleneck of traditional Ge bottom cells, providing a higher-performance and lighter-weight solution for space photovoltaic systems.

[0003] While growing GaInP / GaAs / In 0.3 Ga 0.7 When GaAs flip-chip triple-junction solar cells are manufactured, the lattice mismatch between the third and second GaAs junctions reaches 2.1%, causing stress in the epitaxial material and inducing warpage. This warpage increases the difficulty of subsequent chip fabrication and packaging processes. The current common practice is to increase the maximum In composition layer thickness during the growth of the strain buffer layer to compensate for the In content. 0.3 Ga 0.7 Stress caused by lattice mismatch in As cells can improve warpage. However, excessive thickness of the In-maximum composition layer can hinder the growth of In. 0.3 Ga 0.7 Excessive warpage of the epitaxial wafer during solar cell formation affects the quality of the epitaxial crystal, leading to performance degradation.

[0004] Therefore, it is of great significance to develop a flip-chip triple-junction solar cell that can adjust the stress of the epitaxial layer, thereby improving the warpage and lattice quality of the epitaxial wafer. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a stress-adjustable triple-junction solar cell and its fabrication method, aiming to freely adjust stress without affecting the functional layer structure, thereby improving the crystal quality and production capacity of flip-chip cells and broadening their application scope.

[0006] The purpose of this invention is to provide a triple-junction solar cell capable of adjusting stress, wherein the triple-junction solar cell comprises, from bottom to top, a GaAs substrate, an etching stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell, a second tunnel junction, a strain buffer layer, a bottom cell, a stress adjustment layer, and an ohmic contact layer.

[0007] The stress-adjusting layer is grown in the form of compositional step change, and its lattice constant transitions from matching the bottom cell to a set lattice constant.

[0008] In this technical solution, by introducing a stress-adjusting layer into the bottom cell structure, the lattice constant and thickness can be adjusted to compensate for the stress caused by mismatch, improve the warpage of the epitaxial wafer, and the stress-adjusting layer is epitaxially grown after the bottom cell is completed, so it does not affect the crystal quality of the bottom cell material and has no impact on performance. At the same time, the introduced stress-adjusting layer can freely adjust the stress without affecting the functional layer structure, which helps to improve the production capacity of flip-chip and broaden the application range.

[0009] Furthermore, the stress-adjusting layer, from bottom to top, consists of: In x1 GaAs, In y1 In this GaAs triple junction solar cell, 0.29 ≤ x1 < 0.32 and 0.23 < y1 ≤ 0.27. In this technical solution, because the lattice constant of the third junction layer (InGaAs) in the flip-chip triple junction gallium arsenide solar cell is 5%-7% higher than that of the first two junctions (GaInP / GaAs) and the GaAs substrate, the lattice expansion of the third junction layer during epitaxial growth will transfer compressive strain through the interface, causing elastic deformation of the first two junction layers. Therefore, growing a stress-adjusting layer with a small lattice constant on the third junction, by reducing the In composition y1 or increasing its thickness, increases the tensile strain generated on the third junction. This can compensate for the compressive strain generated by the third junction on the first two junction layers and the substrate, reducing epitaxial wafer warpage, improving epitaxial wafer flatness, and reducing the processing difficulty of high-precision processes in chip manufacturing and packaging, which is beneficial to improving production yield and device reliability.

[0010] Furthermore, the material of the corrosion stop layer is one or a combination of GaInP, AlInP, and AlGaInP; the material of the contact layer is GaAs.

[0011] Furthermore, the top cell is made of (Al)GaInP with a bandgap of 1.80 eV-1.95 eV; the middle cell is made of (In)GaAs with a bandgap of 1.37 eV-1.42 eV; and the bottom cell is made of In. x2 GaAs has a bandgap of 0.90 eV-1.1 eV and 0.29 ≤ x2 < 0.32.

[0012] Furthermore, the first tunnel junction is N ++ GaInP / P ++ AlGaAs structure, where N ++ The dopants in GaInP are one or more combinations of Te, Se, and Si; P ++ AlGaAs is doped with one or more combinations of Mg, Zn, and C.

[0013] Furthermore, the second tunneling junction is N. ++ GaAs / P ++ GaAs structure, where N ++ GaAs dopants are one or more combinations of Te, Se, and Si; P ++ The dopants in GaAs are one or more combinations of Mg, Zn, and C.

[0014] Furthermore, the strain buffer layer is made of InAlGaAs with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopant is at least one of Te, Se, and Si; the ohmic contact layer is made of In. y1 GaAs, doping concentration greater than 2×10 18 / cm 3 The dopant is at least one of Zn, Mg and C, and the In composition is consistent with that of the stress-adjusting layer.

[0015] This invention also provides a method for fabricating a triple-junction solar cell capable of adjusting stress, specifically including the following steps:

[0016] S1. On a GaAs substrate, an etch stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell, and a second tunnel junction are epitaxially grown sequentially.

[0017] S2. A strain buffer layer is grown on the second tunnel junction;

[0018] S3. Growing the bottom cell on the strain buffer layer;

[0019] S4. A stress-regulating layer is grown on the bottom cell;

[0020] S5. An ohmic contact layer is grown on the stress-adjusting layer.

[0021] Furthermore, in S2, the strain buffer layer sequentially comprises 210 nm In... 0.05 Al x3 GaAs, 210nm In 0.1 Al x3 GaAs, 210nm In 0.15 Al x3GaAs, 210nm In 0.2 Al x3 GaAs, 210nm In 0.25 Al x3 GaAs, 210nm In 0.3 Al x3 GaAs, 210nm In 0.36 Al x3 GaAs, 500nm In 0.3 Al x3 GaAs, where 0.1 < x3 ≤ 0.6. In this technical solution, by using a composition-gradient growth method, the lattice can be gradually enlarged to the bottom cell lattice, ensuring the material quality of the bottom cell growth.

[0022] Furthermore, the lattice constant of the ohmic contact layer matches the lattice constant of the stress-adjusting layer.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] Since flip-chip substrates include PI, Cu, and Si, and electrode materials include Au, Ge, Pd, and Ag, the stress generated when these different substrates and electrode materials bond with the epitaxial layer varies significantly. Furthermore, in flip-chip triple-junction gallium arsenide solar cells, the lattice constant of the third junction layer is 5%-7% higher than that of the first two junctions and the GaAs substrate. During epitaxial growth, the lattice expansion of the third junction transfers compressive strain through the interface, causing elastic deformation of the first two junction layers. Therefore, this invention addresses this by growing a stress-regulating layer with a small lattice constant on the third junction layer. This not only compensates for the compressive strain generated by the third junction layer on the first two junction layers and the substrate, but also allows for free adjustment of its lattice constant and thickness without affecting the functional layer structure. This compensates for stress caused by mismatch, improves epitaxial wafer warpage, and helps increase the production yield and device reliability of flip-chips, thus broadening their application range. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the triple-junction solar cell of the present invention.

[0026] Explanation of the labels in the diagram:

[0027] 1. GaAs substrate; 2. Etching stop layer; 3. Contact layer; 4. Top cell; 5. First tunnel junction; 6. Middle cell; 7. Second tunnel junction; 8. Strain buffer layer; 9. Bottom cell; 10. Stress adjustment layer; 11. Ohmic contact layer. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] In the description of this application, it should be understood that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application.

[0030] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0031] Please see Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] An embodiment of the present invention provides a triple-junction solar cell capable of adjusting stress, the structural schematic diagram of which is shown below. Figure 1 As shown, the triple junction solar cell consists of, from bottom to top, a GaAs substrate 1, an etching stop layer 2, a contact layer 3, a top cell 4, a first tunnel junction 5, a middle cell 6, a second tunnel junction 7, a strain buffer layer 8, a bottom cell 9, a stress adjustment layer 10, and an ohmic contact layer 11.

[0033] In some specific embodiments, the corrosion stop layer material is one or a combination of GaInP, AlInP, and AlGaInP.

[0034] In some specific embodiments, the top cell is made of (Al)GaInP with a bandgap of 1.80 eV-1.95 eV; the middle cell is made of (In)GaAs with a bandgap of 1.37 eV-1.42 eV; and the bottom cell is made of In... x2 GaAs has a bandgap of 0.90eV-1.1eV and 0.29≤x2<0.32; wherein the top cell and the middle cell are connected by a first tunnel junction, and the middle cell and the bottom cell are connected by a second tunnel junction.

[0035] In some specific embodiments, the first tunnel junction is N ++ GaInP / P ++ AlGaAs, where N ++ The dopants in GaInP are one or more combinations of Te, Se, and Si; P ++ AlGaAs is doped with one or more combinations of Mg, Zn, and C.

[0036] In some specific embodiments, the second tunnel junction is N. ++ GaAs / P ++ GaAs, where N ++ GaAs dopants are one or more combinations of Te, Se, and Si; P ++ The dopants in GaAs are one or more combinations of Mg, Zn, and C.

[0037] In some specific embodiments, the stress-regulating layer is grown using a compositional step transition, with the lattice constant transitioning from matching the bottom cell to a predetermined lattice constant, from bottom to top as follows: In x1 GaAs, In y1 The composition is GaAs, where 0.29≤x1<0.32 and 0.23<y1≤0.27.

[0038] In some specific embodiments, the material of the ohmic contact layer is In. y1 GaAs with a thickness of 200 nm, where 0.23 < y1 ≤ 0.27.

[0039] Some embodiments of the present invention provide a method for fabricating a stress-adjustable triple-junction solar cell, specifically including the following steps:

[0040] S1. On a GaAs substrate, an epitaxial growth is performed sequentially of an etching stop layer, a contact layer, a top cell, a first tunneling junction, a middle cell, and a second tunneling junction. Specifically, MOCVD (metal-organic chemical vapor deposition) is used for growth. The contact layer is made of GaAs, the etching stop layer is made of one or more of GaInP, AlInP, and AlGaInP, the top cell is made of (Al)GaInP, and the bandgap is 1.80 eV-1.95 eV. The first tunneling junction is made of N-type GaAs. ++ GaInP / P ++ AlGaAs, where N ++ The dopants in GaInP are one or more combinations of Te, Se, and Si; P ++ The dopants in AlGaAs are one or more combinations of Mg, Zn, and C; the material of the mid-cell is (In)GaAs with a band gap of 1.37 eV-1.42 eV; the second tunnel junction is N. ++ GaAs / P ++ GaAs, where N ++ GaAs dopants are one or more combinations of Te, Se, and Si; P ++ The dopants in GaAs are one or more combinations of Mg, Zn, and C.

[0041] S2. A strain buffer layer is grown on the second tunneling junction; specifically, 210 nm In layers are sequentially grown on the second tunneling junction. 0.05 Al x3 GaAs, 210nm In 0.1 Al x3 GaAs, 210nm In 0.15 Al x3 GaAs, 210nm In 0.2 Al x3 GaAs, 210nm In 0.25 Al x3 GaAs, 210nm In 0.3 Al x3 GaAs, 210nm In 0.36 Al x3 GaAs, 500nm In 0.3 Al x3 GaAs is used to form a strain buffer layer, with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopant is at least one of Te, Se and Si, wherein 0.1 < x3 ≤ 0.6.

[0042] S3. A bottom cell is grown on the strain buffer layer; specifically, the material of the bottom cell is In. x2GaAs has a bandgap of 0.90 eV-1.1 eV and 0.29 ≤ x2 < 0.32.

[0043] S4. A stress-regulating layer is grown on the bottom cell; specifically, the stress-regulating layer adopts a compositional step transition, with the lattice constant transitioning from matching the bottom cell to a predetermined lattice constant, in the following order from bottom to top: In x1 GaAs, In y1 Composed of GaAs, with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopant is at least one of Zn, Mg, and C, where 0.29 ≤ x1 < 0.32 and 0.23 < y1 ≤ 0.27. The warpage of the epitaxial wafer can be adjusted by changing the In composition and thickness of the stress-adjusting layer. This layer grows after the bottom cell has been fully grown, without affecting the crystal quality of the bottom cell material or its performance.

[0044] S5. An ohmic contact layer is grown on the stress-adjusting layer, specifically, the material of the ohmic contact layer is In. y1 GaAs, doping concentration greater than 2×10 18 / cm 3 The dopant is at least one of Zn, Mg and C, and the In composition and stress-regulating layer are consistent to ensure lattice matching.

[0045] To further illustrate the present invention, a method for preparing a stress-adjustable triple-junction solar cell provided by the present invention will be described in detail below with reference to specific embodiments.

[0046] Example 1

[0047] A method for fabricating a stress-adjustable triple-junction solar cell specifically includes the following steps:

[0048] Specifically, the following steps are included:

[0049] S1. Using MOCVD technology, the etching stop layer GaInP, the contact layer GaAs, the top cell (Al)GaInP, and the first tunnel junction N are epitaxially grown sequentially on a GaAs substrate. ++ GaInP / P ++ AlGaAs, mid-cell (In)GaAs, second tunnel junction N ++ GaAs / P ++ GaAs; where N ++ The dopant for GaInP is Te; P ++ The dopants in AlGaAs are Mg and N. ++ The dopants in GaAs are Te and P. ++ The dopant in GaAs is Mg.

[0050] S2. 210 nm In atoms are sequentially grown on the second tunnel junction. 0.05 Al 0.2 GaAs, 210nm In 0.1 Al 0.2 GaAs, 210nm In 0.15 Al 0.2 GaAs, 210nm In 0.2 Al 0.2 GaAs, 210nm In 0.25 Al 0.2 GaAs, 210nm In 0.3 Al 0.2 GaAs, 210nm In 0.36 Al 0.2 GaAs, 500nm In 0.3 Al 0.2 GaAs is used to form a strain buffer layer, with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopant is Te.

[0051] S3. Growing the bottom cell In on the strain buffer layer 0.3 GaAs has a bandgap of 0.90 eV-1.1 eV.

[0052] S4. A stress-regulating layer is grown on the bottom cell, consisting of, from bottom to top: 300nm In... 0.3 GaAs, 400nm In 0.25 Composed of GaAs, with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopant is Zn.

[0053] S5. Growing a 200nm ohmic contact layer In on the stress-adjusting layer. 0.25 GaAs, doping concentration greater than 2×10 18 / cm 3 The dopant is Zn.

[0054] Example 2

[0055] A method for fabricating a stress-adjustable triple-junction solar cell specifically includes the following steps:

[0056] Specifically, the following steps are included:

[0057] S1. Using MOCVD technology, an etching stop layer AlInP, a contact layer GaAs, a top cell (Al)GaInP, and a first tunnel junction N are sequentially epitaxially grown on a GaAs substrate. ++ GaInP / P ++AlGaAs, mid-cell (In)GaAs, second tunnel junction N ++ GaAs / P ++ GaAs; where N ++ GaInP is doped with a combination of Se and Si; P ++ AlGaAs is doped with a combination of Zn and C; N ++ GaAs is doped with a combination of Se and Si; P ++ GaAs is doped with a combination of Zn and C.

[0058] S2. 210 nm In atoms are sequentially grown on the second tunnel junction. 0.05 Al 0.6 GaAs, 210nm In 0.1 Al 0.6 GaAs, 210nm In 0.15 Al 0.6 GaAs, 210nm In 0.2 Al 0.6 GaAs, 210nm In 0.25 Al 0.6 GaAs, 210nm In 0.3 Al 0.6 GaAs, 210nm In 0.36 Al 0.6 GaAs, 500nm In 0.3 Al 0.6 GaAs is used to form a strain buffer layer, with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopants are Se and Si.

[0059] S3. Growing the bottom cell In on the strain buffer layer 0.31 GaAs has a bandgap of 0.90 eV-1.1 eV.

[0060] S4. A stress-regulating layer is grown on the bottom cell, consisting of, from bottom to top: 300nm In... 0.31 GaAs, 400nm In 0.26 Composed of GaAs, with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopants are Mg and C.

[0061] S5. Growing a 200nm ohmic contact layer In on the stress-adjusting layer. 0.26 GaAs, doping concentration greater than 2×10 18 / cm 3 The dopants are Mg and C.

[0062] In summary, by growing a stress-adjusting layer with a small lattice constant on the bottom cell layer, this invention can not only compensate for the compressive strain generated by the bottom cell layer on the first two junction cell layers and the substrate, but also freely adjust its lattice constant and thickness to compensate for the stress caused by mismatch without affecting the functional layer structure, thereby adjusting the warpage of the epitaxial wafer and helping to improve the production yield and device reliability of flip-chip.

[0063] Finally, it should be emphasized that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A triple-junction solar cell capable of adjusting stress, characterized in that, The triple junction solar cell, from bottom to top, consists of a GaAs substrate, an etching stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell, a second tunnel junction, a strain buffer layer, a bottom cell, a stress adjustment layer, and an ohmic contact layer. The stress-adjusting layer is grown in the form of compositional step change, and its lattice constant transitions from matching the bottom cell to a set lattice constant. The stress-regulating layers, from bottom to top, are: In x1 GaAs, In y1 GaAs; The material of the ohmic contact layer is In. y1 GaAs, doping concentration greater than 2×10 18 / cm 3 The dopant is at least one of Zn, Mg and C; Where 0.29≤x1<0.32, 0.23<y1≤0.27; The strain buffer layer is made of InAlGaAs with a doping concentration greater than 1×10⁻⁶. 18 / cm 3 The dopant is at least one of Te, Se and Si; The strain buffer layer sequentially comprises 210nm In... 0.05 Al x3 GaAs, 210nm In 0.1 Al x3 GaAs, 210nm In 0.15 Al x3 GaAs, 210nm In 0.2 Al x3 GaAs, 210nm In 0.25 Al x3 GaAs, 210nm In 0.3 Al x3 GaAs, 210nm In 0.36 Al x3 GaAs, 500nm In 0.3 Al x3 GaAs, where 0.1 < x3 ≤ 0.

6.

2. A triple-junction solar cell capable of adjusting stress according to claim 1, characterized in that, The corrosion stop layer is made of one or a combination of GaInP, AlInP, and AlGaInP; the contact layer is made of GaAs.

3. A triple-junction solar cell capable of adjusting stress according to claim 1, characterized in that, The top cell is made of (Al)GaInP with a bandgap of 1.80 eV-1.95 eV; the middle cell is made of (In)GaAs with a bandgap of 1.37 eV-1.42 eV; and the bottom cell is made of In. x2 GaAs has a bandgap of 0.90 eV-1.1 eV and 0.29 ≤ x2 < 0.

32.

4. A triple-junction solar cell capable of adjusting stress according to claim 1, characterized in that, The first tunnel junction is N ++ GaInP / P ++ AlGaAs structure, where N ++ The dopants in GaInP are one or more combinations of Te, Se, and Si; P ++ AlGaAs is doped with one or more combinations of Mg, Zn, and C.

5. A triple-junction solar cell capable of adjusting stress according to claim 1, characterized in that, The second tunnel junction is N ++ GaAs / P ++ GaAs structure, where N ++ GaAs dopants are one or more combinations of Te, Se, and Si; P ++ The dopants in GaAs are one or more combinations of Mg, Zn, and C.

6. A method for fabricating a stress-adjustable triple-junction solar cell according to any one of claims 1-5, characterized in that, Specifically, the following steps are included: S1. On a GaAs substrate, an etch stop layer, a contact layer, a top cell, a first tunnel junction, a middle cell, and a second tunnel junction are epitaxially grown sequentially. S2. A strain buffer layer is grown on the second tunnel junction; S3. Growing the bottom cell on the strain buffer layer; S4. A stress-regulating layer is grown on the bottom cell; S5. An ohmic contact layer is grown on the stress-adjusting layer.

7. A method for fabricating a stress-adjustable triple-junction solar cell according to claim 6, characterized in that, The lattice constant of the ohmic contact layer matches the lattice constant of the stress-adjusting layer.

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