Display device and electronic device including the same

Abstract

The disclosure relates to a display device capable of repairing data lines and an electronic device including the display device. The display device includes: a data line disposed on a substrate; a passivation layer disposed on the data line; the via hole layer is arranged on the passivation layer; a shield line disposed on the via layer and overlapping the data line; a light-emitting element layer disposed on the shield line; a first hole penetrating through the hole layer and overlapping one side of the data line; and a second hole penetrating through the hole layer and overlapping the other side of the data line.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0059889, filed on May 7, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Disclosed are a display apparatus capable of repairing a data line and an electronic apparatus including the same. BACKGROUND

[0003] An organic light emitting diode (OLED) display has a self-light emitting characteristic, and unlike a liquid crystal display (LCD), does not require a separate light source, thereby reducing thickness and weight. The OLED display exhibits high quality characteristics such as low power consumption, high brightness, and high response speed, and thus has been considered as a next generation display apparatus for TVs, monitors, and portable electronic apparatuses.

[0004] It will be appreciated that the Background section is intended to provide a context for the technology. However, the Background section can also include ideas, concepts or recognitions not yet known or appreciated by persons of ordinary skill in the pertinent art(s) as of the respective effective filing date of the subject disclosure. SUMMARY

[0005] Disclosed are a display apparatus capable of repairing a data line.

[0006] However, the disclosed aspects are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings.

[0007] According to an aspect of the disclosure, a display apparatus can include a data line disposed on a substrate, a passivation layer disposed on the data line, a via layer disposed on the passivation layer, a shield line disposed on the via layer and overlapping the data line, an light emitting element layer disposed on the shield line, a first hole penetrating the via layer and overlapping one side of the data line, and a second hole penetrating the via layer and overlapping the other side of the data line.

[0008] The shield line can receive direct current (DC) power.

[0009] The shield line can be disposed in the first hole and the second hole.

[0010] The light emitting element layer can include an anode electrode and a pixel definition layer disposed on the anode electrode, and the first hole and the second hole can not overlap the anode electrode.

[0011] The first hole and the second hole can overlap the pixel definition layer.

[0012] The data line can include first and second sub-data lines separated from each other, and facing ends of the first and second sub-data lines can be disposed between the first and second holes in a plan view.

[0013] The shield line can include a repair electrode, a first sub-shield line, and a second sub-shield line separated from each other.

[0014] The repair electrode can overlap the facing ends of the first and second sub-data lines.

[0015] The first hole can be disposed between an end of the repair electrode facing the first sub-shield line and an end of the first sub-data line facing the second sub-data line in a plan view, and the second hole can be disposed between another end of the repair electrode facing the second sub-shield line and an end of the second sub-data line facing the first sub-data line in a plan view.

[0016] Each of the first and second holes can further penetrate the passivation layer.

[0017] One side of the repair electrode can be connected to the first sub-data line through the first hole, and the other side of the repair electrode can be connected to the second sub-data line through the second hole.

[0018] The repair electrode can receive a data voltage from the data line, and each of the first and second sub-shield lines can receive DC power.

[0019] According to an aspect disclosed, a display device can include a data line disposed on a substrate, a passivation layer disposed on the data line, a via layer disposed on the passivation layer, a shield line disposed on the via layer and overlapping the data line, a light emitting element layer disposed on the shield line, a first hole penetrating the via layer and disposed between one side of the data line and the shield line, and a second hole penetrating the via layer and disposed between the other side of the data line and the shield line.

[0020] The shield line can receive direct current (DC) power.

[0021] The shield line can be disposed in the first and second holes.

[0022] The light emitting element layer can include an anode electrode and a pixel definition layer disposed on the anode electrode, and the first and second holes do not overlap the anode electrode.

[0023] The first and second holes can overlap the pixel definition layer.

[0024] The data line can include first and second sub-data lines separated from each other, and facing ends of the first and second sub-data lines can be disposed between the first and second holes in a plan view.

[0025] The shield line can include a repair electrode, a first sub-shield line, and a second sub-shield line which are separated from each other.

[0026] The repair electrode can overlap with facing end portions of the first and second sub-data lines.

[0027] The first hole can be disposed between an end portion of the repair electrode facing the first sub-shield line and an end portion of the first sub-data line facing the second sub-data line in a plan view, and the second hole is disposed between another end portion of the repair electrode facing the second sub-shield line and an end portion of the second sub-data line facing the first sub-data line in the plan view.

[0028] Each of the first and second holes can further penetrate the passivation layer.

[0029] One side of the repair electrode can be connected to the first sub-data line through the first hole, and the other side of the repair electrode is connected to the second sub-data line through the second hole.

[0030] The repair electrode can receive a data voltage from the data line, and each of the first and second sub-shield lines receives DC power.

[0031] According to an aspect of the disclosure, an electronic device includes a display device including a screen, wherein the display device can include: a data line disposed on a base; a passivation layer disposed on the data line; a via layer disposed on the passivation layer; a shield line disposed on the via layer and overlapping with the data line; a light emitting element layer disposed on the shield line; a first hole penetrating the via layer and overlapping with one side of the data line; and a second hole penetrating the via layer and overlapping with the other side of the data line.

[0032] According to the foregoing and other embodiments disclosed, the data line can be repaired.

[0033] It should be noted that the effects of the disclosure are not limited to the above-mentioned effects, and other effects of the disclosure will be apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0034] The above and other aspects and features of the disclosure will become more apparent by describing in detail the embodiments thereof with reference to the attached drawings, in which: Figure 1 is a schematic plan view illustrating a display device according to an embodiment; Figure 2 is a schematic plan view illustrating a display panel of Figure 1 ; Figure 3 is a schematic view illustrating an equivalent circuit of a pixel according to an embodiment; Figure 4 is a diagram illustrating an array of a display device according to an embodiment; Figure 5 is a schematic cross-sectional view taken along the line XI-XI' of Figure 4 ; Figure 6 is a diagram showing an array of display devices according to an embodiment; Figure 7 is a schematic cross-sectional view taken along the line XII-XII' of Figure 6 ; Figures 8 to 13 is a schematic cross-sectional view for explaining a method of manufacturing a display device according to an embodiment; Figure 14 is a block diagram of an electronic device according to an embodiment; and Figure 15 , Figure 16 and Figure 17 are schematic diagrams of electronic devices according to various embodiments. DETAILED DESCRIPTION

[0035] The advantages and features of the disclosure and methods for achieving them will become apparent from the following description with reference to the accompanying drawings. However, the disclosure is not limited to the embodiments disclosed herein but can be implemented in various different ways. The embodiments are provided so as to make the disclosure thorough and to fully convey the scope of the disclosure to those skilled in the art. It will be noted that the scope of the disclosure is also defined by the claims.

[0036] As used herein, the phrase "element A is on element B" means that element A can be directly on element B and / or element A can be indirectly on element B via another element C. Throughout the description, like reference numerals refer to like elements. The figures given in the drawings are illustrative rather than limiting in terms of graphics, size, proportion, angle, number.

[0037] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0038] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" can be understood to mean "A, B, or A and B." The terms "and" and "or" can be used in the conjunctive or disjunctive sense and can be understood to be equivalent to "and / or."

[0039] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one of the group consisting of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0040] Although terms such as first, second, etc., are used to arbitrarily distinguish elements described by such terms, these terms are not necessarily intended to indicate the time priority or other priority of such elements. These terms are used to distinguish one element from another. Therefore, as used herein, a first element may be a second element within the scope of the disclosed art.

[0041] The term “overlay” or “overlayed” means that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term “overlay” may include layer, stack, facing or oriented, extending over, covering or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art.

[0042] The terms "facing" and "oriented" indicate that the first element can be directly or indirectly opposite the second element. When a third element is placed between the first and second elements, the first and second elements can be understood as being indirectly opposite each other, although they are still facing each other.

[0043] When an element is described as “not overlapping” with another element or “not overlapping” with another element, this may include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable terminology as will be understood and appreciated by one of ordinary skill in the art.

[0044] When the terms “comprising,” “including,” “having,” and / or variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0045] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable deviation of the stated value as determined by one of ordinary skill in the art, taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0046] Unless otherwise defined or implied herein, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0047] It will be understood that when an element (or components, region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, it can be directly on, directly connected to or directly coupled to the mentioned other element or intervening elements can be present.

[0048] It will be understood that the terms "connected" or "coupled" can include physical or electrical connections or physical or electrical couplings.

[0049] Features of various embodiments can be combined partially or wholly. As will be clear to those skilled in the art, various interlocks and operations are technically possible. Various embodiments can be practiced individually or in combination.

[0050] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0051] Figure 1 FIG. 1 is a schematic plan view showing a display device 100 according to an embodiment. Figure 2 FIG. 2 is a schematic plan view showing a display panel 110 of FIG. 1. Figure 1

[0052] Referring to FIGS. 1 and 2, Figure 1 and Figure 2 The display device 100, as a device for displaying a video or a still image, can be used as a display screen of various products such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book reader, a portable multimedia player (PMP), a navigation device, an ultra-mobile PC (UMPC), and a television (TV), a laptop computer, a monitor, a billboard, and an Internet of Things (IoT) device. These are presented as examples, and the display device 100 can also be applied to other electronic devices.

[0053] ​In an embodiment, the display device 100 can be a light emitting display device such as an organic light emitting display device including an organic light emitting diode (OLED), a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, or a super small light emitting display device including a super small light emitting diode (LED) such as a micro LED or a nano LED, but the disclosure is not limited thereto. By way of example, the display device 100 can be another type of display device other than a light emitting display device. Hereinafter, an embodiment in which the display device 100 is a light emitting display device (e.g., an organic light emitting display device) will be disclosed.

[0054] The display device 100 can include a display panel 110 including pixels PX and first and second driving units 120 and 130 supplying driving signals to the pixels PX. The display device 100 can include additional features. For example, the display device 100 can further include a power supply unit for supplying a power supply voltage to the pixels PX, the first and second driving units 120 and 130, and a timing controller for controlling operations of the first and second driving units 120 and 130.

[0055] The display panel 110 can include a display area DA and a non-display area NDA. The display area DA can be an area in which an image is displayed by including the pixels PX. For example, the display area DA can include a pixel area in which the respective pixels PX are disposed. The non-display area NDA is a remaining area other than the display area DA, and an image can not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA can be located or disposed around the display area DA and can surround the display area DA or can be adjacent to the display area DA.

[0056] Figure 1 And Figure 2 A first direction D1, a second direction D2, and a third direction D3 are defined. In an embodiment, the first direction D1 can be a horizontal direction of the display panel 110, the second direction D2 can be a vertical direction of the display panel 110, and the third direction D3 can be a thickness direction of the display panel 110.

[0057] In an embodiment, the display panel 110 can have a rectangular shape in a plan view. Figure 1 And Figure 2 The display panel 110 is illustrated as having a horizontal length longer than a vertical length, but the shape of the display panel 110 is not particularly limited. For example, the display panel 110 can have a vertical length longer than a horizontal length thereof, or the display panel 110 can have a square shape, etc. The display panel 110 can include an angled corner portion or a rounded corner portion.

[0058] The planar shape of the display panel 110 is not limited to the illustrated rectangular shape, and various other shapes can be applied. For example, the display panel 110 can have another polygonal shape that is not rectangular, a circular shape, an elliptical shape, or an irregular shape.

[0059] In an embodiment, the display panel 110 can be substantially flat on a plane defined by the first direction D1 and the second direction D2, and can have a uniform thickness in the third direction D3. By way of example, the display panel 110 can be provided in a three-dimensional (3D) shape having a curved surface.

[0060] The display panel 110 can be provided as a substantially non-deformable rigid panel, or can be provided as a flexible panel that can be deformed (such as foldable, bendable, or rollable) in at least a portion thereof. The display panel 110 can be provided in the display device 100 in a non-curved state or in a curved state in some portions thereof.

[0061] The display panel 110 can include a substrate SUB and pixels PX provided on the substrate SUB. The pixels PX can be arranged or provided in a display area DA on the substrate SUB.

[0062] The substrate SUB, which is a base member for manufacturing or providing the display panel 110, can form a base surface of the display panel 110. The substrate SUB can include a display area DA and a non-display area NDA around the display area DA.

[0063] The display area DA can have various shapes. For example, the display area DA can have a rectangular shape, a polygonal shape that is not rectangular, a circular shape, an elliptical shape, an irregular shape, or another shape. In an embodiment, the display area DA can have a shape corresponding to the shape of the display panel 110.

[0064] In the display area DA, the pixels PX can be provided and / or arranged or disposed. For example, the display area DA can include a pixel area in which the respective pixels PX are arranged or disposed.

[0065] In an embodiment, the display device 100 can be a light emitting display device, and each of the pixels PX can include a light emitting element positioned or disposed in each emission area and a pixel circuit connected to the light emitting element. As used herein, the term "connected" can encompass both electrical and / or physical connections. Each pixel circuit can include a transistor (e.g., a transistor including at least one switching transistor and a driving transistor that generates a driving current corresponding to a data signal) and at least one capacitor (e.g., a storage capacitor).

[0066] The non-display area NDA can include a pad area PA provided with pads (or referred to as "bond pads" or "bonding pads") PD. In an embodiment, the non-display area NDA can further include a driving circuit area located or provided at least one side of the display area DA. In the non-display area NDA, the pads PD, wirings, and / or at least one driving unit can be provided.

[0067] In the driving circuit area, at least one driving unit or a part of a driving unit for driving the pixels PX can be provided. For example, in the driving circuit area on the substrate SUB, circuit elements (e.g., driving transistors and driving capacitors constituting a stage circuit of the first driving unit 120) constituting the first driving unit 120 can be provided. In an embodiment, the circuit elements of the first driving unit 120 can be formed in the display panel 110 together with the pixels PX. In an embodiment, the driving transistors provided in the first driving unit 120 can have substantially the same type and / or structure (or similar type and / or structure) as the transistors provided to the pixels PX, and can be formed at the same time as the transistors of the pixels PX.

[0068] The pads PD can be arranged or provided in the pad area PA. At least one circuit board 140 can be arranged or provided and / or bonded on the pad area PA. In an embodiment, the circuit boards 140 connected to different pads PD can be provided in the pad area PA. The pads PD can include signal pads and power pads for transmitting driving signals and power voltages for driving the pixels PX and / or the first driving unit 120 to the inside of the display panel 110.

[0069] The first driving unit 120 and the second driving unit 130 can generate driving signals for controlling the operation timing and luminance of the pixels PX, and can supply the driving signals to the pixels PX. For example, the first driving unit 120 can be a gate driving unit including a scan driver, and can be connected to the pixels PX through a corresponding gate line. The first driving unit 120 can supply a gate signal (e.g., a scan signal and / or a control signal for controlling the driving timing of the pixels PX including an emission control signal) to the pixels PX. The second driving unit 130 can be a data driving unit including a source driving circuit, and can be connected to the pixels PX through a corresponding data line. The second driving unit 130 can supply a data signal to the pixels PX.

[0070] In an embodiment, at least one of the first driving unit 120 and the second driving unit 130 or a part of the first driving unit 120 and the second driving unit 130 can be embedded in the display panel 110. For example, the first driving unit 120 or a part of the first driving unit 120 can be provided on the substrate SUB of the display panel 110, and can be provided and / or formed in the non-display area NDA.

[0071] In Figure 1 , the first driving unit 120 is illustrated as being formed in one side or side portion of the display area DA (e.g., in a portion of the non-display area NDA on the right side of the display area DA), but the disclosure is not limited thereto. One of the first driving unit 120 and the second driving unit 130 (e.g., the first driving unit 120) can be located or disposed in the other side of the display area DA (e.g., in a portion of the non-display area NDA on the left side of the display area DA), or can be located or disposed in both sides of the display area DA (e.g., in portions of the non-display area NDA on both the left and right sides of the display area DA). By way of example, a portion of the first driving unit 120 can be located or disposed in the non-display area NDA, and another portion of the first driving unit 120 can be located or disposed in a non-emission area (e.g., an area between emission areas of the pixels PX) in the display area DA.

[0072] In an embodiment, another driving unit or a portion of another driving unit can be disposed or formed outside the display panel 110 and electrically connected to the display panel 110. For example, the second driving unit 130 can be implemented with an integrated circuit (IC) chip and disposed on a circuit board 140 electrically connected with the pixels PX of the display panel 110. The second driving unit 130 can be implemented as at least one IC chip and mounted in the non-display area NDA of the display panel 110.

[0073] The circuit board 140 can be connected to the display panel 110 through the pad PD. In an embodiment, the circuit board 140 can be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film (COF), but the disclosure is not limited thereto. In an embodiment, the circuit board 140 can be connected to a timing controller and / or a power supply unit through a circuit board or a connector, etc.

[0074] Figure 3 is a schematic diagram illustrating an equivalent circuit of the pixel PX according to an embodiment. For example, Figure 3 A pixel PX including a light emitting element ED of the display apparatus 100 is illustrated. However, the type and / or structure of the pixel PX included in the display apparatus 100 is not particularly limited and can vary.

[0075] Referring to Figure 1 , Figure 2 and Figure 3 , the pixel PX can include a light emitting element ED and a pixel circuit PC connected to the light emitting element ED. The light emitting element ED as a light source of the pixel PX can be an OLED, but the disclosure is not limited thereto. The pixel circuit PC can control an emission timing and a brightness of the light emitting element ED.

[0076] The pixel circuit PC can include the transistors T and at least one capacitor C. For example, the pixel circuit PC can include first to sixth transistors T1 to T6, a first capacitor C1, and a second capacitor C2. Figure 3 Embodiments in which all of the first to sixth transistors T1 to T6 are N-type transistors are depicted, but the type of the transistors T is not limited thereto. For example, at least one of the transistors T can be formed as a P-type transistor.

[0077] The pixel circuit PC can supply a drive current Id to the light emitting element ED in response to a drive signal supplied from the first and second drive units 120 and 130. For example, the pixel circuit PC can supply the drive current Id to the light emitting element ED in response to each gate signal GS supplied from the first drive unit 120 through a corresponding gate line GL and each data signal DATA supplied from the second drive unit 130 through a corresponding data line DL.

[0078] The first transistor T1 can be a drive transistor of the pixel PX, in which the size of the drain-source current (e.g., the drive current Id) is determined by the gate-source voltage. The second to sixth transistors T2 to T6 can be switching transistors that are turned on or off according to their respective gate-source voltages. According to the type (e.g., P-type or N-type) and / or operating conditions of each of the first to sixth transistors T1 to T6, the first electrode of each of the first to sixth transistors T1 to T6 can be a drain electrode (or drain region) or a source electrode (or source region), and the second electrode of each of the first to sixth transistors T1 to T6 can be an electrode of a different type from the first electrode of each of the first to sixth transistors T1 to T6. For example, if the first electrode of each of the first to sixth transistors T1 to T6 is a drain electrode, the second electrode of each of the first to sixth transistors T1 to T6 can be a source electrode.

[0079] The pixel PX can be connected to a first gate line GWL that transmits a first gate signal (e.g., a scan signal), a second gate line GIL that transmits a second gate signal GI, a third gate line GRL that transmits a third gate signal GR, a first emission control line EML1 that transmits a first emission control signal EM1, a second emission control line EML2 that transmits a second emission control signal EM2, and a data line DL that transmits a data signal DATA. The pixel PX can be connected to a first drive power line VDL that transmits a first pixel voltage ELVDD (also referred to as a "first pixel power voltage") and a second drive power line VSL that transmits a second pixel voltage ELVSS (also referred to as a "second pixel power voltage"). In an embodiment, the pixel PX can also be connected to an initialization power line VIL that transmits an initialization voltage VINT (also referred to as a "third pixel power voltage"), a first reference power line VRL1 that transmits a first reference voltage VREF1 (also referred to as a "fourth pixel power voltage"), and a second reference power line VRL2 that transmits a second reference voltage VREF2 (also referred to as a "fifth pixel power voltage").

[0080] In an embodiment, the first transistor T1 to the sixth transistor T6 can be oxide transistors including an oxide semiconductor (e.g., an oxide semiconductor material) and can also be referred to as "oxide semiconductor transistors". For example, the active layer of each of the first transistor T1 to the sixth transistor T6 can include an oxide semiconductor, although the disclosure is not limited thereto. For example, at least one of the transistors T can be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0081] Since an oxide semiconductor has a high carrier mobility and a low off-current, even in the case where the driving time of an oxide transistor is prolonged, a significant voltage drop does not occur. For example, in the case where the pixel PX can include an oxide transistor, even in the case of driving at a low frequency, the change in the brightness and / or color of an image caused by a voltage drop can be minimal, allowing low-frequency driving. In the case where the first transistor T1 to the sixth transistor T6 are formed as oxide transistors, they can reduce or prevent the off-current in the pixel PX and reduce power consumption.

[0082] An oxide semiconductor can be sensitive to light, and external light can cause a change in the amount of current. In an embodiment, a light-blocking pattern or a light-blocking electrode (e.g., a bottom electrode or a back gate electrode) can be provided under the active layer included in at least one of the transistors T to block external light. This can stabilize the operating characteristics of the at least one transistor T.

[0083] The first transistor T1 can include a gate electrode connected to the first node N1, a first electrode (e.g., a first drain electrode) connected to the second node N2, and a second electrode (e.g., a first source electrode) connected to the third node N3. The first electrode of the first transistor T1 can be connected to the first driving power supply line VDL via the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the light emitting element ED via the sixth transistor T6. The first transistor T1 can control the magnitude (e.g., intensity) of the driving current Id flowing to the light emitting element ED in response to the data signal DATA transmitted to the first node N1.

[0084] In an embodiment, the first transistor T1 can further include a bottom electrode BE (e.g., a bottom gate electrode or a back gate electrode of the first transistor T1) connected to the fourth node N4. By connecting the bottom electrode BE of the first transistor T1 to the fourth node N4, the first transistor T1 can be formed as a dual gate transistor (e.g., a gate synchronous dual gate transistor), thereby improving its operating characteristics.

[0085] The second transistor T2 can include a gate electrode connected to the first gate line GWL, a first electrode (e.g., a second drain electrode) connected to the data line DL, and a second electrode (e.g., a second source electrode) connected to the first node N1. The second transistor T2 can be turned on by the first gate signal GW (e.g., a gate on voltage of the first gate signal GW) transmitted via the first gate line GWL, thereby connecting the data line DL to the first node N1. Accordingly, the data signal DATA transmitted via the data line DL can be transmitted to the first node N1.

[0086] The third transistor T3 can include a gate electrode connected to the third gate line GRL, a first electrode (e.g., a third source electrode) connected to the first reference power supply line VRL1, and a second electrode (e.g., a third drain electrode) connected to the first node N1. The third transistor T3 can be turned on by the third gate signal GR transmitted via the third gate line GRL, thereby transmitting the first reference voltage VREF1 transmitted via the first reference power supply line VRL1 to the first node N1.

[0087] The fourth transistor T4 can include a gate electrode connected to the second gate line GIL, a first electrode (e.g., a fourth drain electrode) connected to the fifth node N5, and a second electrode (e.g., a fourth source electrode) connected to the initialization power supply line VIL. The fourth transistor T4 can be turned on by the second gate signal GI transmitted via the second gate line GIL, thereby transmitting the initialization voltage VINT transmitted via the initialization power supply line VIL to the fifth node N5.

[0088] The fifth transistor T5 can include a gate electrode connected to the first emission control line EML1, a first electrode (e.g., a fifth drain electrode) connected to the first driving power line VDL, and a second electrode (e.g., a fifth source electrode) connected to the second node N2 (or the first electrode of the first transistor T1). The fifth transistor T5 can be turned on by the first emission control signal EM1 (e.g., a gate-on voltage of the first emission control signal EM1) transmitted through the first emission control line EML1, thereby controlling emission timing of the pixel PX.

[0089] The sixth transistor T6 can include a gate electrode connected to the second emission control line EML2, a first electrode (e.g., a sixth drain electrode) connected to the third node N3 (or the second electrode of the first transistor T1), and a second electrode (e.g., a fifth source electrode) connected to the fifth node N5. The sixth transistor T6 can be turned on by the second emission control signal EM2 (e.g., a gate-on voltage of the second emission control signal EM2) transmitted through the second emission control line EML2, thereby controlling emission timing of the pixel PX.

[0090] The second transistor T2 through the sixth transistor T6 can or can not include a bottom electrode. In an embodiment, at least one of the second transistor T2 through the sixth transistor T6 can include a bottom electrode that can be connected to a gate electrode of the at least one switching transistor. Connecting a bottom electrode to a gate electrode of a switching transistor can improve the off characteristics and switching speed of the switching transistor, provide additional voltage margin, reduce leakage current, and enhance voltage stability. For example, by forming the switching transistor as a short channel oxide transistor having a dual gate structure such as a gate-all-around structure, the operating characteristics of the switching transistor can be improved.

[0091] The first capacitor C1 can be connected between the first node N1 and the fourth node N4. As a storage capacitor of the pixel PX, the first capacitor C1 can store a voltage corresponding to a threshold voltage of the first transistor T1 and a data signal DATA (e.g., a data voltage).

[0092] The second capacitor C2 can be connected between the second reference power line VRL2 and the fourth node N4 (e.g., a bottom electrode BE of the first transistor T1). In an embodiment, the capacitance of the second capacitor C2 can be less than the capacitance of the first capacitor C1.

[0093] The light emitting element ED can be connected between the fifth node N5 and the second drive power supply line VSL. For example, the light emitting element ED can include a first electrode (e.g., an anode electrode or a pixel electrode) connected to the fifth node N5, a second electrode (e.g., a cathode electrode or a common electrode) facing the first electrode and connected to the second drive power supply line VSL, and a light emitting layer interposed between the first electrode and the second electrode. In an embodiment, the first electrode of the light emitting element ED can be a separate electrode provided for each pixel PX, and the second electrode of the light emitting element ED can be a common electrode shared by a plurality of pixels PX. The light emitting element ED can emit light having a luminance corresponding to the drive current Id supplied from the pixel circuit PC during a period in which the drive current Id is supplied.

[0094] Figure 4 is a diagram illustrating an array of the display device 100 according to an embodiment, Figure 5 is a schematic cross-sectional view taken along the line X1-X1' of Figure 4 . Figure 4 illustrates an array of, for example, Figure 3 pixels PX.

[0095] Referring to Figure 5 , the display device 100 can include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC. The thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC can be sequentially arranged or disposed on the substrate SUB along a third direction D3. Here, the thin film transistor layer TFTL can include Figure 3 first to sixth transistors T1 to T6, a first capacitor C1, and a second capacitor C2.

[0096] The substrate SUB can be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. The substrate SUB can be formed of an insulating material such as glass, quartz, or a polymer resin. Examples of the polymer resin include polyether sulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. By way of example, the substrate SUB can include a metallic material.

[0097] The first barrier layer BR1 can be provided on the substrate SUB. For example, the first barrier layer BR1 can be provided on the entire surface of the substrate SUB. The first barrier layer BR1 can protect the first to sixth transistors T1 to T6 of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture permeating through the substrate SUB susceptible to moisture. The first barrier layer BR1 can be composed of inorganic films which can be stacked alternately with each other. For example, the first barrier layer BR1 can be formed as a multi-layer film in which one or more inorganic films among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer can be stacked alternately with each other.

[0098] The second barrier layer BR2 can be provided on the first barrier layer BR1. The second barrier layer BR2 can have the same material and composition as the first barrier layer BR1.

[0099] The first gate line GWL, the first reference power supply line VRL1, the light blocking layer, the first driving power supply line VDL, the initialization power supply line VIL, and the second driving power supply line VSL can be provided on the second barrier layer BR2. The light blocking layer can have a hole H superposed with the first gate electrode GE1 of the first transistor TR1. The conductive layer such as the first reference power supply line VRL1, the first driving power supply line VDL, the initialization power supply line VIL, and the second driving power supply line VSL can be formed of a metal material such as chromium (Cr) or molybdenum (Mo), for example. The light blocking layer can be formed of black ink or black dye.

[0100] The buffer layer BF can be provided on the light blocking layer. The buffer layer BF can protect the first to sixth transistors T1 to T6 of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture permeating through the substrate SUB susceptible to moisture. The buffer layer BF can be composed of inorganic films which can be stacked alternately with each other. For example, the buffer layer BF can be formed as a multi-layer film in which one or more inorganic films among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer can be stacked alternately with each other.

[0101] The first active layer ACT1, the second active layer ACT2, and the third active layer ACT3 can be provided on the buffer layer BF. The first active layer ACT1 can be an oxide-based active layer. For example, the first active layer ACT1 can be an oxide semiconductor including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO). The second active layer ACT2 can include the same material as the first active layer ACT1. For example, the second active layer ACT2 can be an active layer of an oxide transistor.

[0102] The gate insulating film GIN can be provided on each of the first active layer ACT1, the second active layer ACT2, the third active layer ACT3, and the buffer layer BF. The gate insulating film GIN can include at least one of tetraethyl orthosilicate (TEOS), silicon nitride (SiN x ), and silicon dioxide (SiO2). For example, the gate insulating film GIN can have a double-layer structure in which a silicon nitride film having a thickness of about 40 nm and a TEOS film having a thickness of about 80 nm can be stacked in order with each other.

[0103] The first gate electrode GE1 of the first transistor T1, the second gate electrode GE2 of the second transistor T2, the third gate electrode GE3 of the third transistor T3, the fourth gate electrode GE4 of the fourth transistor T4, the fifth gate electrode GE5 of the fifth transistor T5, the sixth gate electrode GE6 of the sixth transistor T6, the third gate line GRL, the first emission control line EML1, the second emission control line EML2, and the second gate line GIL can be provided on the gate insulating film GIN. For example, the first gate electrode GE1 can be provided on the gate insulating film GIN to be superimposed on the channel region of the first transistor T1 of the first active layer ACT1, the second gate electrode GE2 can be provided on the gate insulating film GIN to be superimposed on the channel region of the second transistor T2 of the second active layer ACT2, the third gate electrode GE3 can be provided on the gate insulating film GIN to be superimposed on the channel region of the third transistor T3 of the second active layer ACT2, the fourth gate electrode GE4 can be provided on the gate insulating film GIN to be superimposed on the channel region of the fourth transistor T4 of the third active layer ACT3, the fifth gate electrode GE5 can be provided on the gate insulating film GIN to be superimposed on the channel region of the fifth transistor T5 of the first active layer ACT1, and the sixth gate electrode GE6 can be provided on the gate insulating film GIN to be superimposed on the channel region of the sixth transistor T6 of the third active layer ACT3.

[0104] The first gate electrode GE1 can be connected to the lower light-blocking layer through both the contact hole that penetrates the gate insulating film GIN and the hole H of the light-blocking layer. The lower light-blocking layer can be provided below the light-blocking layer. The first drain electrode DE1 and the first source electrode SE1 can be formed on both sides of a channel region of the first transistor T1 of the first active layer ACT1, the second drain electrode DE2 and the second source electrode SE2 can be formed on both sides of a channel region of the second transistor T2 of the second active layer ACT2, the third drain electrode DE3 and the third source electrode SE3 can be formed on both sides of a channel region of the third transistor T3 of the second active layer ACT2, the fourth drain electrode DE4 and the fourth source electrode SE4 can be provided on both sides of a channel region of the fourth transistor T4 of the third active layer ACT3, the fifth drain electrode DE5 and the fifth source electrode SE5 can be formed on both sides of a channel region of the fifth transistor T5 of the first active layer ACT1, and the sixth drain electrode DE6 and the sixth source electrode SE6 can be formed on both sides of a channel region of the sixth transistor T6 of the third active layer ACT3.

[0105] The third gate line GRL can be integral with the third gate electrode GE3.

[0106] The first emission control line EML1 can be integral with the fifth gate electrode GE5.

[0107] The second emission control line EML2 can be integral with the sixth gate electrode GE6.

[0108] The second gate line GIL can be integral with the fourth gate electrode GE4.

[0109] The interlayer insulating film ILD can be provided on the first gate electrode GE1 of the first transistor T1, the second gate electrode GE2 of the second transistor T2, the third gate electrode GE3 of the third transistor T3, the fourth gate electrode GE4 of the fourth transistor T4, the fifth gate electrode GE5 of the fifth transistor T5, the sixth gate electrode GE6 of the sixth transistor T6, the third gate line GRL, the first emission control line EML1, the second emission control line EML2, and the second gate line GIL. The interlayer insulating film ILD can be formed as an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, for example. The interlayer insulating film ILD can include a plurality of inorganic films by way of example.

[0110] The data line DL, the first connection electrode CNE1, the second connection electrode CNE2, the third connection electrode CNE3, the fourth connection electrode CNE4, the fifth connection electrode CNE5, the sixth connection electrode CNE6, the seventh connection electrode CNE7, and the eighth connection electrode CNE8 can be provided on the interlayer insulating film ILD. The data line DL can be connected to the second drain electrode DE2 of the second transistor T2 through the sixth contact hole CT6 that penetrates the interlayer insulating film ILD.

[0111] One side or side portion of the first connection electrode CNE1 can be connected to the first gate electrode GE1 through an eighth contact hole CT8 that penetrates the interlayer insulating film ILD, and the other side or the other side portion of the first connection electrode CNE1 can be connected to the second source electrode SE2 and the third drain electrode DE3 of the second active layer ACT2 through a seventh contact hole CT7 that penetrates the interlayer insulating film ILD.

[0112] One side or side portion of the second connection electrode CNE2 can be connected to the second gate electrode GE2 through a fifth contact hole CT5 that penetrates the interlayer insulating film ILD, and the other side or the other side portion of the second connection electrode CNE2 can be connected to the first gate line GWL through a first contact hole CT1 and a second contact hole CT2 that penetrate the interlayer insulating film ILD and the buffer layer BF.

[0113] One side or side portion of the third connection electrode CNE3 can be connected to the third source electrode SE3 of the second active layer ACT2 through a fourth contact hole CT4 that penetrates the interlayer insulating film ILD, and the other side or the other side portion of the third connection electrode CNE3 can be connected to the first reference power supply line VRL1 through a third contact hole CT3 that penetrates the interlayer insulating film ILD and the buffer layer BF.

[0114] One side or side portion of the fourth connection electrode CNE4 can be connected to the fourth source electrode SE4 of the third active layer ACT3 through a seventeenth contact hole CT17 that penetrates the interlayer insulating film ILD, and the other side or the other side portion of the fourth connection electrode CNE4 can be connected to the initialization power supply line VIL through a sixteenth contact hole CT16 that penetrates the interlayer insulating film ILD and the buffer layer BF.

[0115] One side or side portion of the fifth connection electrode CNE5 can be connected to the fifth drain electrode DE5 through an eleventh contact hole CT11 that penetrates the interlayer insulating film ILD, and the other side or the other side portion of the fifth connection electrode CNE5 can be connected to the first drive power supply line VDL through a thirteenth contact hole CT13 that penetrates the interlayer insulating film ILD and the buffer layer BF.

[0116] The sixth connection electrode CNE6 can be connected to the sixth source electrode SE6 through a fourteenth contact hole CT14 that penetrates the interlayer insulating film ILD.

[0117] One side or side portion of the seventh connection electrode CNE7 can be connected to the first source electrode SE1 through a ninth contact hole CT9 that penetrates the interlayer insulating film ILD, the other side of the seventh connection electrode CNE7 can be connected to the light-blocking layer BML through a tenth contact hole CT10 that penetrates the interlayer insulating film ILD and the buffer layer BF, and still another side of the seventh connection electrode CNE7 can be connected to the sixth drain electrode DE6 of the third active layer ACT3 through a twelfth contact hole CT12 that penetrates the interlayer insulating film ILD.

[0118] The eighth connection electrode CNE8 can be connected to the first sub drive power supply line VSLa through a fifteenth contact hole CT15 that penetrates the interlayer insulating film ILD and the buffer layer BF. The first sub drive power supply line VSLa can be connected to the second sub drive power supply line VSLb. The first sub drive power supply line VSLa and the second sub drive power supply line VSLb can be connected to each other to form a second drive power supply line VSL. For example, the second drive power supply line VSL can include the first sub drive power supply line VSLa extending in the first direction D1 and the second sub drive power supply line VSLb extending in the second direction D2.

[0119] The first passivation layer PAS1 can be provided on the data line DL, the first connection electrode CNE1, the second connection electrode CNE2, the third connection electrode CNE3, the fourth connection electrode CNE4, the fifth connection electrode CNE5, the sixth connection electrode CNE6, the seventh connection electrode CNE7, and the eighth connection electrode CNE8. The first passivation layer PAS1 can include an inorganic film.

[0120] The first via layer VA1 can be provided on the first passivation layer PAS1. The first via layer VA1 can have a first hole HL1 and a second hole HL2. The first hole HL1 and the second hole HL2 can penetrate the first via layer VA1 in the third direction D3. The first hole HL1 and the second hole HL2 can be superposed with the data line DL. For example, in a plan view, the entire first hole HL1 and the entire second hole HL2 can be superposed with the data line DL. The first hole HL1 and the second hole HL2 can be superposed with the shield line SHD. For example, the first hole HL1 can penetrate the first via layer VA1 and be provided between one side or side portion of the data line DL and the shield line SHD, and the second hole HL2 can penetrate the first via layer VA1 and be provided between the other side or another side of the data line DL and the shield line SHD. The first via layer VA1 can include an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0121] The shield line SHD, the shield electrode SHG, the second sub drive power supply line VSLb, and the anode connection electrode ACE can be provided on the first via layer VA1.

[0122] The shield line SHD can be disposed on the first via layer VA1 to overlap the data line DL, the first hole HL1, and the second hole HL2. The shield line SHD can be disposed in the first hole HL1 and the second hole HL2 of the first via layer VA1. Direct current (DC) power (for example, a DC voltage) can be applied to the shield line SHD. To this end, the shield line SHD can be connected to a power supply line. Since the shield line SHD is disposed to overlap the data line DL, coupling between the data line DL and the anode electrode AE can be minimized. Accordingly, capacitance between the data line DL and the anode electrode AE can be minimized. Thus, the voltage of the anode electrode AE can be stably maintained.

[0123] The shield electrode SHG can be disposed on the first via layer VA1 to overlap the first connection electrode CNE1 and the seventh connection electrode CNE7. The shield electrode SHG can be connected to the seventh connection electrode CNE7 through the eighteenth contact hole CT18 that penetrates the first via layer VA1 and the first passivation layer PAS1. Since the shield electrode SHG is disposed to overlap the first connection electrode CNE1, the voltage of the first node N1 can be stably maintained.

[0124] The second sub driving power supply line VSLb can be disposed on the first via layer VA1 to overlap the eighth connection electrode CNE8. The second sub driving power supply line VSLb can be connected to the eighth connection electrode CNE8 through the nineteenth contact hole CT19 that penetrates the first via layer VA1 and the first passivation layer PAS1. The second sub driving power supply line VSLb can be connected to the first sub driving power supply line VSLa through the eighth connection electrode CNE8. The second sub driving power supply line VSLb can be connected to an upper connection electrode disposed in the same layer as the anode electrode AE. For example, the upper connection electrode can be connected to the second sub driving power supply line VSLb through the twenty-first contact hole CT21 that penetrates the second via layer VA2 and the second passivation layer PAS2.

[0125] The anode connection electrode ACE can be disposed on the first via layer VA1 to overlap the fourth connection electrode CNE4 and the sixth connection electrode CNE6. The anode connection electrode ACE can be connected to the sixth connection electrode CNE6 through the twentieth contact hole CT20.

[0126] The second passivation layer PAS2 can be disposed on the shield line SHD, the shield electrode SHG, the second sub driving power supply line VSLb, and the anode connection electrode ACE. The second passivation layer PAS2 can include an inorganic film.

[0127] The second via layer VA2 can be disposed on the second passivation layer PAS2. The second via layer VA2 can include the same material as the first via layer VA1.

[0128] The light emitting element layer EMTL can be provided on the second via layer VA2. The light emitting element layer EMTL can include a pixel defining film (or a pixel defining layer) PDL and a light emitting element ED which can be stacked in the third direction D3. Here, the light emitting element ED can include an anode electrode AE, a light emitting layer EL, and a cathode electrode CE.

[0129] The anode electrode AE of the light emitting element ED can be provided on the second via layer VA2. The anode electrode AE can be connected to the anode connection electrode ACE through a twenty-second contact hole CT22 which penetrates the second via layer VA2 and the second passivation layer PAS2. The anode electrode AE can not be superposed with the first hole HL1 and the second hole HL2. Reference numerals AE' and AE'' refer to anode electrodes of other pixels.

[0130] The emission area EA refers to an area in which the anode electrode AE, the light emitting layer EL, and the cathode electrode CE can be sequentially stacked and holes from the anode electrode AE and electrons from the cathode electrode CE recombine in the light emitting layer EL to emit light.

[0131] In a top emission structure in which light is emitted in the direction of the cathode electrode CE with respect to the light emitting layer EL, the anode electrode AE can be formed as a single layer of Mo, titanium (Ti), copper (Cu), or aluminum (Al), or as a stacked structure such as a titanium / aluminum / titanium (Ti / Al / Ti) structure, an aluminum / ITO / aluminum (ITO / Al / ITO) structure, a silver (Ag)-palladium (Pd)-copper (Cu) (APC) alloy, or an APC alloy / ITO structure (e.g., ITO / APC / ITO) to increase reflectivity.

[0132] The pixel defining film PDL can define the emission area EA of the pixel PX. To this end, the pixel defining film PDL can be provided on the second via layer VA2 to expose a portion of the anode electrode AE. The pixel defining film PDL can cover an edge of the anode electrode AE. The pixel defining film PDL can be superposed with the first hole HL1 and the second hole HL2. The pixel defining film PDL can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0133] The light emitting layer EL can be provided on the anode electrode AE. The light emitting layer EL can include an organic material which can emit light of a selectable color. For example, the light emitting layer EL can include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer can include a host and a dopant. The organic material layer can include a material which emits light of a selectable wavelength, and can be formed using a phosphorescent material or a fluorescent material.

[0134] For example, the organic material layer of the light emitting layer EL emitting light of a first color (e.g., blue) can include a host material including carbazolyl biphenyl (CBP) or 1,3-bis(carbazol-9-yl) (mCP) and a phosphorescent dopant material including (4,6-F2ppy)2Irpic or L2BD111, but the disclosure is not limited thereto.

[0135] The organic material layer of the light emitting layer EL emitting light of a second color (e.g., green) can include a host material including CBP or mCP and a phosphorescent dopant material including fac-tris(2-phenylpyridine)iridium (Ir(ppy)3). By way of example, the organic material layer of the light emitting layer EL emitting light of the second color can be a fluorescent material including tris(8-hydroxyquinoline)aluminum (Alq3), but the disclosure is not limited thereto.

[0136] The organic material layer of the light emitting layer EL emitting light of a third color (e.g., red) can include a host material including CBP or mCP and a phosphorescent dopant material including bis(1-phenylisoquinoline)acetylacetonato iridium (PIQIr(acac)), bis(1-phenylquinoline)acetylacetonato iridium (PQIr(acac)), tris(1-phenylquinoline)iridium (PQIr), or octaethylporphyrin platinum (PtOEP), but the disclosure is not limited thereto. By way of example, the organic material layer of the light emitting layer EL emitting light of the third color can be a fluorescent material including PBD:Eu(DBM)3(Phen) or perylene, but the disclosure is not limited thereto.

[0137] A cathode electrode CE can be disposed on the light emitting layer EL. The cathode electrode CE can be disposed to cover the light emitting layer EL. The cathode electrode CE can be a common layer commonly disposed on the light emitting layer EL. A cap layer can be formed on the cathode electrode CE.

[0138] In a top emission structure, the cathode electrode CE can be formed of a transparent conductive oxide (TCO) such as ITO or indium zinc oxide (IZO) that can transmit light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy thereof. In the case where the cathode electrode CE is formed of a semi-transmissive conductive material, light output efficiency can be increased by a microcavity.

[0139] An encapsulation layer ENC can be formed on the light emitting element layer EMTL. The encapsulation layer ENC can include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. The encapsulation layer ENC can include at least one organic film to protect the light emitting element layer EMTL from foreign substances such as dust. For example, the encapsulation layer ENC can include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0140] The first encapsulation inorganic film TFE1 can be provided on the cathode electrode CE, the encapsulation organic film TFE2 can be provided on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 can be provided on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can be formed as a multilayer film in which one or more kinds of inorganic films among a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and an aluminum oxide film can be stacked alternately with each other. The encapsulation organic film TFE2 can be an organic film including a material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0141] Figure 6 is a view illustrating an array of the display device 100 according to an embodiment, and Figure 7 is a schematic cross-sectional view taken along the line XII-XII' of Figure 6 .

[0142] Figure 6 and Figure 7 The display device 100 of Figure 4 and Figure 5 The display device 100 of

[0143] Referring to Figure 6 and Figure 7 , the shield line SHD can be cut in the first area A1 and the second area A2, and the data line DL can be cut in the third area A3. In a plan view, the third area A3 can be disposed between the first area A1 and the second area A2.

[0144] When the shield line SHD is cut in the first area A1 and the second area A2, the shield line SHD can include the first sub-shield line SS1, the second sub-shield line SS2, and the repair electrode RPE which are separated from each other. The repair electrode RPE can be disposed between the first sub-shield line SS1 and the second sub-shield line SS2.

[0145] When the data line DL is cut in the third area A3, the data line DL can include the first sub-data line SDL1 and the second sub-data line SDL2 which are separated from each other. In a plan view, facing ends of the first sub-data line SDL1 and the second sub-data line SDL2 can be disposed between the first hole HL1 and the second hole HL2.

[0146] The repair electrode RPE can overlap the facing ends of the first sub-data line SDL1 and the second sub-data line SDL2. For example, the repair electrode RPE can overlap one end of the first sub-data line SDL1 in the third area A3 and one end of the second sub-data line SDL2 in the third area A3.

[0147] In a plan view, the first hole HL1 can be disposed between one end of the repair electrode RPE facing the first sub-shield line SS1 and one end of the first sub-data line SDL1 facing the second sub-data line SDL2. In other words, in a plan view, the first hole HL1 can be disposed between one end of the repair electrode RPE in the first area A1 and one end of the first sub-data line SDL1 in the third area A3.

[0148] In a plan view, the second hole HL2 can be disposed between the other end of the repair electrode RPE facing the second sub-shield line SS2 and one end of the second sub-data line SDL2 facing the first sub-data line SDL1. In other words, in a plan view, the second hole HL2 can be disposed between the other end of the repair electrode RPE in the second area A2 and one end of the second sub-data line SDL2 in the third area A3.

[0149] Each of the first hole HL1 and the second hole HL2 can further penetrate the first passivation layer PAS1. In other words, the first hole HL1 can penetrate both the first via layer VA1 and the first passivation layer PAS1, and the second hole HL2 can penetrate both the first via layer VA1 and the first passivation layer PAS1.

[0150] One side or side portion of the repair electrode RPE can be connected to the first sub-data line SDL1, and the other side or side portion of the repair electrode RPE can be connected to the second sub-data line SDL2. For example, one side or side portion of the repair electrode RPE can be connected to the first sub-data line SDL1 through the first hole HL1, and the other side or side portion of the repair electrode RPE can be connected to the second sub-data line SDL2 through the second hole HL2. Accordingly, the cut data line DL can be repaired through the repair electrode RPE. In other words, the first sub-data line SDL1 disposed on one side or side portion of the third area A3 and the second sub-data line SDL2 disposed on the other side or side portion of the third area A3 can be connected to each other through the repair electrode RPE.

[0151] DC power can be appropriately supplied to the cut shield line SHD. In other words, a data signal DATA from the data line DL can be applied to a portion of the cut shield line SHD serving as the repair electrode RPE, while DC power can be supplied to the remaining portion of the cut shield line SHD (e.g., the first sub-shield line SS1 and the second sub-shield line SS2).

[0152] Figures 8 to 13 is a schematic cross-sectional view for explaining a method of manufacturing the display device 100 according to an embodiment. For example, Figures 8 to 13 may be a schematic cross-sectional view for explaining a repair method for a data line DL that is open.

[0153] First, referring to Figure 8 A data line DL can be formed on the substrate SUB. For example, the data line DL can be disposed on the interlayer insulating film ILD. During formation of the data line DL, line defects such as an open circuit can occur in the data line DL. For example, when the data line DL is cut in the third region A3, the data line DL is divided into a first sub-data line SDL1 and a second sub-data line SDL2.

[0154] Thereafter, referring to Figure 9 A first passivation layer PAS1 can be formed on the data line DL.

[0155] Thereafter, referring to Figure 10 A first via layer VA1 having a first hole HL1 and a second hole HL2 can be formed on the first passivation layer PAS1.

[0156] Thereafter, referring to Figure 11 A shield line SHD can be formed on the first via layer VA1.

[0157] Thereafter, referring to Figure 12 A laser beam can be irradiated onto the first region A1 and the second region A2 on the shield line SHD, thereby cutting the shield line SHD in the first region A1 and the second region A2. Accordingly, a repair electrode RPE can be formed in a region overlapping with a region (e.g., the third region A3) at which the data line DL is cut, a first sub-shield line SS1 can be formed on one side or side of the repair electrode RPE, and a second sub-shield line SS2 can be formed on the other side or another side of the repair electrode RPE.

[0158] Thereafter, referring to Figure 13 A laser beam can be irradiated toward the first hole HL1 and the second hole HL2. Accordingly, the first passivation layer PAS1 can be removed in regions corresponding to the first hole HL1 and the second hole HL2, thereby exposing the data line DL. In other words, by irradiating the laser beam, depths of the first hole HL1 and the second hole HL2 can be increased, thereby penetrating the first passivation layer PAS1 and the first via layer VA1 with the first hole HL1 and the second hole HL2. The repair electrode RPE in the first hole HL1 and the second hole HL2 can be connected to the data line DL by irradiation of the laser beam. For example, one side or side of the repair electrode RPE can be connected to the first sub-data line SDL1 through the first hole HL1, and the other side or another side of the repair electrode RPE can be connected to the second sub-data line SDL2 through the second hole HL2.

[0159] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to one embodiment includes the above-described display device and can further include a module or a device having an additional function, in addition to the display device.

[0160] Figure 14 is a block diagram of an electronic device according to one embodiment. Referring to Figure 14 , the electronic device 50 according to one embodiment can include a display module 11, a processor 12, a memory 13, and a power module 14. The electronic device 50 can further include an input module 15, a non-image output module 16, and / or a communication module 17.

[0161] The electronic device 50 can output various information in the form of an image through the display module 11. When the processor 12 executes an application program stored in the memory 13, image information provided by the application program can be provided to a user through the display module 11. The power module 14 can include a power module such as a power adapter or a battery device and a power conversion module that converts power supplied by the power module to generate power required for the operation of the electronic device 50. The input module 15 can provide input information to the processor 12 and / or the display module 11. The non-image output module 16 can receive information other than an image (such as sound, haptics, and light) transmitted from the processor 12 and provide the information to a user. The communication module 17 is a module responsible for transmitting and receiving information between the electronic device 50 and an external device, and can include a reception unit and a transmission unit.

[0162] At least one of the components of the above-described electronic device 50 can be included in the display device according to the above-described embodiments. In addition, some of the respective modules functionally included in one module can be included in the display device, and other modules can be provided separately from the display device. For example, the display device includes the display module 11, and the processor 12, the memory 13, and the power module 14 can be provided in the form of other devices within the electronic device 50 other than the display device.

[0163] Figure 15 、 Figure 16 and Figure 17 are schematic diagrams of electronic devices according to various embodiments. Figures 15 to 17 Examples of various electronic devices to which a display device according to an embodiment is applied are illustrated.

[0164] Figure 15 A smart phone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e are illustrated as examples of electronic devices.

[0165] The smart phone 10_1a can include, in addition to the display module 11, an input module such as a touch sensor and a communication module. The smart phone 10_1a can process information received through the communication module or other input module and display the information through the display module of the display device.

[0166] In the case of the tablet PC 10_1b, the laptop computer 10_1c, the TV 10_1d, and the desktop monitor 10_1e, they also include display modules and input modules similar to those of the smart phone 10_1, and in some cases can additionally include a communication module.

[0167] Figure 16 Examples of electronic devices including display modules applied to wearable electronic devices are illustrated. The wearable electronic devices can be smart glasses 10_2a, a head-mounted display 10_2b, a smart watch 10_2c, etc.

[0168] The smart glasses 10_2a and the head-mounted display 10_2b can include a display module that emits a display image and a reflector that reflects the emitted display image and provides it to the user's eyes, thereby providing a virtual reality picture or an augmented reality picture to the user.

[0169] The smart watch 10_2c includes a biometric sensor as an input device, and can provide the user with biometric information recognized by the biometric sensor through the display module. Figure 17 Examples of electronic devices including display modules applied to vehicles are illustrated. For example, the electronic device 10_3 can be applied to an instrument panel, a center fascia, etc. of a vehicle, or can be applied to a CID (Central Information Display) placed on the instrument panel of a vehicle or an interior mirror display that replaces a side mirror.

[0170] Embodiments have been disclosed herein, although the use of the terms will be used and interpreted only in a generic and descriptive sense and not for limitation purposes. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics and / or elements described in connection with an embodiment can be used alone or in combination with features, characteristics and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Accordingly, one of ordinary skill in the art will recognize that the various embodiments disclosed herein can be practiced with the specific features, structures and / or characteristics individually or in combination with one another, without departing from the spirit and scope of the disclosure as set forth in the claims.

Claims

1. A display device comprising: a data line provided over a substrate; a passivation layer provided over the data line; a via layer provided over the passivation layer; a shield line provided over the via layer and superposed with the data line; a light emitting element layer provided over the shield line; a first hole penetrating the via layer and superposed with one side of the data line; and a second hole penetrating the via layer and superposed with another side of the data line. The shield line receives direct current power.

2. The display device according to claim 1, wherein The shield line is provided in the first hole and the second hole.

3. The display device according to claim 1, wherein 4. The display device according to claim 1, wherein the light emitting element layer includes an anode electrode and a pixel defining layer provided over the anode electrode, and the first hole and the second hole are not superposed with the anode electrode. The first hole and the second hole are superposed with the pixel defining layer.

5. The display device of claim 4, wherein, 6. The display device according to claim 1, wherein the data line includes a first sub-data line and a second sub-data line separated from each other, and facing end portions of the first sub-data line and the second sub-data line are provided between the first hole and the second hole in a plan view. The shield line includes a repair electrode, a first sub-shield line, and a second sub-shield line separated from each other.

7. The display device of claim 6, wherein, The repair electrode is superposed with the facing end portions of the first sub-data line and the second sub-data line.

8. The display device of claim 7, wherein, 9. The display device according to claim 8, wherein the first hole is provided between an end portion of the repair electrode facing the first sub-shield line and an end portion of the first sub-data line facing the second sub-data line in a plan view, and the second hole is provided between another end portion of the repair electrode facing the second sub-shield line and an end portion of the second sub-data line facing the first sub-data line in a plan view. Each of the first hole and the second hole further penetrates the passivation layer.

10. The display device of claim 9, wherein, 11. The display device according to claim 10, wherein one side of the repair electrode is connected to the first sub-data line through the first hole, and another side of the repair electrode is connected to the second sub-data line through the second hole.

12. The display device according to claim 11, wherein the repair electrode receives a data voltage from the data line, and each of the first sub-shield line and the second sub-shield line receives direct current power.

13. A display device comprising: a data line provided over a substrate; a passivation layer provided over the data line; a via layer provided over the passivation layer; a shield line provided over the via layer and superposed with the data line; a light emitting element layer provided over the shield line; a first hole penetrating the via layer and provided between one side of the data line and the shield line; and a second hole penetrating the via layer and provided between another side of the data line and the shield line. The shield line receives direct current power. The shield line is provided in the first hole and the second hole.

14. The display device of claim 13, wherein, 16. The display device according to claim 13, wherein 15. The display device of claim 13, wherein, ​ ​ The light emitting element layer includes an anode electrode and a pixel defining layer disposed on the anode electrode, and The first hole and the second hole do not overlap the anode electrode.

17. The display device of claim 16, wherein, The first hole and the second hole overlap the pixel defining layer. 18.The display device of claim 13, wherein, The data line includes a first sub-data line and a second sub-data line separated from each other, and Opposed end portions of the first sub-data line and the second sub-data line are disposed between the first hole and the second hole in a plan view.

19. The display device of claim 18, wherein, The shield line includes a repair electrode, a first sub-shield line, and a second sub-shield line separated from each other.

20. The display device of claim 19, wherein, The repair electrode overlaps the opposed end portions of the first sub-data line and the second sub-data line. 21.The display device of claim 20, wherein, The first hole is disposed between an end portion of the repair electrode facing the first sub-shield line and an end portion of the first sub-data line facing the second sub-data line in a plan view, and The second hole is disposed between another end portion of the repair electrode facing the second sub-shield line and an end portion of the second sub-data line facing the first sub-data line in a plan view.

22. The display device of claim 21, wherein, Each of the first hole and the second hole further penetrates the passivation layer. 23.The display device of claim 22, wherein, One side of the repair electrode is connected to the first sub-data line through the first hole, and Another side of the repair electrode is connected to the second sub-data line through the second hole. 24.The display device of claim 23, wherein, The repair electrode receives a data voltage from the data line, Each of the first sub-shield line and the second sub-shield line receives direct current power. 25.An electronic device, the electronic device comprising: a display device including a screen; wherein the display device includes: a data line disposed on a base; a passivation layer disposed on the data line; a via layer disposed on the passivation layer; a shield line disposed on the via layer and overlapping the data line; a light emitting element layer disposed on the shield line; a first hole penetrating the via layer and overlapping one side of the data line; and a second hole penetrating the via layer and overlapping another side of the data line.

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