Light-emitting display device

Abstract

The invention provides a light-emitting display device. The light emitting display device includes a substrate, a voltage line positioned on the substrate and transmitting a constant voltage, a passivation layer positioned on the voltage line, a via layer positioned on the passivation layer, a connection electrode positioned on the via layer, a pixel defining layer positioned on the connection electrode, and a cathode electrode positioned on the pixel defining layer.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a light emitting display apparatus, and more particularly, to a light emitting display apparatus applying a laser drilling method. BACKGROUND

[0002] A display apparatus is an apparatus that displays a picture, and includes a liquid crystal display (LCD) and an organic light emitting diode (OLED). The display apparatus is used for various electronic devices, such as a mobile phone, a navigation apparatus, a digital camera, an electronic book, a portable game machine, and various terminals.

[0003] An organic light emitting display apparatus has a self-light emitting characteristic, and unlike a liquid crystal display, does not need a separate light source, so that a thickness and weight can be reduced. In addition, the organic light emitting display apparatus has high quality characteristics, such as low power consumption, high brightness, and fast response speed. SUMMARY

[0004] Embodiments provide a light emitting display apparatus capable of using laser drilling to transmit a voltage using a laser.

[0005] Embodiments provide a high resolution light emitting display apparatus that can confirm whether laser drilling has been properly formed.

[0006] According to embodiments, a light emitting display apparatus includes a substrate, a voltage line positioned on the substrate and transmitting a constant voltage, a passivation layer positioned on the voltage line, a via layer positioned on the passivation layer, a connection electrode positioned on the via layer, a pixel definition layer positioned on the connection electrode, and a cathode electrode positioned on the pixel definition layer, wherein the pixel definition layer has a first opening overlapping the connection electrode in a plan view, the via layer has a second opening overlapping the connection electrode in the plan view, the passivation layer has a third opening overlapping the connection electrode in the plan view, the cathode electrode and the connection electrode are electrically connected to each other through the first opening of the pixel definition layer, the voltage line and the connection electrode are electrically connected to each other through the second opening of the via layer and the third opening of the passivation layer, and at least a portion of the third opening of the passivation layer does not overlap the second opening of the via layer in the plan view.

[0007] The second opening of the via layer and the third opening of the passivation layer can be positioned in the first opening of the pixel definition layer in the plan view.

[0008] The third opening of the passivation layer and the second opening of the via layer can have a planar shape in the plan view.

[0009] The third opening of the passivation layer and the second opening of the via layer can have a triangular, rectangular, hexagonal, octagonal, or other polygonal planar shape, or a planar shape in which a polygonal shape is truncated.

[0010] A direction in which a long side of the second opening of the via layer extends can be different from a direction in which a long side of the third opening of the passivation layer extends.

[0011] A direction in which a long side of the second opening of the via layer extends can be perpendicular to a direction in which a long side of the third opening of the passivation layer extends.

[0012] The second opening of the via layer can be positioned in the third opening of the passivation layer in a plan view.

[0013] The third opening of the passivation layer can be flush with the first opening of the pixel definition layer in a plan view.

[0014] A low driving voltage can be applied to the voltage line electrically connected to the light emitting display device.

[0015] An anode electrode positioned on the via layer can be further included, and the pixel definition layer further includes a fourth opening overlapping the anode electrode in a plan view, and the anode electrode and the connection electrode can be formed of the same material.

[0016] The light emitting display device can further include an intermediate layer positioned on the anode electrode and the pixel definition layer, wherein the intermediate layer is opened at a portion overlapping the connection electrode by laser drilling to electrically connect the cathode electrode and the connection electrode.

[0017] The light emitting display device according to an embodiment includes a substrate, a voltage line positioned on the substrate and transmitting a constant voltage, a via layer positioned on the voltage line, a connection electrode positioned on the via layer, a pixel definition layer positioned on the connection electrode, and a cathode electrode positioned on the pixel definition layer, wherein the pixel definition layer has a first opening overlapping the connection electrode in a plan view, the via layer has a second opening overlapping the connection electrode in the plan view, the cathode electrode and the connection electrode are electrically connected to each other through the first opening of the pixel definition layer, the voltage line and the connection electrode are electrically connected to each other through the second opening of the via layer, and at least a portion of the second opening of the via layer does not overlap the first opening of the pixel definition layer in the plan view.

[0018] The light emitting display device described above includes a passivation layer positioned between the voltage line and the via layer, and the passivation layer has a third opening overlapping the connection electrode in a plan view, and at least a portion of the third opening of the passivation layer can not overlap the first opening of the pixel definition layer in the plan view.

[0019] The second opening of the via layer can be positioned in the third opening of the passivation layer in a plan view.

[0020] The light emitting display device can further include an anode electrode positioned on the via layer, and the pixel definition layer can further include a fourth opening overlapping the anode electrode in a plan view, and the anode electrode and the connection electrode can be formed of the same material.

[0021] The light emitting display device can further include an intermediate layer positioned on the anode electrode and the pixel definition layer, wherein the intermediate layer is opened at a portion overlapping the connection electrode by laser drilling to electrically connect the cathode electrode and the connection electrode.

[0022] The light emitting display device according to an embodiment includes a substrate, a voltage line positioned on the substrate and transmitting a constant voltage, a via layer positioned on the voltage line, a connection electrode positioned on the via layer, a pixel definition layer positioned on the connection electrode, and a cathode electrode positioned on the pixel definition layer, the pixel definition layer having a first opening overlapping the connection electrode in a plan view, the via layer having a second opening overlapping the connection electrode in the plan view, the cathode electrode and the connection electrode being electrically connected to each other through the first opening of the pixel definition layer, and the voltage line and the connection electrode being electrically connected to each other through the second opening of the via layer, and the second opening of the via layer having a planar shape in the plan view.

[0023] The second opening of the via layer can have a triangular, rectangular, hexagonal, octagonal, or other polygonal planar shape, or a planar shape in which a polygonal shape is truncated.

[0024] The light emitting display device can further include an anode electrode positioned on the via layer, and the pixel definition layer can further include an opening overlapping the anode electrode in a plan view, and the anode electrode and the connection electrode can be formed of the same material.

[0025] The light emitting display device can further include an intermediate layer positioned on the anode electrode and the pixel definition layer, wherein the intermediate layer is opened at a portion overlapping the connection electrode by laser drilling to electrically connect the cathode electrode to the connection electrode.

[0026] According to an embodiment, by forming a position of a machining hole formed by laser drilling to at least partially overlap an opening electrically connecting the connection electrode and the voltage line, a space required for laser drilling can be reduced, and laser drilling can be performed in a high-resolution light emitting display device.

[0027] According to an embodiment, by forming or positioning an opening electrically connecting the connection electrode and the voltage line differently from a shape of a machining hole formed by laser drilling, or by distinguishing a position of the machining hole formed by laser drilling and the opening electrically connecting the connection electrode and the voltage line from each other, a space for laser drilling can be secured and it can be secured that laser drilling is properly formed even in a high-resolution light emitting display device.

[0028] According to the embodiment, when the electric connection connects the electrode and the voltage line, by forming the opening of the via layer at least partially having a width narrower than the opening of the passivation layer, it is possible to prevent the cathode electrode from being disconnected due to the steep boundary of the opening of the passivation layer, and to ensure that the driving low voltage can be transmitted to the cathode electrode without a problem. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic plan view showing a structure of a laser-drilled region in a light-emitting display device according to an embodiment.

[0030] Figure 2 and Figure 3 are schematic cross-sectional views taken along lines II-II' and III-III' of Figure 1

[0031] Figure 4 is a schematic photograph of a cross section of a portion of a light-emitting display device.

[0032] Figure 5 is Figure 1 is a schematic plan view of a laser-drilled region in

[0033] Figure 6 and Figure 7 are schematic cross-sectional views taken along lines VI-VI' and VII-VII' of Figure 5

[0034] Figure 8 is a schematic flowchart showing a method for determining whether there is an error in laser drilling according to an embodiment.

[0035] Figure 9 is a schematic diagram showing each center in one embodiment.

[0036] Figure 10 is a schematic table summarizing various embodiments and their characteristics.

[0037] Figure 11 is a schematic plan view showing a structure of a laser-drilled region according to a comparative example.

[0038] Figure 12 is a schematic cross-sectional view of a laser-drilled region of the comparative example of Figure 11

[0039] Figure 13 is a photograph taken after performing laser drilling in a laser-drilled region of the comparative example of Figure 11

[0040] Figure 14 is a schematic table summarizing various comparative examples and their characteristics.​​​​

[0041] Figure 15 is a schematic plan view showing a structure of a laser-drilled region according to another comparative example.

[0042] Figure 16 and Figure 17 is a schematic plan view showing a structure of a laser-drilled region according to another embodiment.

[0043] Figure 18 is a table schematically showing steps for manufacturing some layers of a light-emitting display device according to an embodiment.

[0044] Figure 19 is a schematic cross-sectional view of a light-emitting display device according to an embodiment.

[0045] Figure 20 is a schematic view of an equivalent circuit of a pixel of a light-emitting display device according to an embodiment.

[0046] Figure 21 is a table schematically showing steps for manufacturing some layers of a light-emitting display device according to another embodiment. DETAILED DESCRIPTION

[0047] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein.

[0048] In order to clearly illustrate the present disclosure, portions irrelevant to the description have been omitted, and the same or similar components throughout the specification are assigned the same reference numerals.

[0049] Further, the size and thickness of each component shown in the drawings are arbitrarily shown for the ease of explanation, and thus the present disclosure is not necessarily limited to the size and thickness of each component shown. In the drawings, the thickness is exaggerated for the sake of clarity in illustrating various layers and regions. Also, in the drawings, the thickness of some layers and regions is exaggerated for the ease of explanation.

[0050] In addition, when a part (such as a layer, film, region, plate, or component) is referred to as being "on" or "above" another part, it means not only that the part is "directly on" the other part, but also that there can be another part between the part and the other part. In contrast, when an element is referred to as being "directly on" another element, there is no intervening element. Further, "above" or "over" a reference part means positioned above or below the reference part, and does not necessarily mean positioned "above" or "over" the reference part in a direction opposite to gravity.

[0051] Furthermore, unless otherwise stated, throughout the specification, when a section is referred to as "including" an element, it means that the section may also include other elements, rather than excluding other elements.

[0052] Furthermore, throughout the instruction manual, when "in a plan view" is mentioned, it means when the target part is viewed from above, and when "in a cross section" is mentioned, it means when the target part is vertically cut and viewed from the side.

[0053] Furthermore, throughout the specification, when the word "connected" is used, it means not only when two or more components are directly connected, but also when two or more components are indirectly connected through other components. The two or more components are physically connected, including not only cases of connection or electrical connection, but also cases where all parts (which are called by different names depending on their location or function) are substantially connected to each other.

[0054] Furthermore, throughout the specification, when a part (such as wiring, layer, film, area, plate, or component) is referred to as “extending in a first direction or a second direction”, this means not only a straight shape extending in that direction, but also includes structures that extend integrally along the first or second direction, and also includes structures that bend at some parts, structures with serrated structures, or structures that extend while including bent structures.

[0055] Furthermore, electronic devices including display devices, display panels, etc., described in the specification (e.g., mobile phones, TVs, monitors, laptop computers, etc.), or display devices, display panels, etc., manufactured by the manufacturing methods described in the specification, are not excluded from the scope of this specification.

[0056] In the following description, the accompanying drawings will be used with particular reference to the structure of the laser-drilled area that can be positioned in the display area of ​​the light-emitting display device, and a schematic planar structure will be shown first. Figure 1 To describe.

[0057] Figure 1 This is a schematic plan view showing the structure of the laser drilling area in a light-emitting display device according to an embodiment.

[0058] exist Figure 1 The diagram shows the connecting electrode CE located in the laser drilling area LDA and the openings OPpvx, OPvia and OPpdl located above and below the connecting electrode CE.

[0059] A voltage to be transmitted to the cathode electrode of a light-emitting diode can be applied by laser drilling (e.g., Figure 20The connection electrode CE can be formed in the same layer (also referred to as an anode layer) as an anode electrode included in the light emitting diode, and can be formed of the same material as the anode electrode, and if the anode electrode is formed of a plurality of layers, the connection electrode CE can also be formed of a plurality of layers. The anode layer including the connection electrode CE and the anode electrode can be made of a single layer including a transparent conductive oxide layer or a metal material or a plurality of layers including a transparent conductive oxide layer or a metal material. For example, the transparent conductive oxide layer can include ITO (indium tin oxide), poly-ITO, IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), and ITZO (indium tin zinc oxide), and the metal material can include silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), and aluminum (Al).

[0060] The pixel defining layer (see Figure 2 380) can be positioned on top of the connection electrode CE, and in the pixel defining layer, there can be a first opening OPpdl exposing at least a portion of the connection electrode CE for laser drilling. In a plan view, the first opening OPpdl of the pixel defining layer 380 can overlap the connection electrode CE. The pixel defining layer 380 can include one of a photoresist, a polyacrylic resin, a polyimide resin, and an acrylic resin, and these resins can be used alone or in combination with each other. In other embodiments, the pixel defining layer 380 can have a transparent property so that light can be transmitted, or the pixel defining layer 380 can contain a black organic material or a light blocking material, can be black, and can have a property of absorbing / blocking light.

[0061] A power line (not shown) connected to the connection electrode CE can be positioned below the connection electrode CE, and the connection electrode CE and the power line can be connected through the openings OPvia, OPpdl. A voltage applied to the power line can be transmitted to the connection electrode CE, and the cathode electrode and the connection electrode CE can be electrically connected through laser drilling, so that the voltage applied to the power line can be transmitted to the cathode electrode.

[0062] In an embodiment of the light emitting display device, a via layer (see Figure 2 182) and a passivation layer (see Figure 2The second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 can be positioned in the first opening OPpdl of the pixel definition layer 380 in a plan view. For example, the via layer 182 can be formed of an organic insulating layer, and can include one or more materials selected from the group consisting of photoresist, polyacrylic resin, polyimide resin, acrylic resin, benzocyclobutene, and phenol resin. Meanwhile, the passivation layer 181 can be formed of an inorganic insulating layer, and can include one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON x ), or can be formed using these compounds in a multi-layer structure. The passivation layer 181 can have an inorganic insulating layer structure thicker than other inorganic insulating layers.

[0063] In Figure 1 , the third opening OPpvx of the passivation layer 181 and the second opening OPvia of the via layer 182 can be formed to overlap the first opening OPpdl of the pixel definition layer 380 connecting the connection electrode CE to the cathode electrode above in a plan view, thereby allowing the connection electrode CE to be electrically connected to the power line below, which reduces the area occupied by the laser-drilled area LDA including this configuration. Accordingly, the laser-drilled area LDA can be formed even in a high-resolution light emitting display device.

[0064] In Figure 1 , the third opening OPpvx of the passivation layer 181 and / or the second opening OPvia of the via layer 182 have a rectangular shape rather than a circular shape, and can be elongated at one side rather than a square shape. In other embodiments, the third opening OPpvx of the passivation layer 181 and / or the second opening OPvia of the via layer 182 can have various polygonal planar shapes such as a triangle, a rectangle, a hexagon, an octagon, etc., or have a planar shape in which a polygonal shape is truncated. The long sides of the planar shapes of the third opening OPpvx of the passivation layer 181 and the second opening OPvia of the via layer 182 on which the long sides extend can be different from each other, and in other embodiments, the long sides of the planar shapes of the third opening OPpvx of the passivation layer 181 and the second opening OPvia of the via layer 182 on which the long sides extend can be perpendicular to each other. For example, the long side can be the longest side among the sides of the respective planar shapes.

[0065] In the case of laser drilling, the machined hole formed by laser drilling (see...) Figure 13 The LDP in the laser drilling can be circular. Therefore, by forming holes with shapes (e.g., squares, triangles, and various other shapes) that are different from the shape of the laser-drilled holes, the location of the laser drilling can be clearly identified and it can be confirmed that the laser drilling has been performed correctly, and any problems caused by the laser drilling can be prevented.

[0066] exist Figure 1 In this design, the third opening OPpvx of the passivation layer 181 may not completely overlap with the second opening OPvia of the via layer 182, and at least a portion of the third opening OPpvx of the passivation layer 181 may have a structure that does not overlap with the second opening OPvia of the via layer 182. The passivation layer 181 may have a steep boundary slope, and the conductive layer positioned above it may be broken, so at least a portion of the boundary of the third opening OPpvx of the passivation layer 181 may be covered by the via layer 182 to prevent the conductive layer above from breaking.

[0067] The voltage transmitted to the cathode electrode via the connection electrode CE electrically connected by laser drilling can be the driving voltage ELVDD (see...). Figure 20 ) or drive low voltage ELVSS (participate) Figure 20 Furthermore, the following discussion focuses on the implementation of a low-voltage ELVSS where the voltage transmitted to the cathode electrode is used.

[0068] The following will be through Figure 2 and Figure 3 Let's discuss along Figure 1 The cross-sectional structure shown is cut by cross-section lines II-II' and III-III'.

[0069] Figure 2 and Figure 3 It is along Figure 1 The sectional views taken from lines II-II' and III-III'.

[0070] Figure 2 It is along Figure 1 A schematic sectional view taken from section line II-II', and Figure 3 It is a schematic sectional view taken along section line III-III'.

[0071] Figure 2 and Figure 3The structure in which the connection electrode CE and the auxiliary drive low voltage line 174-1 are electrically connected is shown, and the lower structure of the auxiliary drive low voltage line 174-1 is omitted. The auxiliary drive low voltage line 174-1 can also be referred to as a voltage line, and in other embodiments, the electrically connecting electrode CE can be electrically connected with a voltage line to which a voltage (e.g., a drive voltage ELVDD) other than the drive low voltage ELVSS is applied.

[0072] The auxiliary drive low voltage line 174-1 can be a voltage line through which the drive low voltage ELVSS is transmitted, and can be formed of the same material as one of the transistor and the electrode included in the pixel driver that supplies a current to the light emitting diode to display luminance. The transistor or the electrode included in the pixel driver can include various semiconductor layers, conductive layers, and insulating layers, and the stack structure of some embodiments will be described in Figure 18 or Figure 21 . The auxiliary drive low voltage line 174-1 can be formed as the data conduction layer (see SD in Figure 18 , SD1, SD2 in Figure 21 ), and can include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), etc., and can be made of a single layer or multiple layers.

[0073] Referring to Figure 2 and Figure 3 , the auxiliary drive low voltage line 174-1 can be covered with a passivation layer 181, and a portion of the auxiliary drive low voltage line 174-1 can be exposed through a third opening OPpvx positioned in the passivation layer 181. For example, the passivation layer 181 can be formed of an inorganic insulating layer, and can include one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON x ), or can be formed of multiple layers using these compounds. The passivation layer 181 can have an inorganic insulating layer structure formed thicker than other inorganic insulating layers.

[0074] The passivation layer 181 can be covered with a via layer 182, and the via layer 182 can have a second opening OPvia at least partially overlapping the third opening OPpvx of the passivation layer 181, and the auxiliary drive low voltage line 174-1 can have a structure in which a portion thereof is exposed through the third opening OPpvx of the passivation layer 181 and the second opening OPvia of the via layer 182. The via layer 182 can be formed of an organic insulating layer, and can include one or more materials selected from the group consisting of photoresist, polyacrylic resin, polyimide resin, acrylic resin, benzocyclobutene, and phenol resin.

[0075] A connection electrode CE can be above the via layer 182, and the connection electrode CE is electrically connected to the portion of the auxiliary driving low voltage line 174-1 exposed by the third opening OPpvx of the passivation layer 181 and the second opening OPvia of the via layer 182 while directly contacting the portion of the auxiliary driving low voltage line 174-1 exposed by the third opening OPpvx of the passivation layer 181 and the second opening OPvia of the via layer 182. Like the anode electrode, the connection electrode CE can be made of a single layer including a transparent conductive oxide layer or a metal material or a multi-layer structure including a transparent conductive oxide layer or a metal material. For example, the transparent conductive oxide can include ITO (indium tin oxide), poly-ITO, IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), and ITZO (indium tin zinc oxide), and the metal material can include silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), and aluminum (Al).

[0076] The pixel definition layer 380 can be overlaid on the connection electrode CE, and a first opening OPpdl can be formed in the pixel definition layer 380 to expose a portion of the connection electrode CE. The pixel definition layer 380 can include one of a photoresist, a polyacrylic resin, a polyimide resin, and an acrylic resin, and these resins can be used alone or in combination with each other. In other embodiments, the pixel definition layer 380 can have a transparent property that allows light to pass through, or can include a black organic material or a light-blocking material, can be black, and can have light absorption / blocking properties.

[0077] Figure 2 and Figure 3 It is shown that the width of the third opening OPpvx of the passivation layer 181 and the width of the second opening OPvia of the via layer 182 are different depending on the position of the cross-sectional line, and thus, the structure at the contact of the connection electrode CE and the auxiliary driving low voltage line 174-1 can be different. The via layer 182 can be formed with a gentle slope at the boundary of the second opening OPvia, and the passivation layer 181 can be formed with a steep slope at the boundary between the third openings OPpvx. Thus, whether the connection electrode CE is formed with a gentle slope or a steep slope can vary depending on which opening boundary surface the connection electrode CE is formed along.

[0078] The connection structure of the connection electrode CE and the auxiliary driving low voltage line 174-1 in the structure of Figure 2 will be described.

[0079] Referring to Figure 2The width of the third opening OPpvx of the passivation layer 181 can be formed larger than the width of the second opening OPvia of the via layer 182, so that the boundary of the third opening OPpvx of the passivation layer 181 can be covered by the via layer 182. Thus, the connection electrode CE can have a structure in which the connection electrode CE is electrically connected to the auxiliary drive low voltage line 174-1 only through the second opening OPvia of the via layer 182.

[0080] The connection structure of the connection electrode CE and the auxiliary drive low voltage line 174-1 in the structure of Figure 3 will be discussed.

[0081] Referring to Figure 3 , the width of the third opening OPpvx of the passivation layer 181 can be formed narrower than the width of the second opening OPvia of the via layer 182, so that the boundary of the third opening OPpvx of the passivation layer 181 can be exposed without being covered by the via layer 182. Thus, the connection electrode CE can have a structure in which the connection electrode CE is connected to the auxiliary drive low voltage line 174-1 not only through the second opening OPvia of the via layer 182 but also through the third opening OPpvx of the passivation layer 181. For example, due to the abrupt change in the angle of the upper edge St-O of the third opening OPpvx of the passivation layer 181, the possibility that the conductive layer formed on the passivation layer 181 will be disconnected can be high.

[0082] The actual stacked structure of the conductive layer stacked on the upper edge St-O of the third opening OPpvx of the passivation layer 181 will be discussed. Figure 4

[0083] Figure 4 is a schematic photograph of a cross section of a portion of the light emitting display device.

[0084] In the structure of Figure 4 , only the passivation layer 181 can be positioned on the auxiliary drive low voltage line 174-1, and the via layer 182 can not be formed. In the structure of Figure 4 , the anode electrode Anode, the intermediate layer EL, and the cathode electrode Cathode included in the light emitting diode can be sequentially disposed on the passivation layer 181 in the third direction DR3. The encapsulation layer 400 can be formed on the cathode electrode Cathode to block external moisture and / or oxygen from entering the organic light emitting layer in the intermediate layer EL.

[0085] In the structure of Figure 4 , the anode electrode Anode includes a lower anode electrode layer Anode1 including a metal material and an upper anode electrode layer Anode2 formed of a transparent conductive oxide layer. Although the connection electrode CE is not shown in the structure of Figure 4 , the connection electrode CE can have a double layer structure similar to the anode electrode Anode.​

[0086] Referring to Figure 4 the dashed line in FIG. 18, the boundary surface of the passivation layer 181 can form a steep slope to form an angle close to 90 degrees (between 70 degrees and 90 degrees), and the cathode electrode Cathode in the conductive layer formed above the upper edge St-O of the boundary surface of the passivation layer 181 can be formed to be sharply curved so that a structure in which the thickness is significantly reduced exists above the upper edge St-O of the boundary surface of the passivation layer 181, making the structure extremely vulnerable to disconnection. Therefore, at least a portion of the upper edge St-O of the boundary surface of the passivation layer 181 can be formed to have a structure covered with the via layer 182 so that the cathode electrode Cathode can be positioned without disconnection. In Figure 4 FIG. 18, the anode electrode Anode can be shown to have a low disconnection possibility above the upper edge St-O of the boundary of the passivation layer 181 due to the anode electrode Anode having a double-layer structure, but there is still a possibility of disconnection in the case where the anode electrode Anode has a single-layer structure. This possibility of disconnection of the anode electrode Anode can also be applied to the connection electrode CE formed of the same material in the same layer. Therefore, as Figure 2 shown in FIG. 18, by covering at least a portion of the boundary of the third opening OPpvx of the passivation layer 181 with the via layer 182, the connection electrode CE can be formed to be electrically connected to the auxiliary driving low voltage line 174-1 only through the second opening OPvia of the via layer 182, thereby reducing the possibility of disconnection of the connection electrode CE.

[0087] Referring to Figure 1 the third opening OPpvx of the passivation layer 181 can be formed longer in the first direction DR1 than the second opening OPvia of the via layer 182, portions of the boundary of the third opening OPpvx of the passivation layer 181 positioned on both sides in the first direction DR1 can be covered with the via layer 182, and the connection electrode CE and the cathode electrode Cathode positioned above these portions are not vulnerable to disconnection, thereby making an electrical connection through these portions, having the advantage of preventing overall disconnection.

[0088] Hereinafter, structures in which a processing hole is additionally formed by laser drilling in Figures 5 to 7 will be discussed. Figure 1

[0089] Figure 5 is a schematic plan view of a laser drilling region in Figure 1 after laser drilling.

[0090] In Figure 5 , in addition to Figure 1 ​The processing hole LDP formed by the laser drilling can be shown outside the laser drilling area LDA. The processing hole LDP can be a circular structure in a plan view, and can have a planar shape different from the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181.

[0091] After the laser drilling is discussed as Figure 6 and Figure 7 the cross-sectional structure after the laser drilling is shown. Figure 5

[0092] Figure 6 and Figure 7 are schematic cross-sectional views taken along the cross-sectional line of Figure 5

[0093] Figure 6 is a schematic cross-sectional view taken along the cross-sectional line VI-VI' of Figure 5 and Figure 7 is a schematic cross-sectional view taken along the cross-sectional line VII-VII'.

[0094] In Figure 6 and Figure 7 compared to Figure 2 and Figure 3 , an intermediate layer EL and a cathode electrode Cathode can be further formed. The processing hole LDP formed by the laser drilling can be formed in the intermediate layer EL so that the cathode electrode Cathode and the connection electrode CE can be electrically connected through the processing hole LDP. As shown in Figure 19 , the intermediate layer EL can be positioned above the anode electrode Anode and the pixel defining layer 380, and in a case where the intermediate layer EL can be opened by the laser drilling, the processing hole LDP allowing the structure of the cathode electrode Cathode and the connection electrode CE to be electrically connected can be formed.

[0095] compared to Figure 6 , in Figure 7 , the upper edge St-O of the interface of the passivation layer 181 can be exposed, and the connection electrode CE and the cathode electrode Cathode can be stacked on the upper edge St-O of the interface of the passivation layer 181. In the vicinity of the boundary of the upper edge St-O of the passivation layer 181, the connection electrode CE and the cathode electrode Cathode can be disconnected, and at least a part of the interface of the passivation layer 181 can be formed so that the boundary of the upper edge St-O of the passivation layer 181 can be covered by the via layer 182.

[0096] Figures 5 to 7 ​​The position of the processed hole LDP shown in FIG. 6 can be positioned near the center of the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181. However, in actual laser drilling, the positioning of the processed hole LDP formed due to process errors can be formed at a different position. Therefore, it is desirable to determine whether the actually formed processed hole LDP is formed without a problem, and in Figure 8 A method of determining whether an error is present in laser drilling according to one embodiment is shown in FIG. 7.

[0097] Figure 8 is a schematic flowchart showing a method for determining whether an error is present in laser drilling according to an embodiment.

[0098] Referring to Figure 8 , the method for determining an error in laser drilling according to an embodiment can include the steps of identifying a center position of a connection electrode CE (step S10), identifying a center position of a processed hole LDP formed by laser drilling (step S20), calculating a relative distance between the center of the connection electrode CE and the center of the processed hole LDP (step S30), and determining whether an error is present in laser drilling based on the calculated relative distance (step S40).

[0099] A method for determining Figure 9 an error in laser drilling shown in FIG. 6 will be discussed. Figure 8

[0100] Figure 9 is a schematic diagram showing each center in one embodiment.

[0101] Figure 9 is a photograph of a laser drilling area LDA of a light emitting display panel on which laser drilling has been performed to form a processed hole LDP, and the center of the processed hole LDP and the center of a connection electrode CE are indicated.

[0102] Referring to Figure 8 and Figure 9 , the step S10 of determining a center position of a connection electrode CE in the method of judging an error in laser drilling can be a step of determining a center position of the connection electrode CE as shown in FIG. 6 after identifying a boundary of the connection electrode CE in a laser drilling area LDA. Figure 9

[0103] The step S20 of identifying a center position of a processed hole LDP formed by laser drilling can involve confirming a boundary of the processed hole LDP formed by laser drilling in a laser drilling area LDA, and then using the boundary to determine a center position of the processed hole LDP as shown in FIG. 7. Figure 9

[0104] ​​​As for the step of determining the center position of the connection electrode CE (step S10) and the step of determining the center position of the processing hole LDP (step S20), which step is performed first is not important, and thus both steps (step S10, step S20) can be performed simultaneously or interchangeably.

[0105] The step S30 of calculating the relative distance between the center of the connection electrode CE and the center of the processing hole LDP can be a step performed after the step S10 of identifying the center position of the connection electrode CE and the step S20 of identifying the center position of the processing hole LDP. The step S30 of calculating the relative distance between the center of the connection electrode CE and the center of the processing hole LDP can involve using the coordinates of the centers of the connection electrode CE and the processing hole LDP to calculate the distance between the two centers, the coordinates of the centers of the connection electrode CE and the processing hole LDP being determined in the step S10 of identifying the center position of the connection electrode CE and the step S20 of identifying the center position of the processing hole LDP, respectively.

[0106] For example, the center position of the connection electrode CE can be relatively constant in the plurality of laser drilling regions LDA. In contrast, the position of the processing hole LDP formed by laser drilling can have a relatively large positional change in each laser drilling region LDA. For example, the process of forming the connection electrode CE, which is a process for forming a fine pattern and has a relatively small process error, can be performed by depositing a conductive material, exposing / developing using a mask to form a photoresist, and then patterning the conductive material using the photoresist. On the other hand, the process of performing laser drilling can have a relatively large process error, so that the positioning of the processing hole LDP formed by laser drilling can vary depending on the laser drilling region LDA. Therefore, the distance calculated in the step S30 of calculating the relative distance between the center of the connection electrode CE and the center of the processing hole LDP can be used as a criterion for confirming the position in which the processing hole LDP is formed in the corresponding laser drilling region LDA.

[0107] Therefore, by the step S40 of determining whether there is an error in laser drilling based on the calculated relative distance, the position in which the processing hole LDP is formed in the corresponding laser drilling region LDA can be confirmed based on the calculated relative distance. For example, in the case where the calculated relative distance is greater than a certain value, it can be determined that there is an error in which laser drilling is performed outside the error range.

[0108] The key to determining the above-described laser drilling error can be the step of determining the center position of the connection electrode CE (step S10) and the step of determining the center position of the processing hole LDP (step S20), and the boundaries of the connection electrode CE and the boundaries of the processing hole LDP must be individually identified so that the position of each center can be identified. In the case where it is difficult to identify the boundaries of the connection electrode CE or the boundaries of the processing hole LDP, the use ofFigure 8 The method of the related art cannot determine an error in laser drilling. The connection electrode CE can be formed in a wide range in the laser drilling area LDA, so that the boundary is easily identified, but the boundary of the processing hole LDP can overlap with other openings (the second openings OPvia of the via layer 182 and / or the third openings OPpvx of the passivation layer 181) (see Figure 13 ), causing it to be difficult to accurately identify the boundary of the processing hole LDP.

[0109] The shape of the second openings OPvia of the via layer 182 and / or the shape of the third openings OPpvx of the passivation layer 181 can be formed in a shape different from the circular shape of the processing hole LDP, thereby clearly determining whether there is an error in laser drilling. For example, in Figure 5 an embodiment, the second openings OPvia of the via layer 182 and the third openings OPpvx of the passivation layer 181 can each be formed in a rectangular shape elongated in one direction. Accordingly, the center position of the processing hole LDP can be clearly checked to confirm whether laser drilling has been properly performed and prevent a problem caused by laser drilling.

[0110] In the above, the structure of the Figure 1 is discussed with focus on the structure of the laser drilling area LDA. However, in other embodiments, various embodiments are possible, and in the following, five embodiments including the embodiment of Figure 10 and their characteristics will be described in Figure 1 .

[0111] Figure 10 is a schematic table summarizing various embodiments and their characteristics.

[0112] In Figure 10 , Embodiment 1 to Embodiment 5 (e.g., Embodiment 1 to Embodiment 5) are shown, and for each embodiment, a structure including the passivation layer 181 having the third openings OPpvx formed in the passivation layer 181 (e.g., PVX of Figure 10 ) and a structure not including the passivation layer 181 (e.g., not including PVX of Figure 10 ) are shown.

[0113] The structure including the passivation layer 181 (e.g., PVX of Figure 10 ) will be discussed.

[0114] Embodiment 1 (e.g., Embodiment 1 of Figure 10 ) can have the same planar structure as the above-described Figure 1 Embodiment 2 and Embodiment 3 (e.g., Embodiment 2 and Embodiment 3 of Figure 10Embodiment 2 and Embodiment 3) can be an embodiment in which a planar shape of the second opening OPvia of the via layer 182 and / or a planar shape of the third opening OPpvx of the passivation layer 181 is changed from Embodiment 1, and the first opening OPpdl of the connection electrode CE and the pixel definition layer 380 can have the same shape as Embodiment 1. Figure 1

[0115] In Embodiment 2, the second opening OPvia of the via layer 182 can have an octagonal shape cut in a vertical direction, and the third opening OPpvx of the passivation layer 181 can have a rectangular shape elongated in a horizontal direction. The second opening OPvia of the via layer 182 can be formed to be wider in the vertical direction than the third opening OPpvx of the passivation layer 181. It can be seen that a portion of the third opening OPpvx of the passivation layer 181 does not overlap the second opening OPvia of the via layer 182, and thus has a structure covered by the via layer 182.

[0116] In Embodiment 3, the third opening OPpvx of the passivation layer 181 can have an octagonal shape cut in a vertical direction, the second opening OPvia of the via layer 182 can have a structure elongated in a horizontal direction, and the second opening OPvia of the via layer 182 can be formed with a narrower width in the vertical direction than a width of the third opening OPpvx of the passivation layer 181. In Embodiment 3, it can be seen that at least a portion of the third opening OPpvx of the passivation layer 181 does not overlap the second opening OPvia of the via layer 182, and thus has a structure covered by the via layer 182.

[0117] In Embodiments 1 to 3, the second opening OPvia of the via layer 182 and / or the third opening OPpvx of the passivation layer 181 can not have a circular shape, and different planar shapes of the second opening OPvia of the via layer 182 and / or the third opening OPpvx of the passivation layer 181 make the second opening OPvia of the via layer 182 and / or the third opening OPpvx of the passivation layer 181 easily distinguishable from a processing hole LDP formed by laser drilling.

[0118] Meanwhile, Embodiment 4 (for example, Figure 10 ​Embodiment 4) can have a structure in which the third opening OPpvx of the passivation layer 181 is aligned with the first opening OPpdl of the pixel-defining layer 380 in a plan view, and the second opening OPvia of the via layer 182 can be positioned in the third opening OPpvx of the passivation layer 181 and the first opening OPpdl of the pixel-defining layer 380 in a plan view. Thus, in Embodiment 4), it can be seen that the boundary of the third opening OPpvx of the passivation layer 181 does not overlap the second opening OPvia of the via layer 182, and thus has a structure covered with the via layer 182.

[0119] In Embodiment 4), the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 can each have an octagonal shape, such that the actual formed planar shape can be close to a circular shape, and it can not be distinguished from the machining hole LDP formed by laser drilling and the planar shape. However, in Embodiment 4), the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 can be formed to have a size that is the same as the size of the first opening OPpdl of the pixel-defining layer 380 or is at least about 80% of the size of the first opening OPpdl of the pixel-defining layer 380, and can be formed to be significantly larger than the size of the machining hole LDP, and can be easily distinguished from the machining hole LDP. In an exemplary embodiment, the third opening OPpvx of the passivation layer 181 can be flush with the first opening OPpdl of the pixel-defining layer 380 in a plan view.

[0120] Unlike the previous embodiments, Embodiment 5 (e.g., Figure 10 Embodiment 5) of the present application can have a structure in which a portion of the second opening OPvia of the via layer 182 and a portion of the third opening OPpvx of the passivation layer 181 are formed to protrude outwardly in a position that does not overlap the first opening OPpdl of the pixel-defining layer 380 in a plan view. For example, a portion of the second opening OPvia of the via layer 182 and a portion of the third opening OPpvx of the passivation layer 181 overlap the first opening OPpdl of the pixel-defining layer 380 in a plan view, but the remaining portion can not overlap the first opening OPpdl of the pixel-defining layer 380. In Embodiment 5), the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 can be electrically connected to the connection electrode CE corresponding to the portion protruding outwardly from the first opening OPpdl of the pixel-defining layer 380 in a plan view, and the connection electrode CE can also have a structure further including an extension portion.

[0121] Based on Figure 6 and Figure 7The light-emitting display device according to Embodiments 1 to 4 may include a substrate (see Embodiment 1). Figure 19 110), a voltage line (e.g., an auxiliary driving low voltage line 174-1) positioned on the substrate to transmit a constant voltage, a passivation layer 181 positioned on the voltage line, a via layer 182 positioned on the passivation layer 181, a connection electrode CE positioned on the via layer 182, a pixel defining layer 380 positioned above the connection electrode CE, and a cathode electrode Cathode positioned on the pixel defining layer 380. The pixel defining layer 380 may have a first opening OPpdl overlapping the connecting electrode CE in a planar view. The via layer 182 may have a second opening OPvia overlapping the connecting electrode CE in a planar view. The passivation layer 181 may have a third opening OPpvx overlapping the connecting electrode CE in a planar view. The cathode electrode and the connecting electrode CE can be electrically connected through the first opening OPpdl of the pixel defining layer 380. The voltage line and the connecting electrode CE can be electrically connected through the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181. The third opening OPpvx of the passivation layer 181 may at least partially not overlap with the second opening OPvia of the via layer 182 in a planar view. For example, in a planar view, the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 may be positioned within the first opening OPpdl of the pixel defining layer 380. The second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 may have a planar shape instead of a circular shape. For example, the second opening OPvia of the via layer 182 can have various polygonal planar shapes (such as triangles, rectangles, hexagons and octagons), or a planar shape in which a polygonal shape is truncated.

[0122] based on Figure 6 and Figure 7 The light-emitting display device according to embodiment 5 may include a substrate (see embodiment 5). Figure 19the first opening OPpdl of the pixel definition layer 380, the second opening OPvia of the via layer 182, and the third opening OPpvx of the passivation layer 181 can not overlap with the first opening OPpdl of the pixel definition layer 380 in the plan view. The cathode electrode Cathode and the connection electrode CE can be electrically connected through the first opening OPpdl of the pixel definition layer 380, the voltage line and the connection electrode CE can be electrically connected through the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181, and at least a part of the second opening OPvia of the via layer 182 and / or the third opening OPpvx of the passivation layer 181 can have a structure not overlapping with the first opening OPpdl of the pixel definition layer 380 in the plan view.

[0123] Meanwhile, a structure excluding the passivation layer 181 (excluding PVX) is as follows.

[0124] In each of Embodiments 1 to 5 (for example, Embodiments 1 to 5 of the light emitting display device 100 of Figure 10 , the third opening OPpvx of the passivation layer 181 can be omitted, and in Embodiments 1 to 3 (for example, Embodiments 1 to 3), the second opening OPvia of the via layer 182 can have a polygonal planar shape, rather than a circular shape, and can be planarly distinguished from the processing hole LDP, and in Embodiment 4 (for example, Embodiment 4 of the light emitting display device 100 of Figure 10 , the second opening OPvia of the via layer 182 can have an octagonal shape and can be similar to a circle, but by having a size corresponding to the first opening OPpdl of the pixel definition layer 380, the size of the second opening OPvia of the via layer 182 is distinguished from the processing hole LDP.

[0125] Based on Figure 6 and Figure 7 , the light emitting display device according to Embodiments 1 to 4 (for example, Embodiments 1 to 4 of the light emitting display device 100 of Figure 10 , excluding the passivation layer 181 (for example, excluding PVX) of Figure 10 may include a substrate (see Figure 19The via layer 182 comprises: a voltage line (e.g., an auxiliary driving low voltage line 174-1) positioned on the substrate for transmitting a constant voltage; a via layer 182 positioned above the voltage line; a connection electrode CE positioned above the via layer 182; a pixel defining layer 380 positioned above the connection electrode CE; and a cathode electrode Cathode positioned above the pixel defining layer 380. The pixel defining layer 380 may have a first opening OPpdl overlapping the connection electrode CE in a planar view. The via layer 182 may have a second opening OPvia overlapping the connection electrode CE in a planar view. The cathode electrode Cathode and the connection electrode CE can be electrically connected through the first opening OPpdl of the pixel defining layer 380, and the voltage line and the connection electrode CE can be electrically connected through the second opening OPvia of the via layer 182. The second opening OPvia of the via layer 182 may have a non-circular planar shape. For example, the second opening OPvia of the via layer 182 may have various polygonal planar shapes (such as triangles, rectangles, hexagons, and octagons), or a planar shape with a truncated polygonal shape.

[0126] In implementation 5 (for example, Figure 10 In embodiment 5), the second opening OPvia of the via layer 182 may have a portion protruding outward from the first opening OPpdl of the pixel limiting layer 380, such that in the plan view, the portion of the second opening OPvia of the via layer 182 may not overlap with the first opening OPpdl of the pixel limiting layer 380.

[0127] based on Figure 6 and Figure 7 According to embodiment 5, the passivation layer 181 is not included (for example, Figure 10 Light-emitting display devices (excluding PVX) may include substrates (see [link to documentation]). Figure 19 The via layer 182 comprises: a voltage line (e.g., an auxiliary driving low voltage line 174-1) positioned above the substrate and transmitting a constant voltage; a via layer 182 positioned above the voltage line; a connection electrode CE positioned on the via layer 182; a pixel defining layer 380 on top of the connection electrode CE; and a cathode electrode Cathode positioned above the pixel defining layer 380. The pixel defining layer 380 may have a first opening OPpdl that overlaps with the connection electrode CE in a planar view. The via layer 182 may have a second opening OPvia that overlaps with the connection electrode CE in a planar view. The cathode electrode Cathode and the connection electrode CE can be electrically connected through the first opening OPpdl of the pixel defining layer 380, and the voltage line and the connection electrode CE can be electrically connected through the second opening OPvia of the via layer 182. At least a portion of the second opening OPvia of the via layer 182 may have a structure that does not overlap with the first opening OPpdl of the pixel defining layer 380 in a planar view.

[0128] In Figure 10 Embodiment 1 to Embodiment 5, each width of the first opening OPpdl of the pixel-defining layer 380 viewed in one direction can be as follows.

[0129] Except for Embodiment 5, all the first openings OPpdl of the pixel-defining layer 380 can have the same width, and in Embodiment 5, part of the second opening OPvia of the via layer 182 and / or part of the third opening OPpvx of the passivation layer 181 can protrude outside the first opening OPpdl of the pixel-defining layer 380, and the first opening OPpdl of the pixel-defining layer 380 can also be formed slightly larger.

[0130] In Figure 10 Embodiment 1 to Embodiment 5, each area of the connection electrode CE can be as follows.

[0131] The connection electrode CE of Embodiment 1 to Embodiment 4 can have the same area, but in Embodiment 5, the connection electrode CE can be part of the second opening OPvia of the via layer 182 and / or part of the third opening OPpvx of the passivation layer 181, and the connection electrode CE can also be formed slightly larger while protruding outside the first opening OPpdl of the pixel-defining layer 380.

[0132] Regarding Embodiment 1 to Embodiment 5 as described above, Figure 10 The items “whether overlapping”, “Cathode break”, “LD (laser drilling) check”, and “LD process” are additionally described.

[0133] “Whether overlapping” can refer to whether the first opening OPpdl of the pixel-defining layer 380 overlaps with the second opening OPvia of the via layer 182 or the third opening OPpvx of the passivation layer 181 in a plan view, and Embodiment 1 to Embodiment 4 all overlap, but only Embodiment 5 can have a structure in which the first opening OPpdl of the pixel-defining layer 380 partially does not overlap with the second opening OPvia of the via layer 182 or the third opening OPpvx of the passivation layer 181.

[0134] “Cathode break”, “LD check”, and “LD process” can be used to determine whether there is a risk of defects during the actual manufacturing process in each embodiment, and each has the following meaning.

[0135] As Figure 4As shown, "Cathode open" can refer to whether the cathode electrode Cathode can be open due to the upper edge St-O of the interface of the passivation layer 181, which represents an embodiment with no possibility of opening and some embodiments with a possibility of opening in some areas.

[0136] In embodiment 1, the upper and lower boundaries of the third opening OPpvx of the passivation layer 181 can be exposed by the second opening OPvia of the via layer 182, so that there is a possibility of opening on both sides. However, in embodiment 1, the left and right boundaries of the third opening OPpvx of the passivation layer 181 can be positioned outside the second opening OPvia of the via layer 182 and can be covered with the via layer 182, so that there is no possibility of opening at this part. Therefore, it can have a structure in which the cathode electrode Cathode is electrically connected through this part. In embodiment 2 and embodiment 3, the right boundary or the left boundary of the third opening OPpvx of the passivation layer 181 can be exposed by the second opening OPvia of the via layer 182, so that there is a possibility of opening on one side. However, since the other part of the third opening OPpvx of the passivation layer 181 can be positioned outside the second opening OPvia of the via layer 182 and can be covered with the via layer 182, there is no possibility of opening in this part. In embodiment 4 and embodiment 5, the boundaries of the third opening OPpvx of the passivation layer 181 can all be positioned outside the second opening OPvia of the via layer 182 so that there is no possibility of opening.

[0137] "LD check" can indicate whether the method for determining whether there is an error in the laser drilling clearly identifies the error. Figure 8 As shown, "Shape differentiation" can indicate that the shape of the second opening OPvia of the via layer 182 and / or the third opening OPpvx of the passivation layer 181 is formed differently from the circular shape of the processed hole LDP, allowing the boundary and center of the processed hole LDP to be identified, thus being able to determine the error in the laser drilling. "No possibility" can indicate an example in which a difference in the size or position of the processed hole LDP allows the boundary and center of the processed hole LDP to be identified, thus being able to determine the error in the laser drilling.

[0138] "LD process" can indicate whether there is a possibility of a problem occurring during the laser drilling process, but since each embodiment is formed without a problem in the laser drilling process, all embodiments are described as "no possibility".

[0139] Referring to the above Figure 10In Embodiments 1 to 5, the overlapping openings OPpdl, OPvia, and OPpvx can be positioned in the laser drilling area LDA, and the connection electrode CE can be electrically connected to the lower auxiliary driving low voltage line 174-1, because the structure and the structure electrically connected to the upper cathode electrode Cathode are positioned to overlap each other, the area of the laser drilling area LDA can be formed narrow, which can have the advantage that laser drilling can be performed even in a high resolution light emitting display device.

[0140] Since the second opening OPvia of the via layer 182 and / or the third opening OPpvx of the passivation layer 181 are formed in a shape different from the circular shape of the processing hole LDP, Embodiments 1 to 3 can have the advantage that the center of the processing hole LDP can be identified due to the difference in shape. Thus, in the method shown in FIG. 10, the presence of an error in laser drilling can be determined. In Embodiments 1 to 3, a portion of the third opening OPpvx of the passivation layer 181 can protrude to not overlap the second opening OPvia of the via layer 182 in a plan view, and the boundary of the third opening OPpvx of the passivation layer 181 is covered by the via layer 182 at the portion, so that the conductive layer positioned at the top can have a structure in which electrical connection is not continuously made. Figure 8

[0141] Embodiments 4 and 5 can have processing holes LDP and openings (second openings OPvia of the via layer 182 and / or third openings OPpvx of the passivation layer 181) that are different in size or position.

[0142] In Embodiment 4, openings different in size from the processing hole LDP can be included. Thus, Embodiment 4 can have the advantage that whether an error is present in laser drilling can be identified in a manner similar to that shown in FIG. 10, because the second opening OPvia in the via layer 182 and the third opening OPpvx in the passivation layer 181 are formed in a size the same as or equal to the size of the first opening OPpdl in the pixel defining layer 380, and are formed larger than the processing hole LDP, so it is easy to distinguish the second opening OPvia in the via layer 182 and the third opening OPpvx in the passivation layer 181 from the processing hole LDP. The third opening OPpvx of the passivation layer 181 can be formed larger than the second opening OPvia of the via layer 182, so that all the boundaries of the third opening OPpvx of the passivation layer 181 are covered by the via layer 182, allowing the conductive layer positioned above to have a structure in which electrical connection is not continuously made. Figure 8

[0143] ​​Embodiment 5 can include an opening whose position is different from that of the processing hole LDP. For example, Embodiment 5 can have a structure in which a part of the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 are formed in a position in which the first opening OPpdl of the pixel definition layer 380 does not overlap in a plan view and protrude outward. Thus, the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 can be easily distinguished from the processing hole LDP, and have an advantage that it is possible to determine whether there is an error in laser drilling using the method shown in Figure 8 The third opening OPpvx of the passivation layer 181 can be formed larger than the second opening OPvia of the via layer 182 so that all the boundaries of the third opening OPpvx of the passivation layer 181 are covered by the via layer 182, allowing the electrically conductive layer positioned above to be electrically connected without being disconnected.

[0144] The structure of the comparative example will be discussed using Figures 11 to 13 and the relationship between the processing hole LDP and the openings in the comparative example.

[0145] Figure 11 is a schematic plan view showing a structure of a laser-drilled region according to the comparative example, Figure 12 is a schematic cross-sectional view of the laser-drilled region of the comparative example of Figure 11 , and Figure 13 is a schematic photograph taken after performing laser drilling in the laser-drilled region of the comparative example of Figure 11

[0146] Referring to Figure 11 and Figure 12 , unlike the embodiments in Figure 1 and Embodiments 1 to 5 in Figure 10 , the planar structure (e.g., the structure in a plan view) of the comparative example can have a structure in which the processing hole LDP formed by laser drilling does not differ in shape, position, and size from the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181.

[0147] Figure 13 is a schematic photograph taken after the processing hole LDP has been formed in the comparative example, and the processing hole LDP overlaps the openings OPvia, OPpvx and has a shape and size similar to those of the openings OPvia, OPpvx, making it difficult to clearly identify the boundaries of the processing hole LDP.

[0148] ​For example, in the comparative example, the second openings OPvia of the via layer 182 and the third openings OPpvx of the passivation layer 181 can have an octagonal shape that is technically different from the circular shape of the processing holes LDP, but in actual photographs (see Figure 13 ), it is difficult to distinguish the processing holes LDP from the second openings OPvia of the via layer 182 and the third openings OPpvx of the passivation layer 181 because they all have a circular shape or a similar shape. In the comparative example, the sizes of the processing holes LDP, the second openings OPvia of the via layer 182, and the third openings OPpvx of the passivation layer 181 can not be different enough to be easily distinguished, and their positions can be formed at overlapping positions so that they are difficult to distinguish.

[0149] Therefore, even if the method of determining the laser drilling error as shown in Figure 8 is used, there can be a disadvantage in that it is difficult to determine whether there is a laser drilling error due to the difficulty of checking the center of the processing hole LDP.

[0150] The shapes of the comparative examples can be changed from the shapes in Figure 11 and Figure 12 , and various comparative examples will be discussed through Figure 14 .

[0151] Figure 14 is a schematic table summarizing various comparative examples and their characteristics.

[0152] In Figure 14 , Comparative Examples 1 to 5 (for example, Comparative Examples 1 to 5 of Figure 14 ) are included, and each example is shown in the case of distinguishing between a structure including the passivation layer 181 and formed with the third openings OPpvx of the passivation layer 181 (for example, the PVX-including of Figure 14 ) and a structure not including the passivation layer 181 (for example, the PVX-not-including of Figure 14 ).

[0153] Comparative Example 5 including the passivation layer 181 is the same as the comparative example of Figure 11 .

[0154] In Figure 14 , a table corresponding to the table in Figure 10 is described by comparing the same items as in Figure 10 .

[0155] In each comparative example, the width of the first openings OPpdl of the pixel definition layer 380 in one direction can be as follows.

[0156] In Figure 14The size of the first opening OPpdl of the pixel-defining layer 380 can vary in each of the comparative examples, and thus the width can also vary. Comparative example 1 and comparative example 2 can have the same width for the first opening OPpdl of the pixel-defining layer 380, and comparative example 3 and comparative example 5 can have the same width for the first opening OPpdl of the pixel-defining layer 380. Based on the width of the first opening OPpdl of the pixel-defining layer 380, comparative example 1 and comparative example 2 can have the largest value, comparative example 3 and comparative example 5 can have an intermediate value, and comparative example 4 can have the smallest value.

[0157] Figure 14 The area of the connection electrode CE in each of the comparative examples can be as follows.

[0158] In Figure 14 The area of the connection electrode CE can vary in each of the comparative examples. Based on the area of the connection electrode CE, the area can decrease in the order of comparative example 1, comparative example 2, comparative example 3, comparative example 4, and comparative example 5.

[0159] As Figure 10 and Figure 8 It can be known by "whether overlapping" whether the first opening OPpdl of the pixel-defining layer 380 and the second opening OPvia of the via layer 182 or the third opening OPpvx of the passivation layer 181 overlap in the plane.

[0160] For example, comparative example 1 and comparative example 5 can have the first opening OPpdl of the pixel-defining layer 380 and the second opening OPvia of the via layer 182 or the third opening OPpvx of the passivation layer 181 overlapping in the plan view, but comparative examples 2 to 4 have a structure in which the first opening OPpdl of the pixel-defining layer 380 and the second opening OPvia of the via layer 182 or the third opening OPpvx of the passivation layer 181 do not overlap in the plan view ("not overlapping").

[0161] By "cathode disconnection", "LD inspection", and "LD process", it can be checked that there is a risk of defects occurring during the actual manufacturing process.

[0162] The "cathode disconnection" can not occur in each comparative example, as in Comparative Example 1 to Comparative Example 4, the separate connection electrode CE can be electrically connected to the lower auxiliary drive low voltage line 174-1, so that the third opening OPpvx of the passivation layer 181 is formed larger than the second opening OPvia of the via layer 182, and the boundary of the third opening OPpvx of the passivation layer 181 is covered by the via layer 182, which ensures that the conductive layer positioned above is not disconnected and remains electrically connected. In Comparative Example 5, the third opening OPpvx of the passivation layer 181 can be formed larger than the second opening OPvia of the via layer 182, so that the conductive layer positioned at the top is electrically connected without disconnection.

[0163] The "LD inspection" indicates whether the method of determining whether there is an error in the laser drilling shown in Figure 8 can clearly identify the error in the laser drilling. Comparative Examples 1 to 4 can distinguish the position where the processing hole LDP is to be formed (inside the first opening OPpdl of the pixel defining layer 380) from the third opening OPpvx of the passivation layer 181 and / or the second opening OPvia of the via layer 182, so there is no problem in identifying the boundary of the processing hole LDP. Therefore, by applying the method for determining whether there is a laser drilling error in Figure 13 , the laser drilling error can be clearly confirmed. However, Comparative Example 5 can have a small laser drilling area, but in the case of forming the processing hole LDP, as shown in Figure 8 , the processing hole LDP can overlap the third opening OPpvx of the passivation layer 181 and / or the second opening OPvia of the via layer 182, making it difficult to identify the boundary of the processing hole LDP, thus making it difficult to apply the method of determining errors in laser drilling shown in Figure 14

[0164] In each comparative example, the "LD process" can indicate whether there is a possibility of a problem occurring during the laser drilling process, but since each comparative example is also constructed without a problem in the laser drilling process, all comparative examples are described as "no possibility".

[0165] Referring to the above Figure 13 , each comparative example can have the following characteristics.

[0166] ​Comparative Example 2 to Comparative Example 4 can be shown, in which the position of the first opening OPpdl of the pixel-defining layer 380 for electrically connecting the connection electrode CE to the cathode electrode Cathode overlaps with the position of the second opening OPvia of the via layer 182 and the third opening OPpvx of the passivation layer 181 for electrically connecting the connection electrode CE to the lower auxiliary driving low-voltage line 174-1. Unlike Comparative Example 2 to Comparative Example 4, Comparative Example 1 can be different in that it also forms the second opening OPvia of the via layer 182 overlapping with the connection electrode CE and / or the third opening OPpvx of the passivation layer 181. However, Comparative Example 1 to Comparative Example 4 can have a disadvantage in that the area occupied by the laser-drilling area LDA is larger than that of the embodiment, resulting in difficulty in applying to high-resolution light-emitting display devices.

[0167] Comparative Example 5 can be shown, as in the embodiment, the position of the first opening OPpdl of the pixel-defining layer 380 for electrically connecting the connection electrode CE to the cathode electrode Cathode overlaps with the position of the second opening OPvia in the via layer 182 and / or the third opening OPpvx in the passivation layer 181 for electrically connecting the connection electrode CE to the lower auxiliary driving low-voltage line 174-1, enabling laser drilling even in high-resolution light-emitting display devices. However, as shown, it is difficult to clearly confirm the boundary of the processed hole LDP formed by laser drilling, making it difficult to determine whether there is an error in laser drilling using a method for determining whether there is an error in laser drilling as shown in Figure 8 Figure 15 Thus, it has a disadvantage of being unable to determine an error, making it difficult to detect a problem such as a short circuit in an actual panel.

[0168] Hereinafter, structures of comparative examples having a high disconnection possibility will be discussed. Figure 15

[0169] Figure 15 is a schematic plan view showing a structure of a laser-drilling area according to another comparative example.

[0170] Figure 1 Comparative Example 1 can be similar to Figure 15 ​​The third opening OPpvx of the passivation layer 181 can have a rectangular shape elongated in the second direction DR2 similar to the second opening OPvia of the via layer 182, and the third opening OPpvx of the passivation layer 181 is positioned in the second opening OPvia of the via layer 182. Thus, Figure 3 The cross-sectional structure of the comparative example in Figure 7 and Figure 15 .

[0171] In the comparative example of Figure 8 , the third opening OPpvx of the passivation layer 181 and the second opening OPvia of the via layer 182 can have a rectangular shape distinguished from the circular shape of the processing hole LDP, allowing the use of the method of judging whether there is an error in the laser drilling as shown in Figure 4 However, the third opening OPpvx of the passivation layer 181 can be positioned in the second opening OPvia of the via layer 182, resulting in the boundary of the third opening OPpvx of the passivation layer 181 being exposed and not being completely covered by the via layer 182. Referring to Figure 15 When the side slope of the passivation layer 181 is steeply formed, the possibility of disconnection of the conductive layer such as the cathode electrode Cathode positioned on the top of the passivation layer 181 is high. Thus, Figure 14 The comparative example of

[0172] As shown in Figure 15 and Figure 1 , the embodiments that overcome the problems occurring in the comparative example can include other embodiments in addition to the embodiment of Figure 10 and the embodiments 1 to 5 of Figure 16 The structure of another embodiment can be discussed below by Figure 17 and Figure 16 .

[0173] Figure 17 and Figure 16 are schematic plan views showing the structure of a laser drilling region according to another embodiment.

[0174] In the embodiments of Figure 17 and Figure 16 , the shape of the second opening OPvia of the via layer 182 and / or the shape of the third opening OPpvx of the passivation layer 181 can be formed to be different from the circular shape of the processing hole LDP.

[0175] In the embodiments of Figure 16In an embodiment of the passivation layer 181, the third opening OPpvx can have a shape of a triangle, which can be distinguished from the processing hole LDP having a circular shape. In Figure 17 In an embodiment of the passivation layer 181, the third opening OPpvx can have a shape of a triangle, which can be distinguished from the processing hole LDP having a circular shape. In

[0176] In an embodiment of the passivation layer 181, the third opening OPpvx can have a shape of a triangle, which can be distinguished from the processing hole LDP having a circular shape. In Figure 17 In an embodiment of the passivation layer 181, the third opening OPpvx can have a shape of a rectangle, similar to the shape of the second opening OPvia of the via layer 182, but the extension direction of the longer side of the third opening OPpvx of the passivation layer 181 and the second opening OPvia of the via layer 182 can be different. For example, the longer side can mean the longest side among the sides of the planar structure of each opening. The longer side of the third opening OPpvx of the passivation layer 181 can extend in a first direction DR1, and the longer side of the second opening OPvia of the via layer 182 can extend in a second direction DR2 perpendicular to the first direction DR1. In Figure 17 In an embodiment of the passivation layer 181, the third opening OPpvx can have a shape of a triangle, which can be distinguished from the processing hole LDP having a circular shape. In Figure 17 In an embodiment of the passivation layer 181, the third opening OPpvx can have a shape of a triangle, which can be distinguished from the processing hole LDP having a circular shape. In

[0177] In other embodiments, unlike in Figure 18 In other embodiments, unlike in

[0178] The above description focuses on the shape of the laser drilling area LDA of the light emitting display apparatus, but in the light emitting display apparatus, a light emitting diode and a pixel driver that transmits a current to the light emitting diode are formed around the laser drilling area LDA. The pixel driver can be positioned on a substrate, the light emitting diode can be positioned on the pixel driver, and it will be discussed that some layers of the light emitting display apparatus including the pixel driver are schematically stacked. Figure 19 and Figure 18 The above description focuses on the shape of the laser drilling area LDA of the light emitting display apparatus, but in the light emitting display apparatus, a light emitting diode and a pixel driver that transmits a current to the light emitting diode are formed around the laser drilling area LDA. The pixel driver can be positioned on a substrate, the light emitting diode can be positioned on the pixel driver, and it will be discussed that some layers of the light emitting display apparatus including the pixel driver are schematically stacked.

[0179] A mask for a schematic stack structure and manufacturing sequence based on Figure 18 will be discussed.

[0180] Figure 18 is a table schematically showing steps for manufacturing some layers of a light emitting display device according to an embodiment.

[0181] In Figure 18 , a pixel driver positioned on top of a substrate of a light emitting display device, an anode electrode belonging to a light emitting diode positioned above the pixel driver, and a pixel defining layer 380 separating the anode electrode are described.

[0182] Referring to Figure 18 , a lower shielding layer BML can be positioned on a substrate, and a buffer layer 111 can be positioned on the lower shielding layer BML. A semiconductor layer ACT formed of a silicon semiconductor (e.g., a polycrystalline semiconductor (P-Si)) or an oxide semiconductor can be positioned on the buffer layer 111. A gate insulating layer 141 can be positioned on the semiconductor layer ACT, and a gate conductive layer Gate can be positioned on the gate insulating layer 141. An interlayer insulating layer 161 can be positioned on the gate conductive layer Gate, and a data conductive layer SD can be positioned on the interlayer insulating layer 161. A passivation layer 181 and a via layer 182 can be sequentially formed on the data conductive layer SD, and an anode layer including an anode electrode Anode and a connection electrode CE can be positioned on the via layer 182. A pixel defining layer 380 including an opening can be formed on the anode layer.

[0183] In Figure 19 , layers using masks are also designated, and a total of 9 masks used until the pixel defining layer 380 are shown. For example, a first mask 1 can be used to form the lower shielding layer BML, a second mask 2 can be used to form the semiconductor layer ACT, a third mask 3 can be used to form the gate conductive layer Gate, a fourth mask 4 can be used to form contact openings in the interlayer insulating layer 161, the gate insulating layer 141, and / or the buffer layer 111, a fifth mask 5 can be used to form the data conductive layer SD, a sixth mask 6 can be used to form contact openings in the passivation layer 181, a seventh mask 7 can be used to form contact openings in the via layer 182, an eighth mask 8 can be used to form the anode layer including the anode electrode Anode and the connection electrode CE, and a ninth mask 9 can be used to form an opening in the pixel defining layer 380. Through the ninth mask 9, the pixel defining layer 380 can form an opening exposing the anode electrode Anode (see OP in Figure 1 , and a first opening OPpdl shown in Figure 18 .

[0184] A light emitting diode can be positioned on the pixel driver, and have asFigure 19 The pixel driver of the light emitting display apparatus of the stack structure shown can have a structure as shown in Figure 19 the cross-sectional structure.

[0185] Figure 19 is a schematic cross-sectional view of a light emitting display apparatus according to an embodiment.

[0186] The light emitting diode includes a cathode electrode Cathode, an intermediate layer EL including a functional layer FL and a light emitting layer EML, and an anode electrode Anode, and can be separated from an adjacent light emitting diode by a pixel defining layer 380. In Figure 19 In the cross-sectional view, layers corresponding to the cathode electrode Cathode, the pixel defining layer 380, the intermediate layer EL including the functional layer FL and the light emitting layer EML, and the anode electrode Anode can also be referred to as light emitting device layers.

[0187] In Figure 19 , layers positioned below the light emitting device layers (i.e., below the anode electrode Anode) and layers positioned further below can also be referred to as driver device layers, in which pixel drivers that generate current and transmit the current to the light emitting diode can be positioned. The pixel drivers include transistors and capacitors, and conductive layers, semiconductor layers, and insulating layers constituting the transistors and the capacitors can be positioned in the driver device layers.

[0188] Figure 19 A simplified cross-sectional structure of one light emitting diode and one pixel driver included in one pixel can be shown, the pixel having an opening OP positioned in the pixel defining layer 380 and a path through which current is transmitted from the transistor of the pixel driver to the anode electrode Anode.

[0189] Figure 2 A simplified diagram of the structure of the lower portion of the anode electrode (e.g., the structure of the driver device layers) can be shown, and only one transistor is shown. A brief overview of the driver device layer structure from the substrate 110 to the via layer 182 is as follows.

[0190] The substrate 110 can include a material having a rigid property and not bending, such as glass, or can include a flexible material that can bend, such as plastic or polyimide. In the case of a flexible substrate, the substrate 110 can have a structure of a double layer structure formed with polyimide on a repeated structure and a barrier layer formed of an inorganic insulating material.

[0191] A lower shield layer BML including a metal can be positioned on the substrate 110, and the lower shield layer BML can overlap a channel of one of the transistors positioned in a pixel driver including in a pixel in a plan view. In other embodiments, a drive low voltage line to which a drive low voltage ELVSS is applied can be positioned on the same layer as the lower shield layer BML. For example, the drive low voltage line can be a voltage line electrically connected to the auxiliary drive low voltage line 174-1.

[0192] The substrate 110 and the lower shield layer BML can be covered by a buffer layer 111. The buffer layer 111 can be used to block impurity elements from penetrating into a semiconductor layer ACT, and can be an inorganic insulating layer including silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON x ).

[0193] A semiconductor layer ACT formed of a silicon semiconductor (e.g., a polycrystalline semiconductor (P-Si)) or an oxide semiconductor can be positioned on the buffer layer 111. The semiconductor layer ACT can be a semiconductor layer positioned in a pixel driver included in a pixel, and can include a channel of a transistor driving the transistor and a first region and a second region positioned on both sides of the channel. For example, the channel of the transistor can be a portion of the semiconductor layer ACT overlapping a gate electrode GE, and the first region and the second region can be portions of the semiconductor layer ACT not overlapping the gate electrode GE. For example, the first region and the second region positioned on both sides of the channel of the semiconductor layer ACT can not be covered by the gate electrode GE, and can be processed by plasma or doped to have a conductive layer characteristic, allowing the first region and the second region to function as a first electrode and a second electrode of the transistor.

[0194] A gate insulating layer 141 can be positioned on the semiconductor layer ACT and the buffer layer 111. The gate insulating layer 141 can be an inorganic insulating layer including silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON x ).

[0195] A gate conductive layer including a gate electrode GE of a transistor positioned in a pixel driver can be positioned on the gate insulating layer 141. In addition to forming the gate electrode GE of the transistor positioned in the pixel driver, a scan line can also be formed. The gate conductive layer can include one electrode of a capacitor positioned in the pixel driver. The gate conductive layer can include a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti) or a metal alloy, and can be made of a single layer or multiple layers.

[0196] After the gate conductive layer is formed, a plasma treatment or a doping process can be performed to make the exposed area of the semiconductor layer ACT conductive. For example, the semiconductor layer ACT covered by the gate electrode GE can not be conductive, and the portion of the semiconductor layer ACT not covered by the gate electrode GE can have the same characteristics as the conductive layer.

[0197] The opening exposing the lower shield layer BML can be positioned in the gate insulating layer 141 and the buffer layer 111, and the gate electrode GE and the lower shield layer BML can be electrically connected through the opening in the gate insulating layer 141 and the buffer layer 111.

[0198] The interlayer insulating layer 161 can be positioned on the gate conductive layer and the gate insulating layer 141. The interlayer insulating layer 161 can include an inorganic insulating layer including silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON x ), and in some embodiments, the inorganic insulating material can be formed thickly. In other embodiments, the interlayer insulating layer 161 can be formed of an organic insulating layer and can include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin.

[0199] The data conduction layer including the data line, the driving voltage line, and / or the auxiliary driving low voltage line 174-1 can be positioned on the interlayer insulating layer 161. The data conduction layer can include the other electrode of one of the capacitors positioned in the pixel driver. In other embodiments, the other electrode of the capacitor can be positioned in the portion of the semiconductor layer ACT having the same characteristics as the conductive layer. The data conduction layer can contain a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), and titanium (Ti) or a metal alloy, and can be made of a single layer or multiple layers.

[0200] The passivation layer 181 and the via layer 182 can be sequentially formed on the data conduction layer and the interlayer insulating layer 161. For example, the passivation layer 181 can be formed of an inorganic insulating layer and can include one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON x ), or can be formed as a multi-layer structure using these compounds. The passivation layer 181 can have an inorganic insulating layer structure formed thicker than other inorganic insulating layers. The via layer 182 can be formed of an organic insulating layer and can include one or more materials selected from the group consisting of photoresist, polyacrylic resin, polyimide resin, acrylic resin, benzocyclobutene, and phenol resin. The via layer 182 can also be formed as a multi-layer.

[0201] An anode layer including an anode electrode Anode and a connection electrode CE can be positioned on the via layer 182. The anode electrode Anode can be electrically connected to a second region of the semiconductor layer ACT serving as a second electrode of a transistor through a hole OP2 positioned in the via layer 182, the passivation layer 181, the interlayer insulating layer 161, and the gate insulating layer 141. Accordingly, the anode electrode Anode can receive an output of the transistor.

[0202] Referring to Figure 3 and Figure 2 , the connection electrode CE can be formed of the same material as the anode electrode Anode, and can be electrically connected to the auxiliary driving low voltage line 174-1 through a second opening OPvia positioned in the via layer 182 and a third opening OPpvx positioned in the passivation layer 181. Accordingly, the connection electrode CE can receive a driving low voltage ELVSS. The anode layer can be made of a single layer including a transparent conductive oxide layer or a metal material or a plurality of layers including a transparent conductive oxide layer or a metal material. The transparent conductive oxide layer can include indium tin oxide (ITO), poly-ITO, indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). The metal material can include silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), and aluminum (Al).

[0203] Above the anode layer, a pixel defining layer 380 including an opening OP can be formed, and as shown in Figure 3 and Figure 19 , the pixel defining layer 380 can further include a first opening OPpdl exposing the connection electrode CE.

[0204] The opening (OP; hereinafter also referred to as a light emitting element opening) of the pixel defining layer 380 corresponding to the light emitting region and / or the light emitting layer EML can expose a portion of the anode electrode Anode, and can have a tapered sidewall.

[0205] The light emitting layer EML can be positioned in the opening OP of the pixel defining layer 380, and the light emitting layer EML can also be positioned on the pixel defining layer 380.

[0206] The first functional layer FL1 can be positioned between the anode electrode Anode and the light emitting layer EML, and the second functional layer FL2 can be positioned on the light emitting layer EML. For example, the first functional layer FL1 can include a hole injection layer and / or a hole transport layer, and the second functional layer FL2 can include an electron transport layer and / or an electron injection layer. For example, the functional layer FL and the light emitting layer EML can be combined to form an intermediate layer EL. The first functional layer FL1 and the second functional layer FL2 are formed on the pixel defining layer 380 and in the opening OP. Accordingly, in Figure 19In an embodiment of the present application, the light emitting layer EML and the functional layer FL of the intermediate layer EL can be positioned both above the pixel defining layer 380 and in the opening OP. However, according to an embodiment, the light emitting layer EML can be positioned only in the opening OP of the pixel defining layer 380, and the functional layer FL can be formed both above the pixel defining layer 380 and in the opening OP.

[0207] The cathode electrode Cathode can be formed on the second functional layer FL2, the pixel defining layer 380, and the opening OP.

[0208] The anode electrode Anode, the light emitting layer EML, and the cathode electrode Cathode can constitute a light emitting diode, and the light emitting diode can further include the functional layer FL.

[0209] The current transmitted to the anode electrode Anode can pass through the first functional layer FL1, the light emitting layer EML, and the second functional layer FL2, and can be transmitted to the cathode electrode Cathode. The light emitting layer EML can emit light due to the current flowing through the light emitting layer EML, and the light emitting diode can display brightness.

[0210] In other embodiments, a spacer can also be formed on the pixel defining layer 380, and the spacer can have a tapered sidewall similar to the pixel defining layer 380.

[0211] Although the structure on the cathode electrode Cathode is not shown in Figure 19 In other embodiments, an encapsulation layer can be positioned. The encapsulation layer can include at least one inorganic layer and at least one organic layer, and can have a three-layer structure including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer can be used to protect the light emitting layer EML from moisture or oxygen that can enter from the outside. In other embodiments, the encapsulation layer can include a further sequentially stacked inorganic layer and organic layer structure.

[0212] In other embodiments, a sensing insulating layer and a plurality of sensing electrodes can be positioned on the encapsulation layer for touch sensing.

[0213] In other embodiments, a film including a polarizing plate can be attached to the encapsulation layer to reduce reflection of external light. A color filter or a color conversion layer can be further formed to improve color quality, in which case the polarizing plate can not be attached. A light blocking layer can be positioned between the color filter or the color conversion layer. In other embodiments, a layer formed of a material capable of absorbing light of some wavelengths in external light (hereinafter referred to as a reflection control material) can also be included, in which case the polarizing plate can not be attached. In other embodiments, the front surface of the light emitting display device can be planarized by covering the front surface of the light emitting display device with an additional organic layer (also referred to as a planarization layer).

[0214] Figure 20 is a schematic cross-sectional structure according to one embodiment, but various modified structures can also be possible.

[0215] Hereinafter, a circuit structure of a pixel included in a light emitting display apparatus according to an embodiment will be observed with reference to Figure 20

[0216] Figure 20 is a schematic diagram of an equivalent circuit of a pixel of a light emitting display apparatus according to an embodiment.

[0217] Figure 19 A circuit diagram of three pixels PXa, PXb, and PXc is shown.

[0218] The plurality of pixels can include a first pixel PXa, a second pixel PXb, and a third pixel PXc. Each of the first pixel PXa, the second pixel PXb, and the third pixel PXc includes a plurality of transistors T1, T2, and T3, a storage capacitor Cst, and light emitting diodes EDa, EDb, and EDc. For example, a single pixel PXa, PXb, and PXc can be divided into the light emitting diodes EDa, EDb, and EDc and pixel drivers PCa, PCb, and PCc, and the pixel drivers PCa, PCb, and PCc can be formed on a driving element layer of Figure 20 Referring to Figure 19 , the pixel drivers PCa, PCb, and PCc can include a plurality of transistors T1, T2, and T3 and a storage capacitor Cst corresponding to a portion other than the light emitting diodes EDa, EDb, and EDc in each pixel PXa, PXb, and PXc.

[0219] In other embodiments, a capacitor (Cleda, Cledb, and Cledc; hereinafter referred to as a light emitting unit capacitor) electrically connected to both ends of the light emitting diode EDa, EDb, and EDc can also be included, and the light emitting unit capacitor Cleda, Cledb, and Cledc can not be included in the pixel driver and can be included in the light emitting diode EDa, EDb, and EDc.

[0220] ​The plurality of transistors T1, T2, and T3 may include a driving transistor (T1; also referred to as the first transistor) and two switching transistors T2 and T3, wherein the two switching transistors are distinguished as an input transistor (T2; also referred to as the second transistor) and an initialization transistor (T3; also referred to as the third transistor). Each transistor T1, T2, and T3 may include a gate electrode, a first electrode, and a second electrode, and may also include a semiconductor layer containing a channel, such that current flow or the channel of the semiconductor layer is blocked depending on the voltage of the gate electrode. For example, depending on the voltage applied to each transistor T1, T2, and T3, one of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode.

[0221] The gate electrode of the driving transistor T1 can be electrically connected to one end of the storage capacitor Cst, and also electrically connected to the second electrode (output electrode) of the input transistor T2. The first electrode of the driving transistor T1 can be electrically connected to the driving voltage line 172 for transmitting the driving voltage ELVDD, and the second electrode of the driving transistor T1 can be electrically connected to the anode electrodes of the light-emitting diodes EDa, EDb, and EDc (e.g., Figure 20 The diagram shows the Anode, the other end of the storage capacitor Cst, the first electrode of the initialization transistor T3, and one end of the light-emitting unit capacitors Cleda, Cledb, and Cledc. The driving transistor T1 can receive the data voltages DVa, DVb, and DVc at its gate electrode according to the switching operation of the input transistor T2, and can provide driving current to the light-emitting diodes EDa, EDb, and EDc according to the voltage at the gate electrode. The storage capacitor Cst can store and hold the voltage at the gate electrode of the driving transistor T1.

[0222] The gate electrode of the input transistor T2 can be electrically connected to a first scan signal line 151 that transmits a first scan signal SC. The first electrode of the input transistor T2 can be electrically connected to data lines 171a, 171b, and 171c that transmit data voltages DVa, DVb, and DVc, and the second electrode of the input transistor T2 can be electrically connected to one end of a storage capacitor Cst and the gate electrode of the driving transistor T1. The plurality of data lines 171a, 171b, and 171c can transmit different data voltages DVa, DVb, and DVc, respectively, and the input transistor T2 of each pixel PXa, PXb, and PXc can be electrically connected to different data lines 171a, 171b, and 171c. The gate electrode of the input transistor T2 of each pixel PXa, PXb, and PXc can be electrically connected to the same first scan signal line 151 and can receive the first scan signal SC at the same timing. Even though the input transistor T2 of each pixel PXa, PXb, and PXc is simultaneously turned on by the first scan signal SC having the same timing, different data voltages DVa, DVb, and DVc can be transmitted to the gate electrode of the driving transistor T1 and one end of the storage capacitor Cst of each pixel PXa, PXb, and PXc through different data lines 171a, 171b, and 171c.

[0223] Figure 20 is an embodiment in which the gate electrode of the initialization transistor T3 receives a different scan signal from the gate electrode of the input transistor T2.

[0224] The gate electrode of the initialization transistor T3 can be electrically connected to a second scan signal line 151-1 that transmits a second scan signal SS. The first electrode of the initialization transistor T3 can be electrically connected to the other end of the storage capacitor Cst, the second electrode of the driving transistor T1, the anode electrodes Anode of the light emitting diodes EDa, EDb, and EDc, and one end of the light emitting unit capacitors Cleda, Cledb, and Cledc, and the second electrode of the initialization transistor T3 can be electrically connected to an initialization voltage line 173 that transmits an initialization voltage VINT. The initialization transistor T3 can be turned on according to the second scan signal SS and can transmit the initialization voltage VINT to the anode electrodes Anode of the light emitting diodes EDa, EDb, and EDc, one end of the light emitting unit capacitors Cleda, Cledb, and Cledc, and the other end of the storage capacitor Cst, thereby initializing the voltage of the anode electrodes Anode of the light emitting diodes EDa, EDb, and EDc.

[0225] Before the initialization voltage VINT is applied, the initialization voltage line 173 can function as a sensing line SL by detecting the voltage of the anode electrode Anode of the light emitting diodes EDa, EDb, and EDc. Through the detection operation, it can be confirmed whether the voltage of the anode electrode Anode is maintained at a target voltage. The detection operation and the initialization operation of transmitting the initialization voltage VINT can be performed separately in time, and the initialization operation can be performed after the detection operation is performed.

[0226] In Figure 20 an embodiment, the on periods of the initialization transistor T3 and the input transistor T2 can be distinguished so that the write operation performed by the input transistor T2 and the initialization operation (and / or the detection operation) performed by the initialization transistor T3 can be performed at different timings.

[0227] One end of the storage capacitor Cst can be electrically connected to the gate electrode of the driving transistor T1 and the second electrode of the input transistor T2, and the other end can be electrically connected to the first electrode of the initialization transistor T3, the second electrode of the driving transistor T1, the anode electrode Anode of the light emitting diodes EDa, EDb, and EDc, and one end of the light emitting unit capacitors Cleda, Cledb, and Cledc.

[0228] The light emitting diodes EDa, EDb, and EDc can receive the output current from the driving transistor T1 at the anode electrode Anode, and the cathode electrode Cathode of the light emitting diodes EDa, EDb, and EDc can receive the driving low voltage ELVSS through the driving low voltage line 174, and the light emitting diodes EDa, EDb, and EDc can emit light according to the output current of the driving transistor T1 to display a gray scale.

[0229] The light emitting unit capacitors Cleda, Cledb, and Cledc can be formed across the light emitting diodes EDa, EDb, and EDc so that the voltage across the light emitting diodes EDa, EDb, and EDc can be maintained constant, whereby the light emitting diodes EDa, EDb, and EDc display a constant brightness.

[0230] Below, the operation of a pixel having Figure 20 the circuit shown in FIG. 1A will be discussed.

[0231] In Figure 18 each of the transistors T1, T2, and T3 can be an N-type transistor and can have a characteristic of being turned on in the case where a high-level voltage is applied to the gate electrode. However, in other embodiments, each of the transistors T1, T2, and T3 can be a P-type transistor.

[0232] One frame can start at the end of the emission section. Then, a second scan signal SS of a high level can be provided to turn on the initialization transistor T3. With the initialization transistor T3 turned on, an initialization operation and / or a detection operation can be performed.

[0233] Hereinafter, embodiments in which both the initialization operation and the detection operation are performed will be focused on.

[0234] The detection operation can be performed before the initialization operation is performed. For example, with the initialization transistor T3 turned on, the initialization voltage line 173 can function as a sensing line SL to detect the voltage of the anode electrode Anode of the light emitting diodes EDa, EDb, and EDc. Through the detection operation, it can be confirmed whether the voltage of the anode electrode Anode is maintained at a target voltage.

[0235] Then, the initialization operation can be performed, and the voltage at the other end of the storage capacitor Cst, the second electrode of the drive transistor T1, and the anode electrode Anode of the light emitting diodes EDa, EDb, and EDc can be changed to the initialization voltage VINT transmitted from the initialization voltage line 173 to perform initialization.

[0236] The detection operation and the initialization operation for transferring the initialization voltage VINT can be performed at separate timings, allowing the pixel to perform various operations while using a minimum number of transistors and reducing the area occupied by the pixel. Accordingly, the resolution of the display panel can be improved.

[0237] The first scan signal SC can also be applied at the time when it changes to a high level, simultaneously with the initialization operation or at separate timings, such that the input transistor T2 is turned on, and a write operation can be performed. For example, data voltages DVa, DVb, and DVc from the data lines 171a, 171b, and 171c can be input through the turned-on input transistor T2 and can be stored at the gate electrode of the drive transistor T1 and the one end of the storage capacitor Cst.

[0238] The data voltages DVa, DVb, and DVc and the initialization voltage VINT are applied to both ends of the storage capacitor Cst by the initialization operation and the write operation. In the case where the initialization transistor T3 is turned on, even if the output current is generated in the drive transistor T1, the current can be output to the outside through the initialization transistor T3 and the initialization voltage line 173, and can not be input to the anode electrodes Anode of the light emitting diodes EDa, EDb, and EDc. According to this embodiment, during the write period, in the case where the first scan signal SC of the high level is supplied, the drive voltage ELVDD at the low level voltage or the drive low voltage ELVSS at the high level voltage can be applied to prevent the current from flowing through the light emitting diodes EDa, EDb, and EDc.

[0239] Thereafter, in the case where the first scan signal SC is changed to the low level, the drive transistor T1 can generate and output the output current due to the high level drive voltage ELVDD applied to the drive transistor T1 and the gate voltage of the drive transistor T1 stored in the storage capacitor Cst. The output current of the drive transistor T1 can be input to the light emitting diodes EDa, EDb, and EDc, and the light emission period in which the light emitting diodes EDa, EDb, and EDc emit light can occur.

[0240] On the other hand, according to the embodiment, more conductive layers can be used to be in contact with Figure 21 The light emitting display device is differently formed, and below some steps for manufacturing the light emitting display device according to another embodiment are discussed. Figure 21

[0241] Figure 18 is a table schematically showing steps for manufacturing some layers of the light emitting display device according to another embodiment.

[0242] Unlike Figure 21 , the light emitting display device according to Figure 21 includes two conductive layers as data conducting layers (a first data conducting layer SD1 and a second data conducting layer SD2), and includes two passivation layers (a first passivation layer 181-1 and a second passivation layer 181-2), and further includes two via layers (a first via layer 182-1 and a second via layer 182-2).

[0243] The light emitting display device according to Figure 18 has the same stack structure from the lower shielding layer BML to the interlayer insulating layer 161 as Figure 21 . In Figure 21 ​In the embodiment of the light emitting display device, the first data conduction layer SD1 is positioned above the interlayer insulating layer 161, and above the first data conduction layer SD1, the first passivation layer 181-1 and the first via layer 182-1 are sequentially positioned. The second data conduction layer SD2 is positioned above the first via layer 182-1, and the second passivation layer 181-2 and the second via layer 182-2 are sequentially positioned above the second data conduction layer SD2. The anode layer including the anode electrode Anode and the connection electrode CE is positioned on the second via layer 182-2. The pixel definition layer 380 including the openings is formed on the anode layer.

[0244] Figure 1 The layers using masks are also designated, and a total of 12 masks used until the pixel definition layer 380 are shown. Thus, the first mask 1 is used to form the lower shield layer BML, the second mask 2 is used to form the semiconductor layer ACT, the third mask 3 is used to form the gate conduction layer Gate, the fourth mask 4 is used to form the contact openings in the interlayer insulating layer 161, the gate insulating layer 141, and / or the buffer layer 111, the fifth mask 5 is used to form the first data conduction layer SD1, the sixth mask 6 is used to form the contact openings in the first passivation layer 181-1, the seventh mask 7 is used to form the contact openings in the first via layer 182-1, the eighth mask 8 is used to form the second data conduction layer SD2, the ninth mask 9 is used to form the contact openings in the second passivation layer 181-2, the tenth mask 10 is used to form the contact openings in the second via layer 182-2, the eleventh mask 11 is used to form the anode layer including the anode electrode Anode and the connection electrode CE, and the twelfth mask 12 is used to form the openings in the pixel definition layer 380. Through the twelfth mask 12, the pixel definition layer 380 can be formed to expose the anode electrode Anode and Figure 19 The openings of the first openings OPpdl (see Figures 1 to 3 in OP) are shown.

[0245] Meanwhile, according to the embodiment, Figures 5 to 8 , Figure 10 , Figure 16 , Figures 18 to 21 and ​ The embodiment can also be applied to a light emitting display device having a layer stack structure and a cross-sectional structure different from those in ​ .

[0246] Although the embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto and various modifications and improvements thereof are possible by those skilled in the art using the basic concept of the present disclosure defined in the appended claims.

Claims

1. A light emitting display device, comprising: a substrate; a voltage line positioned on the substrate and transmitting a constant voltage; a passivation layer positioned on the voltage line; a via layer positioned on the passivation layer; a connection electrode positioned on the via layer; a pixel definition layer positioned on the connection electrode; and a cathode electrode positioned on the pixel definition layer, wherein: the pixel definition layer has a first opening overlapping the connection electrode in a plan view, the via layer has a second opening overlapping the connection electrode in a plan view, the passivation layer has a third opening overlapping the connection electrode in a plan view, the cathode electrode and the connection electrode are electrically connected to each other through the first opening of the pixel definition layer, the voltage line and the connection electrode are electrically connected to each other through the second opening of the via layer and the third opening of the passivation layer, and at least a portion of the third opening of the passivation layer does not overlap the second opening of the via layer in a plan view.

2. The light emitting display device of claim 1, wherein: the second opening of the via layer and the third opening of the passivation layer are positioned in the first opening of the pixel definition layer in a plan view.

3. The light emitting display device of claim 2, wherein: the third opening of the passivation layer and the second opening of the via layer have a planar shape in a plan view.

4. The light emitting display device of claim 3, wherein: the third opening of the passivation layer and the second opening of the via layer have a triangular, rectangular, hexagonal, octagonal, or any other polygonal planar shape, or a planar shape truncated by a polygonal shape.

5. The light emitting display device of claim 2, wherein: a direction in which a long side of the second opening of the via layer extends thereon is different from a direction in which a long side of the third opening of the passivation layer extends thereon.

6. The light emitting display device of claim 5, wherein: the direction in which the long side of the second opening of the via layer extends thereon is perpendicular to the direction in which the long side of the third opening of the passivation layer extends thereon.

7. The light emitting display device of claim 2, wherein: the second opening of the via layer is positioned in the third opening of the passivation layer in a plan view.

8. The light emitting display device of claim 7, wherein: the third opening of the passivation layer is flush with the first opening of the pixel definition layer in a plan view.

9. The light emitting display device of claim 1, wherein: the voltage line is electrically connected to the light emitting display device to which a low driving voltage is applied.

10. The light emitting display device of claim 1, further comprising: an anode electrode positioned on the via layer, wherein the pixel definition layer further comprises a fourth opening overlapping the anode electrode in a plan view, and the anode electrode and the connection electrode are formed of the same material.

11. The light emitting display device of claim 10, further comprising: ​ an intermediate layer positioned on the anode electrode and the pixel defining layer, wherein the intermediate layer is opened at a portion overlapping the connection electrode by laser drilling to electrically connect the cathode electrode to the connection electrode.

12. A light emitting display device comprising: a substrate; a voltage line positioned on the substrate and transmitting a constant voltage; a via layer positioned on the voltage line; a connection electrode positioned on the via layer; a pixel defining layer positioned on the connection electrode; and a cathode electrode positioned on the pixel defining layer, wherein: the pixel defining layer has a first opening overlapping the connection electrode in a plan view, the via layer has a second opening overlapping the connection electrode in a plan view, the cathode electrode and the connection electrode are electrically connected to each other through the first opening of the pixel defining layer, the voltage line and the connection electrode are electrically connected to each other through the second opening of the via layer, and at least a portion of the second opening of the via layer does not overlap the first opening of the pixel defining layer in a plan view.

13. The light emitting display device of claim 12, further comprising: a passivation layer positioned between the voltage line and the via layer, wherein: the passivation layer has a third opening overlapping the connection electrode in a plan view, and at least a portion of the third opening of the passivation layer does not overlap the first opening of the pixel defining layer in a plan view.

14. The light emitting display device of claim 13, wherein: the second opening of the via layer is positioned in the third opening of the passivation layer in a plan view.

15. The light emitting display device of claim 13, further comprising: an anode electrode positioned on the via layer, wherein: the pixel defining layer further includes a fourth opening overlapping the anode electrode in a plan view, and the anode electrode and the connection electrode are formed of the same material.

16. The light emitting display device of claim 15, further comprising: an intermediate layer positioned on the anode electrode and the pixel defining layer, wherein the intermediate layer is opened at a portion overlapping the connection electrode by laser drilling to electrically connect the cathode electrode to the connection electrode.

17. A light emitting display device comprising: a substrate; a voltage line positioned on the substrate and transmitting a constant voltage; a via layer positioned on the voltage line; a connection electrode positioned on the via layer; a pixel defining layer positioned on the connection electrode; and a cathode electrode positioned on the pixel defining layer, wherein: the pixel defining layer has a first opening overlapping the connection electrode in a plan view, the via layer has a second opening overlapping the connection electrode in a plan view, the cathode electrode and the connection electrode are electrically connected to each other through the first opening of the pixel defining layer, the voltage line and the connection electrode are electrically connected to each other through the second opening of the via layer, and the second opening of the via layer has a planar shape in a plan view. ​ ​ 18. The light-emitting display device of claim 17, wherein: the second openings of the via layer have a triangular, rectangular, hexagonal, octagonal, or any other polygonal planar shape, or a planar shape truncated by a polygonal shape.

19. The light-emitting display device of claim 17, further comprising: an anode electrode positioned on the via layer, wherein: the pixel defining layer further comprises openings overlapping the anode electrode in plan view, and the anode electrode and the connection electrode are formed of the same material.

20. The light-emitting display device of claim 19, further comprising: an intermediate layer positioned on the anode electrode and the pixel defining layer, wherein the intermediate layer is opened at portions overlapping the connection electrode by laser drilling to electrically connect the cathode electrode to the connection electrode.

Images