Display device and electronic device

Abstract

A display device and an electronic device are provided, the display device including: a first pixel electrode on a substrate; a first light emitting element on the first pixel electrode and including a semiconductor stack and a protective layer; and a common electrode on the substrate. A side surface of the semiconductor stack includes a first portion and a second portion different from each other, the protective layer on the first portion of the side surface of the semiconductor stack, and the common electrode on the second portion of the side surface of the semiconductor stack.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0059586, filed May 7, 2024, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0002] One or more embodiments of the present disclosure relate to a display device. BACKGROUND

[0003] As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display device can be a flat panel display device such as a liquid crystal display, an electroluminescent display, and a light emitting display.

[0004] The light emitting display includes an organic light emitting display including an organic light emitting diode (OLED) element as a light emitting element and a micro light emitting display including a micro light emitting diode element (hereinafter, referred to as a micro light emitting element) as a light emitting element. Since the micro light emitting diode element is made of an inorganic material, they have less degradation problems and thus can have a longer lifespan than the organic light emitting diode (OLED) element. SUMMARY

[0005] Aspects and features of embodiments of the present disclosure provide a display device having improved light emitting efficiency.

[0006] However, embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0007] According to one or more embodiments of the present disclosure, a display device is provided, the display device including: a first pixel electrode on a substrate; a first light emitting element on the first pixel electrode and including a semiconductor stack and a protection layer; and a common electrode on the substrate. A side surface of the semiconductor stack includes a first portion and a second portion different from each other, the protection layer is on the first portion of the side surface of the semiconductor stack, and the common electrode is on the second portion of the side surface of the semiconductor stack.

[0008] The first portion can be closer to the first pixel electrode than the second portion.

[0009] The common electrode can be in contact with the second portion of the side surface of the semiconductor stack.

[0010] The semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the first pixel electrode, and the first portion of the side surface of the semiconductor stack includes a side surface of the first semiconductor layer.

[0011] The second portion of the side surface of the semiconductor stack can include a side surface of the second semiconductor layer.

[0012] The semiconductor stack can further include a third semiconductor layer on the second semiconductor layer, and the second portion of the side surface of the semiconductor stack includes a side surface of the third semiconductor layer.

[0013] The display device can further include a cover layer on the first light emitting element and the common electrode.

[0014] The cover layer can be on the second portion of the side surface of the semiconductor stack.

[0015] A thickness of the second portion of the side surface of the semiconductor stack can be 50% or more of a sum of thicknesses of the second semiconductor layer and the third semiconductor layer of the first light emitting element.

[0016] The thickness of the second portion of the side surface of the semiconductor stack can be 1.1 µm to 2.7 µm.

[0017] The common electrode can include one or more of indium tin oxide (ITO), zinc indium tin oxide (ZITO), and indium zinc oxide (IZO).

[0018] The first light emitting element can further include a contact electrode between the first pixel electrode and the semiconductor stack, and the contact electrode can include a conductive carbon material.

[0019] The first light emitting element can further include a metal layer between the semiconductor stack and the first pixel electrode, the protective layer can partially cover a lower surface of the metal layer to expose at least a portion of the lower surface of the metal layer, and the contact electrode can be in contact with the exposed lower surface of the metal layer.

[0020] The display device can further include a second pixel electrode on the base and separated from the first pixel electrode, and a second light emitting element on the second pixel electrode and including a semiconductor stack and a protective layer. The common electrode can be on a side surface of the second light emitting element.

[0021] The display device can further include a power line on the base and separated from the first pixel electrode, and an organic layer between the power line and the common electrode. The organic layer can include a common connection hole that penetrates the organic layer, and the power line and the common electrode can be electrically connected through the common connection hole.

[0022] According to one or more embodiments of the disclosure, a display device is provided, the display device including: a plurality of pixel electrodes on a substrate; a plurality of light emitting elements respectively on the plurality of pixel electrodes; and a common electrode on the substrate and in contact with side surfaces of the plurality of light emitting elements. Each of the plurality of light emitting elements includes a body part including a metal layer, a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer sequentially stacked, and a protection layer on an edge of a lower surface of the body part, and the protection layer extends on the edge of the lower surface of the body part to cover a portion of the side surface of the body part and expose another portion of the side surface of the body part.

[0023] The side surface of the body part not covered by the protection layer can be in contact with the common electrode.

[0024] A thickness of the side surface of the body part not covered by the protection layer can be 40% or more of a thickness of the body part.

[0025] At least a portion of the side surface of the second semiconductor layer can be exposed without being covered by the protection layer.

[0026] The display device can further include a cover layer on an upper surface and a side surface of the third semiconductor layer.

[0027] According to one or more embodiments of the disclosure, an electronic device is provided, the electronic device including: a display device configured to provide an image; and a processor configured to provide an image data signal into the display device. The display device includes: a first pixel electrode on a substrate; a first light emitting element on the first pixel electrode and including a semiconductor stack and a protection layer; and a common electrode on the substrate. A side surface of the semiconductor stack includes a first portion and a second portion different from each other. The protection layer is on the first portion of the side surface of the semiconductor stack, and the common electrode is on the second portion of the side surface of the semiconductor stack.

[0028] In the display device according to an embodiment, the common electrode is connected to the side surface of the light emitting element. Accordingly, a light emitting area can be increased, and a resistance can be reduced. Accordingly, light emitting efficiency of the display device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other embodiments and features of the disclosure will become more apparent from the following description of embodiments of the disclosure, taken in conjunction with the accompanying drawings, in which: Figure 1 is a perspective view of a display device according to one or more embodiments; Figure 2 is a layout view of a display device according to one or more embodiments; Figure 3is a block diagram of a display device according to one or more embodiments; Figure 4 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments; Figure 5 is a layout diagram showing a pixel of a display area according to one or more embodiments; Figure 6 is a cross-sectional view showing an example of a cross section of a display panel corresponding to a line I1-I1' of Figure 5 Figure 7 is a detailed cross-sectional view of an example of a region A of Figure 6 Figure 8 is a plan view showing a stack of a light emitting element and a metal layer; Figure 9 is an enlarged cross-sectional view of a portion of a display panel according to one or more embodiments; Figures 10 to 16 is a cross-sectional view sequentially showing a process of manufacturing a display device according to one or more embodiments; Figure 17 is an example diagram of a smart watch including a display device according to one or more embodiments; Figure 18 and Figure 19 is an example diagram of a virtual reality (VR) device including a display device according to one or more embodiments; Figure 20 is an example diagram of a VR device including a display device according to one or more embodiments; Figure 21 is an example diagram showing a vehicle dashboard and a center dashboard including a display device according to one or more embodiments; Figure 22 is an example diagram of a transparent display device including a display device according to one or more embodiments; Figure 23 is a block diagram of an electronic device according to an embodiment of the present disclosure; and Figure 24 is a schematic diagram of an electronic device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] ​​Aspects and features of embodiments of the present disclosure, and methods for realizing the same, can be more readily understood by reference to the following detailed description, taken in conjunction with the accompanying drawings. In the following detailed description, embodiments are described in connection with reference to the various drawings. However, the described embodiments can be embodied in various different forms and should not be construed as being limited only to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques not described in detail herein can not be described for the sake of brevity.

[0031] Unless otherwise noted, like drawing reference numerals, characters or combinations thereof in the accompanying drawings and written description denote like elements, and thus descriptions thereof will not be repeated. In addition, portions (components) not related to the description of one or more embodiments can not be shown to make the description clear.

[0032] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity. In addition, the use of cross-hatching and / or shading in the drawings is for clarity and is not intended to limit the various forms of the disclosed subject matter to a particular style of cross-hatching and / or shading. In the drawings, like reference numerals indicate like elements or components throughout the several views.

[0033] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosed subject matter. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. In addition, the specific structural or functional details disclosed herein are not to be interpreted as limiting, but are merely intended to illustrate the embodiments of the present disclosure, and to provide a concept of the scope of the present disclosure. Thus, the embodiments of the present disclosure should not be construed as being limited to the specific forms set forth herein, but should be construed to encompass all modifications, equivalents, and alternatives falling within the scope of the present disclosure.

[0034] For example, an implant region shown as a rectangle can have rounded or curved features at its edges and / or a gradient of implant concentration instead of a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can cause some implantation in the region between the buried region and the surface through which implantation occurs. Thus, the regions shown in the drawings are schematic in nature and their shapes are not intended to show the actual shape of the regions of a device and are not intended to be limiting. In addition, as will be appreciated by those skilled in the art, the embodiments described can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0035] In the detailed description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

[0036] For ease of explanation, spatially relative terms such as "beneath", "below", "lower", "under", "above", and / or "upper" can be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "under" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being "on" a second part, it can mean that the first part is arranged on either the upper side or the lower side of the second part, without being limited to the upper side of the second part based on a gravitational orientation.

[0037] Further, in the present specification, the phrase "on a plane" or "in a plan view" means viewing a target portion from the top, and the phrase "on a sectional plane" means viewing a sectional plane formed by vertically cutting a target portion from the side.

[0038] It will be understood that when an element, layer, region or component is referred to as being "on" or "connected to" or "coupled to" another element, layer, region or component, it can be directly on, connected or coupled to the other element, layer, region or component or intervening elements, layers, regions or components can be present. In contrast, when an element, layer, region or component is referred to as being "directly on", "directly connected to" or "directly coupled to" another element, layer, region or component, there are no intervening elements, layers, regions or components present. Also, it will be understood that when an element is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers or one or more intervening elements or layers can also be present. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region and / or component, it can be directly electrically connected or directly electrically coupled to the other layer, region and / or component, or intervening layers, regions or components can be present. However, "directly connected / coupled" means that a component is directly connected or coupled to another component without intervening components. Similarly, other phrases describing the relationship between components, such as "between", "immediately between", or "adjacent to", and "directly adjacent to", can be interpreted analogously. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers can also be present.

[0039] For purposes of the present disclosure, expressions such as "at least one of...", "one of...", and "selected from a group consisting of..." when preceding a list of elements, modifies the list of elements as a whole without modifying individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from a group consisting of X, Y, and Z" can be interpreted as X alone, Y alone, Z alone, two or more of X, Y, and Z in any combination (e.g., X with Y, X with Z, Y with Z, and X with Y and Z), or any variation of the above examples. Similarly, expressions such as "at least one of A and B" can include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" can include A, B, or A and B. In addition, the use of "may" when describing embodiments of the present disclosure indicates that one or more embodiments of the present disclosure.

[0040] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

[0041] In examples, the x-axis, the y-axis and / or the z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, the y-axis and the z-axis can be perpendicular to each other or can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2 and / or the third direction DR3.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“includes” and / or“including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] As used herein, the terms“substantially,”“approximately,”“about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein,“about” or“approximately” includes the stated value and means within a acceptable range of deviation for a particular value of a measurement and measurement related to a particular quantity (i.e., limitations of a measurement system) as determined by one of ordinary skill in the art. For example,“about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of a stated value. Furthermore, the use of“may” when describing embodiments of the present disclosure indicates“one or more embodiments of the present disclosure.”

[0044] When one or more embodiments can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed at substantially the same time or in the reverse order of the described order.

[0045] Also, any numerical ranges recited herein are intended to include all sub-ranges of the same numerical precision, i.e. one having the same number of decimal places as the numerical range. For example, a range of 1.0 to 10.0 should be read to include the sub-ranges 1.0 to 2.4, 2.4 to 4.8, 4.8 to 7.2, 7.2 to 9.6, and 9.6 to 10.0, as well as 1.0, 2.4, 4.8, 7.2, and 9.6. Also, a range of 1.0 to 10.0 should be read to include the ranges 1.0 to 10.0, 1.0 to 5.0, 5.0 to 10.0, 0.1 to 1.0, 2.4 to 7.6, and 1.0, 2.4, 4.8, 7.2, and 9.6. The same applies to ranges recited with endpoints that are not absolute numeric values, e.g. a range of "less than 1.0" or "between 1.0 and 10.0." Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range including any minimum or maximum numerical limitation recited herein. All such ranges are intended to be inherently described in this specification, such that amending to expressly recite any such sub-ranges would conform to the requirements of 35 U.S.C. § 112, first paragraph, and 35 U.S.C. § 132(a). All such ranges are intended to be inherently described in this specification, such that amending to expressly recite any such sub-ranges would conform to the requirements of 35 U.S.C. § 112, first paragraph, and 35 U.S.C. § 132(a).

[0046] The electronic or electric device and / or any other related device or component according to one or more embodiments of the disclosure described herein can be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on one integrated circuit (IC) chip or on separate IC chips. Also, various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate.

[0047] Also, various components of these devices can be processes or threads running on one or more processors, computing device executing computer program instructions, and interacting with other system components for performing the various functions described herein. The computer program instructions are stored in a memory which can be implemented in a computing device using a standard memory device, such as random access memory (RAM). The computer program instructions can also be stored in other non- transitory computer readable media such as a CD-ROM, a flash drive, etc. Also, those skilled in the art will appreciate that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] Specific embodiments are described below with reference to the accompanying drawings.

[0050] Those of ordinary skill in the art will appreciate that, in view of the entire content of the present disclosure, each suitable feature of various embodiments of the present disclosure can be combined partially or wholly with each other and can be technically interlocked and operated in various suitable ways, and each embodiment can be implemented independently of each other or in conjunction with each other in any suitable way, unless otherwise stated or implied.

[0051] Figure 1 is a perspective view of a display device 10 according to one or more embodiments.

[0052] Referring to Figure 1 The display device 10 is a device for displaying moving images and / or still images. The display device 10 can be used as a display screen in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), and various products such as televisions, notebook computers, monitors, billboards, and / or Internet of Things (IoT) devices.

[0053] The display device 10 can be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro light-emitting display device or a nano light-emitting display device using a micro light-emitting diode or a nano light-emitting diode. Hereinafter, a case in which the display device 10 is a micro light-emitting display device or a nano light-emitting display device will be mainly described, but the present disclosure is not limited thereto. For ease of description, the micro light-emitting diode or the nano light-emitting diode will be referred to as a light-emitting element.

[0054] The display device 10 includes a display panel 100, a display driver 250, a circuit board 300, and a power supply unit 500.

[0055] The display panel 100 can be shaped like a rectangular plane having a short side in the first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. Each corner where the short side extending in the first direction DR1 meets the long side extending in the second direction DR2 can be rounded to have a suitable curvature (e.g., a predetermined curvature), or can be a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral shape, but can also be other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 can be formed to be flat, but embodiments are not limited thereto. For example, the display panel 100 can include curved portions formed at left and right ends and having a constant or varying curvature. In addition, the display panel 100 can be formed to be flexible, so that the display panel 100 can be bent, folded, folded, and / or rolled.

[0056] The display panel 100 can include a main area MA and a sub area SBA.

[0057] The main area MA can include a display area DA displaying an image and a non-display area NDA disposed around the display area DA along an edge or a periphery of the display area DA. The display area DA can include a plurality of pixels displaying an image. Each of the pixels can include a plurality of sub-pixels. For example, each of the pixels can include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, and a third sub-pixel emitting light of a third color, but the present disclosure is not limited thereto.

[0058] The sub area SBA can protrude from one side of the main area MA in the second direction DR2. Although the sub area SBA is unfolded in Figure 1 The sub area SBA can be curved, although the sub area SBA is unfolded in

[0059] The display driver 250 can generate signals and voltages for driving the display panel 100. The display driver 250 can be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, and / or an ultrasonic bonding method. However, the present disclosure is not limited thereto. For example, the display driver 250 can also be attached to the circuit board 300 using a chip on film (COF) method.

[0060] The circuit board 300 can be attached to an end of the sub-area SBA of the display panel 100. Accordingly, the circuit board 300 can be electrically connected to the display panel 100 and the display driver 250. The display panel 100 and the display driver 250 can receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 can be a printed circuit board (PCB) such as a flexible printed circuit board (FPCB) or a flexible film such as a chip on film (COF).

[0061] The power supply unit 500 can generate a plurality of panel driving voltages according to a power supply voltage from the outside. The power supply unit 500 can be formed as an integrated circuit (IC) and attached to the circuit board 300 using a COF method.

[0062] Figure 2 is a layout diagram of a display apparatus 10 according to one or more embodiments. Figure 2 A state in which the sub-area SBA is unfolded is illustrated.

[0063] Referring to Figure 2 The display panel 100 can include a main area MA and a sub-area SBA.

[0064] The main area MA can include a display area DA in which an image is displayed and a non-display area NDA disposed around the display area DA. The display area DA can occupy a majority of the main area MA. The display area DA can be disposed at the center of the main area MA.

[0065] The display area DA can include a plurality of pixels PX for displaying an image, and each of the pixels PX can include a plurality of sub-pixels SPX. The pixel PX can be defined as a minimum sub-pixel group that can express a white gray scale.

[0066] The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can be around the display area DA (e.g., can surround the display area DA). The non-display area NDA can be an edge area of the display panel 100.

[0067] The first scan driver SDC1 and the second scan driver SDC2 can be disposed in the non-display area NDA. The first scan driver SDC1 can be disposed at one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 can be disposed at the other side (e.g., the right side) of the display panel 100. However, the present disclosure is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 can be electrically connected to the display driver 250 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 can receive a scan control signal from the display driver 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0068] The sub-area SBA can protrude from the main area MA at one side in the second direction DR2. A length of the sub-area SBA in the second direction DR2 can be less than a length of the main area MA in the second direction DR2. A length of the sub-area SBA in the first direction DR1 can be less than a length of the main area MA in the first direction DR1, or can be substantially equal to the length of the main area MA in the first direction DR1. The sub-area SBA can be curved and placed under the display panel 100. In this case, the sub-area SBA can overlap the main area MA in the third direction DR3.

[0069] The sub-area SBA can include a connection area CA, a pad (also referred to as "bond pad" or "solder pad") area PA, and a bending area BA.

[0070] The connection area CA is an area protruding from the main area MA at one side in the second direction DR2. One side of the connection area CA can be in contact with the non-display area NDA of the main area MA, and the other side of the connection area CA can be in contact with the bending area BA.

[0071] The pad area PA is an area in which pads PD and the display driver 250 are disposed. The display driver 250 can be attached to the driving pads of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be attached to the pads PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA can be in contact with the bending area BA.

[0072] The bending area BA is an area that is bendable. When the bending area BA is bent, the pad area PA can be placed under the connection area CA and the main area MA. The bending area BA can be disposed between the connection area CA and the pad area PA. One side of the bending area BA can be in contact with the connection area CA, and the other side of the bending area BA can be in contact with the pad area PA.

[0073] Figure 3is a block diagram of a display device 10 according to one or more embodiments.

[0074] Referring to Figure 3 The display area DA can include a plurality of pixels PX, each of which can include a plurality of sub-pixels SPX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0075] The pixels PX can be arranged in a matrix form along a first direction DR1 and a second direction DR2. For example, the pixels PX can be arranged along rows and columns of the matrix along the first direction DR1 and the second direction DR2. The scan lines SL and the emission control lines EL can extend in the first direction DR1 and can be arranged along the second direction DR2. The data lines DL can extend in the second direction DR2 and can be arranged along the first direction DR1. The scan lines SL include a plurality of write scan lines GWL, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0076] Each of the plurality of sub-pixels SPX can be connected to one of the write scan lines GWL, one of the initialization scan lines GIL, one of the bias scan lines GBL, one of the emission control lines EL, and one of the data lines DL. In one or more embodiments, each of the plurality of sub-pixels SPX can also be connected to one of the control scan lines. Each of the sub-pixels SPX can receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and can emit light from the light emitting element according to the data voltage.

[0077] The non-display area NDA includes a first scan driver SDC1, a second scan driver SDC2, and a display driver 250.

[0078] Each of the first scan driver SDC1 and the second scan driver SDC2 can include a write scan signal output unit 611, an initialization scan signal output unit 612, a bias scan signal output unit 613, and an emission control signal output unit 614. Each of the write scan signal output unit 611, the initialization scan signal output unit 612, the bias scan signal output unit 613, and the emission control signal output unit 614 can receive a scan timing control signal SCS from the timing controller 251.

[0079] The write scan signal output unit 611 can generate a write scan signal according to the scan timing control signal SCS of the timing controller 251, and sequentially output the write scan signal to the write scan lines GWL.

[0080] The initialization scan signal output unit 612 can generate an initialization scan signal according to the scan timing control signal SCS, and sequentially output the initialization scan signal to the initialization scan line GIL.

[0081] The bias scan signal output unit 613 can generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL. The emission control signal output unit 614 can generate an emission control signal according to the scan timing control signal SCS, and sequentially output the emission control signal to the emission control line EL.

[0082] The display driver 250 includes a timing controller 251 and a data driver 252.

[0083] The data driver 252 can receive digital video data DATA and a data timing control signal DCS from the timing controller 251. The data driver 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixel SPX can be selected by the write scan signals of the first scan driver SDC1 and the second scan driver SDC2, and the data voltage can be supplied to the selected sub-pixel SPX.

[0084] The timing controller 251 can receive digital video data DATA and a timing signal from the outside. The timing controller 251 can generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100 according to the timing signal. The timing controller 251 can output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing controller 251 can output the digital video data DATA and the data timing control signal DCS to the data driver 252.

[0085] The power supply unit 500 can generate a plurality of panel driving voltages according to a power supply voltage supplied from the outside. For example, the power supply unit 500 can generate a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VINT, and a fourth power supply voltage VAINT, and supply them to the display panel 100.

[0086] Figure 4 is an equivalent circuit diagram of a sub-pixel SPX according to one or more embodiments.

[0087] Referring to Figure 4According to one or more embodiments, the sub-pixel SPX can be connected to the scan lines GWL, GIL, and GBL, the light emission control line EL, and the data line DL. For example, the sub-pixel SPX can be connected to the write scan line GWL, the initialization scan line GIL, the bias scan line GBL, the light emission control line EL, and the data line DL.

[0088] The sub-pixel SPX according to the embodiment includes a drive transistor DT, switching elements, a capacitor C1, and a light emitting element LE. The switching elements include first to sixth transistors ST1 to ST6.

[0089] The drive transistor DT includes a gate electrode, a first electrode, and a second electrode. The drive transistor DT controls a drain-source current Ids (hereinafter, referred to as “drive current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0090] The light emitting element LE can be a micro light emitting diode.

[0091] The light emitting element LE emits light according to the drive current Ids. The amount of light emitted from the light emitting element LE can be proportional to the drive current Ids. The anode of the light emitting element LE can be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode can be connected to the second power supply line VSL to which the second power supply voltage VSS (see Figure 3 ) is applied.

[0092] The capacitor C1 is formed between the gate electrode of the drive transistor DT and the first power supply line VDL to which the first power supply voltage VDD (see Figure 3 ) is applied. The first power supply voltage VDD (see Figure 3 ) can be at a higher level than the second power supply voltage VSS (see Figure 3 ). One electrode of the capacitor C1 can be connected to the gate electrode of the drive transistor DT, and the other electrode can be connected to the first power supply line VDL.

[0093] As shown in Figure 4 , the first to sixth transistors ST1 to ST6 and the drive transistor DT can all be formed as p-type metal oxide semiconductor field effect transistors (MOSFETs). In this case, the active layer of each of the first to sixth transistors ST1 to ST6 and the drive transistor DT can be made of polysilicon.

[0094] The gate electrode of the first transistor ST1 and the gate electrode of the second transistor ST2 can be connected to a write scan line GWL, the gate electrode of the third transistor ST3 can be connected to an initialization scan line GIL, the gate electrode of the fourth transistor ST4 can be connected to a bias scan line GBL, and the gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 can be connected to an emission control line EL. Because the first transistor ST1 to the sixth transistor ST6 are formed as p-type MOSFETs, the first transistor ST1 to the sixth transistor ST6 can be turned on when a scan signal of a gate low voltage and an emission control signal of a gate low voltage are transmitted to the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission control line EL, respectively. One electrode of the third transistor ST3 can be connected to a first initialization voltage line VIL to which a first initialization voltage VINT (see Figure 3 ) is applied, and one electrode of the fourth transistor ST4 can be connected to a second initialization voltage line VAIL to which a fourth initialization voltage VAINT (see Figure 3 ) is applied. The third power supply voltage VINT (see Figure 3 ) and the fourth power supply voltage VAINT (see Figure 3 ) can be different voltages. In addition, the third power supply voltage VINT (see Figure 3 ) and the fourth power supply voltage VAINT (see Figure 3 ) can be at a lower level than the first power supply voltage VDD (see Figure 3 ) and can be at a higher level than the second power supply voltage VSS (see Figure 3 ).

[0095] Alternatively, the driver transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed as p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 can be formed as n-type MOSFETs. In this case, the active layer of each of the driver transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as p-type MOSFETs can be made of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as n-type MOSFETs can be made of an oxide semiconductor. Further, since the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on in response to a write scan signal of a gate high voltage, and the third transistor ST3 can be turned on in response to an initialization scan signal of a gate high voltage. On the other hand, since the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they can be turned on in response to a scan signal of a gate low voltage and a light emission control signal of a gate low voltage, respectively.

[0096] Alternatively, the fourth transistor ST4 can be formed as an n-type MOSFET, and the other transistors DT, ST1, ST2, ST3, ST5, and ST6 can be formed as p-type MOSFETs. In this case, the active layer of the fourth transistor ST4 can be made of an oxide semiconductor, and the active layer of each of the other transistors DT, ST1, ST2, ST3, ST5, and ST6 can be made of polysilicon. Further, the fourth transistor ST4 can be turned on in response to a bias scan signal of a gate high voltage, and the other transistors DT, ST1, ST2, ST3, ST5, and ST6 can be turned on in response to a scan signal of a gate low voltage and a light emission control signal of a gate low voltage, respectively.

[0097] Alternatively, the first transistor ST1 to the sixth transistor ST6 and the driver transistor DT can all be formed as n-type MOSFETs. In this case, the first transistor ST1 to the sixth transistor ST6 and the driver transistor DT can each have an active layer made of an oxide semiconductor, and can be turned on in response to a scan signal of a gate high voltage and a light emission control signal of a gate high voltage, respectively.

[0098] Figure 5 is a layout diagram illustrating a pixel PX of a display region DA according to one or more embodiments.

[0099] Referring to Figure 5Each of the pixels PX in the display area DA can include three sub-pixels SPX1 to SPX3. However, the disclosure is not limited thereto, and each of the pixels PX can also include four sub-pixels. When each of the pixels PX includes three sub-pixels SPX1 to SPX3, it can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0100] The pixels PX can be arranged in a matrix form. In each of the pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged along a first direction DR1.

[0101] When each of the pixels PX includes three sub-pixels SPX1 to SPX3, the first sub-pixel SPX1 can output first light, the second sub-pixel SPX2 can output second light, and the third sub-pixel SPX3 can output third light. Here, the first light can be light in a red color band, the second light can be light in a green color band, and the third light can be light in a blue color band. For example, the red color band can mean that a main peak wavelength of light is included in a band of about 600 nm to 750 nm, the green color band can mean that a main peak wavelength of light is included in a band of about 480 nm to 560 nm, and the blue color band can mean that a main peak wavelength of light is included in a band of about 370 nm to 460 nm.

[0102] Alternatively, when each of the pixels PX includes four sub-pixels, the first sub-pixel can output first light, the second sub-pixel and the fourth sub-pixel can output second light, and the third sub-pixel can output third light. Alternatively, the first sub-pixel can output first light, the second sub-pixel can output second light, the third sub-pixel can output third light, and the fourth sub-pixel can output fourth light. Here, the fourth light can be white light.

[0103] The first sub-pixel SPX1 includes a first pixel electrode PXE1, a light emitting element LE, and a first light conversion layer QDL1. The second sub-pixel SPX2 includes a second pixel electrode PXE2, a light emitting element LE, and a second light conversion layer QDL2. The third sub-pixel SPX3 includes a third pixel electrode PXE3, a light emitting element LE, and a light transmission layer (or a third light conversion layer) TPL.

[0104] Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 can be shaped like a rectangular plane having a short side in the first direction DR1 and a long side in the second direction DR2. The area of the first sub-pixel SPX1, the area of the second sub-pixel SPX2, and the area of the third sub-pixel SPX3 can be set according to a light conversion efficiency of the first light conversion layer QDL1 and a light conversion efficiency of the second light conversion layer QDL2. For example, the lower the light conversion efficiency, the larger the area of the sub-pixel.

[0105] For example, as shown in FIG. 1A, when the light conversion efficiency of the second light conversion layer QDL2 is lower than the light conversion efficiency of the first light conversion layer QDL1, the area of the second pixel electrode PXE2 can be larger than the area of the first pixel electrode PXE1. In addition, because the first light conversion layer QDL1 can convert light, and the light transmission layer TPL transmits the light of the light emitting element LE as it is, the area of the first pixel electrode PXE1 can be larger than the area of the third pixel electrode PXE3. Figure 5

[0106] Each of the pixel electrodes PXE1 to PXE3 can be electrically connected to at least one transistor through a pixel connection hole CT1 / CT2 / CT3. For example, each of the pixel electrodes PXE1 to PXE3 can be electrically connected to a first electrode of a fourth transistor ST4 (see FIG. 1A) and a second electrode of a sixth transistor ST6 (see FIG. 1A) of a corresponding sub-pixel. Figure 4 Figure 4

[0107] The light emitting element LE can be disposed on each of the pixel electrodes PXE1 to PXE3, respectively. The same number of light emitting elements LE can be disposed on each of the pixel electrodes PXE1 to PXE3. For example, one light emitting element LE can be disposed on each of the pixel electrodes PXE1 to PXE3. However, the disclosure is not limited thereto, and a plurality of light emitting elements LE can also be disposed on each of the pixel electrodes PXE1 to PXE3 in the same number. The light emitting element LE can emit third light (for example, light in a blue band), but the disclosure is not limited thereto. If the light emitting element LE of the first sub-pixel SPX1 emits first light, the light emitting element LE of the second sub-pixel SPX2 emits second light, and the light emitting element LE of the third sub-pixel SPX3 emits third light, the light conversion layers QDL1 and QDL2 and the light transmission layer TPL can be omitted.

[0108] The common electrode CE (see FIG. 1A) can be disposed on the pixel electrodes PXE1 to PXE3 in the display area DA, but can expose the upper surface of the light emitting element LE. The common electrode CE can be electrically connected to the second power supply line VSL (see FIG. 1A) through a common connection hole CT4, CT5, or CT6. Figure 6 Figure 6

[0109] ​​​​​The first light conversion layer QDL1 can be completely overlaid with the first pixel electrode PXE1 and the light emitting element LE of the first sub-pixel SPX1. The area of the first light conversion layer QDL1 can be greater than the area of the first pixel electrode PXE1. The first light conversion layer QDL1 can convert or shift a peak wavelength of incident light to another specific peak wavelength and output light of the specific peak wavelength. For example, the first light conversion layer QDL1 can convert or shift the third light emitted from the light emitting element LE of the first sub-pixel SPX1 to the first light.

[0110] The second light conversion layer QDL2 can be completely overlaid with the second pixel electrode PXE2 and the light emitting element LE of the second sub-pixel SPX2. The area of the second light conversion layer QDL2 can be greater than the area of the second pixel electrode PXE2. The second light conversion layer QDL2 can convert or shift a peak wavelength of incident light to another specific peak wavelength and output light of the specific peak wavelength. For example, the second light conversion layer QDL2 can convert or shift the third light emitted from the light emitting element LE of the second sub-pixel SPX2 to the second light.

[0111] The light transmission layer TPL can be completely overlaid with the third pixel electrode PXE3 and the light emitting element LE of the third sub-pixel SPX3. The light transmission layer TPL can transmit incident light as it is. For example, the light transmission layer TPL can transmit the third light emitted from the light emitting element LE of the third sub-pixel SPX3 as it is.

[0112] Figure 6 is a cross-sectional view showing an example of a cross-section of the display panel 100 corresponding to the line I1-I1' of Figure 5 Figure 7 is a detailed cross-sectional view of an example of the area A of Figure 6

[0113] Referring to Figure 6 and Figure 7 The substrate SUB can be made of an insulating material such as glass and / or a polymer resin. When the substrate SUB is made of a polymer resin, the substrate SUB can be a flexible substrate that can be stretched. The polymer resin can be an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin.

[0114] A barrier layer BR can be disposed on the substrate SUB. The barrier layer BR is a layer for protecting the transistors of the thin film transistor layer TFTL and the light emitting element LE on the thin film transistor layer TFTL from moisture introduced through the substrate SUB that is susceptible to moisture penetration. The barrier layer BR can be composed of a plurality of inorganic layers alternately stacked.

[0115] The thin film transistors TFT1 can be disposed on the barrier layer BR. Each of the thin film transistors TFT1 can be a Figure 4 ​​One of the fourth transistor ST4 and the sixth transistor ST6 illustrated in FIG. 1. Each of the thin film transistors TFT1 can include a first active layer ACT1 and a first gate electrode G1.

[0116] The first active layer ACT1 of each of the thin film transistors TFT1 can be provided on the barrier layer BR. The first active layer ACT1 of each of the thin film transistors TFT1 can include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, and / or amorphous silicon. Alternatively, the first active layer ACT1 of each of the thin film transistors TFT1 can be made of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), and / or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0117] The first active layer ACT1 can include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 can be a region overlapping the first gate electrode G1 in a third direction DR3 that is a thickness direction of the substrate SUB. The first source region S1 can be provided on one side of the first channel region CHA1, and the first drain region D1 can be provided on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 can be regions not overlapping the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 can be regions formed to have conductivity by doping a semiconductor material with ions.

[0118] The first gate insulating layer 131 can be provided on the first channel region CHA1, the first source region S1, and the first drain region D1 of the thin film transistor TFT1 and the barrier layer BR.

[0119] The first gate metal layer can be provided on the first gate insulating layer 131. The first gate metal layer can include the first gate electrode G1 and the first capacitor electrode CAE1 of the thin film transistor TFT1. The first gate electrode G1 can overlap the first active layer ACT1 in the third direction DR3. In Figure 6 In the embodiment, the first gate electrode G1 and the first capacitor electrode CAE1 are separated from each other (e.g., spaced apart from each other). However, when each of the thin film transistors TFT1 is a drive transistor DT, the first gate electrode G1 and the first capacitor electrode CAE1 can also be electrically connected or physically connected to each other. Figure 4 In the embodiment, the first gate electrode G1 and the first capacitor electrode CAE1 are separated from each other (e.g., spaced apart from each other). However, when each of the thin film transistors TFT1 is a drive transistor DT, the first gate electrode G1 and the first capacitor electrode CAE1 can also be electrically connected or physically connected to each other. Figure 4 In the embodiment, the first gate electrode G1 and the first capacitor electrode CAE1 are separated from each other (e.g., spaced apart from each other). However, when each of the thin film transistors TFT1 is a drive transistor DT, the first gate electrode G1 and the first capacitor electrode CAE1 can also be electrically connected or physically connected to each other.

[0120] The second gate insulating layer 132 can be disposed on the first gate electrode G1 and the first capacitor electrode CAE1 of the thin film transistor TFT1 and the first gate insulating layer 131.

[0121] The second gate metal layer can be disposed on the second gate insulating layer 132. The second gate metal layer can include a second capacitor electrode CAE2. The second capacitor electrode CAE2 can be superposed on the first capacitor electrode CAE1 in the third direction DR3. Because the second gate insulating layer 132 has a suitable dielectric constant (e.g., a predetermined dielectric constant), a capacitor C1 (see Figure 4 ) can be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating layer 132 disposed therebetween.

[0122] The interlayer insulating layer 141 can be disposed on the second capacitor electrode CAE2 and the second gate insulating layer 132.

[0123] The first data metal layer can be disposed on the interlayer insulating layer 141. The first data metal layer can include a first source connection electrode PCE1. The first source connection electrode PCE1 can be connected to the first source region S1 or the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that penetrates the first gate insulating layer 131, the second gate insulating layer 132, and the interlayer insulating layer 141.

[0124] The first planarization layer 160 can be disposed on the first source connection electrode PCE1 and the interlayer insulating layer 141 to flatten a step caused by the thin film transistor TFT1.

[0125] The second data metal layer can be disposed on the first planarization layer 160. The second data metal layer can include a second source connection electrode PCE2. The second source connection electrode PCE2 can be connected to the first source connection electrode PCE1 through a second source contact hole PCT2 that penetrates the first planarization layer 160.

[0126] The second planarization layer 180 can be disposed on the second source connection electrode PCE2 and the first planarization layer 160.

[0127] The barrier layer BR, the first gate insulating layer 131, the second gate insulating layer 132, and the interlayer insulating layer 141 can be made of an inorganic layer (e.g., silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), and / or aluminum oxide (AlO x )).

[0128] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer can each be a single layer or a multi-layer made of one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0129] The first planarization layer 160 and the second planarization layer 180 can be made of an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin.

[0130] A light emitting element layer can be disposed on the second planarization layer 180. The light emitting element layer can include the pixel electrodes PXE1 to PXE3, the second power supply line VSL, the light emitting elements LE, the common electrode CE, and the organic layers 210 and 211.

[0131] A pixel electrode layer can be disposed on the second planarization layer 180. The pixel electrode layer can include the first pixel electrode PXE1, the second pixel electrode PXE2, the third pixel electrode PXE3, and the second power supply line VSL.

[0132] Each of the pixel electrodes PXE1 to PXE3 can be connected to the second source connection electrode PCE2 through a pixel connection hole CT1 / CT2 / CT3 (see FIG. 4) that penetrates the second planarization layer 180. Figure 5 Each of the pixel electrodes PXE1 to PXE3 can be connected to the first source region S1 or the first drain region D1 of the thin film transistor TFT1 through the first source connection electrode PCE1 and the second source connection electrode PCE2. Accordingly, a voltage controlled by the thin film transistor TFT1 can be applied to each of the pixel electrodes PXE1 to PXE3.

[0133] The second power supply voltage VSS controlled by the driving transistor DT can be applied to the second power supply line VSL. The common electrode CE can be connected to the second power supply line VSL through a common connection hole CT4, CT5, or CT6 (see FIG. 4). In the drawings, the second power supply line VSL can be formed together with the pixel electrodes PXE1 to PXE3. In one or more embodiments, the second power supply line VSL can not extend on the second planarization layer 180 and can be connected to the second data metal layer on the first planarization layer 160 through a hole in some areas. Figure 5

[0134] The pixel electrode layer can be a single layer or a multi-layer made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and / or alloys thereof. For example, the pixel electrode layer can be made of copper (Cu) having a low sheet resistance in order to reduce the resistance of each of the pixel electrodes PXE1 to PXE3. ​

[0135] The first organic layer 210 can be disposed on each of the pixel electrodes PXE1 to PXE3 and the second power supply line VSL. The first organic layer 210 temporarily fixes or adheres the plurality of light emitting elements LE to prevent the light emitting elements LE from tilting or falling during a process of transferring the light emitting elements LE to the display panel 100. That is, the first organic layer 210 can be a layer for temporarily adhering the plurality of light emitting elements LE to the pixel electrodes PXE1 to PXE3, respectively. To facilitate the temporary adhesion, the first organic layer 210 can be thicker than each of the pixel electrodes PXE1 to PXE3 and thicker than the contact electrode CTE.

[0136] The first organic layer 210 can cover the pixel electrodes PXE1 to PXE3 and the second power supply line VSL, but can have a connection hole BH that exposes at least a portion of each of the pixel electrodes PXE1 to PXE3 and a first common connection hole CT4 that exposes at least a portion of the second power supply line VSL.

[0137] The first organic layer 210 can be a photosensitive organic layer such as a photoresist. Alternatively, the first organic layer 210 can be made of an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin.

[0138] The plurality of light emitting elements LE can be disposed on the first organic layer 210. In Figure 6 Each of the light emitting elements LE is a hybrid micro light emitting diode. The hybrid micro light emitting diode can be configured like a vertical micro light emitting diode in which a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 are sequentially disposed in a third direction DR3 that is a vertical direction. However, like a flip-chip micro light emitting diode, the hybrid micro light emitting diode can further include a third semiconductor layer SEM3.

[0139] Each of the light emitting elements LE can be made of an inorganic material such as gallium nitride (GaN). Each of the light emitting elements LE can have a length of several μm to several hundred μm in each of the first direction DR1, the second direction DR2, and the third direction DR3. For example, each of the light emitting elements LE can have a length of about 100 μm or less in each of the first direction DR1, the second direction DR2, and the third direction DR3.

[0140] Each of the light emitting elements LE can be grown on a semiconductor substrate such as a silicon substrate and / or a sapphire substrate. The light emitting elements LE can be transferred from the semiconductor substrate directly onto the pixel electrodes PXE1 to PXE3 of the display panel 100. Alternatively, the light emitting elements LE can be transferred onto the pixel electrodes PXE1 to PXE3 of the display panel 100 by an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicone as a transfer substrate.

[0141] Each of the light emitting elements LE can include a metal layer MTL, a conductive layer E1, a semiconductor stack STC, a contact electrode CTE, and a protective layer INS. The semiconductor stack STC can include a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a third semiconductor layer SEM3, which are sequentially disposed in a third direction DR3. A main part of each of the light emitting elements LE can include the metal layer MTL, the conductive layer E1, and the semiconductor stack STC. The main part of each of the light emitting elements LE can be the light emitting element LE without the protective layer INS and the contact electrode CTE.

[0142] The metal layer MTL can be disposed on a lower surface of the conductive layer E1. The metal layer MTL reflects light emitted from the active layer MQW to an upper surface of the display device 10. The metal layer MTL can include a metal material having high reflectivity such as aluminum (Al) and / or silver (Ag).

[0143] Figure 8 is a plan view illustrating a stack of the semiconductor stack STC and the metal layer MTL. An area of the metal layer MTL can be similar to an area of the semiconductor stack STC, but can be slightly smaller than the area of the semiconductor stack STC. The area of the semiconductor stack STC can be the same as an area of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, or the third semiconductor layer SEM3, and can be a light emitting area. Because the area of the metal layer MTL is similar to the light emitting area, light extraction efficiency can be improved or maximized. The metal layer MTL can cover a central part of the light emitting element LE and expose only an edge of the light emitting element LE.

[0144] The conductive layer E1 can be disposed on a lower surface of the first semiconductor layer SEM1. Although the conductive layer E1 covers the entire lower surface of the first semiconductor layer SEM1 in Figure 7 , the present disclosure is not limited thereto. For example, the conductive layer E1 can also be disposed on a part of the lower surface of the first semiconductor layer SEM1. The conductive layer E1 can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu).

[0145] The first semiconductor layer SEM1 can be disposed on the conductive layer E1. The first semiconductor layer SEM1 can be made of a layer of a semiconductor material (e.g., gallium nitride (GaN) doped with a first conductivity type dopant or a p-type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), and / or barium (Ba)).

[0146] The active layer MQW can be disposed on the first semiconductor layer SEM1. The active layer MQW can include the same semiconductor material as the first semiconductor layer SEM1 and the second semiconductor layer SEM2. For example, when the first semiconductor layer SEM1 and the second semiconductor layer SEM2 include gallium nitride (GaN), the active layer MQW can also include gallium nitride (GaN). For example, the active layer MQW can include gallium nitride (GaN), indium gallium nitride (InGaN), and / or aluminum gallium nitride (AlGaN). The active layer MQW can emit light through recombination of electron-hole pairs according to an electrical signal received through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0147] The active layer MQW can include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW can be a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked. Here, the well layers can be made of InGaN, and the barrier layers can be made of GaN or AlGaN, but the present disclosure is not limited thereto. Alternatively, the active layer MQW can be a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, or can include different group III to group V semiconductor materials according to a wavelength band of light emitted thereby.

[0148] When the active layer MQW includes indium gallium nitride (InGaN), a color of light emitted thereby can vary according to an indium content. For example, as the indium content increases, a wavelength band of light emitted from the active layer MQW can move to a red wavelength band, and as the indium content decreases, the wavelength band of light emitted from the active layer MQW can move to a blue wavelength band. For example, an indium content of the active layer MQW of the light emitting element LE that emits third light (light in a blue wavelength band) can be about 10 wt% to 20 wt%.

[0149] The second semiconductor layer SEM2 can be disposed on the active layer MQW. The second semiconductor layer SEM2 can be made of a layer of a semiconductor material (e.g., gallium nitride (GaN) doped with a second conductivity type dopant or an n-type dopant such as silicon (Si), germanium (Ge), and / or tin (Sn)).

[0150] An electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer for suppressing or preventing an excessive electron from flowing into the active layer MQW. For example, the electron blocking layer can be AlGaN and / or p-AlGaN doped with p-type Mg. The electron blocking layer can be omitted.

[0151] A superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be made of InGaN and / or GaN. The superlattice layer can be omitted.

[0152] A third semiconductor layer SEM3 can be disposed on the second semiconductor layer SEM2. The third semiconductor layer SEM3 can be a layer of a semiconductor material having an n-type dopant lower than a suitable threshold (e.g., a predetermined threshold), and can be referred to as an undoped semiconductor layer. For example, the third semiconductor layer SEM3 can be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and / or indium nitride (InN) having an n-type dopant lower than a suitable threshold (e.g., a predetermined threshold).

[0153] A protective layer INS can be disposed on a side surface (e.g., an outer circumferential surface) and a lower surface of each light emitting element LE to protect the light emitting element LE. The protective layer INS can be disposed on a side surface (e.g., an outer circumferential surface) of the first semiconductor layer SEM1, a side surface (e.g., an outer circumferential surface) of the active layer MQW, and a side surface (e.g., an outer circumferential surface) of the second semiconductor layer SEM2, but at least a portion of a side surface of the third semiconductor layer SEM3 and / or at least a portion of a side surface of the second semiconductor layer SEM2 can be exposed. An area of the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 exposed without being covered by the protective layer INS can be electrically connected to the common electrode CE to receive the second power supply voltage VSS. A portion of the side surface (e.g., an outer circumferential surface) of each light emitting element LE, a portion of the side surface (e.g., an outer circumferential surface) of a main body portion of each light emitting element LE, or a portion of the side surface (e.g., an outer circumferential surface) of the semiconductor stack STC covered by the protective layer INS can be defined as a first portion, and a portion of the side surface (e.g., an outer circumferential surface) of each light emitting element LE, a portion of the side surface (e.g., an outer circumferential surface) of a main body portion of each light emitting element LE, or a portion of the side surface (e.g., an outer circumferential surface) of the semiconductor stack STC not covered by the protective layer INS can be defined as a second portion.

[0154] The protective layer INS covers the lower surface of the metal layer MTL, but can expose at least a portion of the lower surface of the metal layer MTL. The exposed lower surface of the metal layer MTL can be electrically connected to the contact electrode CTE. The protective layer INS can be disposed not only on the edge of the lower surface of the metal layer MTL, but also on the center separated (e.g., spaced apart) from the edge. The protective layer INS also covers the side surface of the conductive layer E1.

[0155] In an embodiment, the thickness T3 of the region in which the side surface (e.g., the outer circumferential surface) of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 is exposed without being covered by the protective layer INS can be 50% or more of the sum T2 of the thicknesses of the second semiconductor layer SEM2 and the third semiconductor layer SEM3. The thickness T3 of the region in which the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 is exposed without being covered by the protective layer INS can be 99% or less of the sum T2 of the thicknesses of the second semiconductor layer SEM2 and the third semiconductor layer SEM3. The thickness T3 of the region in which the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 is exposed without being covered by the protective layer INS can be 55% to 90% of the sum T2 of the thicknesses of the second semiconductor layer SEM2 and the third semiconductor layer SEM3. Within the above range, the side surface of the second semiconductor layer SEM2 having a relatively low resistance than the third semiconductor layer SEM3 can be exposed, and the common electrode CE can be in contact with the second semiconductor layer SEM2 to allow a low resistance connection and to protect the semiconductor stack STC located in the lower portion of each light emitting element LE. The entire side surface of the third semiconductor layer SEM3 having a high resistance can be exposed without being covered by the protective layer INS. The thickness T3 of the region in which the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 is exposed without being covered by the protective layer INS can be the thickness of the second portion of each side surface of the semiconductor stack STC, the thickness of the second portion of each side surface of the main body portion of each light emitting element LE, or the thickness of the second portion of each side surface of each light emitting element LE.

[0156] In one or more embodiments, the thickness T3 of the region where the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 is exposed without being covered by the protective layer INS can be 40% or more of the thickness T1 of the main body portion of each light emitting element LE. The thickness T3 of the region where the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 is exposed without being covered by the protective layer INS can be 99% or less of the thickness T1 of the main body portion of each light emitting element LE. The thickness T3 of the region where the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 is exposed without being covered by the protective layer INS can be 50% to 80% of the thickness T1 of the main body portion of each light emitting element LE. In one or more embodiments, the thickness T3 of the region where the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 is exposed without being covered by the protective layer INS can be 1.1 µm to 2.7 µm. The main body portion of each light emitting element LE can include the metal layer MTL, the conductive layer E1, and the semiconductor stack STC.

[0157] The protective layer INS can be made of an inorganic layer (e.g., silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), and / or aluminum oxide (AlO x )).

[0158] The contact electrode CTE can be disposed between the metal layer MTL and the first organic layer 210. The contact electrode CTE can be in contact with the first organic layer 210 and the bonding electrode BE.

[0159] Although the contact electrode CTE of each light emitting element LE is disposed on the first organic layer 210 in Figure 6 and Figure 7 , the present disclosure is not limited thereto. For example, the first organic layer 210 can be disposed on a portion of each side surface and a lower surface of the contact electrode CTE of each light emitting element LE. Alternatively, the first organic layer 210 can be disposed on the side surface of the conductive layer E1 of each light emitting element LE. Alternatively, the first organic layer 210 can be disposed on the side surface of the first semiconductor layer SEM1, the side surface of the active layer MQW, and the side surface of the second semiconductor layer SEM2 of each light emitting element LE. In this case, the first organic layer 210 can be disposed on a portion of each side surface of the second semiconductor layer SEM2.

[0160] At least a portion of the contact electrode CTE can be connected to the metal layer MTL exposed without being covered by the protective layer INS. At least a portion of the contact electrode CTE can be in contact with the metal layer MTL. In one or more embodiments, the contact electrode CTE and the metal layer MTL can be in contact with each other in a plurality of regions, and the regions can be spaced apart from each other (e.g., spaced apart). Thus, even if one region of the contact electrode CTE is not connected to the metal layer MTL due to a process error, another region of the contact electrode CTE can be connected to the metal layer MTL, thereby preventing the light emitting element LE from not lighting up.

[0161] The contact electrode CTE can include a conductive carbon material. The contact electrode CTE can be a photoresist that can be photo-patterned. The photoresist can have conductivity when subjected to pressure. The contact electrode CTE including the photoresist can have conductivity by receiving a force from the metal layer MTL thereon, and can be electrically connected to the pixel electrode PXE1, PXE2, or PXE3 through the connection electrode BE.

[0162] The connection electrode BE connects the contact electrode CTE of each light emitting element LE to one of the pixel electrodes PXE1 to PXE3. The connection electrode BE can be connected to one of the pixel electrodes PXE1 to PXE3 exposed through the connection hole BH penetrating the first organic layer 210. In addition, the connection electrode BE can be disposed on the upper surface of the first organic layer 210 and the side surface of the contact electrode CTE. In addition, the connection electrode BE can be disposed on a portion of the side surface of each light emitting element LE. In addition, the connection electrode BE can be disposed on a portion of the protective layer INS of each light emitting element LE.

[0163] The connection electrode BE can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu). Alternatively, the connection electrode BE can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) that can transmit light.

[0164] When the connection electrode BE is made of a metal material having high reflectivity such as aluminum (Al), light traveling in a downward direction of each light emitting element LE among light emitted from the active layer MQW of the light emitting element LE can be reflected toward the top of the light emitting element LE by the connection electrode BE. Thus, light loss of the light emitting element LE can be reduced, and thus light efficiency of the light emitting element LE can be increased.

[0165] The second organic layer 211 is a layer for planarizing a step caused by the light emitting element LE. The second organic layer 211 can partially cover the side surface of the light emitting element LE. In addition, the second organic layer 211 can cover the connection electrode BE. In the drawing, the second organic layer 211 entirely covers the side surface of the protective layer INS and partially covers the side surface of the second semiconductor layer SEM2. However, the present disclosure is not limited thereto. The second organic layer 211 can also cover the side surface of the protective layer INS, but can expose at least a portion of each side surface of the protective layer INS (i.e., an upper portion of each side surface of the protective layer INS). The second organic layer 211 can have a first common connection hole CT4 that penetrates the second organic layer 211 and the first organic layer 210.

[0166] The second organic layer 211 can be made of an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin.

[0167] The common electrode CE can be disposed on the upper surface of the second organic layer 211. In addition, the common electrode CE can be disposed on a portion of the side surface of each light emitting element LE. The common electrode CE can be a common layer commonly formed in the first, second, and third sub-pixels SPX1, SPX2, and SPX3 of the display area DA, but can expose the third semiconductor layer SEM3 of each light emitting element LE. The common electrode CE can be connected to the second power supply line VSL through the common connection holes CT4, CT5, or CT6, and can receive the second power supply voltage VSS.

[0168] The common electrode CE can be in contact with the side surface of the second semiconductor layer SEM2 and / or the third semiconductor layer SEM3 that is not covered by the protective layer INS. The common electrode CE can be in contact with the second semiconductor layer SEM2 having a low resistance, and the common electrode CE and each light emitting element LE can be electrically connected. In one or more embodiments, the common electrode CE can also be in contact with the third semiconductor layer SEM3. The contact area between the common electrode CE and the third semiconductor layer SEM3 can be smaller than the contact area between the common electrode CE and the second semiconductor layer SEM2. The common electrode CE can be disposed on a portion of each side surface of the third semiconductor layer SEM3, and can not be disposed on another portion of each side surface of the third semiconductor layer SEM3. In one or more embodiments, the common electrode CE can not be disposed on the light emitting element LE. By reducing the contact area between the common electrode CE and the third semiconductor layer SEM3 having a high resistance and increasing the contact area between the common electrode CE and the second semiconductor layer SEM2 having a low resistance, the resistance of the display device 10 can be reduced.

[0169] The common electrode CE can be made of a transparent conductive material (TCO) that can transmit light, such as indium tin oxide (ITO), indium zinc tin oxide (ZITO), and / or indium zinc oxide (IZO).

[0170] The pixel electrodes PXE1 to PXE3 can be referred to as anodes or first electrodes, and the common electrode CE can be referred to as a cathode or a second electrode.

[0171] The first cover layer CAP1 can be provided on the common electrode CE. The first cover layer CAP1 covers components provided thereunder, such as the light-emitting element LE and the common electrode CE, to protect them from moisture and / or foreign matter.

[0172] The light-blocking layer BM, the first light-conversion layer QDL1, the second light-conversion layer QDL2, and the light-transmitting layer TPL can be provided on the first cover layer CAP1. The first light-conversion layer QDL1, the second light-conversion layer QDL2, and the light-transmitting layer TPL can be separated by the light-blocking layer BM. Thus, the first light-conversion layer QDL1 can be provided on the first cover layer CAP1 in the first sub-pixel SPX1, the second light-conversion layer QDL2 can be provided on the first cover layer CAP1 in the second sub-pixel SPX2, and the light-transmitting layer TPL can be provided on the first cover layer CAP1 in the third sub-pixel SPX3. The light-blocking layer BM can be superposed on the second organic layer 211 and the common electrode CE in the third direction DR3, and can not be superposed on the light-emitting element LE.

[0173] The first light-conversion layer QDL1 can convert a part of the third light (e.g., light in a blue wavelength band) incident from the light-emitting element LE into the first light (e.g., light in a red wavelength band). The first light-conversion layer QDL1 can include a first base resin BRS1 and first wavelength-conversion particles WCP1. The first base resin BRS1 can include a light-transmitting organic material. The first wavelength-conversion particles WCP1 can convert a part of the third light (e.g., light in a blue wavelength band) incident from the light-emitting element LE into the first light (e.g., light in a red wavelength band).

[0174] The second light-conversion layer QDL2 can convert a part of the third light (e.g., light in a blue wavelength band) incident from the light-emitting element LE into the second light (e.g., light in a green wavelength band). The second light-conversion layer QDL2 can include a second base resin BRS2 and second wavelength-conversion particles WCP2. The second base resin BRS2 can include a light-transmitting organic material. The second wavelength-conversion particles WCP2 can convert a part of the third light (e.g., light in a blue wavelength band) incident from the light-emitting element LE into the second light (e.g., light in a green wavelength band).

[0175] The light-transmitting layer TPL can include a light-transmitting organic material.

[0176] For example, the first base resin BRS1, the second base resin BRS2, and the light transmission layer TPL can include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin. The first wavelength conversion particles WCP1 and the second wavelength conversion particles WCP2 can be quantum dots, quantum rods, fluorescent materials, and / or phosphorescent materials.

[0177] The light blocking layer BM can include a first light blocking layer BM1 and a second light blocking layer BM2 which are sequentially stacked. A length of the first light blocking layer BM1 in the first direction DR1 and / or a length of the first light blocking layer BM1 in the second direction DR2 can be greater than a length of the second light blocking layer BM2 in the first direction DR1 and / or a length of the second light blocking layer BM2 in the second direction DR2. The first light blocking layer BM1 and the second light blocking layer BM2 can be made of an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin. The first light blocking layer BM1 and the second light blocking layer BM2 can include a light blocking material to prevent light of the light emitting element LE of any one sub-pixel from traveling to an adjacent sub-pixel. For example, the first light blocking layer BM1 and the second light blocking layer BM2 can include an inorganic black pigment such as carbon black and / or an organic black pigment.

[0178] The second cover layer CAP2 can be disposed on the first cover layer CAP1 and the light blocking layer BM. The second cover layer CAP2 can be disposed on side surfaces and an upper surface of the light blocking layer BM. For example, the second cover layer CAP2 can be disposed on side surfaces of the first light blocking layer BM1 and side surfaces and an upper surface of the second light blocking layer BM2.

[0179] The reflective layer RF can be disposed between the light blocking layer BM and the first light conversion layer QDL1, between the light blocking layer BM and the second light conversion layer QDL2, and between the light blocking layer BM and the light transmission layer TPL. The reflective layer RF can be disposed on the second cover layer CAP2 disposed on side surfaces of the first light blocking layer BM1 and side surfaces of the second light blocking layer BM2. The reflective layer RF can reflect light traveling in a lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0180] The reflective layer RF can include a metal material such as aluminum (Al) having high reflectivity. A thickness of the reflective layer RF can be about 0.1 µm.

[0181] Alternatively, in order to function as a distributed Bragg reflector, the reflective layer RF can include M (M is an integer of 2 or more) pairs of a first layer and a second layer having different refractive indices. In this case, the M first layers and the M second layers can be alternately arranged. The first layer and the second layer can be made of an inorganic layer (for example, silicon nitride (SiN x), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and / or aluminum oxide (AlO) x Made from ).

[0182] The third cover layer CAP3 can be disposed on the second cover layer CAP2, the reflective layer RF, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0183] The first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3 can be made of inorganic layers (e.g., silicon nitride (SiN)). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and / or aluminum oxide (AlO) x The first optical conversion layer QDL1, the second optical conversion layer QDL2, and the optical transmission layer TPL can be encapsulated by the first cover layer CAP1, the second cover layer CAP2, and the third cover layer CAP3.

[0184] The third organic layer 213 can be disposed on the third cover layer CAP3. Multiple color filters CF1 to CF3 can be disposed on the third organic layer 213. Color filters CF1 to CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0185] The first color filter CF1, disposed in the first sub-pixel SPX1, can transmit first light (e.g., light in the red band) and absorb or block third light (e.g., light in the blue band). Therefore, the first color filter CF1 can transmit a portion of the third light (e.g., light in the blue band) emitted from the light-emitting element LE that has been converted into first light (e.g., light in the red band) by the first light conversion layer QDL1, and can absorb or block the third light (e.g., light in the blue band) that has not been converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 can output the first light (e.g., light in the red band).

[0186] The second color filter CF2 provided in the second sub-pixel SPX2 can transmit the second light (e.g., light in a green wavelength band) and absorb or block the third light (e.g., light in a blue wavelength band). Accordingly, the second color filter CF2 can transmit the second light (e.g., light in a green wavelength band) that a portion of the third light (e.g., light in a blue wavelength band) emitted from the light emitting element LE has been converted to by the second light conversion layer QDL2, and can absorb or block the third light (e.g., light in a blue wavelength band) that has not been converted by the second light conversion layer QDL2. Accordingly, the second sub-pixel SPX2 can output the second light (e.g., light in a green wavelength band).

[0187] The third color filter CF3 provided in the third sub-pixel SPX3 can transmit the third light (e.g., light in a blue wavelength band). Accordingly, the third color filter CF3 can transmit the third light (e.g., light in a blue wavelength band) that has passed through the light transmission layer TPL after being emitted from the light emitting element LE. Accordingly, the third sub-pixel SPX3 can emit the third light (e.g., light in a blue wavelength band).

[0188] The first color filter CF1, the second color filter CF2, and the third color filter CF3 that are stacked on each other in the third direction DR3 can be stacked on the light blocking layer BM in the third direction DR3.

[0189] The fourth organic layer 214 for planarization can be provided on the color filters CF1 to CF3.

[0190] The third organic layer 213 and the fourth organic layer 214 can be made of an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin.

[0191] Figure 9 is an enlarged sectional view of a portion of the display panel 100 according to one or more embodiments. Figure 9 The area A' of Figure 7 is a modified example of the area A of

[0192] Figure 9 differs from Figure 7 in that the protective layer INS' is not provided on the center of the lower surface of the metal layer MTL but is provided only on the edge of the lower surface of the metal layer MTL. The area of the lower surface of the metal layer MTL that is exposed without being covered by the protective layer INS' can increase, and the contact area between the lower surface of the metal layer MTL and the contact electrode CTE' can also increase. The contact electrode CTE' and the metal layer MTL can be in contact with each other in one area. The provision of the protective layer INS' is not limited to Figure 9 in the above-described embodiment, and can also be modified in various ways.

[0193] A process of manufacturing the display device 10 according to one or more embodiments will now be described with reference to other drawings.

[0194] Figures 10 to 16 is a cross-sectional view sequentially showing a process of manufacturing the display device 10 according to one or more embodiments.

[0195] Figures 10 to 16 is a cross-sectional view showing a structure according to a formation order of layers of the display device 10, respectively. Figures 10 to 16 Mainly, a process of manufacturing the light-emitting element LE, the second organic layer 211, and the common electrode CE is shown, and each of them can roughly correspond to Figure 7 a cross-sectional view of FIG. 8. Hereinafter, mainly the light-emitting element LE of the first sub-pixel SPX1 will be described.

[0196] In one or more embodiments, the thin-film transistor layer TFTL can be placed on the substrate SUB, and a structure of the thin-film transistor layer TFTL is the same as the structure described above with reference to Figure 6 a cross-sectional view of FIG. 8. Hereinafter, mainly the light-emitting element LE of the first sub-pixel SPX1 will be described.

[0197] With reference to Figure 10 , the pixel electrodes PXE1, PXE2, and / or PXE3 and the second power supply line VSL, which are spaced apart from each other (e.g., are spaced apart from each other), can be formed on the second planarization layer 180, and the first organic layer 210 can be formed on the pixel electrodes PXE1, PXE2, and / or PXE3 and the second power supply line VSL. The pixel electrodes PXE1, PXE2, and / or PXE3 and the second power supply line VSL can be formed concurrently (e.g., simultaneously), and can be formed by a photopatterning process. The first organic layer 210 can be partially removed by the photopatterning process to expose at least a portion of the pixel electrodes PXE1, PXE2, and / or PXE3.

[0198] Next, with reference to Figure 11 , a contact electrode material layer CTEL can be formed on the pixel electrodes PXE1, PXE2, and / or PXE3. The contact electrode material layer CTEL can be a photoresist and can include a carbon material. The contact electrode material layer CTEL can be placed on the pixel electrodes PXE1, PXE2, and / or PXE3 in multiple settings, but the present disclosure is not limited thereto. The contact electrode material layer CTEL can also be placed on the pixel electrodes PXE1, PXE2, and / or PXE3 in a single setting. The contact electrode material layer CTEL can be placed on each of the pixel electrodes PXE1, PXE2, and / or PXE3 by a photopatterning process.

[0199] Next, with reference to Figure 12A body portion of the light emitting element LE having the protective layer INS on the side surfaces thereof can be prepared, and the body portion of the light emitting element LE can be placed on the contact electrode material layer CTEL to join the body portion of the light emitting element LE and the substrate together. At this time, the body portion of the light emitting element LE can be placed so that the metal layer MTL not covered by the protective layer INS is in contact with the contact electrode material layer CTEL. The contact electrode material layer CTEL can become the contact electrode CTE having the electrical conductivity by receiving the pressure from the body portion of the light emitting element LE. The body portion of the light emitting element LE can include the metal layer MTL, the conductive layer E1, the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. A part of each side surface of the body portion of the light emitting element LE can be covered by the protective layer INS, and another part can not be covered by the protective layer INS.

[0200] The body portion of the light emitting element LE can be manufactured using a known method of manufacturing a vertical type micro light emitting diode. After forming the protective material layer to cover the outer surface of the manufactured body portion of the light emitting element LE, the protective material layer can be removed from a part of the lower surface and a part of each side surface of the light emitting element LE to form the protective layer INS.

[0201] Next, referring to FIG. 6, Figure 13 A connection electrode BE can be formed on the pixel electrodes PXE1, PXE2, and / or PXE3 and the first organic layer 210. The connection electrode BE can be in contact with the contact electrode CTE, and can also be in contact with the pixel electrode PXE1, PXE2, and / or PXE3 through the connection hole BH penetrating the first organic layer 210. The connection electrode BE can have the electrical conductivity and electrically connect the body portion of the light emitting element LE and the pixel electrode PXE1, PXE2, or PXE3.

[0202] Next, referring to FIG. 6, Figure 14 A second organic layer 211 can be formed on the connection electrode BE and the first organic layer 210. The side surface of the second semiconductor layer SEM2 and / or the third semiconductor layer SEM3 of the light emitting element LE has an open area not covered by the protective layer INS. The second organic layer 211 can be formed to the open area of the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3. The second organic layer 211 can be formed to expose at least a part of the open area of the side surface of the second semiconductor layer SEM2 and the third semiconductor layer SEM3.

[0203] Next, referring to FIG. 6, Figure 15 A first common connection hole CT4 penetrating the second organic layer 211 and the first organic layer 210 can be formed at a position overlapped with the second power supply line VSL.

[0204] Next, refer to Figure 16 A common electrode CE is formed on the second organic layer 211. The common electrode CE may be in contact with the side surfaces of the second semiconductor layer SEM2 and / or the third semiconductor layer SEM3. The common electrode CE may not be formed on the upper surface of the third semiconductor layer SEM3.

[0205] Figure 17 This is an example diagram of a smartwatch 1000_1 including a display device 10_1 according to one or more embodiments. (Refer to...) Figure 17 The display device 10_1 according to one or more embodiments can be applied to a smartwatch 1000_1, which is a smart device.

[0206] Figure 18 and Figure 19 This is an example diagram of a virtual reality (VR) device including display devices 10_2 and 10_3 according to one or more embodiments.

[0207] Reference Figure 18 and Figure 19 The head-mounted display device 1000_2 according to one or more embodiments includes a first display device 10_2, a second display device 10_3, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0208] The first display device 10_2 provides an image to the user's left eye, and the second display device 10_3 provides an image to the user's right eye. Each of the first display device 10_2 and the second display device 10_3 is associated with a reference. Figure 1 and Figure 2 The described display devices 10 are substantially the same. Therefore, the descriptions of the first display device 10_2 and the second display device 10_3 will be omitted.

[0209] The first optical component 1510 may be disposed between the first display device 10_2 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_3 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0210] The intermediate frame 1400 can be disposed between the first display device 10_2 and the control circuit board 1600, and can also be disposed between the second display device 10_3 and the control circuit board 1600. The intermediate frame 1400 supports and fixes the first display device 10_2, the second display device 10_3, and the control circuit board 1600.

[0211] The control circuit board 1600 can be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_2 and the second display device 10_3 through connectors. The control circuit board 1600 can convert an image source received from the outside into digital video data DATA (see Figure 3 ), and transmit the digital video data DATA to the first display device 10_2 and the second display device 10_3 through the connectors.

[0212] The control circuit board 1600 can transmit digital video data DATA corresponding to a left image optimized for the left eye of the user to the first display device 10_2, and transmit digital video data DATA corresponding to a right image optimized for the right eye of the user to the second display device 10_3. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_2 and the second display device 10_3.

[0213] The display device housing 1100 accommodates the first display device 10_2, the second display device 10_3, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is placed to cover the open surface of the display device housing 1100. The housing cover 1200 can include a first eyepiece 1210 on which the left eye of the user is placed and a second eyepiece 1220 on which the right eye of the user is placed. Although the first eyepiece 1210 and the second eyepiece 1220 are separately disposed in Figure 18 and Figure 19 , the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can also be combined into one.

[0214] The first eyepiece 1210 can be aligned with the first display device 10_2 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_3 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_2 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_3 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0215] The head-mounted band 1300 fixes the display device housing 1100 to the head of the user so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively kept placed on the left eye and the right eye of the user. When the display device housing 1100 is implemented to be light and small, the head-mounted display device 1000_2 can include a spectacle frame as shown in Figure 20 instead of the head-mounted band 1300.

[0216] In addition, the head-mounted display device 1000_2 can further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port for receiving an image source and a wireless communication module. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0217] Figure 20 FIG. 1 is a diagram illustrating an example of a VR device 1000_3 including a display device 10_4 according to one or more embodiments. Figure 20 A VR device 1000_3 to which the display device 10_4 according to one or more embodiments has been applied is illustrated.

[0218] Referring to Figure 20 , the VR device 1000_3 according to one or more embodiments can be a device in the form of glasses. The VR device 1000_3 according to an embodiment can include the display device 10_4, a left lens 10a, a right lens 10b, a support frame 20, glasses temples 30a and 30b, a reflection member 40, and a display device housing 50.

[0219] In Figure 20 , a case in which the VR device 1000_3 is a glasses-type display device including the glasses temples 30a and 30b is illustrated as an example. That is, the VR device 1000_3 according to an embodiment is not limited to the VR device 1000_3 illustrated in Figure 20 , and can be applied to various other electronic devices in various forms.

[0220] The display device housing 50 can accommodate the display device 10_4 and the reflection member 40. An image displayed on the display device 10_4 can be reflected by the reflection member 40 and provided to the right eye of the user through the right lens 10b. Accordingly, the user can view a VR image displayed on the display device 10_4 through the right eye.

[0221] Although the display device housing 50 is disposed at the right end of the support frame 20 in Figure 20 , the present disclosure is not limited thereto. For example, the display device housing 50 can also be disposed at the left end of the support frame 20. In this case, an image displayed on the display device 10_4 can be reflected by the reflection member 40 and provided to the left eye of the user through the left lens 10a. Accordingly, the user can view a VR image displayed on the display device 10_4 through the left eye. Alternatively, the display device housing 50 can be disposed at both the right end and the left end of the support frame 20. In this case, the user can view a VR image displayed on the display device 10_4 through both the left eye and the right eye.

[0222] Figure 21 FIG. 1 is an example diagram illustrating a vehicle instrument panel and a center instrument panel including display devices 10_a to 10_e according to one or more embodiments. Figure 21 A vehicle to which the display devices 10_a to 10_e according to one or more embodiments have been applied is illustrated.

[0223] Referring to Figure 21 , the display devices 10_a to 10_c according to embodiments can be applied to an instrument panel of a vehicle, a center instrument panel of a vehicle, or a central information display (CID) disposed on an instrument panel of a vehicle. In addition, the display devices 10_d and 10_e according to embodiments can be applied to a door mirror display that replaces a side mirror of a vehicle.

[0224] Figure 22 FIG. 5 is an example diagram of a transparent display device including a display device 10_5 according to one or more embodiments.

[0225] Referring to Figure 22 , the display device 10_5 according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Accordingly, a user located in front of the transparent display device can not only watch the image IM displayed on the display device 10_5, but also watch an object RS or a background located behind the transparent display device. When the display device 10_5 is applied to the transparent display device, a substrate of the display device 10_5 can include a light transmission portion that can transmit light, or can be made of a material that can transmit light.

[0226] The display device according to an embodiment of the disclosure can be applied to various electronic devices. The electronic device according to one embodiment of the disclosure includes the above-described display device, and can further include a module or a device having an additional function other than the display device.

[0227] Figure 23 FIG. 1 is a block diagram of an electronic device 1 according to one embodiment of the disclosure.

[0228] Referring to Figure 23 , the electronic device 1 according to one embodiment of the disclosure can include a display module 11, a processor 12, a memory 13, and a power module 14.

[0229] The processor 12 can include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0230] The memory 13 can store data information necessary for the operation of the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, an image data signal and / or an input control signal are transmitted to the display module 11, and the display module 11 can process the received signal and output image information through a display screen.

[0231] The power module 14 can include a power supply module such as a power adapter or a battery, and a power conversion module that converts power supplied by the power supply module to generate power necessary for the operation of the electronic device 1.

[0232] At least one of the components of the electronic device 1 according to one embodiment of the disclosure can be included in the display device 10 according to an embodiment of the disclosure. In addition, some of the respective modules functionally included in one module can be included in the display device 10, and the other modules can be provided separately from the display device 10. For example, the display device 10 can include the display module 11, and the processor 12, the memory 13, and the power module 14 can be provided in the form of other devices within the electronic device 1 without being provided within the display device 10.

[0233] Figure 24 is a schematic view of an electronic device according to various embodiments of the disclosure.

[0234] Referring to Figure 24 The various electronic devices to which the display device 10 according to an embodiment of the disclosure is applied can not only include image display electronic devices such as a smart phone 10_1a, a tablet PC (personal computer) 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e, but also include wearable electronic devices including a display module such as a smart glass 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c, and vehicle electronic devices 10_3a including a display module such as a CID (central information display) and an interior mirror display, a center cluster, and an instrument panel of a car.

[0235] However, it should be understood that aspects and features of embodiments of the disclosure are not limited to those set forth herein. The above and other aspects of the disclosure will become more apparent to one of ordinary skill in the art to which the disclosure pertains by reading the claims with the accompanying drawings.

Claims

1. A display device comprising: a first pixel electrode over a substrate; a first light-emitting element over the first pixel electrode and including a semiconductor stack and a protective layer; and a common electrode over the substrate, wherein a side surface of the semiconductor stack includes a first portion and a second portion different from each other, wherein the protective layer is over the first portion of the side surface of the semiconductor stack, and the common electrode is over the second portion of the side surface of the semiconductor stack. The first portion is closer to the first pixel electrode than the second portion.

2. The display device according to claim 1, wherein The common electrode is in contact with the second portion of the side surface of the semiconductor stack.

3. The display device according to claim 1, wherein The semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially stacked over the first pixel electrode, and the first portion of the side surface of the semiconductor stack includes a side surface of the first semiconductor layer.

4. The display device according to claim 1, wherein The second portion of the side surface of the semiconductor stack includes a side surface of the second semiconductor layer.

5. The display device of claim 4, wherein, The semiconductor stack further includes a third semiconductor layer over the second semiconductor layer, and the second portion of the side surface of the semiconductor stack includes a side surface of the third semiconductor layer.

6. The display device according to claim 4, wherein 7. The display device according to claim 1, further comprising a cover layer over the first light-emitting element and the common electrode. The cover layer is over the second portion of the side surface of the semiconductor stack.

8. The display device of claim 7, wherein, A thickness of the second portion of the side surface of the semiconductor stack is 50% or more of a sum of thicknesses of the second semiconductor layer and the third semiconductor layer of the first light-emitting element.

9. The display device of claim 6, wherein, The thickness of the second portion of the side surface of the semiconductor stack is 1.1 μm to 2.7 μm.

10. The display device according to claim 1, wherein The common electrode includes one or more of indium tin oxide, indium zinc tin oxide, and indium zinc oxide.

11. The display device according to claim 1, wherein The first light-emitting element further includes a contact electrode between the first pixel electrode and the semiconductor stack, and the contact electrode includes a conductive carbon material.

12. The display device according to claim 1, wherein The first light-emitting element further includes a metal layer between the semiconductor stack and the first pixel electrode, wherein the protective layer partially covers a lower surface of the metal layer to expose at least a part of the lower surface of the metal layer, and the contact electrode is in contact with the exposed lower surface of the metal layer.

13. The display device of claim 12, wherein, 14. The display device according to claim 1, further comprising: a second pixel electrode over the substrate and separated from the first pixel electrode; and a second light-emitting element over the second pixel electrode and including a semiconductor stack and a protective layer, wherein the common electrode is over a side surface of the second light-emitting element.

15. The display device according to claim 1, further comprising: a power supply line over the substrate and separated from the first pixel electrode; and an organic layer between the power supply line and the common electrode, wherein the organic layer includes a common connection hole which penetrates through the organic layer, and the common electrode is in contact with the common connection hole. ​ ​ The power supply line and the common electrode are electrically connected through the common connection hole.

16. A display device comprising: a plurality of pixel electrodes over a substrate; a plurality of light-emitting elements over the plurality of pixel electrodes, respectively; and a common electrode over the substrate and in contact with side surfaces of the plurality of light-emitting elements, wherein each of the plurality of light-emitting elements includes a main part and a protective layer, the main part includes a metal layer, a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer which are sequentially stacked, the protective layer is on an edge of a lower surface of the main part, and the protective layer extends on the edge of the lower surface of the main part to cover a part of a side surface of the main part and expose another part of the side surface of the main part.

17. The display device of claim 16, wherein, The side surface of the main part which is not covered with the protective layer is in contact with the common electrode.

18. The display device of claim 16, wherein, A thickness of the side surface of the main part which is not covered with the protective layer is 40% or more of a thickness of the main part.

19. The display device of claim 16, wherein, At least a part of a side surface of the second semiconductor layer is exposed without being covered with the protective layer.

20. The display device according to claim 16, further comprising a cover layer over an upper surface and a side surface of the third semiconductor layer.

21. An electronic device comprising: a display device configured to provide an image; a processor configured to supply an image data signal into the display device, and wherein the display device includes a first pixel electrode over a substrate, a first light-emitting element over the first pixel electrode and including a semiconductor stack and a protective layer, and a common electrode over the substrate, wherein a side surface of the semiconductor stack includes a first portion and a second portion which are different from each other, wherein the protective layer is over the first portion of the side surface of the semiconductor stack, and the common electrode is over the second portion of the side surface of the semiconductor stack.

Images