Display device, method of manufacturing display device, and electronic device

Abstract

A display device, a method of manufacturing the same, and an electronic device are provided. The display device includes: a base layer; an anode electrode disposed on the base layer; a light emitting layer disposed on the anode electrode, the light emitting layer including a first portion and a second portion; a cathode bridge layer disposed on the base layer, the cathode bridge layer disposed in the same layer as the anode electrode and spaced apart from the anode electrode; a residual sacrificial layer disposed on the first portion of the light emitting layer; and a cathode electrode disposed on the light emitting layer, the cathode electrode including a portion disposed on the second portion of the light emitting layer and another portion disposed on the cathode bridge layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0059875, filed on May 7, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to a display device, a method of manufacturing a display device, and an electronic device including the display device. More particularly, the present disclosure relates to a display device capable of reducing a risk of voltage drop of a cathode electrode and a method of manufacturing a display device. BACKGROUND

[0004] As information technology develops, the importance of a display device, which is a medium of connection between a user and information, increases. The display device can include an organic light emitting diode (OLED), and a sub-pixel adjacent to each other can be formed using the OLED.

[0005] The OLED can include an electron transport unit and a hole transport unit and an emission layer positioned between the hole transport unit and the electron transport unit. An exciton can be generated in the emission layer by recombination of an electron from the electron transport unit and a hole from the hole transport unit. When the exciton is converted from an excited state to a ground state, light can be generated. For reliability of an electrical signal supplied to a sub-pixel, it is desirable to reduce a risk of voltage drop due to an increase in electrical resistance of a conductive structure to which the electrical signal is supplied. SUMMARY

[0006] Embodiments provide a display device capable of reducing a risk of voltage drop of a cathode electrode, a method of manufacturing a display device, and an electronic device including the display device.

[0007] Embodiments also provide a display device having improved display quality and a method of manufacturing a display device having improved display quality.

[0008] Embodiments also provide a display device, a method of manufacturing a display device, and an electronic device including the display device, which simplify a process step to improve convenience of a manufacturing process and reduce a process cost.

[0009] According to aspects of the disclosure, a display device is provided, including: a base layer; an anode electrode disposed on the base layer; a light emitting layer disposed on the anode electrode, the light emitting layer including a first portion and a second portion; a cathode bridging layer disposed on the base layer, the cathode bridging layer being disposed in the same layer as the anode electrode and spaced apart from the anode electrode; a residual sacrificial layer disposed on the first portion of the light emitting layer; and a cathode electrode disposed on the light emitting layer, the cathode electrode including a portion disposed on the second portion of the light emitting layer and another portion disposed on the cathode bridging layer.

[0010] The display device can further include: a first power line and a second power line disposed on the base layer, the first power line and the second power line being respectively for supplying a first voltage potential and a second voltage potential. The first power line and the second power line can be disposed closer to the base layer than the cathode bridging layer in a thickness direction. The anode electrode can include anode electrodes adjacent to each other. The cathode bridging layer can be disposed between the adjacent anode electrodes and electrically connected to the second power line.

[0011] The anode electrode and the cathode bridging layer can include a structure in which a transparent conductive material, a reflective conductive material, and a transparent conductive material are sequentially disposed.

[0012] The anode electrode and the cathode bridging layer can include a structure in which ITO / Ag / ITO are sequentially stacked in a thickness direction. The cathode electrode can include a silver magnesium (AgMg) alloy. The residual sacrificial layer can include aluminum (Al).

[0013] The display device can further include: a pixel definition layer exposing the second portion of the light emitting layer and the cathode bridging layer. An upper surface and an outer surface of the residual sacrificial layer can be covered by the pixel definition layer. An inner surface of the residual sacrificial layer can be exposed by the pixel definition layer and directly contact the cathode electrode.

[0014] The display device can include: a display area including a sub-pixel area, the sub-pixel area including a first sub-pixel area, a second sub-pixel area, and a third sub-pixel area. The anode electrode, the light emitting layer, and the cathode electrode can form light emitting elements defined in the display area. The cathode bridging layer can be disposed in the display area. The light emitting elements can include: a first light emitting element formed in the first sub-pixel area and providing light of a first color, a second light emitting element formed in the second sub-pixel area and providing light of a second color, and a third light emitting element formed in the third sub-pixel area and providing light of a third color.

[0015] According to another aspect of the disclosure, a display device is provided, including: a base layer; a pixel circuit layer disposed on the base layer, the pixel circuit layer including a pixel circuit, a protection layer covering the pixel circuit, and a cathode bridging layer adjacent to the protection layer in a planar direction in which the base layer is disposed; an emission element disposed on the pixel circuit layer; and a pixel defining layer disposed on the pixel circuit layer, wherein the emission element includes an anode electrode disposed on the protection layer, an emission layer including a portion disposed on the anode electrode, and a cathode electrode including a portion disposed on the emission layer, wherein the pixel defining layer covers a portion of the anode electrode, and wherein another portion of the cathode electrode is electrically connected to the cathode bridging layer through a contact portion that penetrates the pixel defining layer and the protection layer.

[0016] The cathode electrode can cover an upper surface of the emission layer and a side surface of the emission layer. A portion of the pixel defining layer can be disposed between the emission layer and the anode electrode.

[0017] The anode electrode can include an uppermost anode electrode portion having a first thickness in a thickness direction. The cathode bridging layer can include an uppermost cathode bridging portion having a second thickness in the thickness direction. The second thickness can be greater than the first thickness.

[0018] The uppermost anode electrode portion can include ITO, and the first thickness can be about to about The uppermost cathode bridging portion can include Ti, and the second thickness can be about to about

[0019] The pixel circuit can include a transistor including a source electrode and a drain electrode. The cathode bridging layer, the source electrode, and the drain electrode can be formed in the same layer.

[0020] According to still another aspect of the disclosure, a method of manufacturing a display device is provided, including: forming a pixel circuit layer including a pixel circuit disposed on a base layer; patterning an anode electrode and a cathode bridging layer disposed on the pixel circuit layer; forming a base emission layer and a base sacrificial layer covering the anode electrode and the cathode bridging layer; patterning a photoresist layer including an opening, a first photoresist layer, and a second photoresist layer on the base sacrificial layer using a mask including a half-tone portion, a full-tone portion, and a blocking portion, wherein the first photoresist layer corresponds to a position of the full-tone portion in a thickness direction, and the second photoresist layer corresponds to a position of the half-tone portion in the thickness direction; and etching the base emission layer and the base sacrificial layer based on the photoresist layer, wherein the etching of the base emission layer and the base sacrificial layer includes: providing an emission layer by removing a portion of the base emission layer; and exposing the cathode bridging layer.

[0021] In the etching of the base light emitting layer and the base sacrificial layer, the first photoresist layer can overlap a position of the light emitting layer to be manufactured in a thickness direction, the second photoresist layer can not overlap the cathode bridging layer and the light emitting layer to be manufactured in the thickness direction, and the opening can overlap the cathode bridging layer in the thickness direction.

[0022] The exposing of the cathode bridging layer and the providing of the light emitting layer can be performed based on the photoresist layers as the same etching mask.

[0023] The patterning of the anode electrode and the patterning of the cathode bridging layer can be performed through the same process.

[0024] The etching of the base light emitting layer and the base sacrificial layer can further include forming a sacrificial layer on the light emitting layer by removing at least a portion of the base sacrificial layer using a wet etching process. The method can further include patterning the pixel defining layer to expose at least a portion of the sacrificial layer and at least a portion of the cathode bridging layer, exposing the light emitting layer by removing at least a portion of the sacrificial layer, and forming a cathode electrode electrically connected to the light emitting layer and the cathode bridging layer. The exposing of the light emitting layer can include forming a residual sacrificial layer disposed on a portion of the light emitting layer.

[0025] According to still another aspect of the disclosure, there is provided a method of manufacturing a display device, the method including forming a pixel circuit layer including a pixel circuit, a cathode bridging layer, and a protective layer covering the pixel circuit and the cathode bridging layer on a base layer, patterning an anode electrode and a pixel defining layer covering the anode electrode on the pixel circuit layer, forming a base light emitting layer and a base sacrificial layer covering the anode electrode and the pixel defining layer, patterning a photoresist layer including a first photoresist layer and a second photoresist layer on the base sacrificial layer using a mask including a half-tone portion, a full-tone portion, and a barrier portion, wherein the first photoresist layer corresponds to a position of the full-tone portion in a thickness direction, and the second photoresist layer corresponds to a position of the half-tone portion in the thickness direction, and etching the base light emitting layer, the base sacrificial layer, the pixel defining layer, and the protective layer based on the photoresist layer, wherein the etching of the base light emitting layer, the base sacrificial layer, the pixel defining layer, and the protective layer includes providing a light emitting layer by removing a portion of the base light emitting layer, and exposing the cathode bridging layer.

[0026] The pixel circuit can include a transistor including a source electrode and a drain electrode. The cathode bridging layer can be formed with the source electrode and the drain electrode through the same process.

[0027] The etching of the base light emitting layer, the base sacrificial layer, the pixel defining layer, and the protective layer can further include forming a sacrificial layer on the light emitting layer by removing at least a portion of the base sacrificial layer using a wet etching process. The exposing of the cathode bridging layer can include forming a lower exposure hole penetrating the protective layer and the pixel defining layer.

[0028] The method may further include: fully exposing the upper surface of the light-emitting layer by removing the sacrificial layer; and forming a cathode electrode. A portion of the cathode electrode may be electrically connected to the light-emitting layer, and another portion of the cathode electrode may be electrically connected to the cathode bridging layer through a lower exposure hole.

[0029] According to an aspect of this disclosure, an electronic device is provided, comprising: a processor configured to provide input image data; a display device according to any of the foregoing aspects configured to display an image based on the input image data; and a power supply configured to supply power to the display device. Attached Figure Description

[0030] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0031] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is mentioned as being "between" two elements, it may be the only element between those two elements, or there may be one or more intervening elements. The same reference numerals refer to the same elements throughout.

[0032] Figure 1 This is a schematic plan view illustrating a display device according to an embodiment of the present disclosure.

[0033] Figure 2 This is a schematic block diagram illustrating the electrical connection structure of a light-emitting element included in a pixel according to an embodiment of the present disclosure.

[0034] Figure 3 This is a schematic cross-sectional view illustrating a light-emitting element according to an embodiment of the present disclosure.

[0035] Figure 4 This is a schematic block diagram illustrating the electrical path through which a cathode signal is supplied according to an embodiment of the present disclosure.

[0036] Figure 5 This is a schematic cross-sectional view illustrating a display device according to a first embodiment of the present disclosure.

[0037] Figure 6 This is a schematic cross-sectional view illustrating a display device according to a second embodiment of the present disclosure.

[0038] Figure 7 This is a schematic cross-sectional view illustrating the anode electrode and cathode bridging layer according to an embodiment of the present disclosure.

[0039] Figures 8 to 25 is a schematic cross-sectional view illustrating process steps of a method of manufacturing a display device according to a first embodiment of the present disclosure.

[0040] Figures 26 to 36 is a schematic cross-sectional view illustrating process steps of a method of manufacturing a display device according to a second embodiment of the present disclosure.

[0041] Figure 37 is a schematic block diagram illustrating an electronic device including a display device according to an embodiment.

[0042] Figure 38 is a schematic diagram illustrating an example in which the electronic device of Figure 37 is implemented as a smart phone.

[0043] Figure 39 is a schematic diagram illustrating an example in which the electronic device of Figure 37 is implemented as a tablet computer. DETAILED DESCRIPTION

[0044] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments or implementations of the present invention. As used in this document, "embodiment" and "implementation" are interchangeable words that refer to a non-limiting example of an apparatus or method disclosed herein. However, it will be apparent that various embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In this regard, various embodiments are not necessarily mutually exclusive, nor do they necessarily limit the present disclosure. For example, specific shapes, configurations, and characteristics of an embodiment can be used or implemented in another embodiment.

[0045] Unless otherwise indicated, the illustrated embodiments are to be understood as providing features that can be monotonically combined, separated, interchanged, and / or rearranged, in addition or alternative ways, without departing from the inventive concept, unless otherwise indicated. Thus, features, components, modules, layers, films, panels, regions, and / or aspects of various embodiments (hereinafter referred to individually or collectively as "elements") can be combined, separated, interchanged, and / or rearranged in additional ways not specifically described herein, without departing from the inventive concept.

[0046] The use of cross-hatching and / or shading in the appended figures is generally provided to illustrate the boundaries of certain regions of a component. As the use of such cross-hatching and / or shading is not necessarily meant to imply any particular material, material properties, dimensions, proportions, or absolute or relative positions for the illustrated components, no inference should be drawn for any implied or required meaning. Further, in the appended figures, the size and relative sizes of components can be exaggerated for clarity and / or descriptive purposes. When embodiments can be practiced differently, a specific sequence of processes can be performed differently than described. For example, two processes described in succession can be executed substantially concurrently or in the reverse order as described. Additionally, identical reference characters and / or reference characters with like suffixes and / or prefixes can refer to identical or like components.

[0047] When an element such as a layer, is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. In this regard, the term "connected" can refer to physical or electrical and / or fluid connection, with or without wiring. Further, the X-axis, Y-axis and Z-axis can not be limited to three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The first to third directions can be similarly interpreted. In terms of the present disclosure, "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first", "second", etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0049] Spatially relative terms, such as "under", "below", "lower", "above", "upper", "on", "over", "side" (e.g., as in "sidewall"), and the like, can be used herein for descriptive purposes, and, thereby, to describe one element's relationship to another element(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Well-known functions or constructions can not be described in detail for brevity. The term "substantially" and variations thereof, as used herein, are used to describe an aspect that is acceptable within manufacturing and production tolerances. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal sense unless expressly so defined herein.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including", "includes", "containing", "contains" or "containing", or variations thereof are used in this specification, these terms are intended to be inclusive in a manner similar to the term "comprising" or "comprises" as these terms are interpreted when employed as descriptive terms within the patent or patent application context. It is also to be noted that the term "substantially" and variations thereof, as used herein, are used to describe an aspect that is acceptable within manufacturing and production tolerances. In addition, as used herein when used in the context of describing the presence or absence of a feature, the term "comprising" is used to mean that the feature can or can not be present together with the features recited in the description.

[0051] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures of embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. In this manner, regions illustrated in the figures can be schematic in nature and the shapes of the regions as illustrated in the figures can not reflect actual shapes of regions of a device and, as such, are not intended to limit the scope of embodiments described herein.

[0052] In accordance with common practice, some embodiments are described and illustrated herein with reference to functional block diagrams, units and / or modules. Those skilled in the art will appreciate that these blocks, units and / or modules are represented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and / or wiring connections, which are formed using semiconductor-based fabrication processes or other manufacturing processes. In the case where a block, unit and / or module is implemented by a microprocessor or other similar hardware, it can be programmed and controlled using software (e.g., microcode) to perform various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing certain functions, and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. In addition, each block, unit and / or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the inventive concept. Further, blocks, units and / or modules of some embodiments can be physically combined into a more complex block, unit and / or module without departing from the scope of the inventive concept. The present disclosure generally relates to a display device, a method of manufacturing a display device, and an electronic device including the display device. The display device, the method of manufacturing a display device, and the electronic device including the display device according to embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0053] Figure 1 is a schematic plan view illustrating a display device according to an embodiment of the present disclosure.

[0054] Referring to Figure 1 The display device DD can include a base layer BSL and pixels PXL disposed on the base layer BSL. The display device DD can further include lines, pads, and a driving circuit (e.g., a scan driver and a data driver) for driving the pixels PXL, etc.

[0055] The display device DD (or the base layer BSL) can include a display area DA and a non-display area NDA. The non-display area NDA can refer to an area other than the display area DA. The non-display area NDA can surround at least a portion of the display area DA.

[0056] The base layer BSL can form a base surface of the display device DD. In some embodiments, the base layer BSL can be a lower substrate for disposing layers forming the display device DD. The base layer BSL can be a rigid or flexible substrate or film. For example, the base layer BSL can include a glass material. In another example, the base layer BSL can include a silicon material. In another example, the base layer BSL can include a polyimide. However, the present disclosure is not limited thereto.

[0057] The display area DA can include the pixels PXL. However, the non-display area NDA can not include the pixels PXL. For example, driving circuits, lines, and pads connected to the pixels PXL of the display area DA can be disposed in the non-display area NDA.

[0058] According to an embodiment, the pixels PXL (or the sub-pixels SPX) can be arranged according to a stripe arrangement structure or However, the present disclosure is not limited thereto, and various embodiments can be applied in the present disclosure.

[0059] According to an embodiment, the pixels PXL (or the sub-pixels SPX) can include first sub-pixels SPX1, second sub-pixels SPX2, and third sub-pixels SPX3. Each of the first sub-pixels SPX1, the second sub-pixels SPX2, and the third sub-pixels SPX3 can be a sub-pixel. At least one first sub-pixel SPX1, at least one second sub-pixel SPX2, and at least one third sub-pixel SPX3 can form one pixel unit capable of emitting light of various colors.

[0060] Each of the first sub-pixels SPX1, the second sub-pixels SPX2, and the third sub-pixels SPX3 can emit light of a certain color.

[0061] For example, the first sub-pixels SPX1 can emit light of a red color (e.g., a first color), the second sub-pixels SPX2 can emit light of a green color (e.g., a second color), and the third sub-pixels SPX3 can emit light of a blue color (e.g., a third color). A red pixel can provide light of a wavelength band of about 600 nm to about 750 nm. A green pixel can provide light of a wavelength band of about 480 nm to about 560 nm. A blue pixel can provide light of a wavelength band of about 370 nm to about 460 nm.

[0062] According to an embodiment, the number of the second sub-pixels SPX2 can be greater than the number of the first sub-pixels SPX1, and can also be greater than the number of the third sub-pixels SPX3. However, the color, kind, and / or number of the first sub-pixels SPX1, the second sub-pixels SPX2, and the third sub-pixels SPX3 constituting each pixel unit are not limited to a specific example.

[0063] Figure 2is a schematic block diagram illustrating an electrical connection structure of a light emitting element included in a pixel according to an embodiment of the disclosure. For example, Figure 2 An electrical connection structure of a pixel circuit PXC including a light emitting element LD can be illustrated.

[0064] Referring to Figure 2 , a sub-pixel SPX can include a light emitting element LD and a pixel circuit PXC configured to drive the light emitting element LD. The display device DD can include a scan line SL, a data line DL, a first power line PL1, a second power line PL2, and a cathode bridge layer CBR.

[0065] The pixel circuit PXC can include at least one circuit element. For example, the pixel circuit PXC can include a transistor and at least one storage capacitor. For example, the pixel circuit PXC can include a driving transistor, a switching transistor, and a storage capacitor. However, the disclosure is not limited thereto, and the pixel circuit PXC can further include additional circuit elements. For example, the pixel circuit PXC can include more or less than two transistors and more than one storage capacitor.

[0066] The pixel circuit PXC can be electrically connected to the scan line SL and the data line DL. For example, the scan line SL and the data line DL can be disposed parallel to each other. In another example, the scan line SL and the data line DL can be disposed perpendicular to each other. The scan line SL can supply a scan signal to the pixel circuit PXC. In some embodiments, the scan line SL can be electrically connected to a gate electrode of a switching transistor of the pixel circuit PXC. The light emitting element LD can be configured to emit light corresponding to a data signal provided from the data line DL.

[0067] The pixel circuit PXC can be electrically connected to the first power line PL1 and the second power line PL2. For example, an anode electrode AE of the light emitting element LD can be electrically connected to the pixel circuit PXC and the first power line PL1, and a cathode electrode CE of the light emitting element LD can be electrically connected to the second power line PL2. The first power line PL1 and the second power line PL2 can be disposed on the base layer BSL.

[0068] A power source of the first power line PL1 and a power source of the second power line PL2 can have different potentials. For example, the power source of the first power line PL1 can be a high potential pixel power source supplied with a power source from a first voltage potential VDD, and the power source of the second power line PL2 can be a low potential pixel power source supplied with a power source from a second voltage potential VSS. A potential difference between the power source of the first power line PL1 and the power source of the second power line PL2 can be set to be equal to or higher than a threshold voltage of the light emitting element LD.

[0069] The first power line PL1 can be electrically connected to the pixel circuit PXC (e.g., a driving transistor). In some embodiments, the second power line PL2 can be electrically connected to the cathode electrode CE of the light emitting element LD through the cathode bridge layer CBR. The first power line PL1 and the second power line PL2 can be adjacent to the base layer BSL than the cathode bridge layer CBR.

[0070] The light emitting element LD can be electrically connected in a forward direction between the first power line PL1 and the second power line PL2 to form an effective light source, respectively. These effective light sources are aggregated to constitute the light emitting element LD of the sub-pixel SPX.

[0071] The light emitting element LD can emit light having a luminance corresponding to a driving current supplied through the pixel circuit PXC. The pixel circuit PXC can supply a driving current corresponding to a data signal to the light emitting element LD during each frame period. The light emitting element LD can emit light having a luminance corresponding to a current flowing therethrough.

[0072] Figure 3 is a schematic cross-sectional view illustrating a light emitting element according to an embodiment of the disclosure.

[0073] Referring to Figure 3 , the light emitting element LD can include an anode electrode AE, a light emitting layer EL, and a cathode electrode CE.

[0074] The anode electrode AE can supply an anode signal to the light emitting layer EL. The light emitting layer EL can be disposed on the anode electrode AE.

[0075] The light emitting layer EL can include a plurality of layers. For example, the light emitting layer EL can include a hole transport unit HTU disposed on the anode electrode AE, a light emitting unit EML (or a light generating layer) disposed on the hole transport unit HTU, and an electron transport unit ETU disposed on the light emitting unit EML. Each of the plurality of layers forming the light emitting layer EL can include an organic material. In some embodiments, each of the plurality of layers forming the light emitting layer EL can further include a compound including a metal or an inorganic material such as a quantum dot, etc.

[0076] The hole transport unit HTU can have a multi-layer structure including a plurality of layers including different materials. In an example, the hole transport unit HTU can include a hole injection layer and a hole transport layer. In some embodiments, the hole transport unit HTU can further include a light emitting auxiliary layer and an electron blocking layer, etc.

[0077] The light-emitting unit EML can include a material capable of emitting light of a certain color. The light-emitting unit EML can include a host and a dopant. The host of the light-emitting unit EML can be a light-emitting material capable of trapping carriers (electrons and holes) for generating light and can induce excitons to be effectively generated. The dopant of the light-emitting unit EML can include a phosphorescent dopant and a fluorescent dopant. In some embodiments, examples of the dopant are not particularly limited. In some embodiments, the dopant can include an organic material. The dopant can further include a metal complex, etc.

[0078] The electron transport unit ETU can have a multi-layer structure including a plurality of layers including different materials. The electron transport unit ETU can include an electron injection layer and an electron transport layer. In some embodiments, the electron transport unit ETU can further include an electron buffer layer and a hole blocking layer, etc.

[0079] The cathode electrode CE can supply a cathode signal to the light-emitting layer EL. The cathode electrode CE can be disposed on the top (or upper surface) of the light-emitting layer EL. For example, the cathode electrode CE can be disposed on the electron transport unit ETU.

[0080] The light-emitting element LD can emit light of a certain color. For example, the light-emitting element LD can include a first light-emitting element LD1 (see Figure 4 ) that emits light of a first color, a second light-emitting element LD2 (see Figure 4 ) that emits light of a second color, and a third light-emitting element LD3 (see Figure 4 ) that emits light of a third color.

[0081] Figure 4 is a schematic block diagram illustrating an electrical path through which a cathode signal is supplied according to an embodiment of the disclosure. For example, Figure 4 The positions of the components and the electrical connection relationship between the components can be schematically illustrated based on the display area DA and the non-display area NDA.

[0082] Referring to Figure 4 , the electrical path through which a cathode signal (e.g., a cathode voltage) is supplied according to an embodiment of the disclosure can be defined so that a risk of voltage drop can be reduced.

[0083] In some embodiments, the cathode voltage can be supplied through the second power line PL2, and the second power line PL2 can be electrically connected to the cathode electrode CE as a target through which the cathode voltage is supplied through the cathode bridging layer CBR. In some embodiments, the thickness of the second power line PL2 in the third direction DR3 can be thicker than the thickness of the cathode electrode CE in the third direction DR3.

[0084] The light emitting elements LD can include a first light emitting element LD1 included in the first sub-pixel SPX1, a second light emitting element LD2 included in the second sub-pixel SPX2, and a third light emitting element LD3 included in the third sub-pixel SPX3. The cathode electrode CE can be disposed throughout the first to third sub-pixels SPX1 to SPX3.

[0085] The second power line PL2 can be electrically connected to a power source supplying the second voltage potential VSS in the non-display area NDA. The second power line PL2 can be electrically connected to the cathode bridge layer CBR and the cathode electrode CE in the display area DA.

[0086] The cathode bridge layer CBR can be disposed in the display area DA. The cathode bridge layer CBR can overlap the second power line PL2 in a plan view.

[0087] The plan defined in the present specification is a plan extending in the first direction DR1 and the second direction DR2, and can be defined with respect to a plan on which the base layer BSL is disposed. In some embodiments, the third direction DR3 can be a thickness direction of the base layer BSL. The third direction DR3 can be a light output direction of the display device DD.

[0088] The cathode bridge layer CBR can include a first cathode bridge layer CBR1 included in the first sub-pixel SPX1, a second cathode bridge layer CBR2 included in the second sub-pixel SPX2, and a third cathode bridge layer CBR3 included in the third sub-pixel SPX3. The first cathode bridge layer CBR1 can be electrically connected to a first portion of the cathode electrode CE forming the first light emitting element LD1. The second cathode bridge layer CBR2 can be electrically connected to a second portion of the cathode electrode CE forming the second light emitting element LD2. The third cathode bridge layer CBR3 can be electrically connected to a third portion of the cathode electrode CE forming the third light emitting element LD3.

[0089] As described above, the electrical path through which the cathode voltage is applied can be defined in the second power line PL2 having a relatively small resistance. The electrical path through which the cathode voltage is applied can be defined in the cathode electrode CE as a small portion having a relatively large resistance. As a result, it is possible to significantly reduce the risk of voltage drop of the cathode voltage. Accordingly, it is possible to improve the operation reliability of the light emitting elements LD, and to provide a display device DD having improved display quality.

[0090] Further, a cathode bridge layer CBR for forming an electrical path through which a cathode voltage is supplied can be formed. The cathode bridge layer CBR can be patterned in an etching process for manufacturing the light emitting element LD (e.g., the anode electrode AE) or the pixel circuit PXC. Accordingly, the electrical path through which the cathode voltage is supplied can be appropriately formed without using an additional mask. This will be described in detail later in connection with the method of manufacturing the display device DD described with reference to FIGS. Figure 8 The method of manufacturing the display device DD will be described in detail later.

[0091] The display device DD according to the first embodiment of the present disclosure will be described with reference to Figure 5 The display device DD according to the first embodiment of the present disclosure will be described with reference to Figure 5 In the following description, the description of the same parts as those described above will be simplified or will not be repeated.

[0092] Figure 5 is a schematic cross-sectional view illustrating the display device according to the first embodiment of the present disclosure. Figure 5 illustrates a cross-sectional structure of the display device DD in the display region DA.

[0093] According to the first embodiment of the present disclosure, the cathode bridge layer CBR can be patterned with the anode electrode AE by the same process.

[0094] With reference to Figure 5 The display device DD according to the first embodiment of the present disclosure can include the pixel circuit layer PCL, the light emitting element layer LEL disposed on the pixel circuit layer PCL, and the upper layer UL disposed on the light emitting element layer LEL, and can include the sub-pixel SPX corresponding to the sub-pixel region SPXA.

[0095] In some embodiments, the sub-pixel SPX can form the sub-pixel region SPXA. The sub-pixel region SPXA can be a region in which light of a certain color is viewed. For example, the sub-pixel region SPXA can include a first sub-pixel region SPXA1 formed by the first sub-pixel SPX1 and in which light of a first color is provided, a second sub-pixel region SPXA2 formed by the second sub-pixel SPX2 and in which light of a second color is provided, and a third sub-pixel region SPXA3 formed by the third sub-pixel SPX3 and in which light of a third color is provided.

[0096] The pixel circuit layer PCL can include the base layer BSL, the pixel circuit PXC, the first power line PL1, the second power line PL2, and the protection layer PSV.

[0097] In some embodiments, the pixel circuit layer PCL can be named a backplane layer.

[0098] The pixel circuit PXC can be disposed on the base layer BSL to drive the light emitting element LD. The first power line PL1 can be disposed on the base layer BSL, and the second power line PL2 can be disposed on the first power line PL1 and the pixel circuit PXC. The pixel circuit layer PCL can include a conductive layer and an insulating layer, and the conductive layer can form the pixel circuit PXC, the first power line PL1, and the second power line PL2. The pixel circuit PXC can be included in a corresponding sub-pixel SPX. For example, the first power line PL1 and the pixel circuit PXC can be electrically connected to each other.

[0099] In some embodiments, a source electrode and / or a drain electrode of a transistor included in the pixel circuit PXC can be disposed in the same layer as the second power line PL2, and include the same material as the second power line PL2.

[0100] The protective layer PSV can be formed at an upper portion of the pixel circuit layer PCL. The protective layer PSV can be disposed on the first power line PL1, the second power line PL2, and the pixel circuit PXC. The protective layer PSV can cover the first power line PL1, the second power line PL2, and the pixel circuit PXC.

[0101] The protective layer PSV can be a via layer. For example, a contact portion CNT can be formed in the protective layer PSV. The contact portion CNT can penetrate the protective layer PSV. A portion of the contact portion CNT can electrically connect the pixel circuit PXC and the anode electrode AE to each other. Another portion of the contact portion CNT can electrically connect the cathode bridge layer CBR to the second power line PL2.

[0102] The protective layer PSV can be a planarization layer. In some embodiments, the protective layer PSV can include an organic material. For example, the organic material can include at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin. However, the disclosure is not limited thereto. For example, the protective layer PSV can include an inorganic material.

[0103] The light emitting element layer LEL can include the light emitting element LD, and can be disposed on the pixel circuit layer PCL. The light emitting element layer LEL can include the anode electrode AE, the cathode bridge layer CBR, the light emitting layer EL, the residual sacrificial layer SCF_R, the pixel definition layer PDL, the cathode electrode CE, and the encapsulation layer TFE.

[0104] The anode electrode AE can be disposed on the pixel circuit layer PCL. For example, the anode electrode AE can be disposed on the passivation layer PSV. The anode electrode AE can be electrically connected to the pixel circuit PXC through the contact portion CNT. The anode electrode AE can include a first anode electrode AE1 disposed in the first sub-pixel area SPXA1, a second anode electrode AE2 disposed in the second sub-pixel area SPXA2, and a third anode electrode AE3 disposed in the third sub-pixel area SPXA3.

[0105] The anode electrode AE can include various conductive materials. For example, the anode electrode AE can include a transparent conductive material. For example, the anode electrode AE can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). The anode electrode AE can include an opaque conductive material capable of reflecting light. For example, the anode electrode AE can include at least one selected from the group consisting of titanium nitride (TiN), silver (Ag), and aluminum (Al).

[0106] In some embodiments, the anode electrode AE can include multiple layers. For example, the anode electrode AE can have a structure in which a transparent conductive material / reflection conductive material / transparent conductive material are sequentially disposed. For example, the anode electrode AE can include a structure in which ITO / Ag / ITO are sequentially stacked.

[0107] The cathode bridge layer CBR can be disposed on the pixel circuit layer PCL. For example, the cathode bridge layer CBR can be disposed on the passivation layer PSV. The cathode bridge layer CBR can be electrically connected to the second power supply line PL2 through the contact portion CNT. The cathode bridge layer CBR can include a first cathode bridge layer CBR1 disposed in the first sub-pixel area SPXA1 and adjacent to the first anode electrode AE1, a second cathode bridge layer CBR2 disposed in the second sub-pixel area SPXA2 and adjacent to the second anode electrode AE2, and a third cathode bridge layer CBR3 disposed in the third sub-pixel area SPXA3 and adjacent to the third anode electrode AE3.

[0108] The cathode bridge layer CBR can be covered by the pixel defining layer PDL, and at least a portion of a top surface (or upper surface) of the cathode bridge layer CBR can be exposed by the pixel defining layer PDL.

[0109] The cathode bridge layer CBR can be patterned with the anode electrode AE through the same process, and can include the same material as the anode electrode AE. For example, the cathode bridge layer CBR can include the transparent conductive material described above with reference to the anode electrode AE. In some embodiments, the cathode bridge layer CBR can also include a multi-layer structure. The cathode bridge layer CBR can have a structure in which the transparent conductive material / reflective conductive material / transparent conductive material are sequentially disposed. For example, the cathode bridge layer CBR can include a structure in which ITO / Ag / ITO are sequentially stacked.

[0110] The cathode bridge layer CBR can be a bridge structure for forming an electrical path through which a cathode signal is supplied. For example, the cathode bridge layer CBR can be disposed in a region adjacent to the light emitting layer EL in the display area DA, and accordingly, it is possible to reduce the risk such as voltage drop in the display device DD.

[0111] The light emitting layer EL can be disposed on the anode electrode AE. The light emitting layer EL can include a first light emitting layer EL1 disposed on the first anode electrode AE1 and forming the first sub-pixel SPX1, a second light emitting layer EL2 disposed on the second anode electrode AE2 and forming the second sub-pixel SPX2, and a third light emitting layer EL3 disposed on the third anode electrode AE3 and forming the third sub-pixel SPX3.

[0112] The residual sacrificial layer SCF_R can be disposed on the light emitting layer EL. The residual sacrificial layer SCF_R can be disposed on the first portion P1 of the light emitting layer EL and expose the second portion P2 of the light emitting layer EL. The top surface (or upper surface) and the outer surface of the residual sacrificial layer SCF_R can be covered by the pixel defining layer PDL. The inner surface of the residual sacrificial layer SCF_R can be exposed by the pixel defining layer PDL and can be directly adjacent (e.g., directly contact) to the cathode electrode CE.

[0113] The residual sacrificial layer SCF_R can be a residue of a sacrificial layer formed to protect the light emitting layer EL when the light emitting layer EL is manufactured. Accordingly, since the residual sacrificial layer SCF_R is formed, damage to the light emitting layer EL during the process of manufacturing the display device DD is prevented, so that it is possible to manufacture a light emitting element LD having improved reliability.

[0114] In some embodiments, the residual sacrificial layer SCF_R can include various materials. For example, the residual sacrificial layer SCF_R can include aluminum. However, the present disclosure is not limited thereto.

[0115] The residual sacrificial layer SCF_R can include a first residual sacrificial layer SCF_R1 disposed on the first light emitting layer EL1 in the first sub-pixel area SPXA1, a second residual sacrificial layer SCF_R2 disposed on the second light emitting layer EL2 in the second sub-pixel area SPXA2, and a third residual sacrificial layer SCF_R3 disposed on the third light emitting layer EL3 in the third sub-pixel area SPXA3.

[0116] The pixel definition layer PDL can be disposed on the protective layer PSV and can be disposed on the residual sacrificial layer SCF_R. The pixel definition layer PDL can expose the second portion P2 of the light emitting layer EL. The pixel definition layer PDL can define an area in which the light emitting layer EL and the cathode electrode CE are electrically connected to each other.

[0117] The pixel definition layer PDL can include an inorganic material. For example, the pixel definition layer PDL can include silicon oxide (SiO x ) and silicon nitride (SiN x ). However, the disclosure is not limited thereto. The pixel definition layer PDL can include a multi-layer structure. For example, the pixel definition layer PDL can include a multi-layer structure in which silicon oxide (SiO x ) and silicon nitride (SiN x ) are alternately disposed.

[0118] The cathode electrode CE can be disposed on the pixel definition layer PDL and the light emitting layer EL. The cathode electrode CE can be disposed throughout the first to third sub-pixel areas SPXA1 to SPXA3. The cathode electrode CE can be a common electrode of the first to third light emitting elements LD1 to LD3.

[0119] The cathode electrode CE can include various conductive materials. For example, the cathode electrode CE can include silver (Ag) and can further include an additional metal. The additional metal can include at least one of magnesium (Mg), aluminum (Al), copper (Cu), calcium (Ca), and barium (Ba). For example, the cathode electrode CE can include a silver magnesium (AgMg) alloy. The additional metal can reduce or prevent an aggregation phenomenon of silver (Ag) serving as a host metal and can improve stability of a thin film formed by the cathode electrode CE. However, the disclosure is not limited thereto.

[0120] A portion of the cathode electrode CE can be electrically connected to the second portion of the light emitting layer EL. Another portion of the cathode electrode CE can be electrically connected to a portion of the cathode bridge layer CBR exposed by the pixel definition layer PDL. Accordingly, a cathode signal applied to the second power supply line PL2 can be supplied to the light emitting element LD through the cathode bridge layer CBR.

[0121] The light emitting element LD can be an organic light emitting diode. The light emitting element LD can include a first light emitting element LD1 forming the first sub-pixel SPX1 and disposed in the first sub-pixel region SPXA1, a second light emitting element LD2 forming the second sub-pixel SPX2 and disposed in the second sub-pixel region SPXA2, and a third light emitting element LD2 forming the third sub-pixel SPX3 and disposed in the third sub-pixel region SPXA3. The first light emitting element LD1 can be formed of the first anode electrode AE1, the first light emitting layer EL1, and a portion of the cathode electrode CE located in the first sub-pixel region SPXA1. The second light emitting element LD2 can be formed of the second anode electrode AE2, the second light emitting layer EL2, and a portion of the cathode electrode CE located in the second sub-pixel region SPXA2. The third light emitting element LD3 can be formed of the third anode electrode AE3, the third light emitting layer EL3, and a portion of the cathode electrode CE located in the third sub-pixel region SPXA3.

[0122] The encapsulation layer TFE can be disposed on the light emitting element LD and the cathode electrode CE. The encapsulation layer TFE can remove a step difference formed by the light emitting element LD, and can passivate the light emitting element LD.

[0123] The encapsulation layer TFE can include multiple layers. For example, the encapsulation layer TFE can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. In some embodiments, the first encapsulation layer can include an inorganic material, the second encapsulation layer can include an organic material, and the third encapsulation layer can include an inorganic material. However, the present disclosure is not limited thereto.

[0124] The upper layer UL can be disposed on an upper portion of the display device DD in a display direction (e.g., the third direction DR3) of the display device DD, and can include various layers. For example, the upper layer UL can include a cover window. The upper layer UL can include a color filter. The upper layer UL can further include various functional film layers (e.g., a low reflection film, etc.). However, the present disclosure is not limited to the specific examples.

[0125] A display device DD according to a second embodiment of the present disclosure will be described with reference to Figure 6 and Figure 7 A display device DD according to a second embodiment of the present disclosure will be described with reference to Figure 6 and Figure 7 In

[0126] Figure 6 is a schematic cross-sectional view illustrating a display device according to a second embodiment of the present disclosure. Figure 6 illustrates a cross-sectional structure of the display device DD in the display region DA. Figure 7 is a schematic cross-sectional view illustrating an anode electrode and a cathode bridging layer according to an embodiment of the present disclosure.

[0127] According to a second embodiment of the present disclosure, the cathode bridging layer CBR can be included in the pixel circuit layer PCL, and a residual sacrificial layer SCF R can not be formed.

[0128] A top surface (or an upper surface) of the cathode bridging layer CBR can be exposed by the protective layer PSV. A side surface of the cathode bridging layer CBR can overlap the protective layer PSV in the third direction DR3.

[0129] The cathode bridging layer CBR can be disposed between different anode electrodes AE adjacent to each other. The cathode bridging layer CBR can be closer to the base layer BSL than the anode electrodes AE in the third direction DR3. The cathode bridging layer CBR can be formed of some of the conductive layers used to form the pixel circuit layer PCL. For example, the cathode bridging layer CBR can be disposed in the same layer as a source electrode and / or a drain electrode of a transistor included in the pixel circuit PXC, and can include the same material as the source electrode and / or the drain electrode of the transistor included in the pixel circuit PXC. In some embodiments, the cathode bridging layer CBR in the pixel circuit layer PCL can be electrically connected to the second power line PL2.

[0130] The cathode bridging layer CBR can be positioned adjacent to the protective layer PSV in a planar direction in which the base layer BSL is disposed (e.g., a direction in which a plane defined by the first direction DR1 and the second direction DR2 extends). A side surface of the cathode bridging layer CBR can face the protective layer PSV.

[0131] In some embodiments, the pixel defining layer PDL can cover the anode electrode AE, and can be covered by the light emitting layer EL. A portion of the pixel defining layer PDL can be disposed between the anode electrode AE and the light emitting layer EL.

[0132] The cathode electrode CE can completely cover a top surface (or an upper surface) of the light emitting layer EL, and can be electrically connected to the light emitting layer EL. The cathode electrode CE can also cover a side surface of the light emitting layer EL. A portion of the cathode electrode CE can be electrically connected to the cathode bridging layer CBR through the contact portion CNT that penetrates the pixel defining layer PDL and the protective layer PSV. At least a portion of the cathode electrode CE can cover a side surface of the protective layer PSV and a side surface of the pixel defining layer PDL.

[0133] In the present embodiment, the cathode bridging layer CBR can be disposed in a region adjacent to the light emitting layer EL in the display area DA, and accordingly, a risk such as a voltage drop in the display device DD can be reduced.

[0134] As Figure 7As depicted, the anode electrode AE can include multiple layers. The anode electrode AE can have a structure that includes an uppermost anode electrode portion AE_U and other layers disposed below the uppermost anode electrode portion AE_U. For example, the anode electrode AE can include a first anode electrode portion AE_L1 that includes a transparent conductive material, a second anode electrode portion AE_L2 disposed on the first anode electrode portion AE_L1 and including a reflective conductive material, and a third anode electrode portion AE_L3 disposed on the second anode electrode portion AE_L2 and including a transparent conductive material. For example, the first anode electrode portion AE_L1 can include ITO, the second anode electrode portion AE_L2 can include Ag, and the third anode electrode portion AE_L3 can include ITO. The third anode electrode portion AE_L3 can be the uppermost anode electrode portion AE_U. In some embodiments, the uppermost anode electrode portion AE_U (e.g., the third anode electrode portion AE_L3) can have a first thickness T_AE.

[0135] The cathode bridging layer CBR can include multiple layers. The cathode bridging layer CBR can have a structure that includes an uppermost cathode bridging portion CBR_U and other layers disposed below the uppermost cathode bridging portion CBR_U. For example, the cathode bridging layer CBR can include a first cathode bridging portion CBR_L1 that includes a first conductive material, a second cathode bridging portion CBR_L2 disposed on the first cathode bridging portion CBR_L1 and including a second conductive material, and a third cathode bridging portion CBR_L3 disposed on the second cathode bridging portion CBR_L2 and including a third conductive material. The first cathode bridging portion CBR_L1 can include Ti, the second cathode bridging portion CBR_L2 can include Al, and the third cathode bridging portion CBR_L3 can include Ti. The third cathode bridging portion CBR_L3 can be the uppermost cathode bridging portion CBR_U. In some embodiments, the uppermost cathode bridging portion CBR_U (e.g., the third cathode bridging portion CBR_L3) can have a second thickness T_CBR.

[0136] When the cathode bridge layer CBR is formed in the pixel circuit layer PCL, a process of patterning the first to third light emitting layers EL1 to EL3 can be performed. During the etching process of the first to third light emitting layers EL1 to EL3, the cathode bridge layer CBR can be continuously exposed to the process environment. Accordingly, the second thickness T_CBR of the uppermost cathode bridge portion CBR_U, which is the uppermost layer of the cathode bridge layer CBR, can be provided thick enough so that the structure of the cathode bridge layer CBR can have robustness against the etching process. For example, the uppermost cathode bridge portion CBR_U including Ti, which has robustness against the etching process, can have a relatively thick thickness. In some embodiments, in the third direction DR3, the second thickness T_CBR can be greater than the first thickness T_AE. For example, the second thickness T_CBR can be about 10 nm to about 100 nm, about 20 nm to about 100 nm, about 30 nm to about 100 nm, about 40 nm to about 100 nm, about 50 nm to about 100 nm, about 60 nm to about 100 nm, about 70 nm to about 100 nm, about 80 nm to about 100 nm, about 90 nm to about 100 nm, about 10 nm to about 90 nm, about 20 nm to about 90 nm, about 30 nm to about 90 nm, about 40 nm to about 90 nm, about 50 nm to about 90 nm, about 60 nm to about 90 nm, about 70 nm to about 90 nm, about 80 nm to about 90 nm, about 10 nm to about 80 nm, about 20 nm to about 80 nm, about 30 nm to about 80 nm, about 40 nm to about 80 nm, about 50 nm to about 80 nm, about 60 nm to about 80 nm, about 70 nm to about 80 nm, about 10 nm to about 70 nm, about 20 nm to about 70 nm, about 30 nm to about 70 nm, about 40 nm to about 70 nm, about 50 nm to about 70 nm, about 60 nm to about 70 nm, about 10 nm to about 60 nm, about 20 nm to about 60 nm, about 30 nm to about 60 nm, about 40 nm to about 60 nm, about 50 nm to about 60 nm, about 10 nm to about 50 nm, about 20 nm to about 50 nm, about 30 nm to about 50 nm, about 40 nm to about 50 nm, about 10 nm to about 40 nm, about 20 nm to about 40 nm, about 30 nm to about 40 nm, about 10 nm to about 30 nm, about 20 nm to about 30 nm, or about 10 nm to about 20 nm. The first thickness T_AE can be about The first thickness T_AE can be about The first thickness T_AE can be about The first thickness T_AE can be about The first thickness T_AE can be about However, the present disclosure is not limited to the specific numerical ranges.

[0137] A method of manufacturing the display device DD according to the first embodiment of the present disclosure will be described with reference to Figures 8 to 25 In Figures 8 to 25 , the description of the portions corresponding to the portions described above will be simplified or will not be repeated.

[0138] Figures 8 to 25 is a schematic cross-sectional view illustrating a process step of a method of manufacturing the display device according to the first embodiment of the present disclosure. For ease of description, the process of Figure 5 will be described based on the cross-sectional structure described above with reference to Figures 8 to 25 .

[0139] Figures 8 to 25 illustrates a process step in which the pixel circuit layer PCL and the layers of the light emitting element layer LEL are formed in the process of manufacturing the display device DD.

[0140] Referring to Figure 8 , the first power line PL1, the second power line PL2, and the pixel circuit PXC can be patterned on the base layer BSL, and the protective layer PSV can be formed on the first power line PL1, the second power line PL2, and the pixel circuit PXC. Accordingly, the pixel circuit layer PCL can be manufactured.

[0141] In some embodiments, the conductive layer or the insulating layer on the base layer BSL can be formed based on a process for manufacturing a semiconductor device. For example, the conductive layer or the insulating layer on the base layer BSL can be formed through a photolithography process, can be etched through various processes (wet etching and dry etching, etc.), and can be deposited through various processes (sputtering and chemical vapor deposition, etc.). However, the present disclosure is not limited to the specific examples.

[0142] In some embodiments, the second power line PL2 can be patterned through the same process as a source electrode and / or a drain electrode of a transistor included in the pixel circuit PXC. However, the present disclosure is not limited thereto.

[0143] Referring to Figure 9 The anode electrode AE and the cathode bridge layer CBR can be patterned on the pixel circuit layer PCL.

[0144] In this step, the anode electrode AE and the cathode bridge layer CBR can be patterned through the same process and can have substantially the same structure.

[0145] In this step, a hole penetrating the protection layer PSV can be formed. After the hole is formed, as the anode electrode AE and the cathode bridge layer CBR are patterned, a contact portion CNT can be formed. Accordingly, the anode electrode AE can be electrically connected to the pixel circuit PXC through the contact portion CNT, and the cathode bridge layer CBR can be electrically connected to the second power line PL2 through the contact portion CNT.

[0146] Referring to Figure 10 The first base light emitting layer EL1_B and the first base sacrificial layer SCF_B1 can be formed on the anode electrode AE and the cathode bridge layer CBR.

[0147] The first base light emitting layer EL1_B can include a material for forming the first light emitting layer EL1 of the first sub-pixel SPX1. The first base sacrificial layer SCF_B1 can include a material for forming the residual sacrificial layer SCF_R.

[0148] In this step, the first base light emitting layer EL1_B and the first base sacrificial layer SCF_B1 can be deposited throughout the first to third sub-pixel areas SPXA1 to SPXA3.

[0149] Referring to Figure 11 A photoresist layer PR can be patterned on the first base sacrificial layer SCF_B1 using a mask MAS.

[0150] In some embodiments, the mask MAS can include a full-tone portion FP, a half-tone portion HP, and a blocking portion BP. The photoresist layer PR can include a first photoresist layer PR_F corresponding to positions of the full-tone portion FP in the third direction DR3 and a second photoresist layer PR_H corresponding to positions of the half-tone portion HP. For example, the first photoresist layer PR_F can overlap the full-tone portion FP in a plan view, and the second photoresist layer PR_H can overlap the half-tone portion HP in a plan view. In some embodiments, the photoresist layer PR can form an etching mask structure, and can include an opening OPN at a position corresponding to the blocking portion BP in the third direction DR3.

[0151] In some embodiments, since the photoresist layer PR is patterned using the mask MAS including the full-tone portion FP and the half-tone portion HP, the first photoresist layer PR_F can have a thickness thicker than a thickness of the second photoresist layer PR_H in the third direction DR3. For example, the photoresist layer PR can be manufactured using a negative photoresist. However, the disclosure is not limited thereto.

[0152] In some embodiments, a position of the first photoresist layer RP_F can overlap a position of the light-emitting layer EL to be manufactured in the third direction DR3. For example, the photoresist layer PR manufactured in this step can be an etching mask. In some embodiments, a position of the second photoresist layer PR_H can overlap a position of each of the other light-emitting layers EL except for the light-emitting layer EL to be manufactured in the third direction DR3. For example, a position of the second photoresist layer PR_H can not overlap a position of each of the cathode bridge layer CBR and the light-emitting layer EL to be manufactured in the third direction DR3. In some embodiments, a position of the opening OPN of the photoresist layer PR can overlap a position of the cathode bridge layer CBR to be exposed in the third direction DR3.

[0153] Reference Figure 12 and Figure 13 The first base light-emitting layer EL1_B and the first base sacrificial layer SCF_B1 can be etched using the photoresist layer PR as an etching mask, and the first light-emitting layer EL1 and the first sacrificial layer SCF1 can be provided.

[0154] In this step, since the mask MAS including the half-tone portion HP is used, a process of patterning the light-emitting layer EL and a process of exposing the cathode bridge layer CBR using the same etching mask (i.e., the photoresist layer PR) can be performed. Accordingly, the process steps are simplified, making it possible to reduce the number of masks. In addition, the convenience of the manufacturing process can be improved, and the process cost can also be reduced.

[0155] In this step, a portion of the first base emitting layer EL1_B corresponding to the first photoresist layer PR_F having a relatively thick thickness can not be removed, and accordingly, the first emitting layer EL1 in the first sub-pixel area SPXA1 can be patterned.

[0156] In this step, the first base emitting layer EL1_B and the first base sacrificial layer SCF_B1 corresponding to the opening OPN can be removed, and the cathode bridging layer CBR can be exposed. In this step, the first base emitting layer EL1_B and the first base sacrificial layer SCF_B1 corresponding to the second photoresist layer PR_H can be removed. Accordingly, the first base emitting layer EL1_B and the first base sacrificial layer SCF_B1 in the second sub-pixel area SPXA2 and the third sub-pixel area SPXA3 can be removed. In some embodiments, the first base sacrificial layer SCF_B1 can include aluminum (Al), and can be removed based on a wet etching process. After the first emitting layer EL1 and the first sacrificial layer SCF1 are manufactured, the photoresist layer PR can be removed based on an ashing process. Accordingly, the first emitting layer EL1 and the first sacrificial layer SCF1 can be disposed on the first anode electrode AE1 in the first sub-pixel area SPXA1, the second anode electrode AE2 and the third anode electrode AE3 can be exposed in the second sub-pixel area SPXA2 and the third sub-pixel area SPXA3, and the first to third cathode bridging layers CBR1 to CBR3 can be exposed in the first to third sub-pixel areas SPXA1 to SPXA3.

[0157] Reference Figures 14 to 17 The second emitting layer EL2 and the second sacrificial layer SCF2 can be manufactured similarly to the process of forming the first emitting layer EL1 and the first sacrificial layer SCF1. Accordingly, in conjunction with the above-described portions, the process for patterning the second emitting layer EL2 and the second sacrificial layer SCF2 will be clearly understood.

[0158] Reference Figure 14 The second base emitting layer EL2_B and the second base sacrificial layer SCF_B2 can be formed on the first sacrificial layer SCF1, the second anode electrode AE2 and the third anode electrode AE3, and the cathode bridging layer CBR.

[0159] The second base emitting layer EL2_B can include a material for forming the second emitting layer EL2 of the second sub-pixel SPX2. The second base sacrificial layer SCF_B2 can include a material for forming the residual sacrificial layer SCF_R.

[0160] In this step, the second base emitting layer EL2_B and the second base sacrificial layer SCF_B2 can be disposed throughout the first to third sub-pixel areas SPXA1 to SPXA3.

[0161] Referring to Figure 15 A photoresist layer PR can be patterned on the second base light emitting layer EL2_B using a mask MAS.

[0162] In some embodiments, the mask MAS can include a full tone portion FP, a half tone portion HP, and a blocking portion BP. A first photoresist layer PR_F corresponding to the full tone portion FP in the third direction DR3 can be disposed in the second sub-pixel area SPXA2, and a second photoresist layer PR_H corresponding to the half tone portion HP in the third direction DR3 can be disposed in the first and third sub-pixel areas SPXA1 and SPXA3. The opening OPN can overlap the cathode bridging layer CBR in a plan view.

[0163] Referring to Figure 16 and Figure 17 The second base light emitting layer EL2_B and the second base sacrificial layer SCF_B2 can be etched based on the photoresist layer PR manufactured using the mask MAS including the half tone portion HP, and the second light emitting layer EL2 and the second sacrificial layer SCF2 can be provided.

[0164] In this step, the first to third cathode bridging layers CBR1 to CBR3 can be exposed, and the third anode electrode AE3 can be exposed.

[0165] Referring to Figures 18 to 21 The third light emitting layer EL3 and the third sacrificial layer SCF3 can be manufactured similarly to the processes of forming the first and second light emitting layers EL1 and EL2 and the first and second sacrificial layers SCF1 and SCF2. Accordingly, the processes for patterning the third light emitting layer EL3 and the third sacrificial layer SCF3 will be clearly understood in connection with the above-described portions.

[0166] Referring to Figure 18 The third base light emitting layer EL3_B and the third base sacrificial layer SCF_B3 can be formed on the first and second sacrificial layers SCF1 and SCF2, the third anode electrode AE3, and the cathode bridging layer CBR.

[0167] The third base light emitting layer EL3_B can include a material for forming the third light emitting layer EL3 of the third sub-pixel SPX3. The third base sacrificial layer SCF_B3 can include a material for forming the residual sacrificial layer SCF_R.

[0168] In this step, the third base light emitting layer EL3_B and the third base sacrificial layer SCF_B3 can be disposed throughout the first to third sub-pixel areas SPXA1 to SPXA3.

[0169] Referring toFigure 19 The photoresist layer PR can be patterned on the third substrate sacrificial layer SCF_B3 using a mask MAS.

[0170] In some embodiments, the mask MAS may include a full-tone portion FP, a half-tone portion HP, and a blocking portion BP. A first photoresist layer PR_F corresponding to the full-tone portion FP on the third-direction DR3 may be disposed in the third sub-pixel region SPXA3, and a second photoresist layer PR_H corresponding to the half-tone portion HP on the third-direction DR3 may be disposed in the first sub-pixel region SPXA1 and the second sub-pixel region SPXA2. The opening OPN may overlap with the cathode bridging layer CBR in the planar view.

[0171] refer to Figure 20 and Figure 21 The third substrate luminescent layer EL3_B and the third substrate sacrificial layer SCF_B3 can be etched based on a photoresist layer PR fabricated using a mask MAS that includes a halftone portion HP, and the third luminescent layer EL3 and the third sacrificial layer SCF3 can be provided.

[0172] In this step, the first to third cathode bridging layers CBR1 to CBR3 can be exposed, and the first to third light-emitting layers EL1 to EL3 can be covered by the first to third sacrificial layers SCF1 to SCF3.

[0173] Meanwhile, in some embodiments, the first to third sacrificial layers SCF1 to SCF3 may respectively cover the first to third light-emitting layers EL1 to EL3. Accordingly, damage to the first to third light-emitting layers EL1 to EL3 formed on the bottom of the first to third sacrificial layers SCF1 to SCF3 can be prevented during manufacturing processes after each of the first to third sacrificial layers SCF1 to SCF3 is manufactured.

[0174] In some embodiments, as described above, the cathode bridging layer CBR may be exposed several times during the process of patterning the first to third light-emitting layers EL1 to EL3. Therefore, the cathode bridging layer CBR may be patterned in the same process as the anode electrode AE, but the top surface (or upper surface) of the cathode bridging layer CBR may have a roughness different from that of the top surface (or upper surface) of the anode electrode AE.

[0175] refer to Figure 22 The pixel-defining layer PDL can be patterned to partially cover the first to third sacrificial layers SCF1 to SCF3 and the first to third cathode bridging layers CBR1 to CBR3.

[0176] In this step, the pixel defining layer (PDL) can expose a portion of the top surface (or upper surface) of each of the first to third sacrificial layers (SCF1 to SCF3) located in the first to third sub-pixel regions (SPXA1 to SPXA3). The pixel defining layer (PDL) can expose a portion of the top surface (or upper surface) of each of the first to third cathode bridging layers (CBR1 to CBR3).

[0177] refer to Figure 23 Since at least a portion of each of the first to third sacrificial layers SCF1 to SCF3 is removed, first to third openings OP1 to OP3 that expose the first to third light-emitting layers EL1 to EL3 can be formed respectively.

[0178] In this step, a portion of the second portion P2 of each of the first to third sacrificial layers SCF1 to SCF3 in the corresponding one of the anode electrode AE ​​is removed, and at least a portion of the first portion P1 of each of the first to third sacrificial layers SCF1 to SCF3 in the corresponding one of the anode electrode AE ​​can be retained. Accordingly, the first to third residual sacrificial layers SCF_R1 to SCF_R3 can be provided.

[0179] refer to Figure 24 The cathode electrode CE can be formed by extending over the first to third sub-pixel regions SPXA1 to SPXA3.

[0180] In this step, at least a portion of the cathode electrode CE may be electrically connected to the first to third light-emitting layers EL1 to EL3. At least another portion of the cathode electrode CE may be electrically connected to the exposed top surface (or upper surface) of each of the first to third cathode bridging layers CBR1 to CBR3.

[0181] refer to Figure 25 A TFE (Transmission overlay) can be formed to cover the cathode electrode CE. In this step, a first encapsulation layer comprising inorganic materials, a second encapsulation layer comprising organic materials, and a third encapsulation layer comprising inorganic materials can be formed sequentially to form the TFE. Subsequently, in some embodiments, an upper UL (Ultra-Layer) can be formed on the TFE, and a display device DD according to a first embodiment of this disclosure can be provided.

[0182] Reference Figures 26 to 36 A method for manufacturing a display device DD according to a second embodiment of the present disclosure is described. Figures 26 to 36 In the following sections, descriptions of parts that are the same as those described above will be simplified or will no longer be repeated.

[0183] Figures 26 to 36is a schematic cross-sectional view illustrating a process step of a method of manufacturing a display device according to a second embodiment of the present disclosure. For ease of description, the process step is explained based on the cross-sectional structure described above with reference to Figure 6 . Figures 26 to 36 .

[0184] Referring to Figure 26 , the first to third cathode bridge layers CBR1 to CBR3 can be patterned on the substrate layer BSL, and the protective layer PSV can be formed on the first to third cathode bridge layers CBR1 to CBR3. Accordingly, the pixel circuit layer PCL can be manufactured.

[0185] In this step, each of the first to third cathode bridge layers CBR1 to CBR3 can be electrically connected to the second power line PL2 through a contact portion CNT that penetrates at least one insulating layer of the pixel circuit layer PCL, in some embodiments. In some embodiments, the first to third cathode bridge layers CBR1 to CBR3 can be patterned with a source electrode and / or a drain electrode of a transistor included in the pixel circuit PXC through the same process.

[0186] In this step, the first to third cathode bridge layers CBR1 to CBR3 can be completely covered by the protective layer PSV.

[0187] Referring to Figure 27 , the first to third anode electrodes AE1 to AE3 can be patterned on the protective layer PSV, and the pixel definition layer PDL can be patterned to partially cover each of the first to third anode electrodes AE1 to AE3.

[0188] In this step, each of the first to third anode electrodes AE1 to AE3 can be electrically connected to the pixel circuit PXC through a contact portion CNT that penetrates the protective layer PSV.

[0189] In this step, the pixel definition layer PDL can be formed to overlap the first to third cathode bridge layers CBR1 to CBR3 in a plan view.

[0190] Referring to Figure 28 and Figure 29 , the first to third anode electrodes AE1 to AE3 and the pixel definition layer PDL can be formed with the first substrate light emitting layer EL1_B and the first substrate sacrificial layer SCF_B1, and an etching process can be performed based on a photoresist layer PR manufactured using a mask MAS. Accordingly, the first light emitting layer EL1 and the first sacrificial layer SCF1 can be provided.

[0191] In this step, the mask MAS can include a full-tone portion FP, a half-tone portion HP, and a block portion BP. A first photoresist layer PR_F corresponding to the full-tone portion FP in the third direction DR3 can be disposed in the first sub-pixel area SPXA1, and a second photoresist layer PR_H corresponding to the half-tone portion HP in the third direction DR3 can be disposed in the second sub-pixel area SPXA2 and the third sub-pixel area SPXA3, respectively. An opening OPN corresponding to the block portion BP in the third direction DR3 can overlap the cathode bridging layer CBR in a plan view. The areas in which the full-tone portion FP, the half-tone portion HP, and the block portion BP are formed can be appropriately modified within the scope of the above-described examples. For example, the block portion BP can completely cover the cathode bridging layer CBR in a plan view, and at least a portion of the half-tone portion HP can be formed around the block portion BP covering the cathode bridging layer CBR.

[0192] In this step, the second anode electrode AE2 and the third anode electrode AE3 can be exposed. In this step, at least a portion of each of the pixel-defining layer PDL and the protective layer PSV can be etched using the mask MAS, and a top surface (or an upper surface) of the cathode bridging layer CBR can be exposed. For example, since at least a portion of each of the pixel-defining layer PDL and the protective layer PSV is removed using the mask MAS, a lower exposure hole COP can be formed. The lower exposure hole COP can include a first lower exposure hole COP1 exposing the first cathode bridging layer CBR1, a second lower exposure hole COP2 exposing the second cathode bridging layer CBR2, and a third lower exposure hole COP3 exposing the third cathode bridging layer CBR3.

[0193] Reference Figure 30 and Figure 31 The second base light-emitting layer EL2_B and the second base sacrificial layer SCF_B2 can be formed on the first sacrificial layer SCF1, the second anode electrode AE2, and the third anode electrode AE3, and the pixel-defining layer PDL, and an etching process can be performed based on the photoresist layer PR manufactured using the mask MAS. Accordingly, the second light-emitting layer EL2 and the second sacrificial layer SCF2 can be provided.

[0194] In this step, the mask MAS can include a full-tone portion FP, a half-tone portion HP, and a blocking portion BP. A first photoresist layer PR_F corresponding to the full-tone portion FP in the third direction DR3 can be disposed in the second sub-pixel area SPXA2, and a second photoresist layer PR_H corresponding to the half-tone portion HP in the third direction DR3 can be disposed in the first sub-pixel area SPXA1 and the third sub-pixel area SPXA3, respectively. An opening OPN corresponding to the blocking portion BP in the third direction DR3 can overlap the cathode bridging layer CBR in a plan view. The areas in which the full-tone portion FP, the half-tone portion HP, and the blocking portion BP are formed can be appropriately modified within the scope of the above-described examples. For example, the blocking portion BP can completely cover the cathode bridging layer CBR in a plan view, and at least a portion of the half-tone portion HP can be formed around the blocking portion BP covering the cathode bridging layer CBR.

[0195] In this step, the third anode electrode AE3 can be exposed. In this step, at least a portion of each of the pixel-defining layer PDL and the protective layer PSV can be etched using the mask MAS, and a top surface (or an upper surface) of the cathode bridging layer CBR can be exposed. For example, a portion (e.g., at least a portion of each of the second base light-emitting layer EL2_B and the second base sacrificial layer SCF_B2) formed in a space corresponding to the lower exposure hole COP can be removed using the mask MAS, and the lower exposure hole COP can be formed again.

[0196] REFERENCE Figure 32 AND Figure 33 The third base light-emitting layer EL3_B and the third base sacrificial layer SCF_B3 can be formed on the first sacrificial layer SCF1 and the second sacrificial layer SCF2, the third anode electrode AE3, and the pixel-defining layer PDL, and an etching process can be performed based on a photoresist layer PR manufactured using the mask MAS. Accordingly, the third light-emitting layer EL3 and the third sacrificial layer SCF3 can be provided.

[0197] In this step, the mask MAS can include a full-tone portion FP, a half-tone portion HP, and a blocking portion BP. A first photoresist layer PR_F corresponding to the full-tone portion FP in the third direction DR3 can be disposed in the third sub-pixel area SPXA3, and a second photoresist layer PR_H corresponding to the half-tone portion HP in the third direction DR3 can be disposed in the first sub-pixel area SPXA1 and the second sub-pixel area SPXA2, respectively. An opening OPN corresponding to the blocking portion BP in the third direction DR3 can overlap the cathode bridging layer CBR in a plan view. The areas in which the full-tone portion FP, the half-tone portion HP, and the blocking portion BP are formed can be appropriately modified within the scope of the above-described examples. For example, the blocking portion BP can completely cover the cathode bridging layer CBR in a plan view, and at least a portion of the half-tone portion HP can be formed around the blocking portion BP covering the cathode bridging layer CBR.

[0198] In this step, the first to third anode electrodes AE1 to AE3 can be covered with the first to third sacrificial layers SCF1 to SCF3, respectively. In this step, at least a portion of each of the pixel definition layer PDL and the protective layer PSV can be etched using the mask MAS, and a top surface (or an upper surface) of the cathode bridging layer CBR can be exposed. For example, a portion (e.g., at least a portion of each of the third base light-emitting layer EL3_B and the third base sacrificial layer SCF_B3) formed in a space corresponding to the lower exposure hole COP can be removed using the mask MAS, and the lower exposure hole COP can be formed again.

[0199] Referring to Figure 34 The first to third sacrificial layers SCF1 to SCF3 can be removed. In this step, a wet etching process for removing the first to third sacrificial layers SCF1 to SCF3 can be performed, and top surfaces (or upper surfaces) of the first to third light-emitting layers EL1 to EL3 can be exposed (e.g., completely exposed).

[0200] Referring to Figure 35 The cathode electrode CE can be formed throughout the first to third sub-pixel areas SPXA1 to SPXA3.

[0201] In this step, at least a portion of the cathode electrode CE can be electrically connected to the first to third light-emitting layers EL1 to EL3. At least another portion of the cathode electrode CE can be electrically connected to the top surfaces (or upper surfaces) of the exposed first to third cathode bridging layers CBR1 to CBR3 adjacent to the protective layer PSV.

[0202] Referring to Figure 36A packaging layer TFE covering the cathode electrode CE can be formed. In this step, a first packaging layer including an inorganic material, a second packaging layer including an organic material, and a third packaging layer including an inorganic material can be sequentially formed to form the packaging layer TFE. In some embodiments, an upper layer UL can be formed on the packaging layer TFE, and a display device DD according to a second embodiment of the disclosure can be provided.

[0203] Hereinafter, an electronic device 1000 including a display device DD according to an embodiment will be described.

[0204] Figure 37 is a schematic block diagram illustrating an electronic device including a display device according to an embodiment. Figure 38 is a schematic diagram illustrating an example in which the electronic device of Figure 37 is implemented as a smart phone. Figure 39 is a schematic diagram illustrating an example in which the electronic device of Figure 37 is implemented as a tablet computer.

[0205] Referring to Figures 37 to 39 , the electronic device 1000 can include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 can be a display device DD of Figure 1 . The electronic device 1000 can further include various ports for communicating with a graphics card, a sound card, a memory card, a USB device, or other systems. In an embodiment, as illustrated in Figure 38 , the electronic device 1000 can be implemented as a smart phone. In an embodiment, as illustrated in Figure 39 , the electronic device 1000 can be implemented as a tablet computer. However, the aforementioned examples are illustrative, and the electronic device 1000 is not necessarily limited to the aforementioned examples. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a navigation device for a vehicle, a computer monitor, a laptop computer, or a head-mounted display device, etc.

[0206] The processor 1010 can perform a specific computation or task. In an embodiment, the processor 1010 can be a microprocessor, a central processing unit, or an application processor, etc. The processor 1010 can be connected to other components through an address bus, a control bus, and a data bus, etc. In an embodiment, the processor 1010 can be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In an embodiment, the processor 1010 can provide input image data to the display device 1060. Accordingly, the display device 1060 can display an image based on the input image data provided from the processor 1010.

[0207] The memory device 1020 can store data required for performing operations of the electronic device 1000. For example, the memory device 1020 can include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0208] The storage device 1030 can include a solid state drive (SSD), a hard disk drive (HDD), or a CD-ROM, etc.

[0209] The I / O device 1040 can include an input device such as a keyboard, a keypad, a touchpad, a touchscreen, and a mouse, and an output device such as a speaker and a printer. In an embodiment, the display device 1060 can be included in the I / O device 1040.

[0210] The power supply 1050 can supply power required for performing operations of the electronic device 1000. For example, the power supply 1050 can be a power management integrated circuit (PMIC). In an embodiment, the power supply 1050 can supply power to the display device 1060.

[0211] The display device 1060 can display an image corresponding to visual information of the electronic device 1000. The display device 1060 can be connected to other components through a bus or other communication links.

[0212] According to the present disclosure, it is possible to provide a display device reducing a risk of voltage drop of a cathode electrode, a method of manufacturing a display device, and an electronic device including the display device.

[0213] According to the present disclosure, it is possible to provide a display device having improved display quality and a method of manufacturing a display device having improved display quality.

[0214] According to the present disclosure, it is possible to provide a display device simplifying a process step to improve convenience of a manufacturing process and reduce process cost, a method of manufacturing a display device, and an electronic device including the display device.

[0215] However, the effects of the present disclosure are not limited to those described herein. The above and other effects of the present disclosure will become more apparent by describing the present disclosure with reference to the accompanying drawings, as follows. The above description is merely an example of the technical features of the present disclosure, and various modifications and alterations can be made by those skilled in the art from the above description. Accordingly, the above-described embodiments of the present disclosure can be implemented independently or in combination.

[0216] The embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by the embodiments. The scope of protection of the present disclosure should be interpreted by the claims, and all technical spirits within the equivalent scope should be interpreted as included in the scope of the present disclosure.

Claims

1. A display device comprising: a substrate layer; an anode electrode provided over the substrate layer; a light-emitting layer provided over the anode electrode, the light-emitting layer including a first portion and a second portion; a cathode bridge layer provided over the substrate layer, the cathode bridge layer being provided in the same layer as and spaced apart from the anode electrode; a residual sacrificial layer provided over the first portion of the light-emitting layer; and a cathode electrode provided over the light-emitting layer, the cathode electrode including a portion provided over the second portion of the light-emitting layer and another portion provided over the cathode bridge layer.

2. The display device according to claim 1, further comprising: first and second power supply lines provided over the substrate layer, the first and second power supply lines being for supplying first and second voltage potentials, respectively, wherein the first and second power supply lines are provided closer to the substrate layer in a thickness direction than the cathode bridge layer, the anode electrode includes anode electrodes adjacent to each other, and the cathode bridge layer is provided between the adjacent anode electrodes and electrically connected to the second power supply line.

3. The display device according to claim 1, wherein the anode electrode and the cathode bridge layer include a structure in which a transparent conductive material, a reflective conductive material, and a transparent conductive material are sequentially provided, the anode electrode and the cathode bridge layer include a structure in which ITO / Ag / ITO are sequentially stacked in a thickness direction, the cathode electrode includes a silver-magnesium alloy, and the residual sacrificial layer includes aluminum.

4. The display device according to claim 1, further comprising: a pixel definition layer exposing the second portion of the light-emitting layer and the cathode bridge layer, wherein a top surface and an outer surface of the residual sacrificial layer are covered with the pixel definition layer, an inner surface of the residual sacrificial layer is exposed with the pixel definition layer and is in direct contact with the cathode electrode, the display device includes: a display region including a sub-pixel region, the sub-pixel region including a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region, wherein the anode electrode, the light-emitting layer, and the cathode electrode form light-emitting elements defined in the display region, the cathode bridge layer is provided in the display region, and the light-emitting elements include: a first light-emitting element formed in the first sub-pixel region and providing light of a first color, a second light-emitting element formed in the second sub-pixel region and providing light of a second color, and a third light-emitting element formed in the third sub-pixel region and providing light of a third color.

5. A display device comprising: a substrate layer; a pixel circuit layer provided over the substrate layer, the pixel circuit layer including a pixel circuit, a protective layer covering the pixel circuit, and a cathode bridge layer adjacent to the protective layer in a planar direction in which the substrate layer is provided; a light-emitting element provided over the pixel circuit layer; and a pixel definition layer provided over the pixel circuit layer, wherein ​ ​ The light-emitting element includes an anode electrode provided on the protective layer, a light-emitting layer including a portion provided on the anode electrode, and a cathode electrode including a portion provided on the light-emitting layer, The pixel-defining layer covers a portion of the anode electrode, and Another portion of the cathode electrode is electrically connected to the cathode bridge layer through a contact portion that penetrates the pixel-defining layer and the protective layer.

6. The display device according to claim 5, wherein The cathode electrode covers an upper surface of the light-emitting layer and a side surface of the light-emitting layer, and A portion of the pixel-defining layer is provided between the light-emitting layer and the anode electrode.

7. The display device according to claim 5, wherein The anode electrode includes an uppermost anode electrode portion having a first thickness in a thickness direction, The cathode bridge layer includes an uppermost cathode bridge portion having a second thickness in the thickness direction, The second thickness is greater than the first thickness, The uppermost anode electrode portion includes ITO, and the first thickness is to and the uppermost cathode bridging portion includes Ti, and the second thickness is to 8. The display device according to claim 5, wherein The pixel circuit includes a transistor including a source electrode and a drain electrode, and The cathode bridge layer, the source electrode, and the drain electrode are formed in the same layer.

9. A method of manufacturing a display device, the method comprising: forming a pixel circuit layer including a pixel circuit provided on a base layer; patterning an anode electrode and a cathode bridge layer provided on the pixel circuit layer; forming a base light-emitting layer and a base sacrificial layer covering the anode electrode and the cathode bridge layer; patterning, on the base sacrificial layer, a photoresist layer including an opening, a first photoresist layer, and a second photoresist layer using a mask including a half-tone portion, a full-tone portion, and a block portion, wherein the first photoresist layer corresponds to a position of the full-tone portion in a thickness direction, and the second photoresist layer corresponds to a position of the half-tone portion in the thickness direction; and etching the base light-emitting layer and the base sacrificial layer based on the photoresist layer, wherein the etching of the base light-emitting layer and the base sacrificial layer includes: providing a light-emitting layer by removing a portion of the base light-emitting layer; and exposing the cathode bridge layer.

10. The method according to claim 9, wherein in the etching of the base light-emitting layer and the base sacrificial layer, the first photoresist layer overlaps a position of the light-emitting layer to be manufactured in the thickness direction, the second photoresist layer does not overlap the cathode bridge layer and the light-emitting layer to be manufactured in the thickness direction, and the opening overlaps the cathode bridge layer in the thickness direction, and the exposing of the cathode bridge layer and the providing of the light-emitting layer are performed based on the photoresist layer as a same etching mask.

11. The method according to claim 9, wherein the patterning of the anode electrode and the patterning of the cathode bridge layer are performed by a same process.

12. The method according to claim 9, wherein The etching of the base light emitting layer and the base sacrificial layer further includes forming a sacrificial layer on the light emitting layer by removing at least a portion of the base sacrificial layer using a wet etching process, The method further includes: patterning a pixel defining layer to expose at least a portion of the sacrificial layer and at least a portion of the cathode bridging layer; exposing the light emitting layer by removing at least a portion of the sacrificial layer; and forming a cathode electrode electrically connected to the light emitting layer and the cathode bridging layer, and The exposing of the light emitting layer includes forming a residual sacrificial layer disposed on a portion of the light emitting layer.

13. A method of manufacturing a display device, the method comprising: forming a pixel circuit layer including a pixel circuit, a cathode bridging layer, and a protective layer covering the pixel circuit and the cathode bridging layer on a base layer; patterning an anode electrode and a pixel defining layer covering the anode electrode on the pixel circuit layer; forming a base light emitting layer and a base sacrificial layer covering the anode electrode and the pixel defining layer; patterning a photoresist layer including a first photoresist layer and a second photoresist layer on the base sacrificial layer using a mask including a half-tone portion, a full-tone portion, and a block portion, wherein the first photoresist layer corresponds to a position of the full-tone portion in a thickness direction, and the second photoresist layer corresponds to a position of the half-tone portion in the thickness direction; and etching the base light emitting layer, the base sacrificial layer, the pixel defining layer, and the protective layer based on the photoresist layer, wherein the etching of the base light emitting layer, the base sacrificial layer, the pixel defining layer, and the protective layer includes: providing a light emitting layer by removing a portion of the base light emitting layer; and exposing the cathode bridging layer.

14. The method of claim 13, wherein, the pixel circuit includes a transistor including a source electrode and a drain electrode, and the cathode bridging layer is formed with the source electrode and the drain electrode by a same process.

15. The method of claim 13, wherein, the etching of the base light emitting layer, the base sacrificial layer, the pixel defining layer, and the protective layer further includes forming a sacrificial layer on the light emitting layer by removing at least a portion of the base sacrificial layer using a wet etching process, the exposing of the cathode bridging layer includes forming a lower exposure hole penetrating the protective layer and the pixel defining layer, the method further includes: completely exposing an upper surface of the light emitting layer by removing the sacrificial layer; and forming a cathode electrode, wherein, a portion of the cathode electrode is electrically connected to the light emitting layer, and another portion of the cathode electrode is electrically connected to the cathode bridging layer through the lower exposure hole.

16. An electronic device comprising: a processor configured to provide input image data; a display device according to any one of claims 1 to 8 configured to display an image based on the input image data; and a power supply configured to supply power to the display device.

Images