Display panel and electronic equipment

Abstract

The invention discloses a display panel and electronic equipment, and relates to the technical field of display devices. The circuit layer, the display layer and the thin film packaging layer are arranged on one side of the substrate; a display area and a non-display area surrounding the display area; the circuit layer comprises a driving circuit and a plurality of signal lines connected with the driving circuit, the driving circuit and the signal lines are located in the non-display area, and the signal lines surround at least part of the display area; the non-display area further comprises at least one metal blocking structure. In the first direction, the metal blocking structures and the signal lines are at least partially overlapped and electrically connected, the metal blocking structures make contact with the signal lines and the thin film packaging layer, and the first direction is perpendicular to the plane where the substrate is located. According to the display panel, the metal blocking structure can be arranged in the area, used for arranging the signal lines, of the non-display area, the metal blocking structure does not need an independent additional frame area, and the frame width of the display panel cannot be increased while the packaging reliability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display devices, in particular to a display panel and an electronic device. BACKGROUND

[0002] With the continuous progress of science and technology, more and more electronic devices with display function are widely used in people's daily life and work, which brings great convenience to people's daily life and work, and becomes an indispensable important tool for people today.

[0003] The main component of electronic devices to realize display function is display panel. The display panel includes a multi-layer film layer stack structure with different functions. The interface between adjacent film layers is easily eroded by water vapor, which affects the performance and service life of the electronic device, so a water vapor barrier structure needs to be designed in the display panel. In the existing display panel, the design scheme of the water vapor barrier structure will occupy a large frame area, thereby increasing the frame width of the display panel. SUMMARY

[0004] In view of the above problems, the present application provides a display panel and an electronic device to achieve the purpose of reducing the frame width of the display panel. The specific scheme is as follows:

[0005] The first aspect of the present application provides a display panel, comprising:

[0006] a substrate;

[0007] a circuit layer, a display layer and a thin film encapsulation layer arranged on one side of the substrate;

[0008] a display area and a non-display area surrounding the display area;

[0009] the circuit layer comprises a driving circuit and a plurality of signal lines connected with the driving circuit, the driving circuit and the signal lines are located in the non-display area, and the signal lines surround at least part of the display area;

[0010] the non-display area further comprises at least one metal barrier structure; in a first direction, the metal barrier structure at least partially overlaps and is electrically connected with the signal line, the metal barrier structure contacts the signal line and the thin film encapsulation layer respectively, and the first direction is perpendicular to the plane where the substrate is located.

[0011] According to the above description, the display panel provided by the embodiment of the present application is provided with the metal barrier structure, which is in contact with the signal line and the thin film packaging layer respectively, and can achieve good water vapor blocking effect and improve the water vapor invasion prevention effect in the area surrounded by the metal barrier structure. In addition, in the first direction, the metal barrier structure at least partially overlaps the signal line, and the metal barrier structure can be arranged in the area where the signal line is arranged in the non-display area. The metal barrier structure does not need a separate additional frame area, and can improve the packaging reliability without increasing the frame width of the display panel.

[0012] The second aspect of the present application provides an electronic device comprising the display panel.

[0013] According to the above description, the electronic device provided by the embodiment of the present application comprises the display panel, and the water vapor invasion prevention effect can be improved by the metal barrier structure. In addition, the metal barrier structure does not occupy an additional frame area, and does not increase the width of the frame area, which facilitates the narrow frame design of the electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0015] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and are not used to limit the conditions that can be implemented by the present application. Therefore, any modification of the structure, change of the proportion relationship or adjustment of the size, which does not affect the effects and purposes that can be achieved by the present application, shall still fall within the scope of the technical content disclosed by the present application.

[0016] Figure 1 is a sectional view of a display panel;

[0017] Figure 2 is a top view of a display panel provided by an embodiment of the present application;

[0018] Figure 3 is Figure 2 is a sectional view of the display panel in the non-display area;

[0019] Figure 4 is a top view of another display panel provided by an embodiment of the present application;

[0020] Figure 5 isFigure 4 A cross-sectional view of the display panel shown in FIG. 1A at a display region;

[0021] Figure 6 A top view of another display panel provided by an embodiment of the present application;

[0022] Figure 7 A cross-sectional view of the display panel shown in FIG. 1A at a non-display region; Figure 6 A cross-sectional view of the display panel shown in FIG. 1A at a contact region between adjacent contact regions;

[0023] Figure 8 A top view of another display panel provided by an embodiment of the present application; Figure 6 A cross-sectional view of the display panel shown in FIG. 1A at a non-contact region between adjacent contact regions;

[0024] Figure 9 A top view of another display panel provided by an embodiment of the present application;

[0025] Figure 10 A cross-sectional view of the display panel shown in FIG. 1A at a non-display region; Figure 9

[0026] A top view of another display panel provided by an embodiment of the present application; Figure 11

[0027] A top view of another display panel provided by an embodiment of the present application; Figure 12

[0028] A cross-sectional view of the display panel shown in FIG. 1A at a non-display region; Figure 13

[0029] A cross-sectional view of the display panel shown in FIG. 1A at a non-display region; Figure 14

[0030] A cross-sectional view of the display panel shown in FIG. 1A at a non-display region; Figure 15

[0031] A structure schematic diagram of a pixel circuit provided by an embodiment of the present application; Figure 16

[0032] A structure schematic diagram of an electronic device provided by an embodiment of the present application; Figure 17

[0033] A structure schematic diagram of a shift register unit in a driving circuit provided by an embodiment of the present application. Figure 18 The following is a description of the reference signs:

[0034]

[0035] ​Non-display area 100, first area 100a, second area 100b, third area 100c, fourth area 100d, display area 101, barrier wall 102, substrate 103, first inorganic layer 104, circuit layer 105, thin film packaging layer 106, first inorganic thin film 106a, organic thin film 106b, second inorganic thin film 106c, signal line 107, first signal line 107a, second signal line 107b, metal barrier structure 108, first barrier structure 108a, second barrier structure 108b, groove 109, binding area 110, first power line 111, pixel circuit 112, display layer 113, anode layer 113a, light-emitting functional layer 113b, cathode layer 113c, light-emitting element 113d, pixel definition layer 114, transfer layer 115, contact area 116, non-contact area 117, organic planarization layer 118, electronic device 119, shift register unit 120, first output unit 121, second output unit 122, first driving voltage line 123, second driving voltage line 124, scanning line 125, first direction Y, second direction X, cutting channel A, slotted area B, first barrier wall area C, second barrier wall area D, first spacing area W1, second spacing area W2, third spacing area W3, first metal layer M1, capacitor metal layer Mc, second metal layer M2, third metal layer M3, height H, first height H1, second height H2, first width L1, second width L2, first control transistor T1, data transistor T2, driving transistor T3, threshold compensation transistor T4, first reset transistor T5, second control transistor T6, second reset transistor T7, storage capacitor Cst, first node N1, second node N2, third node N3, fourth node N4, first gate signal SN1, second gate signal SN2, third gate signal SP, light-emitting control signal Em, reset voltage VREF, first power signal PVEE, second power signal PVDD, data voltage DATA. DETAILED DESCRIPTION

[0036] The embodiments in the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Those skilled in the art can know that the technical solutions provided by the embodiments in the present application are also applicable to similar technical problems as the technology develops and new scenarios appear.

[0037] Reference Figure 1 , Figure 1 is a sectional view of a display panel, which includes a display area 101 and a non-display area 100 surrounding the display area 101. For ease of illustration, Figure 1 The structure of the display panel in the display area 101 is not shown in

[0038] As Figure 1As shown, the barrier wall 102 for blocking water vapor erosion is formed in the non-display area 100 of the display panel based on the stack structure of the metal layer and the inorganic layer in the display panel. The barrier wall 102 surrounds the organic material film layer in the display panel on one hand to block the water vapor from invading the organic material film layer from the side, and on the other hand, can also prolong the invasion path of the water vapor, so as to improve the water vapor invasion resistance of the display panel.

[0039] In order to achieve a better water vapor invasion prevention effect, the barrier wall 102 needs to have a sufficient width size. In order to realize the narrow frame design of the display panel, the width of the peripheral non-display area 100 of the display panel is continuously compressed, resulting in that the layout space of the barrier wall 102 is smaller and smaller, and the water prevention design part of the barrier wall 102 alone can not meet the water vapor invasion prevention effect of the display panel.

[0040] Therefore, the embodiment of the present application provides a display panel, which comprises:

[0041] a substrate;

[0042] a circuit layer, a display layer and a thin film encapsulation layer arranged on one side of the substrate;

[0043] a display area and a non-display area surrounding the display area;

[0044] the circuit layer comprises a driving circuit and a plurality of signal lines connected with the driving circuit, the driving circuit and the signal lines are located in the non-display area, and the signal lines surround at least part of the area of the display area;

[0045] the non-display area further comprises at least one metal barrier structure, the metal barrier structure at least partially overlaps and is electrically connected with the signal lines in a first direction, the metal barrier structure is in contact with the signal lines and the thin film encapsulation layer respectively, and the first direction is perpendicular to the plane where the substrate is located.

[0046] The display panel provided by the embodiment of the present application is provided with the metal barrier structure, the metal barrier structure is in contact with the signal lines and the thin film encapsulation layer respectively, can achieve a good water vapor blocking effect, and improve the water vapor invasion prevention effect of the area surrounded by the metal barrier structure in the display panel. In addition, in the first direction, the metal barrier structure can be arranged in the area of the non-display area for arranging the signal lines, the metal barrier structure does not need a separate additional frame area, so as not to increase the frame width of the display panel, and facilitate the narrow frame design of the display panel.

[0047] In order to make the above-mentioned purposes, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0048] Reference Figure 2 and Figure 3 , Figure 2A top view of a display panel provided in an embodiment of the present application, Figure 3 A cross-sectional view of a display panel provided in an embodiment of the present application, Figure 2 A cross-sectional view of a display panel provided in an embodiment of the present application,

[0049] A substrate 103;

[0050] A circuit layer 105, a display layer and a thin film encapsulation layer 106 disposed on one side of the substrate 103; Figure 2 An anode layer 113a in the display layer is shown in the figure;

[0051] A display area 101 and a non-display area 100 surrounding the display area 101;

[0052] The circuit layer 105 includes a driving circuit and a plurality of signal lines 107 connected to the driving circuit, the driving circuit and the signal lines 107 are located in the non-display area 100, and the signal lines 107 surround at least part of the display area 101; the driving circuit includes a plurality of cascaded shift register units (VSRs), which are not shown in the figures of the embodiments of the present application.

[0053] The non-display area 100 further includes at least one metal barrier structure 108; in a first direction Y, the metal barrier structure 108 at least partially overlaps and is electrically connected to the signal lines 107, the metal barrier structure 108 is in contact with the signal lines 107 and the thin film encapsulation layer 106 respectively, and the first direction Y is perpendicular to the plane in which the substrate 103 lies.

[0054] The non-display area 100 on one side of the display panel includes a binding area 110 for binding a control chip. The metal barrier structure 108 can be located in the non-display area 100 on the other three sides of the display panel.

[0055] The thin film encapsulation layer 106 includes a first inorganic thin film 106a, a side surface of the metal barrier structure 108 away from the substrate 103 is in contact with the first inorganic thin film 106a, and a side of the metal barrier structure 108 facing the substrate 103 is in contact with the signal lines 107, the overlapping part of the first inorganic thin film 106a, the metal barrier structure 108 and the signal lines 107 in the first direction Y forms a laminated structure of an inorganic thin film and a metal layer, the inorganic thin film and the metal layer are in direct contact in the laminated structure, so as to isolate the organic layer between the thin film encapsulation layer 106 and the signal lines 107 in the display panel, reduce the risk of water vapor invading the organic layer between the thin film encapsulation layer 106 and the signal lines 107, and improve the water vapor invasion resistance of the display panel.

[0056] The substrate 103 can be a glass plate or a flexible substrate (such as a flexible polyimide plate) that can be bent, and the material of the substrate 103 is not limited in the embodiments of the present application.

[0057] Optionally, the thin film encapsulation layer 106 comprises a first inorganic thin film 106a, an organic thin film 106b and a second inorganic thin film 106c which are sequentially stacked. The metal barrier structure 108 contacts the first inorganic thin film 106a on a side surface of the substrate 103.

[0058] Based on the above description, it can be known that the display panel provided by the embodiment of the present application is provided with the metal barrier structure 108 which contacts the signal line 107 and the thin film encapsulation layer 106, so that a good water vapor blocking effect can be achieved, and the water vapor invasion effect in the area surrounded by the metal barrier structure 108 of the display panel can be improved.

[0059] In the first direction Y, since the metal barrier structure 108 at least partially overlaps the signal line 107, the metal barrier structure 108 can be arranged in the area where the signal line 107 is arranged in the non-display area 100, and the metal barrier structure 108 does not need a separate additional frame area, so that the frame width of the display panel is not increased.

[0060] On the basis of other embodiments, in some embodiments of the embodiment of the present application, the substrate 103 and the circuit layer 105 have a first inorganic layer 104. The first inorganic layer 104 can be a single-layer inorganic thin film or a stacked structure of multiple-layer inorganic thin films. The first inorganic layer 104 is used to achieve at least one of the following effects: insulation and isolation between different metal layers in the display panel, improvement of the adhesion stability of the circuit layer 105 on the surface of the substrate 103, and film formation quality of the film layer structure in the circuit layer 105.

[0061] In the second direction X, the non-display area 100 comprises a first area 100a, a second area 100b, a third area 100c and a fourth area 100d which are sequentially arranged. The second direction is parallel to the direction in which the non-display area 100 points to the display area 101.

[0062] Optionally, the periphery of the first area 100a comprises a cutting channel A, based on which the redundant part of the periphery of the non-display area 100 can be cut and removed. The second area 100b is used to arrange a first power line 111 which is used to transmit a first power signal PVEE. The third area 100c comprises a driving circuit and a signal line 107 connected thereto. The fourth area 100d serves as a transition area between the driving circuit and the display area 101, and is used for the connection wiring of the driving circuit and the pixel circuit in the display area 101.

[0063] On the basis of other embodiments, in some embodiments of the embodiment of the present application, the first inorganic layer 104 located in the first area 100a comprises a slotted area B, and the first inorganic layer 104 has a groove 109 in the slotted area B, which is used to release the stress in the first inorganic layer 104 and prevent the first inorganic layer 104 from cracking.

[0064] Optionally, the display panel further comprises a barrier wall 102, the barrier wall 102 surrounds the plurality of signal lines 107, and each signal line 107 is located on a side of the barrier wall 102 facing the display area 101. The non-display area 100 can comprise at least one barrier wall 102, which can simultaneously block the invasion of water vapor through the barrier wall 102 and the metal barrier structure 108, thereby improving the packaging reliability of the display panel.

[0065] One or more barrier walls 102 can be formed according to the layout space of the non-display area 100 in the display panel, and the number of barrier walls 102 is not limited to two. Figure 2 The slot area B can be arranged between the cutting groove A and the barrier wall 102.

[0066] Optionally, the barrier wall 102 at least partially overlaps the first power line 111, so as to form the barrier wall 102 based on the metal layer of the first power line 111.

[0067] In the manner shown in Figure 3 The display panel comprises two barrier walls 102, the outer barrier wall 102 is located in the first barrier wall area C, and the inner barrier wall 102 is located in the second barrier wall area D. At least the second barrier wall area D is located in the second area 100b. The first barrier wall area C can be at least partially located in the second area 100b. The first barrier wall area C and the slot area B have a first spacing area W1, the first barrier wall area C and the second barrier wall area D have a second spacing area W2, and the second barrier wall area D and the third area 100c have a third spacing area W3. Among them, the first spacing area W1 is a clearance area outside the barrier wall 102, the second spacing area W2 is a gap area between two adjacent barrier walls 102, and the third spacing area W3 is a clearance area inside the barrier wall 102.

[0068] In a narrow-frame display panel, in addition to the barrier wall 102 which can improve the water vapor invasion path, the effective packaging area is mainly the first spacing area W1, the second spacing area W2 and the third spacing area W3. The three spacing areas are the contact areas of the inorganic material film layer and the inorganic material film layer or the contact areas of the inorganic material film layer and the metal layer, which can form a good barrier to prevent water vapor from invading.

[0069] In the first spacing area W1, the first inorganic film 106a in the thin film packaging layer 106 directly contacts the first inorganic layer 104 below the metal layer where the metal barrier structure 108 is located, forming a contact area of the inorganic material film layer and the inorganic material film layer, which surrounds each layer structure in the display panel, and can form a good effect of preventing water vapor from invading.

[0070] In the second interval region W2, the second inorganic thin film 106c in the thin film encapsulation layer 106 directly contacts the multi-layer metal stack layer below the barrier wall 102, forming a contact region of the inorganic material film layer and the metal layer, which surrounds the structures of the layers in the display panel, and can form a good water vapor intrusion prevention effect.

[0071] In the third interval region W3, the first inorganic thin film 106a in the thin film encapsulation layer 106 directly contacts the multi-layer metal stack layer below the barrier wall 102, forming a contact region of the inorganic material film layer and the metal layer, which surrounds the structures of the layers in the display panel, and can form a good water vapor intrusion prevention effect.

[0072] In the three interval regions, the contact region of the inorganic material film layer and the inorganic material film layer or the contact region of the inorganic material film layer and the metal layer surrounds the organic layer and its interface in the display panel to isolate them from the external environment, preventing water vapor from intruding into the display panel based on the higher hydrophilicity of the organic material film layer or its interface, improving the water vapor intrusion prevention performance of the display panel, and thus improving the encapsulation effect of the display panel, and improving the reliability and service life of the display panel.

[0073] The possible intrusion paths of water vapor mainly include: the contact interface of the first inorganic thin film 106a and the first inorganic layer 104 in the first interval region W1 and the contact interface of the first inorganic thin film 106a and the metal layer in the third interval region W3; the organic thin film 106b between the two inorganic thin films in the thin film encapsulation layer 106. As long as the contact effect of the first inorganic thin film 106a with the first inorganic layer 104 and the metal layer below is ensured in the display panel, the encapsulation reliability will not be a problem, and a good water vapor intrusion prevention effect can be achieved.

[0074] However, in order to meet the narrow frame design requirements of the display panel, the width of the non-display area 100 in the second direction X is continuously compressed. The width of the non-display area 100 in the conventional display panel is generally about 750 μm to 800 μm, and in the narrow frame product design, the width of the non-display area 100 needs to be compressed to 500 μm. The reduction of the width of the non-display area 100 will cause the width of the barrier wall 102 and the above-mentioned effective encapsulation region in the display panel to be greatly compressed, thereby reducing the water vapor intrusion prevention effect of the effective encapsulation region.

[0075] For example, for a display panel with a non-display area width of 750 microns, the widths of the first, second and third spacing areas W1, W2 and W3 in the effective packaging area can be 70 microns, 40 microns and 45 microns, respectively. When the width of the non-display area 100 is compressed to 600 microns, the widths of the first, second and third spacing areas W1, W2 and W3 can be 50 microns, 30 microns and 20 microns, respectively. The width of the effective packaging area needs to be compressed by 55 microns in total. When the width of the non-display area 100 is compressed to 500 microns, the widths of the first, second and third spacing areas W1, W2 and W3 can be 40 microns, 20 microns and 20 microns, respectively. The width of the effective packaging area needs to be compressed by 75 microns in total. The width of the effective packaging area is greatly compressed, which will greatly affect the water vapor intrusion prevention effect, thereby affecting the reliability of the display panel.

[0076] For a display panel with a narrow frame design, when the width of the non-display area 100 is less than 750 microns, such as 700 microns, or 600 microns, or 650 microns, or 500 microns, or even less, the width of the non-display area 100 is not sufficient to layout the width dimension of the barrier wall 102 and the effective packaging area that meet the high water vapor intrusion prevention performance. The metal barrier structure 108 can be laid out in the area on the side of the signal line 107 away from the substrate 103 to improve the water vapor intrusion prevention performance of the display panel. Since the metal barrier structure 108 at least partially overlaps the signal line 107 in the first direction Y, the metal barrier structure 108 can be laid out in the space on the side of the signal line 107 away from the substrate 103, without the need to increase the width of the non-display area 100.

[0077] In the embodiments of the present application, one side surface of the metal barrier structure 108 is in contact with the first inorganic thin film 106a, and the other side surface is in contact with the signal line 107. The signal line 107 is in contact with the first inorganic layer 104. The first inorganic thin film 106a, the metal barrier structure 108, the signal line 107 and the first inorganic layer 104 form a stack structure of an inorganic material film layer-metal layer-metal layer-inorganic material thin film. The stack structure is a direct contact stack structure of an inorganic material film layer and a metal layer, which blocks the intrusion path of water vapor from the outside of the display panel to the inside organic layer and its interface, effectively improves the water vapor intrusion prevention performance of the display panel, and improves the packaging reliability of the display panel. Moreover, the metal barrier structure 108 can be laid out in the space on the side of the signal line 107 away from the substrate 103, which can improve the water vapor intrusion prevention performance of the display panel without increasing the width of the non-display area, and can enable the display panel to have good water vapor intrusion prevention performance while realizing a narrow frame design.

[0078] Optionally, the width of the metal barrier structure 108 in the second direction X can be greater than or equal to 15 μm, so that the metal barrier structure 108 can have a larger contact area with the thin film encapsulation layer 106 and the signal line 107, to achieve a better water vapor barrier effect. Further, the width of the metal barrier structure 108 can be greater than or equal to 20 μm. Further, the width of the metal barrier structure 108 can be 20 μm to 60 μm.

[0079] In some embodiments of the present application, as shown in Figure 3 the plurality of signal lines 107 includes at least a first signal line 107a and a second signal line 107b, the width of the first signal line 107a is greater than the width of the second signal line 107b; and the surface of the first signal line 107a is provided with the metal barrier structure 108. In this way, the metal barrier structure 108 can be provided on the surface of the first signal line 107a with a large width, so that the metal barrier structure 108 and the first signal line 107a have a larger contact area, and a better water vapor barrier effect can be achieved, and the encapsulation reliability of the display panel can be greatly improved.

[0080] Reference is made to Figure 4 and Figure 5 , Figure 4 a top view of another display panel provided by the present application, Figure 5 a cross-sectional view of the display panel shown in Figure 4 On the basis of other embodiments, Figure 4 and Figure 5 In the display panel shown in

[0081] The display panel is an OLED panel, and the display layer 113 includes a plurality of light emitting elements 113d, and the light emitting elements 113d are OLEDs. The surface of the circuit layer 105 away from the substrate 103 has an anode layer 113a, and the anode layer 113a includes a plurality of anodes. The surface of the circuit layer 105 away from the substrate 103 has a pixel definition layer 114, and the pixel definition layer 114 has a plurality of pixel openings, and the pixel openings correspond one-to-one to the light emitting elements 113d, and are used to expose the anodes of the corresponding light emitting elements 113d. The light emitting functional layer 113b is formed on the surface of the anode of the pixel opening, and the cathode layer 113c is formed on the surface of the light emitting functional layer 113b. The cathode layer 113c is a common cathode of all the light emitting elements 113d.

[0082] The anode of the light-emitting element 113d is connected to the pixel circuit 112. The cathode of the light-emitting element 113d is connected to the first power line 111 to receive the first power signal PVEE.

[0083] In the display layer 113, the light-emitting functional layer 113b and the pixel definition layer 114 are made of organic materials, which are easily penetrated by moisture. Figure 4 and Figure 5 In the illustrated configuration, by surrounding the cathode layer 113c with the metal barrier structure 108, moisture can be effectively prevented from entering the display layer 113 through the interface between the cathode layer 113c and the pixel definition layer 114, thereby improving the moisture intrusion resistance of the display panel and enhancing the reliability of the packaging.

[0084] like Figure 5 As shown, the circuit layer 105 includes multiple metal layers, which include a first metal layer M1, a capacitor metal layer Mc, a second metal layer M2, and a third metal layer M3 sequentially formed on the surface of the substrate 103. An insulating layer is provided between adjacent metal layers; the insulating layer can be an inorganic thin film or a planarization layer of an organic material. Within the display area 101, the circuit layer includes a pixel circuit 112, which includes a transistor and a storage capacitor. The first metal layer M1 is used at least to fabricate the gate of the transistor, the capacitor metal layer Mc is used at least to fabricate the electrode of the storage capacitor, the second metal layer M2 is used at least to fabricate the source and drain of the transistor, and the third metal layer M3 is used at least to fabricate the connection line between the pixel circuit and the anode of the light-emitting element.

[0085] In some embodiments of this application, based on other methods, the signal line 107 is located in the second metal layer M2, that is, the signal line 107 and the source and drain of the transistor are located in the same metal layer.

[0086] Alternatively, a metal barrier structure 108 can be fabricated using a third metal layer M3.

[0087] In this embodiment, the metal barrier structure 108 can be fabricated using one or more metal layers between the second metal layer M2 and the anode layer 113a, and is not limited to being fabricated based on the third metal layer M3. In other embodiments, a fourth metal layer may be included between the third metal layer M3 and the anode layer 113a. The metal barrier structure 108 can also be formed based on a stacked structure where the third metal layer M3 and the fourth metal layer are in direct contact, or it can be formed solely based on the fourth metal layer. In the display area 101, the fourth metal layer can also be used to form the wires connected to the pixel circuit 112 and / or the transition lines between different metal layers.

[0088] Optionally, the first power line 111 may be a metal stack structure of the second metal layer M2 and the third metal layer M3, or a metal stack structure of the second metal layer M2, the third metal layer M3 and the fourth metal layer, in which adjacent metal layers are in direct contact.

[0089] refer to Figures 6-8 , Figure 6 This is a top view of yet another display panel provided in an embodiment of this application. Figure 7 for Figure 6 The image shown is a cross-sectional view of the display panel at the contact area between the metal barrier structure and the thin-film encapsulation structure. Figure 8 for Figure 6 The image shows a cross-sectional view of the non-contact area between adjacent contact areas of the display panel. Based on other methods, Figure 6 and Figure 8 In the display panel shown, the circuit layer 105 also includes a first power line 111. The first power line 111 is located on the side of the multiple signal lines 107 away from the display area 101, that is, the first power line 111 surrounds the multiple signal lines 107. The cathode line 111 can not only provide the first power signal PVEE, but also provide electromagnetic shielding for the metal structures in the area it surrounds, preventing these metal structures from being damaged by electrostatic discharge.

[0090] like Figures 6-8 As shown, multiple signal lines 107 have a transition layer 115 on the side facing away from the substrate 103; the cathode layer 113c and the first power line 111 are electrically connected through the transition layer 115; the first power line 111 is located outside the metal barrier structure 108, surrounding the metal barrier structure 108, the signal lines 107, and the cathode layer 113c, providing good electrostatic protection. Since the metal barrier structure 108 is located between the first power line 111 and the cathode layer 113c, a transition layer 115 that can cross the metal barrier structure 108 is needed to connect the first power line 111 and the cathode layer 113c. Optionally, the transition layer 115 can be located in the anode layer 113a, that is, the transition layer 115 and the anode of the light-emitting element 113d are located in the same metal layer, and are insulated from the anode of the light-emitting element 113d.

[0091] like Figures 6-8 As shown, along the extension path of the metal barrier structure 108, a plurality of contact regions 116 are spaced apart between the metal barrier structure 108 and the thin-film encapsulation layer 106, and non-contact regions 117 are separated from adjacent contact regions 116. In the contact regions 116, the metal barrier structure 108 can directly contact the underlying signal line 107. In the non-contact regions 117, the metal barrier structure 108 does not contact the underlying signal line 107, and the two are insulated from each other.

[0092] likeFigure 6 As shown, in the contact area 116, the adapter layer 115 includes an opening and is insulated from the metal barrier structure 108. The opening in the contact area 116 allows the metal barrier structure 108 to directly contact the signal line 107 below, and prevents short circuits between the adapter layer 115 and the metal barrier structure 108, thus achieving insulation between the adapter layer 115 and the metal barrier structure 108.

[0093] like Figure 7 As shown, in the contact area 116 between the metal barrier structure 108 and the thin-film encapsulation layer 106, the metal barrier structure 108 and the thin-film encapsulation layer 106 are in direct contact to form a laminated structure of inorganic material film and metal layer with good water vapor intrusion resistance, which can improve the encapsulation reliability of the display panel. The non-contact area 117 between the contact areas 116 is used to cross the transition layer 115 to electrically connect the first power line 111 and the cathode layer 113c.

[0094] In addition to other methods, some implementations of the embodiments of this application, such as Figure 7 and Figure 8 As shown, an organic planarization layer 118 is included between the metal barrier structure 108 and the thin-film encapsulation layer 106. For example... Figure 7 As shown, the organic planarization layer 118 has a through-region, through which the metal barrier structure 108 and the thin-film encapsulation layer 106 contact, forming a contact region 116. For example... Figure 8 As shown, along the first direction Y and between adjacent through-areas, the transition layer 115 and the metal barrier structure 108 include an organic planarization layer 118 and a metal barrier structure 108, thereby achieving insulation between the transition layer 115 and the metal barrier structure 108. In this method, the patterned organic planarization layer 118 is removed at the corresponding contact area 116, allowing the metal barrier structure 108 to directly contact the thin-film encapsulation layer 106, forming a stacked structure of inorganic material thin film and metal layer, thus improving the encapsulation reliability of the display panel. The organic planarization layer 118 between the metal barrier structure 108 and the thin-film encapsulation layer 106 is retained at the corresponding non-contact area 117. The organic planarization layer 118 has a relatively large thickness, enabling good insulation between the transition layer 115 and the metal barrier structure 108. When the first power line 111 and the cathode layer 113c are connected through the transition layer 115, a short circuit problem can be effectively prevented with the signal line 107 connected to the metal barrier structure 108.

[0095] In some embodiments of this application, in the non-contact region 117, the transition layer 115 can contact and be electrically connected to the cathode layer 113c. For example... Figure 8As shown, in the non-contact area 117, the metal blocking structure 108 and the signal line 107 can be insulated and separated by the organic planarization layer 118, the transfer layer 115 can connect the first power supply line 111 and the cathode layer 113c in the non-contact area 117, and the transfer layer 115 can be insulated and separated from the metal blocking structure 108 based on the organic planarization layer 118 in the non-contact area 117.

[0096] As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 6 As shown, the metal blocking structure 108 and the thin film encapsulation layer 106 have a plurality of non-contact areas 117 arranged at intervals, and the adjacent non-contact areas 117 have a contact area 116; the transfer layer 115 can pass through the plurality of non-contact areas 117 to connect the first power supply line 111 and the cathode layer 113c. In this way, the first power supply line 111 and the cathode layer 113c have a plurality of connection positions, so as to reduce the contact resistance, improve the voltage uniformity of the cathode layer 113c, and avoid the problem of uneven display caused by uneven voltage on the cathode layer 113c.

[0097] As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 9 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 10 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 9 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 10 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 9 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 9 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 10 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 9 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 10 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115.

[0098] As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115.

[0099] As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 9 As shown in FIG. 1, the display panel 100 includes a display area 101 and a non-display area 100 surrounding the display area 101. The display area 101 includes a plurality of sub-pixels 110, and each of the sub-pixels 110 includes a first power supply line 111, a cathode layer 113c, and a transfer layer 115. Figure 10In the shown mode, a plurality of metal barrier structures 108 can be formed based on different signal lines 107, and the plurality of metal barrier structures 108 can respectively form a waterproof stack structure of inorganic thin film layer (first inorganic thin film 106a in the thin film encapsulation layer 106)-metal layer (metal barrier structure 108)-metal layer (signal line 107) with the inorganic thin film and the metal layer or the metal layer and the metal layer between adjacent film layers in the waterproof stack structure being in direct contact, blocking the organic material layer, which can greatly improve the encapsulation reliability and make the display panel have better waterproof vapor invasion effect.

[0100] Further, in the shown mode, the metal barrier structure 108 can be arranged in the display area 101 and the non-display area 100. Figure 9 and Figure 10 In the shown mode, in the direction of the non-display area 100 pointing to the display area 101, there is at least one signal line 107 between the signal lines 107 contacted by the two adjacent metal barrier structures 108, so that there is enough layout space between the two adjacent metal barrier structures 108 to facilitate the process preparation of the plurality of metal barrier structures 108, and also can prevent the short circuit problem between the metal barrier structures 108 caused by too small spacing between the adjacent metal barrier structures 108.

[0101] Reference is made to Figure 11 , Figure 11 Another top view of a display panel provided by the embodiments of the present application is provided, which is based on other modes. Figure 11 In the shown mode, in the extension path of the metal barrier structure 108, the metal barrier structure 108 and the thin film encapsulation layer 106 have a plurality of contact areas 116 arranged at intervals, and the adjacent contact areas 116 include a non-contact area 117, and the metal barrier structure 108 and the thin film encapsulation layer 106 are not in contact in the non-contact area 117. As described above, the metal barrier structure 108 and the thin film encapsulation layer 106 can be isolated based on the organic planarization layer 118 in the non-contact area 117. For the two adjacent metal barrier structures 108, in the direction of the non-display area 100 pointing to the display area 101, the contact area 116 corresponding to one metal barrier structure 108 at least partially overlaps with the non-contact area 117 corresponding to the other metal barrier structure 108, as shown in Figure 11 The contact area 116 in the first barrier structure 108a and the non-contact area 117 in the second barrier structure 108b at least partially overlap, which can stagger the layout of the contact areas 116 in the two adjacent metal barrier structures 108.

[0102] As described above, the transition layer 115 connecting the first power line 111 and the cathode layer 113c needs to cross the metal barrier structure 108 at the non-contact area 117, so that the transition layer 115 can be insulated from the metal barrier structure 108 by the organic planarization layer 118 at the non-contact area 117 to avoid short circuit between the transition layer 115 and the metal barrier structure 108. Therefore, the organic planarization layer 118 needs to be reserved between the metal barrier structure 108 and the thin film encapsulation layer 106 at the non-contact area 117, and the organic planarization layer 118 at the non-contact area 117 is at risk of being invaded by water vapor. In Figure 11 In the illustrated manner, in the direction from the non-display area 100 to the display area 101, the contact areas 116 in the two adjacent metal barrier structures 108 are staggered, so that for the two adjacent metal barrier structures 108, the contact area 116 of one metal barrier structure 108 can block the water vapor invasion path of the corresponding non-contact area 117 of the other metal barrier structure 108, thereby improving the encapsulation reliability of the display panel.

[0103] Reference Figure 12 , Figure 12 Another top view of a display panel is provided for the embodiments of the present application, which is based on other manners, Figure 11 In the illustrated manner, in the extension path of the metal barrier structure 108, the metal barrier structure 108 and the thin film encapsulation layer 106 have a plurality of contact areas 116 arranged at intervals, the non-contact area 117 is included between adjacent contact areas 116, and the metal barrier structure 108 and the thin film encapsulation layer 106 are not in contact at the non-contact area 117; for the two adjacent metal barrier structures 108, in the direction from the non-display area 100 to the display area 101, the non-contact area 117 corresponding to one metal barrier structure 108 at least partially overlaps the non-contact area 117 corresponding to the other metal barrier structure 108. In Figure 12 In the illustrated manner, the non-contact areas 117 in the two adjacent metal barrier structures 108 are completely overlapped, that is, the non-contact areas 117 corresponding to the two metal barrier structures 108 are completely arranged opposite to each other, and in other manners, the non-contact areas 117 in the two adjacent metal barrier structures 108 can also be partially overlapped.

[0104] The non-contact area 117 is used to achieve the insulation of the transition layer 115 crossing the metal barrier structure 108, and the non-contact area 117 is the insulation area of the transition layer 115 crossing the metal barrier structure 108. If the non-contact areas 117 in the two adjacent metal barrier structures 108 are completely staggered, that is, the non-contact areas 117 in the two adjacent metal barrier structures 108 have no overlapping part, so that the transition layer 115 needs to adopt a more complex bending pattern structure when crossing the two metal barrier structures 108. Figure 12In the shown mode, for two adjacent metal barrier structures 108, the non-contact area 117 in one metal barrier structure 108 at least partially overlaps the non-contact area 117 in the other metal barrier structure 108, and the transfer layer 115 can linearly cross the two metal barrier structures 108 based on the overlapping part of the non-contact area 117, avoiding the transfer layer 115 adopting a bending pattern structure when crossing the two metal barrier structures 108, and simplifying the manufacturing process of the transfer layer 115.

[0105] With reference to Figure 13 , Figure 13 A cross-sectional view of a display panel in a non-display area is provided in an embodiment of the present application. On the basis of other embodiments, when the display panel has a plurality of metal barrier structures 108, the height H of each metal barrier structure 108 is the same. The height H of the metal barrier structure 108 can be the height of the metal barrier structure 108 relative to the base 103.

[0106] In Figure 13 the shown mode, the height H of each metal barrier structure 108 is the same, and the different metal barrier structures 108 can be manufactured using the same pattern structure, simplifying the manufacturing process of the metal barrier structure 108 in the display panel.

[0107] With reference to Figure 14 , Figure 14 A cross-sectional view of a display panel in a non-display area is provided in an embodiment of the present application. On the basis of other embodiments, when the display panel has a plurality of metal barrier structures 108, the height of at least two metal barrier structures 108 is different. In this mode, the height of at least two metal barrier structures 108 can be made different by adjusting the number of film layers between the signal line 107 and the base 103. As Figure 14 shown, one metal barrier structure 108 has a first height H1, and the other metal barrier structure 108 has a second height H2.

[0108] In Figure 14 the shown mode, because the height of at least two metal barrier structures 108 is different, the path of external water vapor in the display panel from the non-display area 100 to the display area 101 can be extended to a greater extent, and the packaging reliability is better improved.

[0109] Further, in Figure 14In the shown mode, in the direction of the display area 101 from the non-display area 100, the height of each metal barrier structure 108 is alternately arranged in the first height H1 and the second height H2. In this mode, each metal barrier structure 108 can be alternately arranged in the first height H1 and the second height H2 to form a periodic height distribution with staggered heights, which on the one hand facilitates the process preparation of the metal barrier structure 108, and on the other hand can greatly extend the path of the water vapor from the outside of the display panel to the display area 101 through the non-display area 100, thereby better improving the packaging reliability.

[0110] Reference Figure 15 , Figure 15 A cross-sectional view of a display panel in a non-display area is provided in an embodiment of the present application. On the basis of other embodiments, when the display panel has a plurality of metal barrier structures 108, in the direction of the display area 101 from the non-display area 100, the width of each metal barrier structure 108 decreases in turn. Figure 15 For example, two metal barrier structures 108 are illustrated, the metal barrier structure 108 close to the display area 101 has a first width L1, and the metal barrier structure 108 close to the display area 101 has a second width L2, L1 is greater than L2.

[0111] As Figure 15 shown, in the direction of the display area 101 from the non-display area 100, due to the width of each metal barrier structure 108 decreasing in turn, the metal barrier structure 108 farther from the display area 101 has a greater width, that is, the closer the metal barrier structure 108 is to the outside of the display panel, the greater the width. In this way, when the water vapor invades from the non-display area 100 to the display area 101, it needs to pass through the metal barrier structure 108 with a greater width first, and the metal barrier structure 108 with a greater width can greatly increase the water vapor invasion path, and can greatly block the water vapor invasion in the initial stage of water vapor invasion. Since a large part of the water vapor is blocked by the metal barrier structure 108 with a greater width in the outer region of the non-display area 100, a better water vapor blocking effect can be achieved by passing through the metal barrier structure 108 with a smaller width in the inner region of the non-display area 100. The metal barrier structure 108 with a smaller width can also reduce the material cost.

[0112] In the direction of the display area 101 from the non-display area 100, when the width of each metal barrier structure 108 decreases in turn, the height of each metal barrier structure 108 can be the same, or the height of at least two metal barrier structures 108 can be different.

[0113] In other manners, when the display panel has a plurality of metal barrier structures 108, the width of each metal barrier structure 108 is the same, so that each metal barrier structure 108 in the display panel can be processed based on the same width parameter, to simplify the manufacturing process of the metal barrier structure 108.

[0114] On the basis of the other manners, in some embodiments of the present application, for the metal barrier structure 108 and the signal line 107 contacted thereby, the width of the metal barrier structure 108 is less than the width of the signal line 107. In this way, the overlapping part of the metal barrier structure 108 and the signal line 107 in the first direction Y has a width less than the width of the signal line 107, so that the contact area 116 is located between the two side walls adjacent to the signal line 107 in the second direction X, to avoid the reliability problem caused by the exposure of the two side walls.

[0115] When the display panel has a plurality of metal barrier structures 108, two or three or even more metal barrier structures 108 can be provided, and it is not limited to one or two as shown in the drawings of the present application. When there are three or more metal barrier structures 108, the sum of the widths of all the metal barrier structures 108 is not less than 30 μm, which can greatly improve the packaging reliability.

[0116] The display area 101 has a light emitting element 113d and a pixel circuit 112 connected to the light emitting element 113d; the driving circuit is electrically connected to the transistor in the pixel circuit 112 through the scan line, for providing a gate control signal for the transistor in the pixel circuit 112.

[0117] The signal line 107 includes at least one of an initial signal line, a clock signal line, a first driving voltage line, and a second driving voltage line. In this way, the metal barrier structure 108 can be arranged based on the space layout of the existing signal line 107 in the display panel, without increasing the width of the frame of the display panel.

[0118] The initial signal line is used to input an initial signal STV for a shift register unit in the driving circuit. The clock signal line includes a first clock signal line used to input a first clock signal CK for the shift register unit in the driving circuit and a second clock signal line used to input a second clock signal XCK for the shift register unit in the driving circuit, the first clock signal CK and the second clock signal XCK being two clock signals with opposite phases. The first driving voltage line is used to input a high-level signal VGH for the shift register unit in the driving circuit. The second driving voltage line is used to input a low-level signal VGL for the shift register unit in the driving circuit. The shift register unit can output a gate control signal based on the initial signal STV, the first clock signal CK, the second clock signal XCK, the high-level signal VGH, and the low-level signal VGL.

[0119] refer to Figure 18 , Figure 18 This is a schematic diagram of a shift register unit in a driving circuit provided in an embodiment of this application. The driving circuit includes multiple cascaded shift register units 120. Each shift register unit 120 includes a first output unit 121 and a second output unit 122. The input terminal of the first output unit 121 is electrically connected to a first driving voltage line 123, and the output terminal of the first output unit 121 is electrically connected to a scan line 125. The input terminal of the second output unit 122 is electrically connected to a second driving voltage line 124, and the output terminal of the second output unit 122 is electrically connected to the scan line 125. The first driving voltage line 123 transmits a first voltage signal, and the second driving voltage line 124 transmits a second voltage signal. The potential of the second voltage signal is lower than the potential of the first voltage signal. Figure 8 In the illustrated configuration, both the first output unit 121 and the second output unit 122 include at least one transistor. The specific circuit structure of the shift register unit 120 can refer to existing circuit structures; however, this application embodiment does not limit the specific circuit structure of the first output unit 121 and the second output unit 122.

[0120] The shift register unit 120 outputs a gate control signal through the scan line 125 to control the conduction state of the transistors in the pixel circuit. The first voltage signal can be a high-level signal VGH, and the second voltage signal can be a low-level signal VGL.

[0121] exist Figure 18 In the illustrated configuration, the signal line 107 includes a first driving voltage line 123 and a second driving voltage line 124. At least one of the first driving voltage line 123 and the second driving voltage line 124 can be connected to the metal barrier structure 108 to improve the packaging reliability of the display panel. Furthermore, since the first driving voltage line 123 and the second driving voltage line 124 are wider than the clock signal line, they can be used to connect to a wider metal barrier structure 108, thereby significantly improving packaging reliability.

[0122] refer to Figure 16 , Figure 16 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. (See the accompanying drawings for the above embodiments.) Figure 16 As shown, the pixel circuit 112 includes a storage capacitor Cst and multiple transistors. Figure 16In the shown mode, the pixel circuit is a 7T1C circuit structure, that is, the pixel circuit has seven transistors and one capacitor. It should be noted that the circuit structure of the pixel circuit can be designed according to requirements, and is not limited to the circuit structure with seven transistors. The pixel circuit can be an 8-transistor circuit structure or a 9-transistor circuit structure, and the pixel circuit is not limited to the circuit structure with one capacitor, but also to the circuit structure including at least two capacitors.

[0123] Figure 16 The pixel circuit shown includes:

[0124] The driving transistor T3 has the gate connected to the first node N1, the first electrode connected to the second node N2, and the second electrode connected to the third node N3.

[0125] The first reset transistor T5 has the gate connected to the first gate signal SN1, the first electrode connected to the reset voltage VREF, and the second electrode connected to the first node N1.

[0126] The threshold compensation transistor T4 has the gate connected to the second gate signal SN2, the first electrode connected to the first node N1, and the second electrode connected to the third node N3.

[0127] The first control transistor T1 has the gate connected to the light-emitting control signal Em, the first electrode connected to the second power supply signal PVDD, and the second electrode connected to the second node N2.

[0128] The data transistor T2 has the gate connected to the third gate signal SP, the first electrode connected to the data voltage DATA, and the second electrode connected to the second node N2.

[0129] The second control transistor T6 has the gate connected to the light-emitting control signal Em, the first electrode connected to the third node N3, and the second electrode connected to the fourth node N4.

[0130] The second reset transistor T7 has the gate connected to the third gate signal SP, the first electrode connected to the reset voltage VREF, and the second electrode connected to the fourth node N4.

[0131] The fourth node N4 is connected to the anode of the light-emitting element 113d, and the cathode of the light-emitting element 113d is connected to the first power supply line to access the first power supply signal PVEE. The first power supply signal PVEE is a low-voltage signal, and the second power supply signal PVDD is a high-voltage signal. The storage capacitor Cst is connected between the first node N1 and the first electrode of the first light-emitting control transistor T1.

[0132] The first reset transistor T5 and the threshold compensation transistor T4 can be NMOS, and the other transistors can be PMOS.

[0133] For Figure 16 The display panel includes at least three driving circuits, including a first driving circuit, a second driving circuit, and a third driving circuit. A plurality of cascaded shift register units in the first driving circuit are configured to provide a first gate signal SN1 and a second gate signal SN2. A plurality of cascaded shift register units in the second driving circuit are configured to provide a third gate signal SP. A plurality of cascaded shift register units in the third driving circuit are configured to provide an emission control signal Em.

[0134] Based on the display panel provided in the above embodiments, another embodiment of the present application further provides an electronic device, as shown in the Figure 17

[0135] Referring to Figure 17 , Figure 17 FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. The electronic device 119 includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a smart wearable device, and other electronic products with a display function. The electronic device 119 includes the display panel provided by any of the above embodiments.

[0136] The electronic device provided by the embodiment of the present application adopts the display panel provided by the above embodiments, which can improve the waterproof effect by the metal barrier structure 108, and the metal barrier structure 108 does not occupy the additional frame area and does not increase the width of the frame area, thereby facilitating the narrow frame design of the electronic device.

[0137] In the description of the present application, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts of each embodiment can be referred to. The embodiments provided by the embodiments of the present application can be combined with each other without contradiction.

[0138] It should be noted that in the description of the present application, it should be understood that the drawings and the description of the embodiments are illustrative rather than limiting. The same reference numerals in the embodiments throughout the specification indicate the same structure. In addition, for the purpose of understanding and ease of description, the thickness of some layers, films, panels, regions, etc. may be exaggerated in the drawings. It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as "on" another element, the element can be directly on the other element or there can be an intermediate element. In addition, "on" means positioning an element on another element or below another element, but not essentially on the upper side of another element according to the direction of gravity.

[0139] ​The terms "upper", "lower", "top", "bottom", "inner", "outer" and the like, indicate an orientation or positional relationship based on the orientation or positional relationship as shown in the drawings, and are used only to facilitate description of the application and are not a declaration of an actual orientation of the apparatus or element, and therefore should not be construed to limit the application as described herein. When one component is said to be "connected" to another component, it can be directly connected to the other component or can exist while a component is interposed therebetween.

[0140] It is also to be noted that, as used in the specification and the appended claims, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Further, the terms "comprises", "comprising", or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0141] The above description of disclosed embodiments provides enabling disclosure sufficient for one of ordinary skill in the art to practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a circuit layer, a display layer and a thin film encapsulation layer arranged on one side of the substrate; a display area and a non-display area surrounding the display area; the circuit layer comprises a driving circuit and a plurality of signal lines connected to the driving circuit, the driving circuit and the signal lines are located in the non-display area, and the signal lines surround at least part of the display area; the non-display area further comprises at least one metal barrier structure; in a first direction, the metal barrier structure at least partially overlaps and is electrically connected to the signal line, the metal barrier structure is in contact with the signal line and the thin film encapsulation layer respectively, and the first direction is perpendicular to the plane in which the substrate lies.

2. The display panel of claim 1, wherein, the display layer comprises an anode layer, a light-emitting functional layer and a cathode layer, and the cathode layer is located on the side of the light-emitting functional layer away from the substrate; the metal barrier structure surrounds at least part of the cathode layer.

3. The display panel of claim 2, wherein, the circuit layer further comprises a first power supply line, and the first power supply line is located on the side of the plurality of signal lines away from the display area; the side of the plurality of signal lines away from the substrate has a transfer layer; the cathode layer and the first power supply line are electrically connected through the transfer layer; in the extension path of the metal barrier structure, the metal barrier structure and the thin film encapsulation layer comprise a plurality of contact areas arranged at intervals, and a non-contact area is arranged between adjacent contact areas; in the contact area, the transfer layer comprises an opening and the transfer layer is insulated from the metal barrier structure.

4. The display panel of claim 3, wherein, the metal barrier structure and the thin film encapsulation layer comprise an organic planarization layer; the organic planarization layer comprises a through region, the metal barrier structure and the thin film encapsulation layer are in contact through the through region, forming the contact area; in the first direction and between adjacent through regions, the transfer layer and the metal barrier structure comprise the organic planarization layer.

5. The display panel of claim 3, wherein: in the non-contact area, the transfer layer is in contact with and electrically connected to the cathode layer.

6. The display panel of claim 1, wherein, in the direction of the non-display area pointing to the display area, at least two metal barrier structures are arranged in sequence, and each metal barrier structure is in contact with the signal line at different positions in the direction.

7. The display panel of claim 6, wherein, in the extension path of the metal barrier structure, the metal barrier structure and the thin film encapsulation layer have a plurality of contact areas arranged at intervals, and a non-contact area is arranged between adjacent contact areas, and the metal barrier structure and the thin film encapsulation layer are not in contact in the non-contact area; for two adjacent metal barrier structures, in the direction of the non-display area pointing to the display area, the contact area corresponding to one metal barrier structure at least partially overlaps the non-contact area corresponding to the other metal barrier structure.

8. The display panel of claim 6, wherein, in the extension path of the metal barrier structure, the metal barrier structure and the thin film encapsulation layer have a plurality of contact areas arranged at intervals, and a non-contact area is arranged between adjacent contact areas, and the metal barrier structure and the thin film encapsulation layer are not in contact in the non-contact area; For two adjacent metal barrier structures, in a direction from the non-display area to the display area, a non-contact area corresponding to one of the metal barrier structures at least partially overlaps a non-contact area corresponding to the other metal barrier structure.

9. The display panel of claim 6, wherein, The heights of the metal barrier structures are all the same.

10. The display panel of claim 6, wherein, The heights of at least two of the metal barrier structures are different.

11. The display panel of claim 10, wherein, In a direction from the non-display area to the display area, the heights of the metal barrier structures are alternately arranged in a first height and a second height.

12. The display panel of claim 6, wherein, In a direction from the non-display area to the display area, at least one signal line is present between the metal barrier structures of two adjacent metal barrier structures.

13. The display panel of claim 6, wherein, In a direction from the non-display area to the display area, the widths of the metal barrier structures are sequentially reduced, or The widths of the metal barrier structures are all the same.

14. The display panel of claim 1, wherein, The plurality of signal lines includes at least a first signal line and a second signal line, the width of the first signal line being greater than the width of the second signal line. The surface of the first signal line is provided with the metal barrier structure.

15. The display panel of claim 1, wherein, For the metal barrier structure and the signal line contacted thereby, the width of the metal barrier structure is less than the width of the signal line.

16. The display panel of claim 1, wherein, The width of the metal barrier structure is greater than or equal to 15 μm.

17. The display panel of claim 1, wherein, Further comprising: A barrier wall surrounding the plurality of signal lines.

18. The display panel of claim 1, wherein, The display area has light emitting elements and pixel circuits connected to the light emitting elements. The driving circuit is electrically connected to a transistor in the pixel circuit through a scan line, and is configured to provide a gate control signal for the transistor in the pixel circuit. The signal lines include at least one of an initial signal line, a clock signal line, a first driving voltage line, and a second driving voltage line.

19. The display panel of claim 18, wherein The driving circuit includes a plurality of cascaded shift register units, and each shift register unit includes a first output unit and a second output unit; an input end of the first output unit is electrically connected to a first driving voltage line, and an output end of the first output unit is electrically connected to the scan line; an input end of the second output unit is electrically connected to a second driving voltage line, and an output end of the second output unit is electrically connected to the scan line. The first driving voltage line transmits a first voltage signal, and the second driving voltage line transmits a second voltage signal, and the potential of the second voltage signal is less than the potential of the first voltage signal.

20. An electronic device, comprising: The display panel as claimed in any one of claims 1-19.

Images