Electron source device and preparation method thereof

Abstract

The invention provides an electron source device and a preparation method thereof. The preparation method comprises the following steps: preparing nanocrystals with a limited particle size by using a self-limiting chemical reaction; a device substrate is provided, the device substrate comprises a first face and a second face which are opposite, and the first face is provided with a conductive area; assembling the nanocrystal grains on a device substrate to form an electron emission layer; preparing a top electrode structure on the electron emission layer to form an electron emission junction; and forming a bottom electrode structure electrically connected with the conductive region on the first surface or the second surface of the device substrate. Nanocrystalline grains of the electron emission layer are prepared through a self-limiting chemical reaction and then are prepared on a device substrate through an assembly technology, so that the nanocrystalline grains are high in morphology and size uniformity; therefore, the electron source device provided by the invention has the advantages of better electron emission capability, smaller electron energy color difference, better performance uniformity, better performance stability and longer service life.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to an electronic source device and its preparation method. Background Technology

[0002] The development of the semiconductor microfabrication industry has placed increasingly higher demands on electron beam direct writing technology. These demands include ensuring the accuracy of fine pattern imaging and significantly increasing the writing speed. To meet these industry needs, multi-electron beam direct writing technology is developing rapidly, playing an irreplaceable role in fine pattern direct writing during integrated circuit manufacturing. Specifically, in semiconductor manufacturing, imaging of high-tech node patterns (including photomask patterns and structural patterns at various device levels) requires not only finer and more accurate direct writing but also high-speed writing under conditions of dramatically increasing pattern data volume. From the perspective of accurate direct writing of fine patterns, the electron beam spot needs to be reduced to enable precise scanning. With a constant current density, reducing the electron beam spot size means reducing the electron beam current, resulting in longer writing times. On the other hand, when the pattern size to be written is below tens of nanometers, the smaller the linewidth, the more significant the shot noise becomes, severely affecting the critical dimension uniformity and line edge roughness. To ensure that the critical linewidth uniformity and edge roughness of small-linewidth patterns are sufficient to meet product performance requirements, lower-sensitivity electron beam photoresists are needed for pattern direct writing. This results in a higher exposure required for writing smaller linewidth patterns. Consequently, with a constant current density, smaller linewidth patterns require a longer writing time. To improve the production capacity per unit time of electron beam direct writing equipment, multi-electron beam direct writing machines using multiple electron beams for simultaneous writing have become necessary. To meet practical needs, the number of writing electron beams in a multi-electron beam direct writing machine needs to be in the hundreds of thousands. Currently, practical multi-electron beam direct writing machines generally use a single electron source, splitting the source electron beam emitted from this single source into multiple writing electron beams. To increase the current density of the writing electron beams, the total current of the source electron beams needs to be increased. However, increasing the total current of the source electron beam is difficult, and the increase in current density of each writing electron beam is relatively limited.

[0003] Electron sources with high current density, high current collimation, and concentrated electron energy can be fabricated using porous silicon materials. Existing electron source devices based on porous silicon materials utilize porous silicon materials prepared through electrochemical etching and ultra-high frequency PECVD processes.

[0004] Porous silicon materials prepared by electrochemical etching have the following problems: it is difficult to form a completely uniform nanocrystalline particle layer, and some unetched nanocrystalline silicon pillars exist. The presence of nanocrystalline silicon pillars alters the surrounding electric field distribution, affecting electron transport and impacting emission collimation and energy uniformity. Furthermore, the close proximity of the top of the nanocrystalline silicon pillars to the top electrode makes them susceptible to dielectric breakdown, leading to device performance degradation or even damage.

[0005] Porous silicon materials prepared using ultra-high frequency PECVD technology have the following problems: The particle size of nano-silicon particles exhibits a certain degree of fluctuation. When the particle size changes, the internal discrete quantum energy levels also change. This non-uniformity in particle size affects the smooth transport of electrons, potentially causing additional scattering and reducing the mean free path of electrons in the porous silicon material. For larger nano-silicon particles, internal phonon scattering is more severe, leading to collisions with emitted electrons, resulting in reduced device current density and broadened electron energy distribution (dispersion).

[0006] Furthermore, when electronic source devices are fabricated based on electrochemical etching or ultra-high frequency PECVD processes, the electronic components need to undergo several high-temperature processes, which is not conducive to their co-integration with other functional structures that have low thermal budgets, are not resistant to ionizing electric fields, and are not resistant to chemical corrosion environments.

[0007] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an electronic source device and its preparation method, so as to solve the problems of poor stability and large electron dispersion of electronic source devices in the prior art.

[0009] To achieve the above and other related objectives, the present invention provides a method for fabricating an electronic source device, the method comprising the steps of: preparing nanocrystals with a defined particle size using a self-limiting chemical reaction; providing a device substrate, the device substrate comprising a first surface and a second surface opposite to each other, the first surface having a conductive region; assembling the nanocrystals onto the device substrate to form an electron emission layer; fabricating a top electrode structure on the electron emission layer to form an electron emission junction; and forming a bottom electrode structure electrically connected to the conductive region on the first surface or the second surface of the device substrate.

[0010] Optionally, an insulating dielectric film is prepared between the electron emission layer and the top electrode structure before the top electrode structure is prepared.

[0011] Optionally, the thickness of the insulating dielectric film is less than or equal to 2 nanometers, and the film is prepared by one of the following processes: high-temperature oxidation annealing process, electrochemical oxidation process, chemical solvent oxidation process, oxygen plasma oxidation process, nitrogen-containing oxidant nitriding process, atomic layer deposition process, and chemical vapor deposition process.

[0012] Optionally, the nanocrystals are further surrounded by an insulating dielectric layer, the thickness of which is less than 2 nanometers. The method for forming the insulating dielectric layer includes one or more of electrochemical oxidation, electrochemical nitriding, chemical solution oxidation, oxygen atmosphere oxidation, nitrogen atmosphere nitriding, oxygen plasma oxidation, nitrogen plasma nitriding, and atomic layer deposition. The material of the insulating dielectric layer includes one or more of SiO2, Si3N4, SiON, Al2O3, HfO2, ZrO2, and TiO2.

[0013] Optionally, the self-limiting chemical reaction includes one of the following chemical reactions with size-limiting effects: electrochemical corrosion reaction, chemical corrosion reaction, and high-temperature oxidation reaction, and the limited particle size range of the nanocrystals is 2 nanometers to 10 nanometers.

[0014] Optionally, the method for assembling the nanocrystals onto the device substrate includes a sol-gel method, which includes: stirring the nanocrystals and solvent to form a sol with suspended nanocrystals, coating the sol onto the surface of the device substrate, and separating the solvent in the sol to form a solidified nanocrystal film on the surface of the device substrate. The method for separating the solvent in the sol includes one or more of heating, photodecomposition, reactive decomposition, sublimation, and volatilization.

[0015] Optionally, the method for assembling the nanocrystals onto the device substrate includes an electrostatic enrichment method, which includes: electret treatment of the nanocrystals to make them chargeable; spraying the nanocrystals into the air or vacuum above the device substrate, or dissolving the nanocrystals in a non-polar insulating liquid and injecting it above the device substrate to form a suspended region of nanocrystals above the device substrate; connecting the device substrate to a potential with the opposite polarity of the charge of the nanocrystals, and under the action of electrostatic force, the nanocrystals gradually accumulate on the device substrate; and performing a nanocrystal fixation treatment on the device substrate with the adsorbed nanocrystals to form a solidified nanocrystal film on the surface of the device substrate.

[0016] Optionally, fabricating the top electrode structure on the electron emission layer includes: fabricating a conductive thin film using a vapor deposition or deposition apparatus; and transferring the conductive thin film above the electron emission layer by a thin film transfer method to form the top electrode structure.

[0017] Optionally, fabricating a top electrode structure on the electron emission layer includes: fabricating a metal thin film on the electron emission layer using a vapor deposition or deposition apparatus; reacting the metal thin film with the electron emission layer using an annealing process to form a conductive alloy thin film; and removing the remaining metal thin film using a selective etching process to form a top electrode structure, wherein the thickness of the top electrode structure is less than 10 nanometers.

[0018] Optionally, the device substrate is a patterned substrate, on which groove structures and / or boss structures are formed to adjust the assembly state of the nanocrystals to improve the flexibility and freedom of subsequent device processes. The assembly state includes one or both of the positional distribution and thickness distribution of the nanocrystals.

[0019] Optionally, the patterned substrate may also have one or more of the following: a pixel isolation structure for an electronic source device, an electrode lens structure, and a signal transmission line structure.

[0020] Optionally, the device substrate may also have one or both of an integrated circuit system and a microelectromechanical system pre-formed thereon, wherein the integrated circuit system includes a driving circuit for an electronic source device, and the signal transmission line of the electronic source device is connected to a reserved signal path of the integrated circuit system.

[0021] The present invention also provides an electron source device, the electron source device comprising: a device substrate, the device substrate including a first surface and a second surface opposite to each other, the first surface having a conductive region; a device emission layer, the device emission layer including nanocrystals having a defined particle size formed by assembly on the first surface of the device substrate; a top electrode structure formed on the electron emission layer; and a bottom electrode structure formed on the first surface or the second surface of the device substrate and electrically connected to the conductive region.

[0022] Optionally, the defined particle size range of the nanocrystals is 2 nanometers to 10 nanometers.

[0023] Optionally, an insulating dielectric film is further covered between the device emitter layer and the top electrode structure, the thickness of which is less than or equal to 2 nanometers.

[0024] Optionally, the nanocrystals are further surrounded by an insulating dielectric layer, the thickness of which is less than 2 nanometers, and the material of the insulating dielectric layer includes one or more of SiO2, Si3N4, SiON, Al2O3, HfO2, ZrO2 and TiO2.

[0025] Optionally, the thickness of the electron reflective layer ranges from 2 nanometers to 5 micrometers.

[0026] Optionally, the nanocrystals are semiconductor nanocrystals, including silicon nanocrystals.

[0027] Optionally, the device substrate is one of a semiconductor substrate, an insulating substrate, and a composite material substrate.

[0028] Optionally, the device substrate is a patterned substrate, on which groove structures and / or boss structures are formed to adjust the assembly state of the nanocrystals.

[0029] Optionally, the device substrate is formed with one or both of an integrated circuit system and a microelectromechanical system, wherein the integrated circuit system includes a driving circuit for an electronic source device, and the signal transmission line of the electronic source device is connected to a reserved signal path of the integrated circuit system.

[0030] Optionally, the bottom electrode structure extends from the bottom of the device emitter layer along a first surface of the device substrate; or, when the device substrate is a semiconductor substrate, the bottom electrode structure is formed on a second surface of the device substrate to achieve the extension of the device emitter layer.

[0031] As described above, the electronic source device and its fabrication method of the present invention have the following beneficial effects:

[0032] The nanocrystals of the electron emission layer of the present invention are prepared by self-limiting chemical reaction and then assembled on the device substrate by assembly process. This results in high uniformity of morphology and size of the nanocrystals of the present invention. Therefore, the electron source device of the present invention has good electron emission capability, small electron energy color difference, good performance uniformity, good performance stability and long service life.

[0033] This invention separates the preparation and screening processes of nanocrystals from the substrate process, significantly reducing the difficulty of preparing high-quality nanocrystal layers. At the same time, it eliminates the need for the device substrate structure to undergo electrochemical processes, furnace tube processes, and other high-temperature and corrosion processes, thus gaining the freedom to process the device substrate independently. The electronic source device is easy to integrate with other functional structures and modules, thereby greatly improving the flexibility of the process. Attached Figure Description

[0034] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0035] Figures 1 to 7 The diagram shows the structural schematics of each step in the fabrication method of the electronic source device of the present invention.

[0036] Figures 8-11 The diagrams shown are schematic representations of the structures of several different electronic source devices of the present invention.

[0037] Component designation explanation

[0038] 101 Device Substrate

[0039] 102 nanocrystals

[0040] 103 Solvent

[0041] 104 Electron Emission Layer

[0042] 105 Insulating Dielectric Thin Film

[0043] 106 Top Electrode Structure

[0044] 107 Bottom Electrode Structure

[0045] 201-pixel isolation structure

[0046] 202 Electrode Lens Structure

[0047] 203 Integrated Circuit Systems Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0050] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0051] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0052] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0053] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0054] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0055] like Figures 1 to 11 As shown, this embodiment provides a method for fabricating an electronic source device, the method comprising the following steps:

[0056] First, step 1) is performed, using a self-limiting chemical reaction to prepare nanocrystals 102 with a defined particle size.

[0057] In one embodiment, the self-limiting chemical reaction includes a size-limiting chemical reaction, such as an electrochemical corrosion reaction, a chemical corrosion reaction, or a high-temperature oxidation reaction. Through this self-limiting chemical reaction, nanocrystals 102 with good particle size uniformity can be obtained. In a specific example, the limited particle size range of the nanocrystals 102 is 2 nm to 10 nm. Of course, by selecting appropriate self-limiting chemical reaction conditions, such as reaction temperature, concentration of the reaction gas or reaction liquid, reaction atmosphere, and reaction time, nanocrystals 102 with a narrower particle size range can be obtained, for example, a particle size range between 4 nm and 8 nm, or between 5 nm and 7 nm.

[0058] The nanocrystals 102 are materials with electron emission capabilities. In one embodiment, the nanocrystals 102 are semiconductor nanocrystals, including silicon nanocrystals. Of course, in other embodiments, the semiconductor nanocrystals may also be other semiconductor materials such as germanium-silicon or group III-V compounds, and are not limited to the examples listed herein.

[0059] In one embodiment, the nanocrystals 102 are further surrounded by an insulating dielectric layer (not shown). The thickness of the insulating dielectric layer is less than 2 nanometers. The method for forming the insulating dielectric layer includes one or more of electrochemical oxidation, electrochemical nitriding, chemical solution oxidation, oxygen atmosphere oxidation, nitrogen atmosphere nitriding, oxygen plasma oxidation, nitrogen plasma nitriding, and atomic layer deposition. The material of the insulating dielectric layer includes one or more of SiO2, Si3N4, SiON, Al2O3, HfO2, ZrO2, and TiO2, and is not limited to the examples listed above. It should be noted that the process of forming the insulating dielectric layer can be after the preparation of the nanocrystals 102 and before the assembly of the nanocrystals 102; it can also be after the nanocrystals 102 are assembled onto the device substrate 101; or it can be a combination of the above two process sequences.

[0060] like Figure 1 As shown, then step 2) is performed, providing a device substrate 101, the device substrate 101 including a first surface and a second surface opposite to each other, the first surface having a conductive region;

[0061] In one embodiment, the device substrate 101 is one of a semiconductor substrate, an insulating substrate, and a composite material substrate. When the device substrate 101 is a substrate material with conductive properties, such as a semiconductor substrate, the conductive region can be the surface of the semiconductor substrate itself, and it is not necessary to additionally fabricate the conductive region; when the device substrate 101 is an insulating substrate or an insulating composite material substrate, the conductive region can be pre-fabricated on the first surface of the device substrate 101.

[0062] The semiconductor substrate may be, for example, silicon, germanium silicon, or group III-V compounds with ion doping; the insulating substrate may be, for example, silicon dioxide or silicon nitride; and the composite material substrate may be a combination of two or more semiconductor substrates, a combination of a semiconductor substrate and an insulating substrate, or a combination of two or more insulating substrates, etc.

[0063] like Figures 2-4 As shown, then step 3) is performed to assemble the nanocrystals 102 onto the device substrate 101 to form an electron emission layer 104.

[0064] In one embodiment, the method for assembling the nanocrystals 102 onto the device substrate 101 can be a sol-gel method, which includes the following steps:

[0065] Step a) The nanocrystals 102 prepared in step 1) are stirred evenly with solvent 103 to form a sol with suspended nanocrystals 102.

[0066] Step b) Coat the sol onto the surface of the device substrate 101, for example, by spin coating, spray coating or other methods, and separate the solvent 103 in the sol to form a solidified nanocrystalline film on the surface of the device substrate 101. The nanocrystalline particles 102 in the nanocrystalline film have a certain regular arrangement. The method for separating the solvent 103 in the sol includes one or more of the following: heating, photodecomposition, reaction decomposition, sublimation and volatilization.

[0067] It should be noted that the nanocrystalline film meeting the thickness requirement can be formed by one step b) above, or step b) can be repeated multiple times to obtain a nanocrystalline film with a larger thickness.

[0068] In yet another embodiment, the method of assembling the nanocrystals 102 onto the device substrate 101 includes an electrostatic enrichment method, the electrostatic enrichment method comprising the steps of:

[0069] Step a) involves electret treatment of the nanocrystals 102 prepared in step 1) to impart a charge to the nanocrystals 102, which may be positive or negative.

[0070] Step b) Spray the nanocrystals 102 into the air or vacuum above the device substrate 101, or integrate the nanocrystals 102 into a non-polar insulating liquid and inject it above the device substrate 101 to form a suspended region of nanocrystals 102 above the device substrate 101.

[0071] Step c) Connect the device substrate 101 to a potential with the opposite charge polarity to that of the nanocrystals 102. For example, when the nanocrystals 102 are positively charged, connect the device substrate 101 to a negative potential to attract the nanocrystals 102. Conversely, under the action of electrostatic force, the nanocrystals 102 gradually accumulate on the device substrate 101.

[0072] Step d) involves performing a nanocrystal 102 fixation treatment on the device substrate 101 on which the nanocrystals 102 have been adsorbed, so as to form a solidified nanocrystal film on the surface of the device substrate 101. The nanocrystal 102 fixation treatment may be, for example, heating, oxidation, or introducing a suitable adhesive gas or liquid.

[0073] In one embodiment, the thickness of the electron reflective layer ranges from 2 nanometers to 5 micrometers. For example, the thickness of the electron reflective layer can be 5 nanometers, 10 nanometers, 100 nanometers, 1 micrometer, 3 micrometers, etc., and can be selected according to actual needs, and is not limited to the examples listed here.

[0074] The nanocrystals 102 of the electron emission layer 104 of the present invention are prepared by self-limiting chemical reaction and then assembled on the device substrate 101 by assembly process. This results in high uniformity of morphology and size of the nanocrystals 102 of the present invention. Therefore, the electron source device of the present invention has good electron emission capability, small electron energy color difference, good performance uniformity, good performance stability and long service life.

[0075] like Figures 5-6 As shown, then step 4) is performed to fabricate a top electrode structure 106 on the electron emission layer 104 to form an electron emission junction;

[0076] In one embodiment, fabricating the top electrode structure 106 on the electron emission layer 104 may include the following steps:

[0077] Step a) involves preparing a conductive thin film on a transfer substrate using a vapor deposition or deposition apparatus. The conductive thin film can be, for example, copper, gold, aluminum, graphene, metal nitride, etc.

[0078] Step b) involves transferring the conductive thin film onto the electron emission layer 104 via a thin film transfer method to form a top electrode structure 106. After transfer, an annealing process can be used to enhance the bonding between the conductive thin film and the electron emission layer 104, or the conductive thin film can react with the electron emission layer 104 to generate a conductive compound.

[0079] In yet another embodiment, fabricating the top electrode structure 106 on the electron emission layer 104 may also include the following steps:

[0080] Step a) A metal thin film is prepared above the electron emission layer 104 using a vapor deposition or deposition apparatus. The metal thin film may be, for example, copper, gold, aluminum, titanium, etc.

[0081] Step b) involves annealing the metal film to react with the electron emission layer 104 to form a conductive alloy film.

[0082] Step c) involves using a selective etching process to remove the remaining metal film to form a top electrode structure 106, the thickness of which is less than 10 nanometers.

[0083] In one embodiment, such as Figure 5As shown, the process also includes a step of preparing an insulating dielectric film 105 between the electron emission layer 104 and the top electrode structure 106 before preparing the top electrode structure 106. The thickness of the insulating dielectric film 105 is less than or equal to 2 nanometers, and it is prepared by one of the following processes: high-temperature oxidation annealing, electrochemical oxidation, chemical solvent oxidation, oxygen plasma oxidation, nitrogen-containing oxidant nitriding, atomic layer deposition, and chemical vapor deposition. When the insulating dielectric film 105 is present, the metal film can simultaneously react with the insulating dielectric film 105 and the electron emission layer 104 to form a conductive alloy film.

[0084] like Figure 7 As shown, step 5) is performed last, forming a bottom electrode structure 107 electrically connected to the conductive region on the first or second surface of the device substrate 101.

[0085] In one embodiment, such as Figure 7 As shown, when the device substrate 101 is a substrate material with conductive properties, such as a semiconductor substrate, the conductive region can be the surface of the semiconductor substrate itself, and a bottom electrode structure 107 can be formed on the second surface of the device substrate 101 to realize the extraction of the electron reflection layer.

[0086] In another embodiment, when the device substrate 101 is an insulating substrate or an insulating composite material substrate, the conductive region can be pre-fabricated on the first surface of the device substrate 101, and then the bottom electrode structure 107 can be fabricated on the first surface of the device substrate 101 and connected to the conductive region by leads. Alternatively, the conductive region can be led out to the second surface of the device substrate 101 by forming conductive vias in the substrate, and the bottom electrode structure 107 can be fabricated on the second surface of the device substrate 101.

[0087] like Figure 8 The electron source device may also have a pixel isolation structure 201 to isolate adjacent electron emission layers 104; an electrode lens structure 202 may also be formed on the pixel isolation structure 201 of adjacent electron emission layers 104 to improve the performance and function of the electron source device.

[0088] like Figure 9 As shown, the electron source device can be fabricated into an array of electron emission layers 104 by an array of pixel isolation structures 201, and an electrode lens structure 202 can be formed on the pixel isolation structures 201 of adjacent electron emission layers 104 to greatly improve the performance of the electron source device.

[0089] Meanwhile, a signal transmission line structure can also be formed on or inside the device substrate 101 to bring out the electronic source device and facilitate interconnection with other functional modules.

[0090] The device substrate 101 can be a patterned substrate, and groove structures and / or boss structures are formed on the device substrate 101 to adjust the assembly state of the nanocrystals 102 to improve the flexibility and freedom of subsequent device processes. The assembly state includes one or both of the positional distribution and thickness distribution of the nanocrystals 102. Figure 10 As shown, in one embodiment, a groove structure is formed on the device substrate 101. This groove structure can be, for example, a U-shaped groove, and the electron emission layer 104 fills the groove structure. Simultaneously, the electron source device with the groove structure can also be configured with pixel isolation structures 201 and electrode lens structures 202 to meet different performance requirements. The pixel isolation structure 201 can be formed on the device substrate 101 by depositing and etching an epitaxial layer, or it can be formed by directly etching the device substrate 101 to create a groove structure, with the sidewalls of adjacent groove structures serving as pixel isolation structures 201.

[0091] like Figure 11 As shown, the device substrate 101 may also pre-form one or both of an integrated circuit system 203 and a microelectromechanical system (MEMS). The integrated circuit system 203 includes a driving circuit for an electronic source device, and the signal transmission lines of the electronic source device (such as through conductive vias in the substrate) are connected to the reserved signal paths of the integrated circuit system 203. Since the device process involving the electronic source device substrate 101 can all be carried out using low-temperature processes, it will not damage the performance of the integrated circuit. A spacer layer may be provided between the integrated circuit system 203 and the electron emission layer 104. The integrated circuit system 203 and the electron emission layer 104 can be separated by the top layer of the device substrate 101 itself, or by covering the integrated circuit system 203 with an insulating layer, and forming conductive vias in the spacer layer to connect the integrated circuit system 203 and the electron emission layer 104.

[0092] Figure 11An electronic source device (interconnects not shown) fabricated on a patterned substrate containing CMOS circuitry is demonstrated. The substrate 101 of this device includes a pixel isolation structure 201, an electrode lens structure 202, and an array of recessed structures, as well as a pre-fabricated CMOS circuit module responsible for controlling the operating state of the electronic source device. Because this device employs a post-assembly process using nanocrystalline particles, which eliminates the need for high-temperature processing, the CMOS circuit module can be fabricated without undergoing high-temperature processing in the electron emission layer 104, thus preserving its electrical performance and significantly improving the functional integration of the electronic source device.

[0093] This invention separates the preparation and screening process of nanocrystals 102 from the substrate process, which significantly reduces the difficulty of preparing high-quality nanocrystal 102 layers. At the same time, it eliminates the need for the device substrate 101 structure to undergo electrochemical processes, furnace tube processes, and other high-temperature and corrosion processes, thus gaining the freedom to process the device substrate 101 independently. The electronic source device is easy to integrate with other functional structures and modules, thereby greatly improving the process flexibility.

[0094] like Figures 7-11 As shown, this embodiment also provides an electron source device, which can be fabricated by the above-described fabrication process. The electron source device includes: a device substrate 101, which includes a first surface and a second surface opposite to each other, the first surface having a conductive region; a device emission layer, which includes nanocrystals 102 with a defined particle size formed on the first surface of the device substrate 101 by assembly; a top electrode structure 106 formed on the electron emission layer 104; and a bottom electrode structure 107 formed on the first surface or the second surface of the device substrate 101 and electrically connected to the conductive region.

[0095] In one embodiment, the defined particle size range of the nanocrystals 102 is 2 nanometers to 10 nanometers.

[0096] In one embodiment, an insulating dielectric film 105 is further covered between the device emitter layer and the top electrode structure 106, and the thickness of the insulating dielectric film 105 is less than or equal to 2 nanometers.

[0097] In one embodiment, the nanocrystals 102 are further surrounded by an insulating dielectric layer (not shown), the thickness of which is less than 2 nanometers, and the material of which includes one or more of SiO2, Si3N4, SiON, Al2O3, HfO2, ZrO2 and TiO2.

[0098] In one embodiment, the thickness of the electron reflective layer ranges from 2 nanometers to 5 micrometers.

[0099] In one embodiment, the nanocrystal 102 is a semiconductor nanocrystal, which includes silicon nanocrystals.

[0100] In one embodiment, the device substrate 101 is one of a semiconductor substrate, an insulating substrate, and a composite material substrate.

[0101] In one embodiment, the device substrate 101 is a patterned substrate, and the device substrate 101 has a groove structure and / or a boss structure formed on it to adjust the assembly state of the nanocrystals 102.

[0102] In one embodiment, the device substrate 101 is formed with one or both of an integrated circuit system 203 and a microelectromechanical system (MEMS). The integrated circuit system 203 includes a driving circuit for an electronic source device, and the signal transmission line of the electronic source device is connected to a reserved signal path of the integrated circuit system 203.

[0103] In one embodiment, the bottom electrode structure extends from the bottom of the device emitter layer along a first surface of the device substrate 101; or, when the device substrate 101 is a semiconductor substrate, the bottom electrode structure is formed on a second surface of the device substrate 101 to achieve the extension of the device emitter layer.

[0104] As described above, the electronic source device and its fabrication method of the present invention have the following beneficial effects:

[0105] The nanocrystals 102 of the electron emission layer 104 of the present invention are prepared by self-limiting chemical reaction and then assembled on the device substrate 101 by assembly process. This results in high uniformity of morphology and size of the nanocrystals 102 of the present invention. Therefore, the electron source device of the present invention has good electron emission capability, small electron energy color difference, good performance uniformity, good performance stability and long service life.

[0106] This invention separates the preparation and screening process of nanocrystals 102 from the substrate process, which significantly reduces the difficulty of preparing high-quality nanocrystal 102 layers. At the same time, it eliminates the need for the device substrate 101 structure to undergo electrochemical processes, furnace tube processes, and other high-temperature and corrosion processes, thus gaining the freedom to process the device substrate 101 independently. The electronic source device is easy to integrate with other functional structures and modules, thereby greatly improving the process flexibility.

[0107] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an electronic source device, characterized in that, The preparation method includes the following steps: Nanocrystals with defined particle sizes were prepared using self-limiting chemical reactions; A device substrate is provided, the device substrate including opposing first and second surfaces, the first surface having a conductive region; The nanocrystals are assembled onto the device substrate to form an electron emission layer; A top electrode structure is fabricated on the electron emission layer to form an electron emission junction; A bottom electrode structure electrically connected to the conductive region is formed on the first or second surface of the device substrate.

2. The method for fabricating the electronic source device according to claim 1, characterized in that: It also includes the step of: preparing an insulating dielectric film between the electron emission layer and the top electrode structure before preparing the top electrode structure.

3. The method for fabricating the electronic source device according to claim 2, characterized in that: The thickness of the insulating dielectric film is less than or equal to 2 nanometers, and it is prepared by one of the following processes: high-temperature oxidation annealing process, electrochemical oxidation process, chemical solvent oxidation process, oxygen plasma oxidation process, nitrogen-containing oxidant nitriding process, atomic layer deposition process, and chemical vapor deposition process.

4. The method for fabricating the electronic source device according to claim 1, characterized in that: The nanocrystals are further surrounded by an insulating dielectric layer with a thickness of less than 2 nanometers. The method for forming the insulating dielectric layer includes one or more of electrochemical oxidation, electrochemical nitriding, chemical solution oxidation, oxygen atmosphere oxidation, nitrogen atmosphere nitriding, oxygen plasma oxidation, nitrogen plasma nitriding, and atomic layer deposition. The material of the insulating dielectric layer includes one or more of SiO2, Si3N4, SiON, Al2O3, HfO2, ZrO2, and TiO2.

5. The method for fabricating the electronic source device according to claim 1, characterized in that: The self-limiting chemical reaction includes one of the following chemical reactions with size-limiting effects: electrochemical corrosion reaction, chemical corrosion reaction, and high-temperature oxidation reaction. The defined particle size range of the nanocrystals is 2 nanometers to 10 nanometers.

6. The method for fabricating the electronic source device according to claim 1, characterized in that: The method for assembling the nanocrystals onto the device substrate includes a sol-gel method, which includes: stirring the nanocrystals and a solvent to form a sol with suspended nanocrystals; coating the sol onto the surface of the device substrate; and separating the solvent from the sol to form a solidified nanocrystal film on the surface of the device substrate. The method for separating the solvent from the sol includes one or more of the following: heating, photodecomposition, reactive decomposition, sublimation, and volatilization.

7. The method for fabricating the electronic source device according to claim 1, characterized in that: The method for assembling the nanocrystals onto the device substrate includes an electrostatic enrichment method, the electrostatic enrichment method comprising: The nanocrystals are subjected to electret treatment to make them carry an electric charge; The nanocrystals are sprayed into the air or vacuum above the device substrate, or the nanocrystals are incorporated into a non-polar insulating liquid and injected above the device substrate to form a suspended region of nanocrystals above the device substrate. When the device substrate is connected to a potential with the opposite charge polarity to that of the nanocrystals, the nanocrystals gradually accumulate on the device substrate under the action of electrostatic force. The device substrate on which the adsorbed nanocrystals are attached is subjected to a nanocrystal fixation treatment to form a solidified nanocrystal film on the surface of the device substrate.

8. The method for fabricating the electronic source device according to claim 1, characterized in that: Fabricating a top electrode structure on the electron emission layer includes: preparing a conductive thin film using a vapor deposition or deposition apparatus; and transferring the conductive thin film above the electron emission layer by a thin film transfer method to form a top electrode structure.

9. The method for fabricating an electronic source device according to claim 1, characterized in that: The fabrication of a top electrode structure on the electron emission layer includes: fabricating a metal thin film on the electron emission layer using a vapor deposition or deposition apparatus; reacting the metal thin film with the electron emission layer through an annealing process to form a conductive alloy thin film; and removing the remaining metal thin film using a selective etching process to form a top electrode structure, wherein the thickness of the top electrode structure is less than 10 nanometers.

10. The method for fabricating the electronic source device according to claim 1, characterized in that: The device substrate is a patterned substrate, and groove structures and / or boss structures are formed on the device substrate to adjust the assembly state of the nanocrystals to improve the flexibility and freedom of subsequent device processes. The assembly state includes one or both of the positional distribution and thickness distribution of the nanocrystals.

11. The method for fabricating the electronic source device according to claim 10, characterized in that: The patterned substrate also has one or more of the following: pixel isolation structure, electrode lens structure, and signal transmission line structure for electronic source devices.

12. The method for fabricating the electronic source device according to claim 1, characterized in that: The device substrate is also pre-formed with one or both of an integrated circuit system and a microelectromechanical system. The integrated circuit system includes a driving circuit for an electronic source device, and the signal transmission line of the electronic source device is connected to a reserved signal path of the integrated circuit system.

13. An electronic source device, characterized in that, The electronic source device includes: A device substrate, the device substrate including a first surface and a second surface opposite to each other, the first surface having a conductive region; A device emission layer, the device emission layer comprising nanocrystals having a defined particle size formed by assembly on a first surface of the device substrate; A top electrode structure is formed on the electron emission layer; A bottom electrode structure is formed on the first or second surface of the device substrate and is electrically connected to the conductive region.

14. The electronic source device according to claim 13, characterized in that: The defined particle size range of the nanocrystals is 2 nanometers to 10 nanometers.

15. The electronic source device according to claim 13, characterized in that: An insulating dielectric film is also covered between the emitter layer of the device and the top electrode structure, and the thickness of the insulating dielectric film is less than or equal to 2 nanometers.

16. The method for fabricating an electronic source device according to claim 13, characterized in that: The nanocrystals are further surrounded by an insulating dielectric layer with a thickness of less than 2 nanometers. The insulating dielectric layer is made of one or more of the following materials: SiO2, Si3N4, SiON, Al2O3, HfO2, ZrO2, and TiO2.

17. The electronic source device according to claim 13, characterized in that: The thickness of the electron reflective layer ranges from 2 nanometers to 5 micrometers.

18. The electronic source device according to claim 13, characterized in that: The nanocrystals are semiconductor nanocrystals, including silicon nanocrystals.

19. The electronic source device according to claim 13, characterized in that: The device substrate is one of a semiconductor substrate, an insulating substrate, and a composite material substrate.

20. The electronic source device according to claim 13, characterized in that: The device substrate is a patterned substrate, and groove structures and / or boss structures are formed on the device substrate to adjust the assembly state of the nanocrystals.

21. The electronic source device according to claim 13, characterized in that: The device substrate is formed with one or both of an integrated circuit system and a microelectromechanical system. The integrated circuit system includes a driving circuit for an electronic source device, and the signal transmission line of the electronic source device is connected to a reserved signal path of the integrated circuit system.

22. The electronic source device according to claim 13, characterized in that: The bottom electrode structure extends from the bottom of the device emitter layer along the first surface of the device substrate, or, when the device substrate is a semiconductor substrate, the bottom electrode structure is formed on the second surface of the device substrate to achieve the extension of the device emitter layer.

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