Substrate of radio frequency device and preparation method thereof
By forming an air gap and an amorphous silicon layer in the trenches of a high-resistivity silicon substrate, the problem of poor vertical isolation in RF devices is solved, improving the isolation performance of the devices and reducing noise impact.
Patent Information
- Application Number
- CN202510972272.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-11-11
AI Technical Summary
Radio frequency devices based on high-resistivity silicon substrates exhibit poor vertical isolation, which affects device performance.
Trenches are etched in a high-resistivity substrate, and an amorphous silicon layer is formed on the bottom wall of the trench through an ion implantation process. Subsequently, an intrinsic epitaxial layer is formed in the trench, and the isolation effect is enhanced by the formation of air gaps during the epitaxial process.
By forming an air gap and an amorphous silicon layer in the trench of a high-resistivity substrate, the isolation effect of RF devices is enhanced, the impact of crosstalk and substrate noise on the devices is reduced, and the harmonic performance is improved.
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Figure CN120933231A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a substrate for a radio frequency device and a method for preparing the same. Background Technology
[0002] Radio frequency devices, such as RF switches and low-noise amplifiers, place particular emphasis on electrical isolation from the substrate. Commonly used technologies include SOI (Silicon-On-Insulator) or triple well isolation. While SOI substrate isolation offers good performance, it is also more expensive.
[0003] To reduce manufacturing costs, the industry has considered using high-resistivity bulk silicon substrates as the base for RF devices, but the vertical isolation of these devices is poor. Summary of the Invention
[0004] This application provides a substrate for radio frequency devices and a method for fabricating the same, which can solve the problem of poor vertical isolation performance of radio frequency devices based on high-resistivity bulk silicon substrates.
[0005] On one hand, embodiments of this application provide a method for fabricating a substrate for a radio frequency device, including:
[0006] A high-resistivity substrate is provided, on which a hard mask layer is formed;
[0007] A photoresist layer is coated on the hard mask layer;
[0008] A trench pattern is defined on the photoresist layer to obtain a patterned photoresist layer;
[0009] Using the patterned photoresist layer as a mask, the hard mask layer and a portion of the high-resistivity substrate are etched to obtain several trenches;
[0010] An ion implantation process is performed on the high-resistivity substrate to form an amorphous silicon layer on the bottom wall of the trench;
[0011] Remove the patterned photoresist layer and the hard mask layer;
[0012] An intrinsic epitaxial layer is formed, the intrinsic epitaxial layer being located in the trench and covering the high-resistivity substrate, wherein, during the formation of the intrinsic epitaxial layer, an air gap is formed below each of the trenches, the air gap being located between the amorphous silicon layer and the intrinsic epitaxial layer;
[0013] The surface of the intrinsic epitaxial layer is planarized.
[0014] Optionally, in the method for fabricating the substrate of the radio frequency device, the resistivity of the intrinsic epitaxial layer is greater than or equal to 1 kΩ·cm.
[0015] Optionally, in the method for fabricating the substrate of the radio frequency device, after planarizing the surface of the intrinsic epitaxial layer, the distance between the top of the air gap and the upper surface of the intrinsic epitaxial layer is 0.2 μm to 0.5 μm.
[0016] Optionally, in the method for fabricating the substrate of the radio frequency device, the height of the trench is 1 μm to 10 μm.
[0017] Optionally, in the method for fabricating the substrate of the radio frequency device, the aspect ratio of the trench is (5:1) to (500:1).
[0018] Optionally, in the method for fabricating the substrate of the radio frequency device, during the process of forming the amorphous silicon layer on the bottom wall of the trench, the high-resistivity substrate is subjected to at least one oxygen ion implantation and at least one argon ion implantation.
[0019] Optionally, in the method for fabricating the substrate of the radio frequency device, during the process of forming the amorphous silicon layer on the bottom wall of the trench, oxygen ion and argon ion implantation are performed simultaneously on the high-resistivity substrate.
[0020] Optionally, in the method for fabricating the substrate of the radio frequency device, the resistivity of the high-resistivity substrate is greater than or equal to 1 kΩ·cm.
[0021] On the other hand, embodiments of this application also provide a substrate for a radio frequency device, comprising:
[0022] High-resistivity substrate;
[0023] Several trenches, the trenches being located within a portion of the thickness of the high-resistivity substrate;
[0024] An amorphous silicon layer is located on the bottom wall of the trench;
[0025] An intrinsic epitaxial layer is located in the trench and covers the surface of the high-resistivity substrate, wherein an air gap is formed below each trench, and the air gap is located between the amorphous silicon layer and the intrinsic epitaxial layer.
[0026] The technical solution of this application has at least the following advantages:
[0027] This application provides a substrate for radio frequency (RF) devices and a method for fabricating the same. In the fabrication method, several trenches are first etched into a high-resistivity substrate. Then, an ion implantation process is performed on the high-resistivity substrate to form an amorphous silicon layer on the bottom wall of the trenches. Next, an intrinsic epitaxial layer is formed in the trenches using an epitaxial process. During the formation of this intrinsic epitaxial layer, epitaxy occurs not only in the vertical direction but also laterally. The density of the silicon source gas at the bottom of the trench is lower than that at the top, so the epitaxial growth rate of the intrinsic epitaxial layer at the bottom is slower than that at the top. Therefore, the top opening of the trench is sealed in advance, forming an air gap in the space near the bottom of each trench. This air gap is located between the amorphous silicon layer and the intrinsic epitaxial layer on the bottom wall of the trench. By forming air gaps in the trenches of the high-resistivity substrate and forming an amorphous silicon layer on the bottom wall of the trench at the bottom of the air gap, this application can enhance isolation, reduce crosstalk, and improve harmonic performance, thereby significantly reducing the impact of substrate noise on RF devices. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0029] Figure 1 This is a flowchart of a method for fabricating a substrate for a radio frequency device according to an embodiment of the present invention;
[0030] Figures 2-7 This is a schematic diagram of the semiconductor structure in each process step of fabricating the substrate for radio frequency devices according to an embodiment of the present invention;
[0031] The reference numerals in the attached figures are explained as follows:
[0032] 10-High resistivity substrate, 11-Trench, 20-Hard mask layer, 30-Photoresist layer, 40-Amorphous silicon layer, 50-Air gap, 60-Intrinsic epitaxial layer. Detailed Implementation
[0033] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0036] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0037] This application provides a method for fabricating a substrate for a radio frequency device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a substrate for a radio frequency (RF) device according to an embodiment of the present invention. The method for fabricating the substrate for the RF device includes:
[0038] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the formation of the hard mask layer according to an embodiment of this application. A high-resistivity substrate 10 is provided, on which a hard mask layer 20 is formed.
[0039] Preferably, the resistivity of the high-resistivity substrate 10 is greater than or equal to 1 kΩ·cm.
[0040] Preferably, the hard mask layer 20 is made of silicon nitride or silicon oxide.
[0041] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the trench is formed according to an embodiment of this application, with a photoresist layer 30 coated on the hard mask layer 20.
[0042] Next, proceed to step S3: Continue to refer to Figure 3A trench pattern is defined on the photoresist layer 30 to obtain a patterned photoresist layer 30.
[0043] Further, proceed to step S4: Continue to refer to Figure 3 Using the patterned photoresist layer 30 as a mask, the hard mask layer 20 and a portion of the high-resistivity substrate 10 are etched to obtain several trenches 11.
[0044] In this application, a dry etching process is used to etch the hard mask layer 20 and a portion of the high-resistivity substrate 10 to obtain a number of trenches 11.
[0045] Preferably, the height of the groove 11 is 1 μm to 10 μm.
[0046] Preferably, the depth-to-width ratio of the groove 11 is (5:1) to (500:1).
[0047] Next, proceed to step S5: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the amorphous silicon layer according to an embodiment of this application. The high-resistivity substrate 10 is subjected to an ion implantation process to form an amorphous silicon layer 40 on the bottom wall of the trench 11.
[0048] In this embodiment, during the formation of the amorphous silicon layer on the bottom wall of the trench, the high-resistivity substrate undergoes at least one oxygen ion implantation and at least one argon ion implantation. During oxygen ion implantation, the implantation is a vertical implantation perpendicular to the high-resistivity substrate 10, with an ion implantation energy of 50 keV to 10 MeV and an ion implantation dose of 1E13 / cm². 2 ~5E15 / cm 2 Similarly, during argon ion implantation, the implantation was performed vertically onto the high-resistivity substrate 10, with an ion implantation energy of 50 keV to 10 MeV and an ion implantation dose of 1 E13 / cm². 2 ~5E15 / cm 2
[0049] In another embodiment, during the formation of the amorphous silicon layer on the bottom wall of the trench, oxygen ion and argon ion implantation is performed simultaneously on the high-resistivity substrate.
[0050] Further, proceed to step S6: Refer to Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after removing the patterned photoresist layer and the hard mask layer according to an embodiment of this application, with the patterned photoresist layer 30 and the hard mask layer 20 removed.
[0051] In this embodiment, a dry etching process is used to remove the patterned photoresist layer 30 and the hard mask layer 20.
[0052] Next, proceed to step S7: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the intrinsic epitaxial layer and the air gap according to an embodiment of this application. The intrinsic epitaxial layer 60 is formed, which is located in the trench 11 and covers the high-resistivity substrate 10. During the formation of the intrinsic epitaxial layer 60, there is not only vertical epitaxy but also lateral epitaxy. The density of silicon source gas at the bottom of the trench 11 is lower than that at the top of the trench 11. Therefore, the epitaxy speed of the intrinsic epitaxial layer at the bottom of the trench 11 is slower than that at the top of the trench 11. Therefore, the opening at the top of the trench 11 is sealed in advance, thereby forming an air gap 11 in the space near the bottom of each trench 11. The air gap 11 is located between the amorphous silicon layer 50 and the intrinsic epitaxial layer 60.
[0053] Specifically, during the formation of the intrinsic epitaxial layer 60, doping should be avoided in the intrinsic epitaxial layer 60.
[0054] Preferably, the resistivity of the intrinsic epitaxial layer 60 should also be greater than 1 kΩ·cm.
[0055] Finally, proceed to step S8: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of a semiconductor structure after planarization of the intrinsic epitaxial layer surface according to an embodiment of this application. The intrinsic epitaxial layer 60 surface is planarized.
[0056] Preferably, after planarization of the surface of the intrinsic epitaxial layer 60, the distance between the top of the air gap 50 and the upper surface of the intrinsic epitaxial layer 60 is 0.2 μm to 0.5 μm.
[0057] In this application, by forming an air gap in a trench of a high-resistivity substrate and forming an amorphous silicon layer on the bottom wall of the trench at the bottom of the air gap, isolation can be enhanced, crosstalk can be reduced, and harmonic performance can be improved, thereby greatly reducing the impact of substrate noise on radio frequency devices.
[0058] Based on the same inventive concept, embodiments of this application also provide a substrate for a radio frequency device, with reference to... Figure 7 The substrate of the radio frequency device includes:
[0059] High-resistivity substrate 10;
[0060] A plurality of trenches 11, the trenches 11 being located in the high-resistivity substrate 10 of a certain thickness;
[0061] An amorphous silicon layer 40 is located on the bottom wall of the trench 11;
[0062] Intrinsic epitaxial layer 60, which is located in the trench 11 and covers the surface of the high resistivity substrate 10, wherein an air gap 50 is formed below each trench 11, and the air gap 50 is located between the amorphous silicon layer 40 and the intrinsic epitaxial layer 60.
[0063] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a substrate for a radio frequency device, characterized in that, include: A high-resistivity substrate is provided, on which a hard mask layer is formed; A photoresist layer is coated on the hard mask layer; A trench pattern is defined on the photoresist layer to obtain a patterned photoresist layer; Using the patterned photoresist layer as a mask, the hard mask layer and a portion of the high-resistivity substrate are etched to obtain several trenches; An ion implantation process is performed on the high-resistivity substrate to form an amorphous silicon layer on the bottom wall of the trench; Remove the patterned photoresist layer and the hard mask layer; An intrinsic epitaxial layer is formed, the intrinsic epitaxial layer being located in the trench and covering the high-resistivity substrate, wherein, during the formation of the intrinsic epitaxial layer, an air gap is formed below each of the trenches, the air gap being located between the amorphous silicon layer and the intrinsic epitaxial layer; The surface of the intrinsic epitaxial layer is planarized.
2. The method for fabricating a substrate for a radio frequency device according to claim 1, characterized in that, The resistivity of the intrinsic epitaxial layer is greater than or equal to 1 kΩ·cm.
3. The method for fabricating a substrate for a radio frequency device according to claim 1, characterized in that, After planarization of the intrinsic epitaxial layer surface, the distance between the top of the air gap and the upper surface of the intrinsic epitaxial layer is 0.2 μm to 0.5 μm.
4. The method for fabricating a substrate for a radio frequency device according to claim 1, characterized in that, The height of the trench is 1μm to 10μm.
5. The method for fabricating a substrate for a radio frequency device according to claim 1, characterized in that, The depth-to-width ratio of the trench is (5:1) to (500:1).
6. The method for fabricating a substrate for a radio frequency device according to claim 1, characterized in that, During the formation of the amorphous silicon layer on the bottom wall of the trench, the high-resistivity substrate is subjected to at least one oxygen ion implantation and at least one argon ion implantation.
7. The method for fabricating a substrate for a radio frequency device according to claim 1, characterized in that, During the formation of the amorphous silicon layer on the bottom wall of the trench, oxygen ions and argon ions are simultaneously implanted into the high-resistivity substrate.
8. The method for fabricating a substrate for a radio frequency device according to claim 1, characterized in that, The resistivity of the high-resistivity substrate is greater than or equal to 1 kΩ·cm.
9. A substrate for a radio frequency device, characterized in that, include: High-resistivity substrate; Several trenches, the trenches being located within a portion of the thickness of the high-resistivity substrate; An amorphous silicon layer is located on the bottom wall of the trench; An intrinsic epitaxial layer is located in the trench and covers the surface of the high-resistivity substrate, wherein an air gap is formed below each trench, and the air gap is located between the amorphous silicon layer and the intrinsic epitaxial layer.