A selection method and system for a high spectral efficiency R16QAM structured bit selector

Abstract

This invention belongs to the field of wireless communication technology and discloses a selection method for a high-spectrum-efficiency R16QAM (Rateless 16QAM) structured bit selector. First, N information bits are encoded using a 1 / 3 code rate Turbo code to obtain a 3N-length coded bit block to be transmitted. Then, the coded bit block is progressively selected in a structured manner according to the symbol transmission order, and finally transmitted and received in a rateless manner. Specifically, bits are extracted from multiple candidate sub-blocks and recombined to generate structured bit sub-blocks. Multiple bit sub-blocks constitute a single bit block, and different bit blocks are progressively generated. This structured "bit sub-block-bit block-progressive bit block" construction method reintegrates the entire coded bit block to be transmitted into a hierarchical structured block, providing the receiver with iteratively demodulated and decoded multi-dimensional correlation observation information.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and particularly relates to a selection method and system for a high-spectrum-efficiency R16QAM structured bit selector. Background Technology

[0002] With the continuous development of wireless communication technology, the Internet of Things (IoT) is undergoing an unprecedented transformation. The high speed, low latency, and wide connectivity of 5G networks provide strong technical support for IoT. In current IoT application scenarios, most nodes are battery-powered, with limited computing resources and energy. However, the energy consumption of IoT nodes mainly comes from the data transmission consumption of uplink transmission. To reduce node transmission power while meeting coverage requirements, existing IoT communication standards often employ low code rate + low-order modulation and repetitive transmission techniques, such as NB-IoT using 1 / 3 code rate Turbo code + BPSK / QPSK + up to 128 repetitions. Since fixed code rate + repetitive transmission has poor channel adaptability, in practical applications, if the receiver cannot successfully demodulate and decode, the transmitter needs to repeat the transmission with double the number of symbols until successful reception. Obviously, under time-varying channels, this repetitive transmission strategy has the problem of low energy efficiency. How to achieve high spectral efficiency and high energy efficiency wireless transmission over a wide range of channel variations to meet the large dynamic coverage requirements of IoT communication and effectively extend node lifetime is of great significance to IoT communication.

[0003] Adaptive transmission technology is an effective method to improve the transmission rate of wireless communication. Traditional adaptive transmission technologies, such as Adaptive Modulation and Coding (AMC), widely used in standards like 802.16 and 802.11, can achieve finite-state rate adjustment through code rate and modulation scheme. However, it requires accurate channel information to achieve high spectral efficiency. In reality, accurate channel information is often difficult to obtain, causing AMC to struggle to maintain good transmission performance under wide channel conditions.

[0004] In the past decade, to achieve continuous and high adaptive rate adjustment, many scholars have proposed new adaptive transmission techniques, such as Rate Compatible Modulation (RCM), Analog Fountain Codes (AFC), Strider, and Spinal Codes. These new adaptive transmission techniques all employ a rateless transmission scheme. Specifically, the receiver only needs to continuously receive symbols without requiring feedback on channel state. When the number of received symbols reaches the demodulation threshold, demodulation is attempted. If demodulation fails, symbols are continuously received. When the incremental symbol count reaches the threshold, all received symbols are demodulated again, and this process is repeated until the current transmitted data is successfully demodulated. Once demodulation is successful, the receiver sends an ACK signal back to the transmitter. Upon receiving this signal, the transmitter begins generating and transmitting the next frame of mapped symbols. Because the incremental symbols can be adjusted in small steps, these rateless transmission techniques can achieve a near-continuous transmission rate. The differences between different rateless transmission techniques lie in the different bit-symbol mapping methods and demodulation methods used. However, these rateless adaptive transmission technologies all suffer from high demodulation complexity, making them difficult to apply in IoT scenarios where computing power is sufficient.

[0005] In 2021, we proposed a Lightweight Rate Compatible Modulation (TLRCM) scheme based on Turbo coding (published in IEEE Internet of Things, Vol. 8, No. 13, 2021, a leading international journal in IoT technology). Due to the simple weight set sampling of TLRCM, its demodulation complexity is greatly reduced, to approximately 1% of RCM. Furthermore, TLRCM can operate in a rate-free manner in low signal-to-noise ratio environments, achieving smooth rate adaptation to channel changes, making it very suitable for IoT uplink transmission. However, the maximum transmission rate of TLRCM is only 1.7 bits / s / Hz. To achieve adaptive transmission with a higher maximum transmission rate over a wider channel range... Subsequently, we proposed a rateless 16QAM (R16QAM) IoT uplink transmission scheme based on 16QAM (approved as a Chinese invention patent in November 2021, ZL201810775385.7, and published in IEEE Internet of Things, Vol. 9, No. 21, 2022), whose demodulation complexity is comparable to TLRCM. The R16QAM transmitter maps the coded bits to be transmitted to 16QAM symbols for rateless transmission using a random bit selector and a weighted symbol mapper. The receiver uses serial BP iterative demodulation-decoding, enabling reliable transmission of high-order 16QAM modulation within a large dynamic range of channel signal-to-noise ratio (-15 to +15 dB), and achieving continuous and higher transmission rates.

[0006] Specifically, in R16QAM modulation, an information bit block of length N is Turbo encoded at 1 / 3 code rate to obtain a coded bit block of length 3N. The first N bits are the information bits to be transmitted, the next N bits are the parity bits output by RSC1, and the last N bits are the parity bits output by RSC2. The R16QAM transmitter uses a bit selector and a specially designed 16QAM symbol mapper to map the coded bits to be transmitted into a series of 16QAM symbols, and then transmits the symbols in a rateless manner. Since the bits and symbols satisfy an algebraic weighted relationship, the receiver uses this relationship for Belief Prorogation (BP) demodulation.

[0007] Studies have shown that the bit selector has a significant impact on the transmission performance of R16QAM. The original R16QAM uses a sequential + random bit selection strategy, resulting in a significant loss of spectral efficiency in the mid-to-high signal-to-noise ratio range (5-15dB). This is because the first 3N / 4 16QAM symbols are sequentially mapped from 3N bits (N information bits, 2N parity bits), while subsequent symbols are all mapped from random bits. Therefore, under sufficiently high channel conditions (close to 15dB), only N / 4 16QAM symbols mapped from all information bits need to be transmitted, and the receiver can recover N information bits with a high probability, enabling the system to achieve a maximum spectral efficiency of close to 4 bits / s / Hz. However, the bits corresponding to the i-th symbol in the subsequent progressive transmission have three possibilities:

[0008] 1) When 2N / 4 ≥ i > N / 4, each symbol si is mapped by 4 sequential RS1 encoded bits;

[0009] 2) When 3N / 4 ≥ i > 2N / 4, each symbol si is mapped from 4 sequential RS2 encoded bits;

[0010] 3) When i>3N / 4, each symbol si will be mapped by randomly selecting 4 bits from 3N bits (including N information bits and 2N parity bits).

[0011] Clearly, if channel conditions are poor, this sequential + random bit selector strategy means that the N / 4+1 to 2N / 4th symbols in the asymptotic transmission are entirely mapped from the coded bits of RSC1. These symbols do not fully utilize the corresponding coded bits of RSC2. Only as the number of transmitted symbols continues to increase does the coded bits of RSC2 gradually become available. Therefore, when the signal-to-noise ratio is in the mid-to-high range, the number of symbols required for successful demodulation is often between N / 4 and 3N / 4. During the asymptotic transmission process, the information from RSC1 and RSC2 is not fully utilized, resulting in insufficient error correction capability of Turbo and inadequate decoding performance. Furthermore, while the subsequent completely random bit selection strategy ensures that all bits are selected with equal probability when the total number of transmitted symbols is large, it cannot guarantee that all 3N bits will be selected once every 3N / 4 transmitted symbols during the asymptotic transmission process. This prevents uniform bit selection during asymptotic transmission, potentially causing some bits to be selected multiple times while others are not selected, reducing the success rate of demodulation-decoding at the receiver.

[0012] Based on the above analysis, the main problems with the existing rateless 16QAM (R16QAM) technology based on "sequential + random" bit selectors are as follows:

[0013] (1) The first 3N / 4 16QAM symbols of the existing R16QAM are mapped sequentially from 4 bits selected from 3N coding bits (including N information bits, N RSC1 parity bits, and N RSC2 parity bits). The advantage of this sequential selection strategy is that the first N / 4 symbols contain all N information bits, which allows the first N / 4 symbols to be successfully demodulated with a high probability under high signal-to-noise ratio, thereby achieving a maximum spectral efficiency of close to 4 bits / s / Hz. However, once the demodulation of the N / 4 symbols fails, the continuously transmitted N / 4+1 to 3N / 4 symbols cannot simultaneously utilize the parity bits of encoder RSC1 and RSC2, so that under medium to high channel conditions, the continuously transmitted symbols cannot fully utilize the error correction capability of the Turbo code.

[0014] (2) In the existing R16QAM, a "random" bit selection strategy is adopted for symbols starting from the 3N / 4th symbol. Under this strategy, if the channel conditions are poor, each symbol is mapped by completely random coded bits starting from the 3N / 4+1th transmitted symbol. According to the law of large numbers, under the random selection strategy, uniform selection of all coded bits can only be achieved when the number of transmitted symbols M is much greater than the coded bit length 3N. However, under medium- to high-band channel conditions, the incremental symbols transmitted continuously are often less than the coded bit length. Therefore, it is impossible to guarantee that all coded bits are uniformly selected, meaning that some bits may not be covered, forming an "information blind spot," which affects demodulation performance.

[0015] Therefore, the existing "sequential + random" bit selector of R16QAM will cause R16QAM to be unable to fully utilize the error correction capability of Turbo codes in the commonly used mid-to-high channel range (5-15dB), and will not be able to ensure that the subsequent symbols of continuous transmission are selected evenly. This results in significant performance degradation of R16QAM in a wide channel range, especially in mid-to-high channel conditions, which has become a key bottleneck restricting the continuous improvement of spectral efficiency of R16QAM in actual channel environments.

[0016] The difficulty in solving the above problems is:

[0017] (1) Demodulation and decoding are crucial to the transmission performance of R16QAM. Random bit selection strategies offer better demodulation performance, but structured bit selection strategies are more effective at utilizing the paired parity bits of the two convolutional encoders RSC1 and RSC2 in Turbo codes, thereby fully leveraging the error correction capability of Turbo codes. However, the randomness and structure of the bit selector strategy are contradictory in practical applications. Therefore, under mid-to-high-band channel conditions, ensuring both the randomness of the encoded bits corresponding to continuously transmitted symbols and fully utilizing the error correction capability of Turbo codes is the core challenge in R16QAM bit selector design.

[0018] (2) In incremental transmission, rateless transmission technology inherently conflicts with the integrity and uniformity of bit coverage due to the finite number of incremental symbols transmitted continuously. Especially under medium to low signal-to-noise ratio (SNR) conditions, ensuring that the 3N coded bits are selected uniformly within the number of continuously incremental transmission symbols—avoiding the repeated selection of already transmitted "redundant bits" while preventing the omission of untransmitted "critical bits"—is challenging. Therefore, while improving the spectral efficiency of R16QAM under medium to high channel conditions, ensuring that each coded bit can be uniformly selected by the continuously transmitted symbols under low SNR conditions, avoiding the formation of local "selection blind spots," and maintaining good transmission performance over a wider channel range is another key challenge for R16QAM bit selectors.

[0019] In summary, designing a hybrid selection strategy for the R16QAM bit selector that balances randomness and structure, maximizing spectral efficiency at high signal-to-noise ratios, enabling progressively transmitted symbols to utilize the paired parity bits of RSC1 and RSC2 in medium- to high-channel ranges to fully leverage the error correction capability of Turbo codes, and ensuring that each coded bit is uniformly selected by continuously transmitted incremental symbols under low signal-to-noise ratio conditions, thereby guaranteeing good transmission performance of R16QAM across the entire channel variation range, is extremely challenging. Summary of the Invention

[0020] To address the problems existing in the prior art, this invention provides a selection method for a high spectral efficiency R16QAM structured bit selector.

[0021] This invention is implemented as follows: a selection method for a high-spectral-efficiency R16QAM structured bit selector includes:

[0022] Step 1, Sequential information bit sub-block;

[0023] Step 2, randomly verify bit sub-blocks;

[0024] Step 3, candidate bit sub-block initialization;

[0025] Step 4, generating structured bit sub-blocks;

[0026] Step 5, generating structured bit blocks;

[0027] Step 6, generating structured progressive bit blocks;

[0028] Repeat steps 3-5 to progressively generate multiple different structured bit blocks, such that the total number of bit sub-blocks equals the maximum number of transmitted symbols M;

[0029] Step 7: Record the bit numbers of N / 4 sequential bit sub-blocks, N / 2 random parity bit sub-blocks, and all subsequently generated structured asymptotic bit sub-blocks, and store them in the memories of the transmitting and receiving ends. Once transmission begins, the transmitting end sequentially reads 4 bit numbers from the memory each time, then selects the corresponding 4 bits from the encoded bit block, maps them to R16QAM constellation points, and transmits them in a rateless manner. The receiving end can perform iterative demodulation and decoding using the BP method based on the relationship between the received symbol number and the corresponding bit in the memory.

[0030] Furthermore, the sequence information bit sub-block:

[0031] From an information bit block of length N [b1,b2,...,b] N In this process, four information bits are selected sequentially each time, resulting in a total of N / 4 sequential information bit sub-blocks b, each with a length of 4. SL The i-th sequential information bit sub-block is:

[0032] b SL (i)=[b 4i-3 ,b 4i-2 ,b 4i-1 ,b 4i ], i = 1, 2, ..., N / 4; (1)

[0033] Furthermore, the random check bit sub-block:

[0034] The parity bit block of length N [c11,c12,...,c1] ​​obtained from encoder RSC1 N In the process, two parity bits are randomly and non-repeatingly selected each time, and a parity bit block of length N [c21,c22,...,c2] is obtained from encoder RSC2. N Select two parity bits at the corresponding positions to form a random parity bit sub-block C of length 4. RL for:

[0035] C RL (i)=[c1 rp(i,N,1) c1 rp(i,N,2) c2rp(i,N,1) c2 rp(i,N,2) ], i=1,2,...,N / 2; (2)

[0036] Where rp(i,N,1) and rp(i,N,2) are the first and second numbers randomly selected from 1 to N (excluding the 2(i-1) numbers selected in the first i-1 times) respectively; a total of N / 2 random parity bit sub-blocks are obtained; thus, N / 4 sequential information bit sub-blocks and N / 2 random parity bit sub-blocks select each bit in the information + parity bit block of length 3N once;

[0037] Subsequent bit blocks are structured bit blocks, each consisting of 3N / 4 structured bit sub-blocks of length 4.

[0038] Furthermore, the candidate bit sub-block is initialized as follows:

[0039] To facilitate the generation of subsequent structured bit blocks, the N / 4 sequential bit sub-blocks and N / 2 random parity bit sub-blocks obtained in steps 1-2 are used as 3N / 4 initial candidate bit sub-blocks.

[0040] Furthermore, the structured bit sub-blocks are generated as follows:

[0041] Randomly select 4 sub-blocks from the current candidate sub-blocks; then randomly select 1 bit from each sub-block to obtain a bit sub-block of length 4; then remove the selected bit sequence number from the corresponding candidate sub-block (sequence information bit sub-block or random check bit sub-block); if all 4 bits of a candidate sub-block are removed, then remove the candidate sub-block from the current candidate sub-blocks.

[0042] Furthermore, the structured bit block generation:

[0043] Repeat step 4 3N / 4 times to obtain 3N / 4 structured bit sub-blocks of length 4, which together form a structured bit block.

[0044] Another object of the present invention is to provide a selection system for a high spectral efficiency R16QAM structured bit selector, comprising:

[0045] Sequence module, used to sequence information bit sub-blocks;

[0046] The random verification module is used to randomly verify bit sub-blocks;

[0047] An initialization module is used for initializing candidate bit sub-blocks;

[0048] Bit sub-block generation module, used for structured bit sub-block generation;

[0049] Bit block generation module, used for generating structured bit blocks;

[0050] The progressive bit block generation module is used for structured progressive bit block generation;

[0051] The demodulation and decoding module records the bit indices of N / 4 sequential bit sub-blocks, N / 2 random parity bit sub-blocks, and all subsequently generated structured asymptotic bit sub-blocks, and stores them in the memories of both the transmitting and receiving ends. Once transmission begins, the transmitting end sequentially reads 4 bit indices from the memory each time, then selects the corresponding 4 bits from the encoded bit block, maps them to R16QAM constellation points, and transmits them in a rateless manner. The receiving end, based on the relationship between the received symbol indices and corresponding bits in the memory, can perform iterative demodulation and decoding using the BP method.

[0052] Another object of the present invention is to provide a computer device including a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the steps of the selection method of the high spectral efficiency R16QAM structured bit selector.

[0053] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the selection method of the high spectral efficiency R16QAM structured bit selector.

[0054] Another object of the present invention is to provide an information data processing terminal for implementing the selection system of the high spectral efficiency R16QAM structured bit selector.

[0055] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0056] The structured "bit sub-block-bit block-progressive bit block" R16QAM bit selector construction method reorganizes the entire coded bit block to be transmitted into a hierarchical structured block. This provides the receiver with multi-dimensional correlation observation information for iterative demodulation and decoding, continuously improving the transmission performance of R16QAM in common wireless channel environments. It effectively increases the success rate of demodulation and decoding, thereby enhancing the reliability of the communication system and significantly improving the spectral efficiency of R16QAM in the mid-to-high signal-to-noise ratio range, effectively reducing transmission power consumption and saving energy. Furthermore, the structured design method allows for flexible adjustment of the transmission block length N as needed, rapidly generating a large number of random R16QAM bit selectors with identical performance to meet the transmission delay requirements of different systems.

[0057] By fully utilizing the structural characteristics of R16QAM coded bits, a structured progressive bit selector can be designed to fully leverage the error correction capability of Turbo codes. This can provide new ideas and methods for the development and application of rateless transmission systems based on traditional high-order modulation techniques such as MQAM and MPSK using Turbo codes or LDPC codes, thereby promoting innovation and application demonstration of high-spectral-efficiency rateless transmission technologies.

[0058] (1) The expected benefits and commercial value of the technical solution of this invention after transformation are as follows:

[0059] Without increasing modulation and demodulation complexity, this invention, through a structured bit selector design, can continuously improve the spectral efficiency of R16QAM, reduce transmission energy consumption, and effectively improve transmission reliability over a wide range of practical wireless channels (signal-to-noise ratio -10 to 15 dB). Therefore, the direct benefits of this invention are as follows:

[0060] Capacity Gain: Within the same spectral bandwidth, existing R16QAM technology based on "sequential + random" bit selectors achieves approximately 30% spectral efficiency improvement compared to adaptive coding and modulation techniques widely used in wireless communication standards such as 802.11 and 802.16e. However, R16QAM technology based on the structured bit selector of this invention, compared to existing R16QAM technology using "sequential + random" bit selectors, can maintain a maximum spectral efficiency improvement of approximately 25% over a wider channel range. This means that system capacity can be significantly enhanced and transmission rates increased without increasing system spectrum resources and costs.

[0061] Energy efficiency optimization: Under the same signal-to-noise ratio and transmit power, the high spectral efficiency structured bit selector R16QAM of this invention can reduce transmission symbols by up to 50% compared with currently commercially available adaptive coding and modulation technology, effectively reducing power consumption at the transmitting end, meeting the green development requirements of the "dual carbon" target, and is particularly suitable for wireless communication scenarios with large dynamic range, wide coverage, low signal-to-noise ratio and energy constraints.

[0062] Enhanced reliability: The R16QAM rateless transmission technology based on the structured bit selector of this invention can continuously reduce the bit error rate and block error rate under harsh channel conditions and commonly used medium-to-high signal-to-noise ratio conditions, maintaining highly reliable and low-interruption-rate communication.

[0063] The aforementioned expected benefits will ultimately translate into significant commercial value in the field of wireless communication, particularly in areas such as IoT communication, satellite communication, and emergency communication, bringing development opportunities to various market players.

[0064] (2) Whether the technical solution of the present invention solves the technical problem that people have long wanted to solve but have never been able to solve successfully:

[0065] How to design bit-symbol mapping and transmission with low implementation complexity based on the structure of encoded bits, and improve spectral efficiency and transmission reliability over a wide channel range, is a technical problem that people have long wanted to solve but has not yet been well solved.

[0066] While traditional adaptive coding and modulation (ACTM) can improve spectral efficiency to some extent, it is limited by the finite coding rate and modulation order, allowing only step-like transmission rate adjustments. Rateless transmission techniques, such as RCM and AFC, can achieve continuous and high transmission rates, but their demodulation complexity is high, making them difficult to apply practically. R16QAM can improve spectral efficiency over a wide channel range with lower complexity, but its "sequential + random" bit selector fails to consider the structural characteristics of the coded bits, cannot fully utilize the error correction capabilities of channel coding, and cannot simultaneously ensure the randomness, integrity, and uniformity of bit selection during continuous transmission, making it difficult to further improve system performance.

[0067] The R16QAM bit selector proposed in this invention, without altering the basic structure of existing communication systems, combines rateless transmission technology and performs structured bit selection based on the structural characteristics of coded bits, achieving a collaborative design effect of "encoding-bit-symbol" during rateless transmission. Specifically, in the R16QAM bit selector design, a structured bit selection design is performed according to the symbol transmission order. This ensures high-probability successful reception even with only information symbols transmitted at high signal-to-noise ratios. Furthermore, in the mid-to-high-end channel range, the progressively transmitted R16QAM check symbols are mapped from the check bits simultaneously output by the two convolutional encoders of the Turbo code, fully leveraging the error correction capability of the Turbo code. In addition, the symbols subsequently transmitted, mapped from the information-check hybrid bits, maintain both uniformity and integrity of the selected bits within the block and good randomness between blocks. This structured "bit sub-block-bit block-progressive bit block" construction method reintegrates the entire coded bit block to be transmitted into a hierarchical structured block, providing the receiver with multi-dimensional correlation observation information for iterative demodulation and decoding. Without increasing the complexity of the transmitter and receiver, R16QAM can achieve spectral efficiency close to symbol entropy under high channel conditions, and enable progressively transmitted symbols to fully utilize the error correction capability of channel coding. Thus, it can effectively improve the transmission reliability and spectral efficiency of R16QAM and optimize transmission performance within a wide range of dynamic channel changes. Attached Figure Description

[0068] Figure 1This is a flowchart of the selection method for a high spectral efficiency R16QAM structured bit selector provided in an embodiment of the present invention.

[0069] Figure 2 This is a block diagram of the selection system structure of the high spectral efficiency R16QAM structured bit selector provided in the embodiments of the present invention.

[0070] Figure 3 This is a diagram of the coded bit block structure provided in an embodiment of the present invention.

[0071] Figure 4 This is a schematic diagram of the structured progressive bit selector provided in an embodiment of the present invention.

[0072] Figure 5 This is an example of a bit scatter plot corresponding to the R16QAM transmission symbols provided in this embodiment of the invention (N=48, M=288).

[0073] Figure 6 This is a comparison chart of the cumulative probability distribution curves of successful demodulation of R16QAM provided in the embodiments of the present invention and existing R16QAM under different signal-to-noise ratios.

[0074] Figure 7 This is a comparison curve of the spectral efficiency of R16QAM and other schemes provided in the embodiments of the present invention.

[0075] Figure 8 This is a system implementation block diagram of the R16QAM structured progressive bit selector provided in an embodiment of the present invention.

[0076] Figure 9 This is a diagram illustrating the system implementation steps of the R16QAM structured progressive bit selector provided in an embodiment of the present invention.

[0077] Figure 10 This is a comparison of the bit error rate performance of the present invention with that of existing bit selectors in R16QAM (N=48), provided by the embodiments of the present invention.

[0078] Figure 11 This is a comparison of the block error rate performance of the present invention with that of the existing bit selector R16QAM (N=48) provided in the embodiments of the present invention.

[0079] Figure 12 This is a comparison chart of the spectral efficiency performance of the present invention and existing bit selectors in the R16QAM format provided by the embodiments of the present invention.

[0080] Figure 13 This is a graph showing the R16QAM spectral efficiency improvement of the bit selector provided in this embodiment of the invention.

[0081] Figure 14This is a comparison chart of the R16QAM spectral efficiency of the bit selector provided in the embodiments of the present invention.

[0082] Figure 15 This is a graph showing the percentage improvement in R16QAM spectral efficiency of the bit selector provided in this embodiment of the invention.

[0083] Figure 16 This is a detailed flowchart of the selection method for the high spectral efficiency R16QAM structured bit selector provided in the embodiments of the present invention. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0085] Currently, commercially available high-spectrum-efficiency modulation systems mainly employ high-order modulation combined with channel coding. However, due to their relatively small Euclidean distance, traditional high-order modulation exhibits poor noise immunity, and even with the addition of low-rate channel coding, it can only operate under conditions of high signal-to-noise ratio. For example, in adaptive coding modulation techniques widely used in wireless standards such as 802.11n and 802.16e, 64QAM modulation with 2 / 3 of the LDPC code can only operate above 15dB, and 16QAM modulation with 3 / 4 of the LDPC code can only operate above 10dB. R16QAM, due to its rateless transmission technology, can achieve continuous and high spectral efficiency over a wide channel range. However, the core bottleneck of R16QAM technology lies in how to design the bit selector to ensure good randomness and uniformity between the continuously transmitted modulation symbols and their corresponding coded bits, enabling the system to achieve improved transmission performance over a wide range of channel variations. Traditional bit selection methods based on "sequential + random" selection suffer from several drawbacks. First, the sequence check bits transmitted in intermediate transmissions lack randomness. Second, they can only utilize the check bits of the single encoder RSC of the Turbo code, failing to fully leverage its error correction capabilities. Third, the bits corresponding to subsequently transmitted modulation symbols are completely random, leading to uneven bit selection in local areas. This results in symbols with small intervals repeatedly selecting certain coded bits or symbols with large intervals missing certain bits, impacting constellation point utilization and coding gain. Consequently, the bit correlation between symbols cannot be fully utilized, limiting the iterative demodulation and decoding performance at the receiver. The system exhibits significant performance loss in the bit error rate curve at high signal-to-noise ratios. This problem directly hinders the industrialization and widespread adoption of R16QAM in high-speed wireless transmission and high-capacity access scenarios.

[0086] The basic idea for solving the above problems lies in the structured combination and progressive generation of information bits and parity bits. A hybrid strategy of sequential and random sub-blocks is used to construct a candidate bit set with uniform coverage. This process ensures that each bit has an equal opportunity for mapping during transmission, preventing some bits from being marginalized in higher-order constellation point mappings and losing decoding gain. With the progressive generation mechanism, the entire bit mapping space is dynamically filled, guaranteeing complete coverage within the maximum number of transmitted symbols, thereby improving spectral efficiency at the joint optimization level of coding and modulation.

[0087] In terms of specific working principles, the construction of sequential information bit sub-blocks ensures both the integrity and timing consistency of information bits, facilitating the receiver to obtain reliable prior information during the initial iteration process. Furthermore, under high signal-to-noise ratio (SNR) conditions, the first N / 4 symbols can directly recover the N information bits to be transmitted, achieving maximum spectral efficiency to maximize symbol information entropy. The introduction of random parity sub-blocks overcomes the shortcomings of traditional parity bit selection, which prevents parity bits output by two encoders from being utilized in the same symbol, thus affecting error correction performance. Simultaneously, it ensures good randomness in parity bit selection, effectively improving the error correction performance of Turbo codes under medium-to-high SNR conditions.

[0088] The essence of the structured bit sub-block generation stage is to extract bits from multiple candidate sub-blocks and recombine them, with multiple bit sub-blocks forming a structured bit block. Different structured progressive bit blocks provide a stable data pool for rateless transmission. Specifically, 3N / 4 bit sub-blocks constitute a structured block, thus ensuring that each structured bit block achieves full coverage of 3N bits (N information bits and 2N parity bits). This more structured "bit sub-block-bit block-progressive bit block" construction method reintegrates the entire encoded bits to be transmitted into hierarchical structured blocks, providing the receiver with multi-dimensional correlated observation information for iterative demodulation and decoding. The bit selector ensures that the same encoded bits are not repeatedly selected within a sub-block, but have good correlation across bit blocks. This allows the receiver to eliminate uncertainty faster than message passing during iterative demodulation using the BP algorithm, enhancing the reliability of the demodulated output soft information.

[0089] In the transmission stage, the bit sequence numbers and mapping relationships recorded in the memory ensure that the sending and receiving ends maintain a consistent bit schedule table, thus avoiding the additional signaling overhead in the rate matching process. The sending end outputs bit sequence numbers in a fixed order and completes constellation mapping, while the receiving end reverses the corresponding bits of the received symbols based on the stored mapping relationships. Through iterative updates using the Belief Prorogation (BP) method, the demodulation and decoding processes can gradually approximate the true bit distribution, achieving a significant reduction in the bit error rate. This rateless transmission method effectively avoids the complexity and power consumption issues of the rate matching stage.

[0090] From an industrial application perspective, this method provides crucial support for high-speed links, large-scale IoT access, and low-latency communication in next-generation wireless communication systems. By achieving higher spectral efficiency and lower bit error rate in R16QAM scenarios, base station equipment can support more users accessing simultaneously under the same bandwidth conditions, mobile terminals can maintain stable connections under complex channel conditions, and the overall energy efficiency and cost structure of the system are optimized. This bit selection and mapping method is not only a breakthrough in theoretical performance but also has direct engineering application value in the subsequent evolution of 5G and the design of 6G New Radio.

[0091] like Figure 1 , Figure 16 As shown, the selection method of a high spectral efficiency R16QAM structured bit selector provided in this embodiment of the invention includes the following steps:

[0092] S1, Sequential information bit sub-block;

[0093] S2, random parity bit sub-block;

[0094] S3, candidate bit sub-block initialization;

[0095] S4, generation of structured bit sub-blocks;

[0096] S5, structured bit block generation;

[0097] S6, Structured Progressive Bit Block Generation;

[0098] By repeatedly performing steps S3-S5, multiple different structured bit blocks are gradually generated, such that the total number of bit sub-blocks is equal to the maximum number of transmitted symbols M.

[0099] S7 records the bit indices of N / 4 sequential bit sub-blocks, N / 2 random parity bit sub-blocks, and all subsequently generated structured asymptotic bit sub-blocks, and stores them in the memories of both the transmitting and receiving ends. Once transmission begins, the transmitting end sequentially reads 4 bit indices from the memory each time, then selects the corresponding 4 bits from the encoded bit block, maps them to R16QAM constellation points, and transmits them in a rateless manner. The receiving end, based on the relationship between the received symbol indices and corresponding bits in the memory, can perform iterative demodulation and decoding using the BP method.

[0100] The sequential information bit sub-block provided in this embodiment of the invention:

[0101] From an information bit block of length N [b1,b2,...,b] N In this process, four information bits are selected sequentially each time, resulting in a total of N / 4 sequential information bit sub-blocks b, each with a length of 4. SL The i-th sequential information bit sub-block is:

[0102] b SL (i)=[b 4i-3 ,b 4i-2 ,b 4i-1 ,b 4i ], i = 1, 2, ..., N / 4. (1)

[0103] The random parity bit sub-block provided in this embodiment of the invention:

[0104] The parity bit block of length N [c11,c12,...,c1] ​​obtained from encoder RSC1 N In the process, two parity bits are randomly and non-repeatingly selected each time, and a parity bit block of length N [c21,c22,...,c2] is obtained from encoder RSC2. N Select two parity bits at the corresponding positions to form a random parity bit sub-block C of length 4. RL for:

[0105] C RL (i)=[c1 rp(i,N,1) c1 rp(i,N,2) c2 rp(i,N,1) c2 rp(i,N,2) ], i = 1, 2, ..., N / 2; (2)

[0106] Where rp(i,N,1) and rp(i,N,2) are the first and second numbers randomly selected from 1 to N (excluding the 2(i-1) numbers selected in the first i-1 times) respectively; a total of N / 2 random parity bit sub-blocks are obtained; thus, N / 4 sequential information bit sub-blocks and N / 2 random parity bit sub-blocks select each bit in the information + parity bit block of length 3N once;

[0107] Subsequent bit blocks are structured bit blocks, each consisting of 3N / 4 structured bit sub-blocks of length 4.

[0108] Candidate bit sub-block initialization provided in this embodiment of the invention:

[0109] To facilitate the generation of subsequent structured bit blocks, the N / 4 sequential bit sub-blocks and N / 2 random parity bit sub-blocks obtained in steps 1-2 are used as 3N / 4 initial candidate bit sub-blocks.

[0110] The structured bit sub-block generation provided by the embodiments of the present invention:

[0111] Randomly select 4 sub-blocks from the current candidate sub-blocks; then randomly select 1 bit from each sub-block to obtain a bit sub-block of length 4; then remove the selected bit sequence number from the corresponding candidate sub-block (sequence information bit sub-block or random check bit sub-block); if all 4 bits of a candidate sub-block are removed, then remove the candidate sub-block from the current candidate sub-blocks.

[0112] The structured bit block generation provided in this embodiment of the invention:

[0113] Repeat step 4 3N / 4 times to obtain 3N / 4 structured bit sub-blocks of length 4, which together form a structured bit block.

[0114] like Figure 2 As shown, the selection system of a high-spectral-efficiency R16QAM structured bit selector provided in this embodiment of the invention includes:

[0115] Sequence module, used to sequence information bit sub-blocks;

[0116] The random verification module is used to randomly verify bit sub-blocks;

[0117] An initialization module is used for initializing candidate bit sub-blocks;

[0118] Bit sub-block generation module, used for structured bit sub-block generation;

[0119] Bit block generation module, used for generating structured bit blocks;

[0120] The progressive bit block generation module is used for structured progressive bit block generation;

[0121] The demodulation and decoding module records the bit indices of N / 4 sequential bit sub-blocks, N / 2 random parity bit sub-blocks, and all subsequently generated structured asymptotic bit sub-blocks, and stores them in the memories of both the transmitting and receiving ends. Once transmission begins, the transmitting end sequentially reads 4 bit indices from the memory each time, then selects the corresponding 4 bits from the encoded bit block, maps them to R16QAM constellation points, and transmits them in a rateless manner. The receiving end, based on the relationship between the received symbol indices and corresponding bits in the memory, can perform iterative demodulation and decoding using the BP method.

[0122] Another object of the present invention is to provide a computer device including a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the steps of the selection method of the high spectral efficiency R16QAM structured bit selector.

[0123] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the selection method of the high spectral efficiency R16QAM structured bit selector.

[0124] Another object of the present invention is to provide an information data processing terminal for implementing the selection system of the high spectral efficiency R16QAM structured bit selector.

[0125] Specific implementation of the present invention:

[0126] The structured bit selector designed in this invention successfully solves the problem that the spectral efficiency of existing R16QAM transmissions cannot be further improved in the medium-to-high signal-to-noise ratio (5-15dB) range. It significantly improves the transmission rate of R16QAM in commonly used wireless channels and further reduces the uplink power consumption of IoT nodes. To date, there are no reports of this invention domestically or internationally. This invention is a technological breakthrough achieved through in-depth research based on the inventor's academic work, "Arateless 16QAMS scheme for IoT Uplink Communications," which was granted a Chinese invention patent in November 2021 (ZL201810775385.7) and published in IEEE Internet of Things, Volume 9, Issue 21, 2022. Specifically, the N information bits in the coded bit block to be transmitted are selected sequentially to ensure that the radio symbol composed of all information bit sub-blocks can be successfully demodulated with a high probability under high signal-to-noise ratio conditions. Then, the same random selection strategy is used for the subsequent RCS1 and RSC2 coded bits, each with a length of N. This ensures that the parity bits corresponding to the continuously transmitted 16QAM symbols have good randomness under mid-to-high-end channel conditions, ensuring good spectral efficiency, and also allows the 4 coded bits output by RCS1 and RCS2 when the 4 parity bits corresponding to each 16QAM symbol are 2 random information bits input. This correspondence allows the receiver to fully utilize the error correction performance of the Turbo decoder. If the channel conditions are poor, the subsequent transmitted symbols will randomly select 4 sub-blocks from all information bit sub-blocks and parity bit sub-blocks, and then select 1 bit from each sub-block for symbol mapping. This ensures that every 3N / 4 symbols in continuous transmission can select all 3N-length coded bits, giving R16QAM good randomness in the medium to low channel range while ensuring uniformity in coded bit selection. This guarantees that R16QAM can achieve good transmission performance throughout the entire channel variation range.

[0127] In summary, to address the problems existing in the prior art, this invention provides a structured bit selector. Using this invention in conjunction with the R16QAM transmission scheme significantly solves the performance degradation problem at medium to high signal-to-noise ratios (5-15dB). The technical solution of this invention will be described in detail below with reference to specific embodiments.

[0128] Example 1

[0129] like Figure 3 As shown, the coded bit block structure of the present invention is implemented as follows: information bits of length N [b1, b2, ..., b...] NAfter 1 / 3 Turbo encoding, the parity bits [c11,c12,...,c1] ​​output by RSC1 are... N The parity bits [c21,c22,...,c2] output by RSC2 and RSC2 N ], concatenated into a 3N-length coded bit block to be transmitted [b1,b2,...,b N c11, c12..., c1 N c21, c22, ..., c2 N The bit selector selects 4 bits at a time from a 3N-length coded bit block and maps them to R16QAM constellation symbols for transmission.

[0130] Figure 4 A bit selector selection demonstration of the present invention is given, wherein the information bit block length is N and the maximum number of transmitted symbols is M. The structure of the bit selector is as follows:

[0131] 1) The first N / 4 bit blocks are sequential information bit sub-blocks. Specifically, starting from the information bit block of length N [b1, b2, ..., b...] N In this process, four information bits are selected sequentially each time, resulting in a total of N / 4 sequential information bit sub-blocks b, each with a length of 4. SL The i-th sequential information bit sub-block is:

[0132] b SL (i)=[b 4i-3 ,b 4i-2 ,b 4i-1 ,b 4i ], i = 1, 2, ..., N / 4;

[0133] 2) The bit sub-blocks from N / 4+1 to 3N / 4 are random parity bit blocks. The parity bit sub-blocks of length N obtained from encoder RSC1 are [c11,c12,...,c1...]. N In the process, two parity bits are randomly and non-repeatingly selected each time, and then a parity bit sub-block of length N [c21,c22,...,c2] is obtained from encoder RSC2. N Select two parity bits at the corresponding positions to form a random parity bit sub-block C of length 4. RL for:

[0134] C RL (i)=[c1 rp(i,N,1) c1 rp(i,N,2) c2 rp(i,N,1) c2 rp(i,N,2) ], i = 1, 2, ..., N / 2;

[0135] Where rp(i,N,1) and rp(i,N,2) are the first and second numbers respectively, randomly selected from 1 to N (excluding the 2(i-1) numbers selected in the first i-1 times) in the i-th iteration; a total of N / 2 random parity bit sub-blocks C are obtained. RL (1),C RL (2),...,C RL (N / 2); This ensures that under medium to high signal-to-noise ratio conditions, each continuously transmitted symbol can fully utilize the two parity bits of RSC1 and RSC2 simultaneously, maximizing the error correction capability of the Turbo code;

[0136] The above selection results in N / 4 sequential information bit sub-blocks and N / 2 random check bit sub-blocks, selecting each bit in the information + check bit block of length 3N once; at the same time, the N / 4 sequential information bit sub-blocks and N / 2 random check bit sub-blocks are used as the initial candidate bit sub-blocks for the subsequent structured bit block;

[0137] 3) Following the random parity bit block is the progressively structured bit block. Each structured bit block consists of 3N / 4 structured bit sub-blocks. Each structured bit sub-block is composed of one bit from each of four different candidate bit sub-blocks. The 3N / 4 structured bit sub-blocks can select all 3N encoded bits (including N information bits and 2N parity bits) without repetition. Different structured bit blocks have the same structural characteristics but maintain different levels of randomness, ensuring that the selection of symbol pairs in progressive transmission under medium-to-low signal-to-noise ratio conditions is both random and uniform.

[0138] Figure 5 A schematic diagram of bit selection for this invention is given, with an information bit block length of N = 48 and 16QAM symbol number M = 288. Here, "x" represents in-phase component bits, and "." represents quadrature component bits. Each symbol is mapped from 4 bits. First, the information bits of length N = 48 are encoded using 1 / 3 Turbo code to obtain coded bits of length 144, where the information bit indices are 1 to 48, the parity bit indices generated by RSC1 are 49 to 96, and the parity bit indices generated by RSC2 are 97 to 144. To achieve high spectral efficiency at high signal-to-noise ratios, the bit selector of this invention sequentially selects 4 adjacent sequential information bits from the first N / 4 = 12 16QAM symbols, with each 4 sequential bits forming a sequential bit sub-block b. SL The first and second bits of each sequential sub-block are in-phase bits, and the third and fourth bits are quadrature bits. A total of 12 sequential sub-blocks b are obtained. SL .

[0139] Each symbol from N / 4+1 = 13 to 3N / 4 = 36 is mapped by 4 parity bits. Specifically, the bit selector randomly selects 2 bits from the 48 parity bits of RSC1 as in-phase component bits each time, and then takes the corresponding 2 bits from RSC2 as quadrature component bits. This ensures both the randomness of 16QAM symbols and parity bits, and that each symbol contains parity information corresponding to RSC1 and RSC2, allowing the continuously received symbols at the receiver to fully utilize the error correction capability of the Turbo code to achieve better transmission performance under medium-to-high signal-to-noise ratio conditions. For example, in the 13th bit selector, the bit numbers selected are 76 and 58, i.e., the 28th and 10th parity bits in RSC1 as in-phase component bits, and the bit numbers selected are 124 and 106, i.e., the 28th and 10th parity bits in RSC2 as quadrature component bits. These four bits are combined into a parity check sub-block C. RL Repeat this step, each time selecting two different RSC1 parity bits and the corresponding two RSC2 parity bits, until all parity bits for both RSC1 and RSC2 have been selected, resulting in a total of 24 parity sub-blocks C. RL .

[0140] Next, the selected bits from 3N / 4+1 to 6N / 4 form a structured bit block. Within this structured bit block, each bit sub-block is selected from 12 candidate sequential sub-blocks b. SL and 24 candidate check sub-blocks C RL In this process, four sub-blocks are randomly selected, and then one bit is chosen from each of the selected candidate sub-blocks to form a structured sub-block. Simultaneously, the selected bit index is removed from the corresponding candidate sub-block. If all four bits of a candidate sub-block are removed, that candidate sub-block is removed from the current candidate sub-block list. This process is repeated 3N / 4 times, resulting in 3N / 4 different structured bit sub-blocks of length 4. Each structured bit block selects each bit once from the 3N encoded bit blocks (N information bits + 2N check bits), thus ensuring the randomness and uniformity of bit selection.

[0141] Repeat the above method to generate multiple structured sub-blocks that satisfy the maximum number of symbols.

[0142] Finally, all sequential bit subblocks, parity bit subblocks, and all structured subblocks are stored sequentially in four arrays or memories, with the four selected bit indices for each subblock. During transmission, the transmitter reads four positions sequentially each time, then uses these positions to find the corresponding four encoded bits for R16QAM symbol mapping and transmits symbols in a rateless manner. The receiver pre-stores the bit indices corresponding to each symbol in memory. The demodulator organizes the likelihood ratio memory structure of symbol nodes and variable nodes according to the relationship between symbol order and corresponding bits, and performs BP iterative demodulation.

[0143] Figure 6 The cumulative probability distribution curves for successful reception of R16QAM based on the structured bit selector of this invention and the existing best-performing "sequential + random" bit selector are presented. Simulation conditions were as follows: information bit length was 48, after 1 / 3 code rate Turbo coding, the coded bit block length was 144, and the SNR channel variation range was 1–15 dB. At each signal-to-noise ratio (SNR), the cumulative probability of successful demodulation (CDF) was statistically analyzed after 10,000 frames of simulation. As can be seen from the figures, with the increase of SNR, the cumulative probability of successful demodulation of R16QAM based on the structured progressive bit selector of this invention significantly increases compared to the original "sequential + random" bit selector. Specifically, the performance of R16QAM based on the present invention at SNR=4dB is the same as that of the original R16QAM at SNR=5dB, meaning that R16QAM based on the structured progressive bit selector of the present invention can achieve a performance gain of 1dB at approximately SNR=4dB. When SNR=7dB, the performance of R16QAM based on the present invention at SNR=4dB is the same as that of the original R16QAM at SNR=9dB, meaning that R16QAM based on the structured progressive bit selector of the present invention can achieve a performance gain of approximately 2dB at SNR=7dB. Therefore, the R16QAM transmission scheme using the present invention has a higher cumulative probability distribution, i.e., it can achieve more reliable data transmission.

[0144] Figure 7This invention relates to the R16QAM bit selector, comparing the spectral efficiency of existing fully random and "sequential + random" bit selectors with commonly used adaptive coding modulation (LDPC coding at different rates and BPSK, QPSK, 16QAM, 64QAM) and rateless transmission (RCM and TLRCM). All the above schemes used the same experimental conditions: information bit length of 48, a Gaussian channel, and a channel SNR range of -10 to 15 dB. As can be seen from the figure, traditional adaptive coding modulation techniques can only select different code rates and modulation orders within different channel ranges to obtain better transmission rates. Due to the limitations of finite coding rates and modulation orders, adaptive coding modulation can only achieve step-like rate adjustments. Rateless RCM and TLRCM can achieve continuous transmission rates, but RCM uses a high-density constellation, resulting in extremely high demodulation complexity; although TLRCM uses a simple weight set and a low-density constellation, it reaches a saturation rate of approximately 1.7 bits / s / Hz at around 10 dB. R16QAM with three different selectors exhibits higher spectral efficiency than other schemes over a wide channel range. However, the advantage of R16QAM based on existing fully random and "sequential + random" bit selectors gradually diminishes compared to RCM as the signal-to-noise ratio (SNR) increases from 5 to 15 dB, making it difficult to continuously improve. In contrast, R16QAM based on the bit selector of this invention demonstrates significantly higher spectral efficiency than R16QAM based on fully random and "sequential + random" bit selectors at commonly used medium to high SNR (5–15 dB) conditions, and still maintains a significant advantage over RCM. Therefore, the R16QAM of the bit selector of this invention not only maintains good transmission performance under low SNR conditions but also continuously improves spectral efficiency at medium to high SNR conditions, achieving excellent performance gains.

[0145] like Figure 8 As shown in the figure, the implementation framework of the R16QAM structured progressive bit selector system provided in this embodiment of the invention includes: a sequence information bit sub-block generation module 1; a random check bit sub-block generation module 2; a structured candidate sub-block initialization module 3; a structured progressive bit block generation module 4; and a complete bit selector result sequence number storage module 5.

[0146] Sequential information bit sub-block generation module 1 is used to generate N / 4 sequential information bit sub-blocks to realize the sequential selection of N information bits;

[0147] Random parity bit sub-block generation module 2 is used to generate N / 2 random parity bit sub-blocks; to realize the corresponding selection of N parity bits of RSC1 and N parity bits of RSC2;

[0148] The structured candidate sub-block initialization module 3 initializes the candidate sub-blocks of subsequent structured bit blocks by using N / 4 sequential information bit sub-blocks and N / 2 random check bit sub-blocks as the initial values ​​of 3N / 4 candidate sub-blocks.

[0149] The structured progressive bit block generation module 4 is used to generate multiple structured bit blocks of length 3N / 4 with different randomness and the same structure, so as to achieve random and uniform selection of all 3N encoded bits including information bits and parity bits.

[0150] The complete bit selector result sequence number storage module 5 is used to store the address of each bit sequence number selected in the produced bit selector, so as to provide symbol mapping at the R16QAM transmitter and BP demodulation at the receiver.

[0151] like Figure 9 The diagram illustrates the system implementation steps of the R16QAM structured progressive bit selector provided in this embodiment of the invention. Specifically, it includes the following steps:

[0152] S101, Sequential information bit sub-block generation: From an information bit block of length N, select 4 sequential information bits each time to obtain a total of N / 4 sequential information bit sub-blocks;

[0153] S102, Random parity bit sub-block generation: Each time, from the parity bit block of length N obtained from encoder RSC1, 2 parity bits are randomly and non-repeatedly selected, and then 2 parity bits at corresponding positions are selected from the parity bits of encoder RSC2 to form a parity bit sub-block of length 4; this is repeated N / 2 times in total, and after selecting all 2N parity bits, N / 2 parity bit sub-blocks are obtained;

[0154] S103, Candidate bit sub-block initialization: The obtained N / 4 information bit sub-blocks and N / 2 parity bit sub-blocks are used as the initial values ​​of 3N / 4 candidate sub-blocks;

[0155] S104, Structured bit sub-block generation: Randomly select 4 sub-blocks from the current candidate sub-blocks; then randomly select 1 bit from each selected sub-block to obtain a bit sub-block of length 4; then remove the selected bit index from the corresponding sub-block; if all four bits of a sub-block are removed, then remove the sub-block from the current candidate sub-blocks.

[0156] S105, Structured bit block generation: Repeat step 4 for a total of 3N / 4 times, and combine the 3N / 4 structured bit sub-blocks of length 4 into a structured bit block.

[0157] S106, Progressive structured sub-block generation: Repeat steps 3-5 continuously to obtain subsequent progressive structured bit blocks until the total number of bit sub-blocks generated is equal to the maximum number of transmitted symbols M;

[0158] In step S107, the bit indices of N / 4 sequential information bit sub-blocks, N / 2 random parity bit sub-blocks, and all subsequently generated structured asymptotic bit sub-blocks are recorded and stored in the memories of both the transmitting and receiving ends. Once transmission begins, the transmitting end sequentially reads four bit indices from memory each time, selects the corresponding four bits from the encoded bit block, maps them to R16QAM constellation points, and transmits them in a rateless manner. The receiving end, based on the relationship between the received symbol indices and corresponding bits in memory, performs iterative demodulation and decoding using the BP method.

[0159] In the above embodiments, the structured high spectral efficiency R16QAM bit selector designed in this invention can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When all or part of the functionality is implemented in the form of a computer program product, the computer program product contains one or more computer instructions. When these computer instructions are loaded or executed on a computer, all or part of the bit selection process and transmission performance improvement effect conforming to the embodiments of this invention will be generated. The computer here can be a general-purpose computer, a dedicated communication device, a computer network, or other programmable communication processing device. The computer instructions can be stored in a computer-readable storage medium and can be transferred from one computer-readable storage medium to another, for example, from a communication node, computer, server, or data center via wired means (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless means (such as infrared, wireless, microwave, etc.). Computer-readable storage media can be any available medium that a computer can access, or it can be a data storage device such as a server or data center that integrates one or more available media. Available media include magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media (such as DVDs), or semiconductor media (such as solid-state drives (SSDs)).

[0160] The structured bit selector of this invention is not only applicable to R16QAM modulation in IoT uplink communication, but also to other rateless modulation wireless communication systems using Turbo coding, especially showing significant advantages in commonly used mid-to-high signal-to-noise ratio wireless channel conditions (5-15dB). Compared to the original R16QAM's "sequential + random" bit selection strategy, the structured design of this invention, through innovative bit selection logic, allows progressively transmitted symbols to simultaneously utilize the check bits of the Turbo decoder's RSC1 and RSC2. Only the selection strategy of the bit selector needs to be changed, without any changes to the existing R16QAM transmitter and receiver processing. In the original strategy, uniform bit selection cannot be guaranteed during progressive transmission, while the structured bit selector of this invention can precisely control the uniformity of bit selection. In continuous transmission symbols under mid-to-high channel conditions, it can simultaneously utilize the check bits of the Turbo code dual-component encoder, improving error correction capability and transmission reliability. Meanwhile, all symbols and their corresponding bit numbers can be viewed as a mapping matrix. This invention can quickly generate a large number of mapping matrices with good structure and randomness. While maintaining good transmission performance, the transmitting and receiving sides can also perform online replacement as needed, making R16QAM based on the structured bit selector of this invention highly flexible and adaptable.

[0161] The technical or experimental effects being compared. This includes:

[0162] Tables 1 and 2 present the technical characteristics and spectral efficiency comparison results of NB-IoT repetitive transmission, rateless RCM, TLRCM, and R16QAM including the three bit selectors of this invention, respectively.

[0163] Table 1 shows that, to achieve reliable transmission within a wide dynamic channel range, the NB-IoT standard employs a strategy of 1 / 3 code rate Turbo coding + QPSK / BPSK modulation with repeated transmissions. While this reduces receiver demodulation complexity, the repeated doubling of retransmissions at low signal-to-noise ratios leads to wasted transmission energy. The original RCM uses a weight set of {±1, ±2, ±4, ±4} and a rateless transmission method, achieving high spectral efficiency over a wide channel range. However, its large weight values ​​and numerous weight elements result in extremely high demodulation complexity. To reduce implementation complexity, TLRCM uses a minimum weight set of {±1}, but its maximum spectral efficiency is limited. Since R16QAM uses a 16QAM constellation with a radio symbol entropy of 4 bits / s, it can effectively improve spectral efficiency while maintaining the same implementation complexity as TLRCM.

[0164] Table 1. Comparison of the characteristics of several IoT transmission technologies and R16QAM with different bit selectors.

[0165] technology Bit selector Transmission method Spectral efficiency Complexity NB-IoT BPSK order Repeated transmission lowest Low NB-IoT QPSK order Repeated transmission Low Low RCM Fully random selection No-rate transmission higher high TLRCM Fully random selection No-rate transmission lower Low R16QAM[1] Fully random selection No-rate transmission higher Low R16QAM[2] Sequential + Random No-rate transmission high Low R16QAM[3] Structured order + random No-rate transmission Highest Low

[0166] The transmission performance of R16QAM is closely related to its bit selector. Table 2 shows the spectral efficiency comparison of R16QAM with RCM and TLRCM with different bit selectors. Among them, R16QAM[1] is a fully random bit selector, R16QAM[2] is a "sequential + random" bit selector, and R16QAM[3] is the structured progressive bit selector proposed in this invention.

[0167] Table 2 Comparison of spectral efficiency of R16QAM, RCM, and TLRCM with different bit selectors (unit: bits / s / Hz)

[0168]

[0169]

[0170] Table 2 shows that although TLRCM significantly improves spectral efficiency in the low-to-mid channel range (-10 to 8 dB) compared to RCM, it approaches its maximum saturation rate of 1.7 bits / s / Hz when the signal-to-noise ratio (SNR) is 10 dB. In contrast, R16QAM, employing a higher-density 16QAM constellation, maintains high spectral efficiency not only in the low-to-mid channel range (-10 to 8 dB) but also achieves further improvements in the mid-to-high channel range (5 to 15 dB). However, the specific performance of R16QAM in the mid-to-high channel range is closely related to the bit selector. When SNR = 11dB, the spectral efficiency of R16QAM[1] based on a fully random bit selector is 2.717 bits / s / Hz, the spectral efficiency of R16QAM[2] based on a "sequential + random" bit selector is 2.727 bits / s / Hz, and the spectral efficiency of R16QAM[3] based on the structured progressive bit selector of this invention is 3.408 bits / s / Hz. Compared with the two existing R16QAM[1,2] based on traditional bit selectors, the spectral efficiency of R16QAM[3] based on the bit selector of this invention increases by 0.691 and 0.681 bits / s / Hz respectively at 11dB. When SNR = 15dB, the spectral efficiency of R16QAM based on the bit selector of this invention can reach 3.99 bits / s / Hz, while the maximum spectral efficiencies of R16QAM[1,2] based on traditional bit selectors are 3.373 and 3.935 bits / s / Hz respectively.

[0171] In summary, compared to the limited and discrete repetitive transmissions of NB-IoT, the small weight set TLRCM, and the traditional "sequential + random" bit selector R16QAM, the R16QAM based on the structured progressive bit selector of this invention can fully utilize the error correction potential of Turbo codes without increasing implementation complexity, effectively improve the spectral efficiency under practical medium-to-high channel conditions, improve the transmission performance of R16QAM, and effectively reduce the number of transmitted symbols, reduce transmission time, expand system capacity, and extend the lifespan of IoT devices over a wider channel range.

[0172] Adaptive transmission has always been one of the core directions of wireless communication development due to its ability to effectively improve transmission rates. Rateless transmission is a novel adaptive wireless communication technology. As a lightweight rateless transmission technology that can effectively improve spectral efficiency over a wide channel range, the R16QAM technology based on the structured bit selector of this invention has broad application prospects, and its specific application areas are as follows:

[0173] Wireless Sensor Networks: Nodes in wireless sensor networks are typically energy-constrained, and channel quality is unstable. Traditional retransmission mechanisms are energy-intensive. The R16QAM rateless coding based on the structured bit selector of this invention can further reduce the number of transmission symbols compared to traditional R16QAM, significantly reducing energy consumption, extending network lifetime, increasing transmission rate, improving system capacity, and enhancing network coverage. Specifically, the R16QAM of the structured bit selector of this invention can continuously improve spectral efficiency and transmission reliability over a large channel dynamic range, and its "rateless" characteristic perfectly matches the massive device connections and diverse channel conditions in massive IoT, enabling nodes with different coverage requirements to achieve reliable communication with as few transmission symbols as possible. Applications of this invention in the field of wireless sensor networks include, but are not limited to: high-reliability, low-latency industrial IoT communication; UAV network communication with high dynamic topology and fluctuating link quality; and high-capacity, wide-coverage IoT communication networks.

[0174] Satellite and Deep Space Communication: Satellite and deep space communication often faces problems such as ultra-long latency, high bit error rate, and signal interruption caused by frequent signal blockage due to satellite movement. Based on the R16QAM technology of the structured bit selector of this invention, the four bits selected by the structured bit selector are mapped to R16QAM constellation symbols each time, and the encoded symbols are continuously transmitted in a rateless manner until the ground station successfully decodes them. Compared with traditional satellite communication systems based on LDPC+PSK / QAM modulation, such as DVB-S2 (Digital Video Broadcasting Standard), this invention can significantly improve the transmission rate, enhance transmission reliability, and reduce transmission power consumption, making it very suitable for dealing with long latency and sudden interruptions in deep space communication.

[0175] Emergency and Extreme Environment Communication: In extreme environments such as disaster relief, power-limited transmission, and strong interference, the probability of communication link interruption is high as channel conditions deteriorate. The R16QAM rateless transmission technology based on the bit selector of this invention can effectively reduce symbol transmission volume, save transmission energy, and improve data transmission reliability under extremely low channel conditions (-10dB and below), ensuring a higher probability of successful communication under extreme conditions. It can be used for emergency communication in disaster relief, communication support in complex electromagnetic environments, and geological exploration, among other harsh field environments.

[0176] Future mobile communication systems, such as 5G / 6G, place extremely high demands on transmission reliability and latency, while also requiring support for massive connectivity. The R16QAM rateless transmission system based on the structured bit selector of this invention can flexibly adjust the code length, and its transmission performance is independent of the code length. It maintains excellent transmission reliability even at low code lengths (N=48, or even lower). Its low-complexity logarithmic demodulation ensures extremely low latency. Therefore, the R16QAM structured bit selector of this invention is also very suitable for the broadcast / multicast service requirements of future mobile communications such as 6G and Vehicle-to-Everything (V2X).

[0177] The high-spectrum-efficiency structured bit selector of this invention was not only verified through software simulation, but also tested in practice using two Pluto SDR software radio platforms (one for transmitting and one for receiving) from Analog Devices (ADI) to test R16QAM transmission systems based on the structured and "sequential + random" bit selectors designed in this invention. Before testing, the bit address sequences of the structured bit selector generated by this invention and the traditional "sequential + random" bit selector were stored in files on the transceiver computers for use by the transmitting end for bit selection and by the receiving end for demodulation. During testing, by adjusting the transmit power and changing the signal-to-noise ratio range, the receiving end performed rateless belief propagation demodulation-decoding.

[0178] When testing bit block length N = 48 and symbol numbers M of 24, 36, 72, 144, and 288, the symbol signal-to-noise ratio (SNR) varied from -10 to 10 dB. Each SNR was used to transmit 100,000 bit blocks, and the bit error rate (BER) and block error rate (BRR) were then calculated. The specific comparison results of BER and BRR are as follows: Figure 10 , 11 As shown.

[0179] The results show that the R16QAM based on the structured progressive bit selector of this invention significantly improves the bit error rate and block error rate in the channel range of -10 to 15 dB. Specifically, as the signal-to-noise ratio increases, the symbol information entropy increases, and the number of transmitted symbols required for successful demodulation-decoding decreases. When the information block length N = 48 and the number of transmitted R16QAM symbols M = 24 (i.e., the transmission rate is 2 bits / s / Hz), the bit error rate is 10... -4 At the same time, the bit error rate of R16QAM based on the bit selector of this invention has a performance gain of more than 2dB compared with the traditional "sequential + random" bit selector R16QAM, and the block error rate also shows similar performance. The reason is that the structured bit selector of this invention not only ensures that the bits corresponding to the asymptotic transmission symbols have good randomness in the mid-to-high-end channel range, but also utilizes the check bits of the two recursive system convolutional (RSC) encoders RSC1 and RSC2 of the Turbo code, effectively improving the error correction capability of the Turbo code at the R16QAM receiver. This effectively improves the transmission reliability of the R16QAM system in the mid-to-high-end channel range. When the signal-to-noise ratio is low, the subsequent structured asymptotic bit selection can ensure the randomness and uniformity of bit selection, thus improving the transmission reliability under low signal-to-noise ratio conditions.

[0180] Furthermore, we tested the spectral efficiency of the R16QAM bit selector of this invention. The test scheme was as follows: bit block length N = 48, symbol signal-to-noise ratio (SNR) varied from -10 to 10 dB. Once the number of received symbols reached the symbol threshold corresponding to the current SNR, demodulation and decoding were attempted. If demodulation-decoding failed, incremental symbol demodulation-decoding was continued until successful decoding. The spectral efficiency was calculated after 10,000 bit blocks were successfully transmitted at each SNR, and the results are as follows: Figure 12 As shown.

[0181] like Figure 12 The spectral efficiency performance curves shown indicate that, across the entire large dynamic channel variation range of -10 to 15 dB, the spectral efficiency of the R16QAM based on this invention is improved compared to the R16QAM based on a "sequential + random" bit selector. Particularly in the commonly used medium-to-high signal-to-noise ratio range (5–15 dB), the spectral efficiency improvement of this invention is significant, effectively reducing the number of transmitted symbols and significantly saving transmission energy consumption.

[0182] Figure 13The figure visually demonstrates the spectral efficiency improvement of R16QAM based on the bit selector of this invention compared to R16QAM of the "sequential + random" bit selector over a wide channel range (-10dB to 15dB). As shown in the figure, the spectral efficiency of R16QAM of the structured progressive bit selector of this invention is superior to the current best-performing "sequential + random" bit selector R16QAM across the entire channel variation range (-10 to 15dB). In particular, the spectral efficiency improvement of R16QAM is significant in the commonly used mid-to-high-band wireless channel range (5 to 15dB), with a maximum improvement of approximately 0.7 bits / s / Hz at 11dB, representing a 25% improvement in spectral efficiency.

[0183] In summary, both the test results for transmission reliability (bit error rate and block error rate) and spectral efficiency demonstrate that R16QAM based on the structured bit selector of this invention is significantly improved compared to R16QAM based on the existing "sequential + random" bit selector. In particular, the transmission performance of this invention is significantly improved in the commonly used medium to high signal-to-noise ratio range (5 to 15 dB).

[0184] like Figure 14 A comparison chart of the R16QAM spectral efficiency of the bit selector of this invention.

[0185] like Figure 15 The graph shows the percentage improvement in spectral efficiency of the bit selector in this invention using the R16QAM method.

[0186] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.

[0187] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A selection method for a high-spectral-efficiency R16QAM structured bit selector, characterized in that, The method comprises the following steps: Step 1, sequential information bit sub-blocks; Step 2, random check bit sub-blocks; Step 3, candidate bit sub-block initialization; Step 4, structured bit sub-block generation; Step 5, structured bit block generation; Step 6, structured progressive bit sub-block generation; Steps 3 to 5 are repeatedly performed to progressively generate a plurality of different structured bit blocks, so that the total number of bit sub-blocks is equal to the maximum number of transmission symbols M; Step 7, bit sequence numbers of the N / 4 sequential information bit sub-blocks, the N / 2 random check bit sub-blocks and all the subsequently generated structured progressive bit sub-blocks are recorded and stored in the memory of the sending end and the receiving end; After the transmission starts, the sending end sequentially reads the 4 bit sequence numbers in the memory, selects the corresponding 4 bits in the encoding bit block and maps them to the R16 QAM constellation point, and transmits in a rateless manner; the receiving end uses the BP method to complete iterative demodulation and decoding based on the relationship between the received symbol sequence number and the corresponding bit in the memory; The random check bit sub-block is randomly and non-repeatedly selected from 2 check bits in a check bit block with a length of N obtained from the encoder RSC1, and 2 check bits in a corresponding position check bit block obtained from the encoder RSC2, to form a random check bit sub-block with a length of 4, and a total of N / 2 random check bit sub-blocks are obtained; During the initialization of the candidate bit sub-block, the N / 4 sequential information bit sub-blocks and the N / 2 random check bit sub-blocks are taken together as 3N / 4 initial candidate bit sub-blocks; During the generation of the structured bit sub-block, 4 sub-blocks are randomly selected from the current candidate sub-block, and 1 bit is randomly selected from the 4 sub-blocks to form a bit sub-block with a length of 4; and the selected bit sequence number is removed from the corresponding candidate sub-block; when all the bits in the candidate sub-block are removed, the candidate sub-block is removed; The structured bit block generation is performed by repeatedly executing the structured bit sub-block generation 3N / 4 times to obtain 3N / 4 structured bit sub-blocks with a length of 4, which are combined to form a structured bit block; and the process is repeatedly performed to progressively generate a plurality of different structured bit blocks until the total number of sub-blocks is equal to the maximum number of symbols M.

2. The method of claim 1, wherein, The sequential information bit sub-block is sequentially selected from 4 information bits in an information bit block with a length of N, and a total of N / 4 sequential information bit sub-blocks with a length of 4 are obtained.

3. A selection system of a high spectral efficiency R16 QAM structured bit selector using the selection method of any one of claims 1-2, characterized in that, It comprises: a sequential module for generating sequential information bit sub-blocks; a random check module for generating random check bit sub-blocks; an initialization module for completing candidate bit sub-block initialization; a bit sub-block generation module for performing structured bit sub-block generation; a bit block generation module for performing structured bit block generation; and a progressive bit block generation module for performing structured progressive bit sub-block generation; a demodulation and decoding module for storing and managing bit sequence numbers and realizing iterative demodulation and decoding based on the relationship between the received symbol and the bit.

4. The system of claim 3, wherein, The sequential module sequentially selects 4 bits from an information bit block with a length of N to generate N / 4 sequential information bit sub-blocks with a length of 4.

5. The system of claim 3, wherein, The random check module is used for randomly and repeatedly selecting 2 check bits in the RSC1 encoder output, and selecting 2 check bits in the corresponding position of the RSC2 encoder output, to generate a random check bit sub-block with a length of 4, and a total of N / 2.

6. The system of claim 3, wherein, The demodulation and decoding module is used for sequentially reading the bit sequence number in the memory at the sending end, mapping the corresponding bit to the R16 QAM constellation point and transmitting, and using the bit sequence number recorded in the memory and the symbol sequence number relationship at the receiving end, combining the BP method to complete the iterative demodulation and decoding.

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