Light-emitting element, display device, method of manufacturing display device, and electronic device

Abstract

Disclosed are a light emitting element, a display device, a method of manufacturing the display device, and an electronic device. The light emitting element may include: a first light emitting unit in a first pixel region; a second light emitting unit on the first light emitting unit in the first pixel region; and a third light emitting unit in a second pixel region spaced and / or separated (or spaced or separated) from the first pixel region in a plan view. The first light emitting unit may be to emit a first light. The second light emitting unit may be to emit second light having a wavelength that may be different from a wavelength of the first light. The third light emitting unit may be to emit third light having a wavelength that may be different from each of the wavelength of the first light and the wavelength of the second light.

Description

Technical Field

[0001] One or more embodiments of this disclosure relate to a light-emitting element, a display device including a light-emitting element, a method of manufacturing a display device, and an electronic device including a display device. One or more embodiments of this disclosure relate to a light-emitting element including a semiconductor layer, a display device including a light-emitting element, a method of manufacturing a display device, and an electronic device including a display device. Background Technology

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become apparent. For example, the use of display devices such as liquid crystal displays, organic light-emitting displays, plasma displays, and / or micro light-emitting diode (LED) displays is increasing.

[0003] Miniature LED display devices may include inorganic light-emitting elements. Inorganic light-emitting elements are semiconductor light-emitting elements that convert electric current into light and have relatively high light conversion efficiency. In addition, inorganic light-emitting elements are relatively semi-permanent (e.g., having a long lifespan and / or high durability) and / or environmentally friendly, with low energy consumption. Summary of the Invention

[0004] One or more aspects of embodiments of this disclosure relate to a light-emitting element produced by (utilizing) a manufacturing process that is appropriately simplified or modified.

[0005] One or more aspects of embodiments of this disclosure relate to a display device including a light-emitting element.

[0006] One or more aspects of embodiments of this disclosure relate to a method of manufacturing a display device.

[0007] One or more aspects of embodiments of this disclosure relate to an electronic device including a display device.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be taught by practicing the embodiments presented in this disclosure.

[0009] A light-emitting element according to one or more embodiments may include: a first light-emitting unit disposed (or provided) in a first pixel region; a second light-emitting unit disposed (or provided) on the first light-emitting unit in the first pixel region; and a third light-emitting unit disposed (or provided) in a second pixel region, the second pixel region being spaced apart from the first pixel region in a plan view.

[0010] In one or more embodiments, the first light-emitting unit may be used to emit first light.

[0011] In one or more embodiments, the second light-emitting unit can be used to emit a second light having a wavelength different from that of the first light.

[0012] In one or more embodiments, the third light-emitting unit can be used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

[0013] In one or more embodiments, the third light-emitting unit may be arranged (or provided) on the first light-emitting unit.

[0014] In one or more embodiments, the light-emitting element may further include: a fourth light-emitting unit disposed (or provided) in the second pixel region, the fourth light-emitting unit being disposed (or provided) below the third light-emitting unit and emitting the first light.

[0015] In one or more embodiments, the first light-emitting unit may include a first semiconductor layer 1-1, a first active layer disposed (or provided) on the first semiconductor layer 1-1, and a first semiconductor layer 1-2 disposed (or provided) on the first active layer.

[0016] In one or more embodiments, the second light-emitting unit may include a second-1 semiconductor layer, a second active layer disposed on the second-1 semiconductor layer, and a second-2 semiconductor layer disposed on the second active layer.

[0017] In one or more embodiments, each of the first-1 semiconductor layer and the second-2 semiconductor layer may include a negative (n-type or n-class) semiconductor layer.

[0018] In one or more embodiments, each of the first-2 semiconductor layers and the second-1 semiconductor layer may include a positive (p-type or p-class) semiconductor layer.

[0019] In one or more embodiments, the light-emitting element may further include connection electrodes electrically connected to (or coupled to) each of the first-2 semiconductor layers and the second-1 semiconductor layer.

[0020] A light-emitting element according to one or more embodiments may include: a first light-emitting unit disposed (or provided) in a first pixel region and emitting first light; a second light-emitting unit disposed (or provided) on the first light-emitting unit in the first pixel region and emitting second light having a wavelength different from the wavelength of the first light; and a third light-emitting unit disposed (or provided) in a second pixel region and emitting third light having a wavelength different from each of the wavelength of the first light and the wavelength of the second light, the second pixel region being spaced apart from the first pixel region in a plan view.

[0021] In one or more embodiments, the first light-emitting unit may include: a first semiconductor layer, including an n-type semiconductor layer; a first active layer disposed on (or provided on) the first semiconductor layer; and a first semiconductor layer, disposed on (or provided on) the first active layer and including a p-type semiconductor layer.

[0022] In one or more embodiments, the second light-emitting unit may include: a second-1 semiconductor layer, including a p-type semiconductor layer; a second active layer disposed on (or provided on) the second-1 semiconductor layer; and a second-2 semiconductor layer disposed on (or provided on) the second active layer and including an n-type semiconductor layer.

[0023] In one or more embodiments, the third light-emitting unit may include: a third-1 semiconductor layer, including a p-type semiconductor layer; a third active layer disposed on (or provided on) the third-1 semiconductor layer; and a third-2 semiconductor layer disposed on (or provided on) the third active layer and including an n-type semiconductor layer.

[0024] In one or more embodiments, the third light-emitting unit may be arranged (or provided) on the first light-emitting unit.

[0025] In one or more embodiments, the light-emitting element may further include connection electrodes electrically connected to (or coupled to) each of the first-2 semiconductor layers and the second-1 semiconductor layer.

[0026] In one or more embodiments, the light-emitting element may further include: a fourth light-emitting unit disposed (or provided) in the second pixel region, the fourth light-emitting unit being disposed (or provided) below the third light-emitting unit and emitting the first light.

[0027] In one or more embodiments, the fourth light-emitting unit may include: a fourth-1 semiconductor layer, including an n-type semiconductor layer; a fourth active layer disposed on (or provided on) the fourth-1 semiconductor layer; and a fourth-2 semiconductor layer disposed on (or provided on) the fourth active layer and including a p-type semiconductor layer.

[0028] In one or more embodiments, the first light-emitting unit may be arranged (or provided) continuously (e.g., substantially continuously) throughout the first pixel region and the second pixel region.

[0029] A light-emitting element according to one or more embodiments may include: a first light-emitting unit disposed (or provided) in a first pixel region and emitting first light; a second light-emitting unit disposed (or provided) on the first light-emitting unit in the first pixel region and emitting second light having a wavelength different from the wavelength of the first light; and a third light-emitting unit disposed (or provided) in a second pixel region and emitting third light having a wavelength different from each of the wavelength of the first light and the wavelength of the second light, the second pixel region being spaced apart from the first pixel region in a plan view.

[0030] In one or more embodiments, the first light-emitting unit may include: a first semiconductor layer, including a p-type semiconductor layer; a first active layer disposed on (or provided on) the first semiconductor layer; and a first semiconductor layer, disposed on (or provided on) the first active layer and including an n-type semiconductor layer.

[0031] In one or more embodiments, the second light-emitting unit may include: a second-1 semiconductor layer, including an n-type semiconductor layer; a second active layer disposed on (or provided on) the second-1 semiconductor layer; and a second-2 semiconductor layer disposed on (or provided on) the second active layer and including a p-type semiconductor layer.

[0032] In one or more embodiments, the third light-emitting unit may include: a third-1 semiconductor layer, including an n-type semiconductor layer; a third active layer disposed on (or provided on) the third-1 semiconductor layer; and a third-2 semiconductor layer disposed on (or provided on) the third active layer and including a p-type semiconductor layer.

[0033] In one or more embodiments, the third light-emitting unit may be arranged (or provided) on the first light-emitting unit.

[0034] In one or more embodiments, the light-emitting element may further include connection electrodes electrically connected to (or coupled to) each of the first-2 semiconductor layers and the second-1 semiconductor layer.

[0035] In one or more embodiments, the light-emitting element may further include: a fourth light-emitting unit disposed (or provided) in the second pixel region, the fourth light-emitting unit being disposed (or provided) below the third light-emitting unit and emitting the first light.

[0036] In one or more embodiments, the fourth light-emitting unit may include: a fourth-1 semiconductor layer, including a p-type semiconductor layer; a fourth active layer disposed on (or provided on) the fourth-1 semiconductor layer; and a fourth-2 semiconductor layer disposed on (or provided on) the fourth active layer and including an n-type semiconductor layer.

[0037] A display device according to one or more embodiments may include a circuit board and light-emitting elements disposed (or provided) on the circuit board.

[0038] In one or more embodiments, the light-emitting element may include: a first light-emitting unit disposed (or provided) in a first pixel region; a second light-emitting unit disposed (or provided) on the first light-emitting unit in the first pixel region; and a third light-emitting unit disposed (or provided) in a second pixel region, the second pixel region being spaced apart from the first pixel region in a plan view.

[0039] In one or more embodiments, the first light-emitting unit may be used to emit first light.

[0040] In one or more embodiments, the second light-emitting unit can be used to emit a second light having a wavelength different from that of the first light.

[0041] In one or more embodiments, the third light-emitting unit can be used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

[0042] In one or more embodiments, the third light-emitting unit may be arranged (or provided) on the first light-emitting unit.

[0043] In one or more embodiments, the first light-emitting unit may include a first semiconductor layer 1-1, a first active layer disposed (or provided) on the first semiconductor layer 1-1, and a first semiconductor layer 1-2 disposed (or provided) on the first active layer.

[0044] In one or more embodiments, the second light-emitting unit may include a second-1 semiconductor layer, a second active layer disposed on the second-1 semiconductor layer, and a second-2 semiconductor layer disposed on the second active layer.

[0045] In one or more embodiments, each of the first-1 semiconductor layer and the second-2 semiconductor layer may include an n-type semiconductor layer.

[0046] In one or more embodiments, each of the first-2 semiconductor layer and the second-1 semiconductor layer may include a p-type semiconductor layer.

[0047] In one or more embodiments, the circuit board may include a first electrode, a second electrode, and a third electrode.

[0048] In one or more embodiments, the first-2 semiconductor layer and the second-1 semiconductor layer may be electrically connected to (or coupled to) the first electrode.

[0049] In one or more embodiments, the first semiconductor layer may be electrically connected to (or coupled to) the second electrode.

[0050] In one or more embodiments, the second-second semiconductor layer may be electrically connected to (or coupled to) the third electrode.

[0051] In one or more embodiments, the second-second semiconductor layer may be electrically connected to (or coupled to) the third electrode via a connection electrode that penetrates at least a portion of each of the first and second light-emitting units.

[0052] A method of manufacturing a display device may include: forming a first light-emitting unit disposed (or provided) in a first pixel region on a circuit board; forming a second light-emitting unit disposed (or provided) in the first pixel region on a first growth substrate; forming a third light-emitting unit disposed (or provided) in the second pixel region on the first growth substrate, the second pixel region being spaced apart from the first pixel region in a plan view; and attaching the second light-emitting unit and the third light-emitting unit to the first light-emitting unit.

[0053] In one or more embodiments, the first light-emitting unit may be used to emit first light.

[0054] In one or more embodiments, the second light-emitting unit can be used to emit a second light having a wavelength different from that of the first light.

[0055] In one or more embodiments, the third emitting unit can be used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

[0056] In one or more embodiments, forming the first light-emitting unit may include: forming a first semiconductor layer on a second growth substrate; forming an active layer on the first semiconductor layer; forming a second semiconductor layer on the active layer; removing the second growth substrate; and removing portions of the first semiconductor layer, the active layer, and the second semiconductor layer that do not overlap with the first pixel region in the plan view on the circuit board.

[0057] In one or more embodiments, the method may further include: forming a first connection electrode that penetrates at least a portion of the first light-emitting unit and is electrically connected to (or coupled to) an electrode included in the circuit board; and forming a second connection electrode that penetrates at least a portion of the second light-emitting unit and is electrically connected to (or coupled to) the first connection electrode.

[0058] In one or more embodiments, forming the second light-emitting unit may include: forming a pre-insulating (e.g., electrically insulating) layer on the first growth substrate; forming an insulating (e.g., electrically insulating) layer by removing a portion of the pre-insulating (e.g., electrically insulating) layer that overlaps with the first pixel region and the second pixel region; forming a first semiconductor layer on the first growth substrate in the first pixel region; forming an active layer on the first semiconductor layer; and forming a second semiconductor layer on the active layer.

[0059] In one or more embodiments, the second semiconductor layer may be electrically connected to (or coupled to) the second connection electrode.

[0060] An electronic device according to one or more embodiments may include: a circuit board; a light-emitting element disposed on (or provided) the circuit board; and a memory device configured to store data.

[0061] In one or more embodiments, the light-emitting element may include: a first light-emitting unit disposed (or provided) in a first pixel region; a second light-emitting unit disposed (or provided) on the first light-emitting unit in the first pixel region; and a third light-emitting unit disposed (or provided) in a second pixel region, the second pixel region being spaced apart from the first pixel region in a plan view.

[0062] In one or more embodiments, the first light-emitting unit may be used to emit first light.

[0063] In one or more embodiments, the second light-emitting unit can be used to emit a second light having a wavelength different from that of the first light.

[0064] In one or more embodiments, the third light-emitting unit can be used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

[0065] A display device according to one or more embodiments may include a circuit board and light-emitting elements. The light-emitting elements may include: a first light-emitting unit disposed (or provided) in a first pixel region; a second light-emitting unit disposed (or provided) on the first light-emitting unit in the first pixel region; and a third light-emitting unit disposed (or provided) in a second pixel region, the second pixel region being spaced apart from the first pixel region in a plan view. The first light-emitting unit may be used to emit a first light. The second light-emitting unit may be used to emit a second light having a wavelength different from the wavelength of the first light. The third light-emitting unit may be used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

[0066] A method of manufacturing the display device may include: forming (or providing) a first light-emitting unit disposed in a first pixel region on the circuit board; forming (or providing) a second light-emitting unit disposed in the first pixel region on a first growth substrate; forming (or providing) a third light-emitting unit disposed in the second pixel region on the first growth substrate, the second pixel region being spaced apart from the first pixel region in a plan view; and attaching the second light-emitting unit and the third light-emitting unit to the first light-emitting unit. The first light-emitting unit may be used to emit a first light. The second light-emitting unit may be used to emit a second light having a wavelength different from the wavelength of the first light. The third light-emitting unit may be used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

[0067] For example, a display device that realizes a full-color system of red, green, and blue (RGB) can be manufactured by a single bonding process that attaches the second and third light-emitting units to the first light-emitting unit. Therefore, the manufacturing process of the display device can be appropriately simplified or modified. Attached Figure Description

[0068] Exemplary, non-limiting embodiments of this disclosure will become clearer from the following more detailed description taken in conjunction with the accompanying drawings.

[0069] Figure 1 This is a plan view illustrating a display device according to one or more embodiments.

[0070] Figure 2 This shows the section taken along line I-II. Figure 1 A cross-sectional view of the display device.

[0071] Figure 3 It is shown that it includes Figure 2 A cross-sectional view of the light-emitting element in a display device.

[0072] Figure 4 It is shown that it includes Figure 1 A plan view of the display area in a display device.

[0073] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 and Figure 33 It shows the manufacturing process. Figure 2 A cross-sectional view of the method for displaying the device.

[0074] Figure 34 This is a cross-sectional view showing a display device according to one or more embodiments.

[0075] Figure 35 This is a cross-sectional view showing a display device according to one or more embodiments.

[0076] Figure 36 This is a block diagram illustrating an electronic device according to an embodiment.

[0077] Figure 37 It is shown Figure 36 The diagram shows an example of an electronic device implemented as a smartphone. Detailed Implementation

[0078] In the following, a display device according to one or more embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for substantially the same components in the drawings, and redundant descriptions of substantially the same components will not be provided.

[0079] Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the (described)” as used herein are intended to include the plural forms as well. Furthermore, the use of “may” in describing embodiments of this disclosure refers to “one or more embodiments of this disclosure.”

[0080] In the context of this disclosure and unless otherwise defined, the term “use (use, using, and used)” may be considered synonymous with the term “utilize (utilizing, utilizing, and utilized)”, respectively.

[0081] It will be understood that although the terms “first,” “second,” and / or “third,” etc., may be used herein to describe one or more elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, area, layer, or portion described below may be referred to as the second element, component, area, layer, or portion.

[0082] For ease of explanation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature as shown in the figures and another (or more) elements or features. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “below” or “below” other elements or features will be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0083] It will be understood that if an element or layer is referred to as being "on" another element or layer, "connected to," or "coupled to" another element or layer (e.g., when an element or layer is referred to as being "on" another element or layer, "connected to," or "coupled to" another element or layer), the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediary elements or layers may be present. Additionally, it will be understood that if an element or layer is referred to as being "between" two elements or layers (e.g., when an element or layer is referred to as being "between" two elements or layers), the element or layer may be the only element or layer between the two elements or layers, or one or more intermediary elements or layers may be present.

[0084] Throughout this specification, the terms “comprising” or “having” are intended to indicate the presence of the stated features, integrals, steps, operations, constituent elements, components, and / or combinations thereof (e.g., any suitable combinations thereof), but do not exclude the presence or addition of one or more other features, integrals, steps, operations, constituent elements, components, and / or groups thereof. Therefore, unless expressly stated otherwise, the terms “comprising” and variations such as “including” or “containing” will be understood to imply the inclusion of the stated elements, but do not exclude any other suitable elements.

[0085] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire column of elements when they precede or follow the column of elements, rather than modifying individual elements of the column.

[0086] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have substantially the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in general dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense.

[0087] Figure 1 This is a plan view illustrating a display device according to one or more embodiments.

[0088] refer to Figure 1 The display device DD according to one or more embodiments may include a display area DA and a non-display area NDA.

[0089] Multiple pixel regions can be arranged (or provided) in the display area DA. For example, a first pixel region PX1 and / or a second pixel region PX2 can be arranged (or provided) in the display area DA. Each of the first pixel region PX1 and the second pixel region PX2 can be a source of light emanating from a light-emitting element (e.g., Figure 3 The light emitted by the light-emitting element (LED) is emitted to the area outside the display device DD.

[0090] For example, the first pixel region PX1 may be where the light-emitting unit (e.g., Figure 2 The first light-emitting unit 200) and / or the second light-emitting unit (e.g., Figure 2 The light emitted by the second light-emitting unit 300 is emitted to an area outside the display device DD. For example, the second pixel area PX2 may be a region in which light emitted from the third light-emitting unit (e.g., Figure 2The third light-emitting unit 400) and / or the fourth light-emitting unit (e.g., Figure 2 The light emitted by the fourth light-emitting unit 500 is emitted to the area outside the display device DD.

[0091] Multiple pixel regions may be arranged (or provided) repeatedly along a first direction DR1 and / or a second direction DR2 intersecting the first direction DR1. For example, a second pixel region PX2 may be separated from and / or separated from the first pixel region PX1 in a planar view (e.g., spaced apart or separated). For example, the second pixel region PX2 may be separated from and / or separated from the first pixel region PX1 in the first direction DR1 (e.g., spaced apart or separated).

[0092] A non-display area NDA may be arranged (or provided) around (e.g., surrounding) the display area DA. For example, the non-display area NDA may be around (e.g., surrounding) at least a portion of the display area DA. A driver may be arranged (or provided) in the non-display area NDA. The driver may provide signals and / or voltages to multiple pixel areas. For example, the driver may include data drivers and / or gate drivers, etc. The non-display area NDA may not display an image.

[0093] In one or more embodiments, a first direction DR1 and a second direction DR2 intersecting the first direction DR1 may be defined. For example, the second direction DR2 may be orthogonal to the first direction DR1 (e.g., substantially perpendicular). However, embodiments of the present disclosure are not limited thereto, and the second direction DR2 may form (or provide) an acute or obtuse angle with the first direction DR1. Additionally, a third direction DR3 intersecting the plane formed (or provided) by the first direction DR1 and / or the second direction DR2 may be defined. For example, the third direction DR3 may be orthogonal to (e.g., substantially perpendicular) the plane formed (or provided) by the first direction DR1 and / or the second direction DR2. However, embodiments of the present disclosure are not limited thereto, and the third direction DR3 may form (or provide) an acute or obtuse angle with the plane formed (or provided) by the first direction DR1 and / or the second direction DR2.

[0094] Figure 2 This shows the section taken along line I-II. Figure 1 A cross-sectional view of the display device. Figure 3 It is shown that it includes Figure 2 A cross-sectional view of the light-emitting element in a display device.

[0095] refer to Figure 2 and Figure 3 The display device DD may include a circuit board 100 and / or a light-emitting element (LED).

[0096] The circuit board 100 may include circuit elements for controlling the light-emitting elements LEDs. For example, the circuit board 100 may include circuit elements for controlling each of the first light-emitting unit 200, the second light-emitting unit 300, the third light-emitting unit 400, and the fourth light-emitting unit 500. For example, the circuit board 100 may include thin-film transistor (TFT), P-channel metal-oxide-semiconductor (PMOS), N-channel metal-oxide-semiconductor (NMOS), and / or complementary metal-oxide-semiconductor (CMOS) structures, etc.

[0097] In one or more embodiments, the circuit board 100 may include a first electrode 110, a second electrode 120, a third electrode 130, a fourth electrode 140, and / or a fifth electrode 150. The second electrode 120 may be spaced apart from and / or separated from the first electrode 110 in a first direction DR1 (e.g., spaced apart or separated). The third electrode 130 may be spaced apart from and / or separated from the second electrode 120 in the first direction DR1 (e.g., spaced apart or separated). The fourth electrode 140 may be spaced apart from and / or separated from the third electrode 130 in the first direction DR1 (e.g., spaced apart or separated). The fifth electrode 150 may be spaced apart from and / or separated from the fourth electrode 140 in the first direction DR1 (e.g., spaced apart or separated).

[0098] For example, each of the first electrode 110, the second electrode 120, the third electrode 130, the fourth electrode 140, and the fifth electrode 150 may comprise metals, alloys, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0099] The light-emitting element (LED) can be arranged (or provided) on the circuit board 100. The light-emitting element (LED) may include a first light-emitting unit 200, a second light-emitting unit 300, a third light-emitting unit 400, a fourth light-emitting unit 500, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, a fifth insulating layer IL5, a sixth insulating layer IL6, a first connecting electrode CE1, a second connecting electrode CE2, a third connecting electrode CE3, a fourth connecting electrode CE4, a fifth connecting electrode CE5, a sixth connecting electrode CE6, a seventh connecting electrode CE7, a first conductive layer CL1, a second conductive layer CL2, a third conductive layer CL3, a fourth conductive layer CL4, a first lower metal layer LE1, a second lower metal layer LE2, a first adhesive layer BM1, a second adhesive layer BM2, a first upper metal layer UE1, a second upper metal layer UE2, a third upper metal layer UE3, a fourth upper metal layer UE4, a first side insulating layer SL1, a second side insulating layer SL2, a third side insulating layer SL3 and / or a fourth side insulating layer SL4.

[0100] The first light-emitting unit 200 may be arranged (or provided) on the circuit board 100. The first light-emitting unit 200 may be arranged (or provided) in the first pixel region PX1. For example, the first light-emitting unit 200 may be used to emit first light in the first pixel region PX1. For example, the first light-emitting unit 200 may be used to emit first light to the outside of the display device DD in the first pixel region PX1.

[0101] In one or more embodiments, the first light may be red light. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the first light may have a wavelength different from that of red light. For example, the first light may be green light.

[0102] The first light-emitting unit 200 may include a first-1 semiconductor layer 210, a first active layer 220, and / or a first-2 semiconductor layer 230. For example, the first active layer 220 may be disposed on (or provided on) the first-1 semiconductor layer 210. In addition, the first-2 semiconductor layer 230 may be disposed on (or provided on) the first active layer 220.

[0103] In one or more embodiments, the first-1 semiconductor layer 210 may include a negative (n / N type or n / N class) semiconductor layer. For example, the first-1 semiconductor layer 210 may include semiconductor materials such as gallium nitride (GaN), indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and / or indium nitride (InN), and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., n-type dopant) such as silicon (Si), tin (Sn), tellurium (Te), selenium (Se), sulfur (S), oxygen (O), and / or germanium (Ge). For example, the first-1 semiconductor layer 210 may include a GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the first-1 semiconductor layer 210 may include a positive (p / P type or p / P class) semiconductor layer.

[0104] For example, the first active layer 220 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the first active layer 220 may include a multi-quantum well structure. In one or more embodiments, the first active layer 220 may include a structure in which well layers and barrier layers are alternately stacked. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but embodiments of this disclosure are not limited thereto.

[0105] In one or more embodiments, the first-second semiconductor layer 230 may include a p-type semiconductor layer. For example, the first-second semiconductor layer 230 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant). For example, the first-second semiconductor layer 230 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the first-second semiconductor layer 230 may include an n-type semiconductor layer.

[0106] In one or more embodiments, the first light-emitting unit 200 may have a trapezoidal shape (e.g., substantially trapezoidal shape) in a cross-sectional view. However, embodiments of this disclosure are not limited thereto, and the first light-emitting unit 200 may have a shape different from the trapezoidal shape (e.g., substantially trapezoidal shape) in a cross-sectional view. For example, the first light-emitting unit 200 may have a triangular shape (e.g., substantially triangular shape) in a cross-sectional view.

[0107] In one or more embodiments, a first lower metal layer LE1 may be disposed (or provided) below the first light-emitting unit 200. For example, the first lower metal layer LE1 may be disposed (or provided) below the first-1 semiconductor layer 210. The first lower metal layer LE1 may be disposed (or provided) in the first pixel region PX1.

[0108] For example, the first lower metal layer LE1 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the first lower metal layer LE1 may include indium tin oxide (ITO), indium zinc oxide (IZO), and / or indium gallium oxide (IGO). These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0109] However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the first lower metal layer LE1 may not be provided. In one or more embodiments, the first semiconductor layer 210 may be in direct contact with the first adhesive layer BM1.

[0110] In one or more embodiments, a first adhesive layer BM1 may be disposed (or provided) beneath a first lower metal layer LE1. The first light-emitting unit 200 may be attached to the circuit board 100 via the first adhesive layer BM1. For example, the first lower metal layer LE1 may be attached to the circuit board 100 via the first adhesive layer BM1. For example, the first adhesive layer BM1 may include solder bumps, solder balls, anisotropic conductive (e.g., electrically conductive) films, and / or anisotropic conductive (e.g., electrically conductive) paste, etc.

[0111] However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the first light-emitting unit 200 may be attached to the circuit board 100 by a metal bonding method. For example, a first lower metal layer LE1 may be attached to the circuit board 100 by a metal bonding method. In one or more embodiments, the first metal layer may be additionally disposed (or provided) between the circuit board 100 and the first adhesive layer BM1.

[0112] For example, each of the first adhesive layer BM1 and the first metal layer may include copper (Cu) and / or titanium (Ti), and the first lower metal layer LE1 may be attached to the circuit board 100 by a Cu-Cu bonding method and / or a Ti-Ti bonding method.

[0113] In one or more embodiments, a first upper metal layer UE1 may be disposed (or provided) on the first light-emitting unit 200. For example, the first upper metal layer UE1 may be disposed (or provided) on the first-second semiconductor layer 230. The first upper metal layer UE1 may be disposed (or provided) in the first pixel region PX1.

[0114] For example, the first upper metal layer UE1 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the first upper metal layer UE1 may include ITO, IZO, and / or IGO. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0115] The second light-emitting unit 300 may be arranged (or provided) on the first light-emitting unit 200. For example, the second light-emitting unit 300 may be spaced apart from and / or separated from the first light-emitting unit 200 on a third-direction DR3 (e.g., spaced apart or separated). The second light-emitting unit 300 may be arranged (or provided) in the first pixel region PX1. For example, the second light-emitting unit 300 may be used to emit second light in the first pixel region PX1. For example, the second light-emitting unit 300 may be used to emit second light to the outside of the display device DD in the first pixel region PX1.

[0116] In one or more embodiments, the second light may have a wavelength different from that of the first light emitted from the first light-emitting unit 200. For example, the second light may be blue light. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the second light may have a wavelength different from that of blue light. For example, the second light may be green light.

[0117] The second light-emitting unit 300 may include a second-first semiconductor layer 310, a second active layer 320, and / or a second-second semiconductor layer 330. For example, the second active layer 320 may be disposed on (or provided on) the second-first semiconductor layer 310. In addition, the second-second semiconductor layer 330 may be disposed on (or provided on) the second active layer 320.

[0118] In one or more embodiments, the second-first semiconductor layer 310 may include a p-type semiconductor layer. For example, the second-first semiconductor layer 310 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, the second-first semiconductor layer 310 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the second-first semiconductor layer 310 may include an n-type semiconductor layer.

[0119] For example, the second active layer 320 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the second active layer 320 may include a multi-quantum well structure. In one or more embodiments, the second active layer 320 may include a structure in which well layers and barrier layers are alternately stacked. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but embodiments of this disclosure are not limited thereto.

[0120] In one or more embodiments, the second-2 semiconductor layer 330 may include an n-type semiconductor layer. For example, the second-2 semiconductor layer 330 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, the second-2 semiconductor layer 330 may include a GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the second-2 semiconductor layer 330 may include a p-type semiconductor layer.

[0121] In one or more embodiments, the second light-emitting unit 300 may have a shape that protrudes from the second upper metal layer UE2 toward the circuit board 100. For example, in a cross-sectional view, the second light-emitting unit 300 may have a shape in which rectangles (e.g., substantially rectangular) and triangles (e.g., substantially triangular) are sequentially stacked in a direction opposite to the third direction DR3. However, embodiments of this disclosure are not limited thereto, and the shape of the second light-emitting unit 300 may be appropriately changed or modified.

[0122] In one or more embodiments, a second upper metal layer UE2 may be disposed (or provided) on the second light-emitting unit 300. For example, the second upper metal layer UE2 may be disposed (or provided) on the second-second semiconductor layer 330. The second upper metal layer UE2 may be disposed (or provided) in the first pixel region PX1.

[0123] For example, the second upper metal layer UE2 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the second upper metal layer UE2 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0124] The third light-emitting unit 400 may be arranged (or provided) in the second pixel region PX2. For example, the third light-emitting unit 400 may be spaced apart from and / or separated from the second light-emitting unit 300 in the first direction DR1 (e.g., spaced apart or separated). For example, the third light-emitting unit 400 may be on top of the first light-emitting unit 200 (here, "on top of" may mean "not directly above"). For example, the third light-emitting unit 400 may be used to emit third light from the second pixel region PX2. For example, the third light-emitting unit 400 may be used to emit third light from the second pixel region PX2 toward the outside of the display device DD.

[0125] In one or more embodiments, the third light may have a wavelength different from each of the wavelengths of the first light emitted from the first light-emitting unit 200 and the second light emitted from the second light-emitting unit 300. For example, the third light may be green light. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the third light may have a wavelength different from that of green light. For example, the third light may be blue light.

[0126] The third light-emitting unit 400 may include a third-first semiconductor layer 410, a third active layer 420, and / or a third-second semiconductor layer 430. For example, the third active layer 420 may be disposed on (or provided on) the third-first semiconductor layer 410. Alternatively, the third-second semiconductor layer 430 may be disposed on (or provided on) the third active layer 420.

[0127] In one or more embodiments, the third-first semiconductor layer 410 may include a p-type semiconductor layer. For example, the third-first semiconductor layer 410 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, the third-first semiconductor layer 410 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the third-first semiconductor layer 410 may include an n-type semiconductor layer.

[0128] For example, the third active layer 420 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the third active layer 420 may include a multi-quantum well structure. In one or more embodiments, the third active layer 420 may include a structure in which well layers and barrier layers are alternately stacked. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but embodiments of this disclosure are not limited thereto.

[0129] In one or more embodiments, the third-second semiconductor layer 430 may include an n-type semiconductor layer. For example, the third-second semiconductor layer 430 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, the third-second semiconductor layer 430 may include a GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the third-second semiconductor layer 430 may include a p-type semiconductor layer.

[0130] In one or more embodiments, the third light-emitting unit 400 may have a shape in which rectangles (e.g., substantially rectangular) and trapezoids (e.g., substantially trapezoidal) are sequentially stacked in a direction opposite to the third direction DR3 in a cross-sectional view. However, embodiments of this disclosure are not limited thereto, and the shape of the third light-emitting unit 400 may be appropriately changed or modified.

[0131] In one or more embodiments, a third upper metal layer UE3 may be disposed (or provided) on the third light-emitting unit 400. For example, the third upper metal layer UE3 may be disposed (or provided) on the third-second semiconductor layer 430. The third upper metal layer UE3 may be disposed (or provided) in the second pixel region PX2.

[0132] For example, the third upper metal layer UE3 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the third upper metal layer UE3 may include ITO, IZO, and / or IGO. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0133] A fourth light-emitting unit 500 may be disposed (or provided) on the circuit board 100. The fourth light-emitting unit 500 may be disposed (or provided) below the third light-emitting unit 400. For example, the fourth light-emitting unit 500 may be spaced apart from and / or separated from the third light-emitting unit 400 in a direction opposite to the third direction DR3 (e.g., spaced apart or separated). The fourth light-emitting unit 500 may be disposed (or provided) in the second pixel region PX2. For example, the fourth light-emitting unit 500 may be used to emit a fourth light from the second pixel region PX2. For example, the fourth light-emitting unit 500 may be used to emit a fourth light from the second pixel region PX2 toward the exterior of the display device DD.

[0134] In one or more embodiments, the fourth light may be red light. For example, the fourth light and the first light emitted from the first light-emitting unit 200 may have substantially the same wavelength. For example, the fourth light-emitting unit 500 may be used to emit the first light. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the fourth light may have a wavelength different from that of red light. For example, the fourth light may be green light.

[0135] The fourth light-emitting unit 500 may include a fourth-1 semiconductor layer 510, a fourth active layer 520, and / or a fourth-2 semiconductor layer 530. For example, the fourth active layer 520 may be disposed on (or provided on) the fourth-1 semiconductor layer 510. In addition, the fourth-2 semiconductor layer 530 may be disposed on (or provided on) the fourth active layer 520.

[0136] In one or more embodiments, the fourth-1 semiconductor layer 510 may include an n-type semiconductor layer. For example, the fourth-1 semiconductor layer 510 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, the fourth-1 semiconductor layer 510 may include a GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the fourth-1 semiconductor layer 510 may include a p-type semiconductor layer.

[0137] For example, the fourth active layer 520 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the fourth active layer 520 may include a multi-quantum well structure. In one or more embodiments, the fourth active layer 520 may include a structure in which well layers and barrier layers are alternately stacked. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but embodiments of this disclosure are not limited thereto.

[0138] In one or more embodiments, the fourth-second semiconductor layer 530 may include a p-type semiconductor layer. For example, the fourth-second semiconductor layer 530 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, the fourth-second semiconductor layer 530 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the fourth-second semiconductor layer 530 may include an n-type semiconductor layer.

[0139] In one or more embodiments, the fourth light-emitting unit 500 may have a trapezoidal shape (e.g., substantially trapezoidal shape) in a cross-sectional view. However, embodiments of this disclosure are not limited thereto, and the fourth light-emitting unit 500 may have a shape different from the trapezoidal shape (e.g., substantially trapezoidal shape) in a cross-sectional view. For example, the fourth light-emitting unit 500 may have a triangular shape (e.g., substantially triangular shape) in a cross-sectional view.

[0140] In one or more embodiments, a second lower metal layer LE2 may be disposed (or provided) below the fourth light-emitting unit 500. For example, the second lower metal layer LE2 may be disposed (or provided) below the 4-1 semiconductor layer 510. The second lower metal layer LE2 may be disposed (or provided) in the second pixel region PX2.

[0141] For example, the second lower metal layer LE2 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the second lower metal layer LE2 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0142] However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, a second lower metal layer LE2 may not be provided. In one or more embodiments, the fourth-first semiconductor layer 510 may be in direct contact with the second adhesive layer BM2.

[0143] In one or more embodiments, the second adhesive layer BM2 may be disposed (or provided) below the second lower metal layer LE2. The fourth light-emitting unit 500 can be attached to the circuit board 100 via the second adhesive layer BM2. For example, the second lower metal layer LE2 can be attached to the circuit board 100 via the second adhesive layer BM2. For example, the second adhesive layer BM2 may include solder bumps, solder balls, anisotropic conductive (e.g., electrically conductive) films and / or anisotropic conductive (e.g., electrically conductive) pastes, etc.

[0144] However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the fourth light-emitting unit 500 may be attached to the circuit board 100 by a metal bonding method. For example, the second lower metal layer LE2 may be attached to the circuit board 100 by a metal bonding method. In one or more embodiments, a second metal layer may be additionally disposed (or provided) between the circuit board 100 and the second adhesive layer BM2.

[0145] For example, each of the second adhesive layer BM2 and the second metal layer may include copper (Cu) and / or titanium (Ti), and the second lower metal layer LE2 may be attached to the circuit board 100 by a Cu-Cu bonding method and / or a Ti-Ti bonding method.

[0146] In one or more embodiments, a fourth upper metal layer UE4 may be disposed (or provided) on the fourth light-emitting unit 500. For example, the fourth upper metal layer UE4 may be disposed (or provided) on the 4-2 semiconductor layer 530. The fourth upper metal layer UE4 may be disposed (or provided) in the second pixel region PX2.

[0147] For example, the fourth upper metal layer UE4 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the fourth upper metal layer UE4 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0148] A first insulating layer IL1 may be disposed (or provided) on the circuit board 100. For example, the first insulating layer IL1 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0149] A first conductive layer CL1 may be disposed (or provided) on a first insulating layer IL1, a first light-emitting unit 200, and / or a fourth light-emitting unit 500. The first conductive layer CL1 may be in contact with a first upper metal layer UE1. For example, the first conductive layer CL1 may be electrically connected to (or coupled to) the first upper metal layer UE1. The first conductive layer CL1 may be in contact with a fourth upper metal layer UE4. For example, the first conductive layer CL1 may be electrically connected to (or coupled to) the fourth upper metal layer UE4. The first conductive layer CL1 may be in contact with a seventh connecting electrode CE7, which will be described in more detail later.

[0150] For example, the first conductive layer CL1 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the first conductive layer CL1 may include ITO, IZO, and / or IGO. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0151] The second insulating layer IL2 may be disposed (or provided) on the first conductive layer CL1. For example, the second insulating layer IL2 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0152] A first side insulating layer SL1 may be disposed (or provided) on circuit board 100. The first side insulating layer SL1 may cover the first-1 connection electrode CE1-1, which will be described in more detail later. For example, the first side insulating layer SL1 may cover the side surface of the first-1 connection electrode CE1-1. The first side insulating layer SL1 may be connected to (or coupled to) a second insulating layer IL2 and extend onto a third-party direction DR3. The first side insulating layer SL1 and the second insulating layer IL2 may comprise substantially the same material.

[0153] A fourth side insulating layer SL4 may be disposed (or provided) on circuit board 100. The fourth side insulating layer SL4 may cover the second-second connection electrode CE2-2, which will be described in more detail later. For example, the fourth side insulating layer SL4 may cover the side surface of the second-second connection electrode CE2-2. The fourth side insulating layer SL4 may be connected to (or coupled to) the second insulating layer IL2 and may extend on the third-side direction DR3. The fourth side insulating layer SL4 and the second insulating layer IL2 may comprise substantially the same material.

[0154] A second conductive layer CL2 may be disposed (or provided) on the second insulating layer IL2. For example, the second conductive layer CL2 may be in contact with the fourth connection electrode CE4, which will be described in more detail later. For example, the second conductive layer CL2 may be electrically connected to (or coupled to) the fourth connection electrode CE4.

[0155] For example, the second conductive layer CL2 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the second conductive layer CL2 may include ITO, IZO, and / or IGO. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0156] A third conductive layer CL3 may be disposed (or provided) on the second conductive layer CL2. For example, the third conductive layer CL3 may be in contact with the second conductive layer CL2. For example, the third conductive layer CL3 may be electrically connected to (or coupled to) the second conductive layer CL2.

[0157] For example, the third conductive layer CL3 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the third conductive layer CL3 may include ITO, IZO, and / or IGO. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0158] The third insulating layer IL3 may be disposed (or provided) on the third conductive layer CL3. For example, the third insulating layer IL3 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) xZirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0159] A fourth conductive layer CL4 may be disposed (or provided) on the third insulating layer IL3. For example, the fourth conductive layer CL4 may cover the second light-emitting unit 300 and / or the third light-emitting unit 400. For example, the fourth conductive layer CL4 may cover the second-first semiconductor layer 310 and / or the third-first semiconductor layer 410. The fourth conductive layer CL4 may be in contact with the fifth connecting electrode CE5, which will be described in more detail later. For example, the fourth conductive layer CL4 may be electrically connected to (or coupled to) the fifth connecting electrode CE5. The fourth conductive layer CL4 may be in contact with the sixth connecting electrode CE6, which will be described in more detail later. For example, the fourth conductive layer CL4 may be electrically connected to (or coupled to) the sixth connecting electrode CE6.

[0160] A fourth insulating layer IL4 may be disposed (or provided) on the fourth conductive layer CL4. The fourth insulating layer IL4 may define a first cutout portion in a portion that at least partially overlaps with the first pixel region PX1 in a planar view. The second-second semiconductor layer 330 may be disposed (or provided) in the first cutout portion. The fourth insulating layer IL4 may be in contact with one end of each of the second-first semiconductor layer 310 and the second active layer 320.

[0161] The fourth insulating layer IL4 may define a second cutout portion in a portion that at least partially overlaps with the second pixel region PX2 in a planar view. The third-second semiconductor layer 430 may be disposed (or provided) in the second cutout portion. The fourth insulating layer IL4 may be in contact with one end of each of the third-first semiconductor layer 410 and the third active layer 420.

[0162] For example, the fourth insulating layer IL4 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0163] The fifth insulating layer IL5 may be disposed (or provided) on the fourth insulating layer IL4. For example, the fifth insulating layer IL5 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0164] The second side insulating layer SL2 may cover the first-second connecting electrode CE1-2, which will be described in more detail later. For example, the second side insulating layer SL2 may cover the side surface of the first-second connecting electrode CE1-2.

[0165] For example, the second side insulating layer SL2 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0166] The third side insulating layer SL3 may cover the second-first connecting electrode CE2-1, which will be described in more detail later. For example, the third side insulating layer SL3 may cover the side surface of the second-first connecting electrode CE2-1.

[0167] For example, the third-side insulating layer SL3 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) xZirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0168] The sixth insulating layer IL6 may be disposed (or provided) on the fifth insulating layer IL5. For example, the sixth insulating layer IL6 may cover the second upper metal layer UE2 and / or the third upper metal layer UE3.

[0169] For example, the sixth insulating layer IL6 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0170] Figure 4 It is shown that it includes Figure 1 A plan view of the display area in a display device. For example, Figure 4 It is shown Figure 3 A plan view illustrating an example arrangement or position of the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3.

[0171] Further reference Figure 4 and combined Figure 2 The first connecting electrode CE1 may penetrate at least a portion of each of the first light-emitting unit 200 and the second light-emitting unit 300. For example, the first connecting electrode CE1 may include a first-1 connecting electrode CE1-1 that penetrates at least a portion of the first light-emitting unit 200 and / or a first-2 connecting electrode CE1-2 that penetrates at least a portion of the second light-emitting unit 300.

[0172] The first-1 connecting electrode CE1-1 can be electrically connected to (or coupled to) the third electrode 130 through a first opening OP1 formed (or provided) in the first-side insulating layer SL1. The first-1 connecting electrode CE1-1 and the first-2 connecting electrode CE1-2 can be electrically connected to (or coupled to) each other through a second opening OP2 formed (or provided) in the second-side insulating layer SL2. The first-2 connecting electrode CE1-2 can be electrically connected to (or coupled to) the second upper metal layer UE2. The second upper metal layer UE2 can be electrically connected to (or coupled to) the second-2 semiconductor layer 330. For example, the second-2 semiconductor layer 330 can be electrically connected to (or coupled to) the third electrode 130 through the first connecting electrode CE1 and / or the second upper metal layer UE2. For example, the third electrode 130 can be the cathode (cathode electrode) of the second light-emitting unit 300.

[0173] For example, the first connecting electrode CE1 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the first connecting electrode CE1 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0174] The second connecting electrode CE2 may penetrate at least a portion of each of the third light-emitting unit 400 and the fourth light-emitting unit 500. For example, the second connecting electrode CE2 may include a second-1 connecting electrode CE2-1 that penetrates at least a portion of the third light-emitting unit 400 and / or a second-2 connecting electrode CE2-2 that penetrates at least a portion of the fourth light-emitting unit 500.

[0175] The 2-2 connecting electrode CE2-2 can be electrically connected to (or coupled to) the fifth electrode 150 through a fourth opening OP4 formed (or provided) in the fourth-side insulating layer SL4. The 2-2 connecting electrode CE2-2 and the 2-1 connecting electrode CE2-1 can be electrically connected to (or coupled to) each other through a third opening OP3 formed (or provided) in the third-side insulating layer SL3. The 2-1 connecting electrode CE2-1 can be electrically connected to (or coupled to) the third upper metal layer UE3. The third upper metal layer UE3 can be electrically connected to (or coupled to) the 3-2 semiconductor layer 430. For example, the 3-2 semiconductor layer 430 can be electrically connected to (or coupled to) the fifth electrode 150 through the second connecting electrode CE2 and / or the third upper metal layer UE3. For example, the fifth electrode 150 can be the cathode of the third light-emitting unit 400.

[0176] For example, the second connecting electrode CE2 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the second connecting electrode CE2 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0177] The first-1 semiconductor layer 210 may be electrically connected to (or coupled to) the second electrode 120. For example, the first-1 semiconductor layer 210 may be electrically connected to (or coupled to) the second electrode 120 through the first lower metal layer LE1 and / or the first adhesive layer BM1. For example, the second electrode 120 may be the cathode electrode of the first light-emitting unit 200.

[0178] The fourth semiconductor layer 510 may be electrically connected to (or coupled to) the fourth electrode 140. For example, the fourth semiconductor layer 510 may be electrically connected to (or coupled to) the fourth electrode 140 via the second lower metal layer LE2 and / or the second adhesive layer BM2. For example, the fourth electrode 140 may be the cathode electrode of the fourth light-emitting unit 500.

[0179] The third connecting electrode CE3 may be disposed (or provided) on the circuit board 100. For example, the third connecting electrode CE3 may be disposed (or provided) between the circuit board 100 and the first conductive layer CL1. The third connecting electrode CE3 may be spaced apart from and / or separated from the first pixel region PX1 in a direction opposite to the first direction DR1 (e.g., spaced apart or separated). For example, the third connecting electrode CE3 may be spaced apart from and / or separated from the first light-emitting unit 200 in a direction opposite to the first direction DR1 (e.g., spaced apart or separated). For example, the third connecting electrode CE3 may be disposed (or provided) on one side of the display region DA. However, the embodiments of this disclosure are not limited thereto, and the arrangement or position of the third connecting electrode CE3 in the plan view may be appropriately changed or modified. For example, the third connecting electrode CE3 may be disposed in the plan view with the non-display region NDA (see Figure 1 They overlap at least partially.

[0180] For example, the third connecting electrode CE3 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the third connecting electrode CE3 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0181] The fourth connecting electrode CE4 may be disposed (or provided) between the first conductive layer CL1 and the second conductive layer CL2. The fourth connecting electrode CE4 may at least partially overlap with the third connecting electrode CE3 in a plan view.

[0182] For example, the fourth connecting electrode CE4 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the fourth connecting electrode CE4 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0183] The fifth connecting electrode CE5 may be disposed (or provided) on the third conductive layer CL3. For example, the fifth connecting electrode CE5 may be disposed (or provided) between the third conductive layer CL3 and the fourth conductive layer CL4. For example, the fifth connecting electrode CE5 may at least partially overlap with the third connecting electrode CE3 in a plan view.

[0184] For example, the fifth connecting electrode CE5 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the fifth connecting electrode CE5 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used alone or in combination with each other (e.g., in any suitable manner).

[0185] A sixth connecting electrode CE6 may be disposed (or provided) on the third conductive layer CL3. For example, the sixth connecting electrode CE6 may be disposed (or provided) between the third conductive layer CL3 and the fourth conductive layer CL4. For example, the sixth connecting electrode CE6 may be spaced apart from and / or separated from the fifth connecting electrode CE5 in the first direction DR1 (e.g., spaced apart or separated). For example, the sixth connecting electrode CE6 may be disposed (or provided) between the first pixel region PX1 and the second pixel region PX2.

[0186] For example, the sixth connecting electrode CE6 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the sixth connecting electrode CE6 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used alone or in combination with each other (e.g., in any suitable manner).

[0187] A seventh connecting electrode CE7 may be disposed (or provided) on the circuit board 100. For example, the seventh connecting electrode CE7 may be disposed (or provided) between the circuit board 100 and the first conductive layer CL1. For example, the seventh connecting electrode CE7 may be spaced apart from and / or separated from the third connecting electrode CE3 in the first direction DR1 (e.g., spaced apart or separated). For example, the seventh connecting electrode CE7 may be disposed (or provided) between the first pixel region PX1 and the second pixel region PX2. The seventh connecting electrode CE7 may prevent or reduce color mixing between the first light-emitting unit 200 and the fourth light-emitting unit 500 (or may reduce the degree or occurrence of color mixing). In addition, electrical signals can be effectively applied from the first electrode 110 to the fourth-second semiconductor layer 530 through the seventh connecting electrode CE7. The seventh connecting electrode CE7 may not be provided.

[0188] For example, the seventh connecting electrode CE7 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the seventh connecting electrode CE7 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0189] In one or more embodiments, the first electrode 110 may be electrically connected to (or coupled to) the third connecting electrode CE3. The third connecting electrode CE3 may be electrically connected to (or coupled to) the first conductive layer CL1. The first conductive layer CL1 may be electrically connected to (or coupled to) the first upper metal layer UE1. The first conductive layer CL1 may be electrically connected to (or coupled to) the seventh connecting electrode CE7. The first conductive layer CL1 may be electrically connected to (or coupled to) the fourth upper metal layer UE4. The first conductive layer CL1 may be electrically connected to (or coupled to) the fourth connecting electrode CE4. The fourth connecting electrode CE4 may be electrically connected to (or coupled to) the second conductive layer CL2. The second conductive layer CL2 may be electrically connected to (or coupled to) the third conductive layer CL3. The third conductive layer CL3 may be electrically connected to (or coupled to) the fifth connecting electrode CE5. The third conductive layer CL3 may be electrically connected to (or coupled to) the sixth connecting electrode CE6.

[0190] The first and second semiconductor layers 230 may be electrically connected to (or coupled to) the first electrode 110. For example, the first and second semiconductor layers 230 may be electrically connected to (or coupled to) the first electrode 110 via the third connecting electrode CE3, the first conductive layer CL1 and / or the first upper metal layer UE1.

[0191] The second-first semiconductor layer 310 may be electrically connected to (or coupled to) the first electrode 110. For example, the second-first semiconductor layer 310 may be electrically connected to (or coupled to) the first electrode 110 via the third connecting electrode CE3, the first conductive layer CL1, the fourth connecting electrode CE4, the second conductive layer CL2, the third conductive layer CL3, the fifth connecting electrode CE5 and / or the fourth conductive layer CL4.

[0192] The third-first semiconductor layer 410 may be electrically connected to (or coupled to) the first electrode 110. For example, the third-first semiconductor layer 410 may be electrically connected to (or coupled to) the first electrode 110 through the third connecting electrode CE3, the first conductive layer CL1, the fourth connecting electrode CE4, the second conductive layer CL2, the third conductive layer CL3, the sixth connecting electrode CE6 and / or the fourth conductive layer CL4.

[0193] The fourth-second semiconductor layer 530 may be electrically connected to (or coupled to) the first electrode 110. For example, the fourth-second semiconductor layer 530 may be electrically connected to (or coupled to) the first electrode 110 via the third connecting electrode CE3, the first conductive layer CL1 and / or the fourth upper metal layer UE4.

[0194] In one or more embodiments, the first electrode 110 may be the anode of each of the first light-emitting unit 200, the second light-emitting unit 300, the third light-emitting unit 400, and the fourth light-emitting unit 500.

[0195] The third pixel region PX3 may be separated from and / or separated from the second pixel region PX2 in the first direction DR1 (e.g., spaced apart or separated). The third pixel region PX3 and the first pixel region PX1 may have substantially the same structure. For example, the cross-sectional structure of the third pixel region PX3 and the cross-sectional structure of the first pixel region PX1 may be substantially the same.

[0196] The fourth pixel region PX4 may be separated from and / or isolated from the third pixel region PX3 in the first direction DR1 (e.g., spaced apart or separated). The fourth pixel region PX4 and the second pixel region PX2 may have substantially the same structure. For example, the cross-sectional structure of the fourth pixel region PX4 and the cross-sectional structure of the second pixel region PX2 may be substantially the same.

[0197] The fifth pixel region PX5 may be separated from and / or separated from the first pixel region PX1 in the second direction DR2 (e.g., spaced apart or separated). The fifth pixel region PX5 and the second pixel region PX2 may have substantially the same structure. For example, the cross-sectional structure of the fifth pixel region PX5 and the cross-sectional structure of the second pixel region PX2 may be substantially the same.

[0198] The sixth pixel region PX6 may be separated from the second pixel region PX2 in the second direction DR2 (e.g., spaced apart or separated). Additionally, the sixth pixel region PX6 may be separated from the fifth pixel region PX5 in the first direction DR1 (e.g., spaced apart or separated). The sixth pixel region PX6 and the first pixel region PX1 may have substantially the same structure. For example, the cross-sectional structure of the sixth pixel region PX6 and the cross-sectional structure of the first pixel region PX1 may be substantially the same.

[0199] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 and Figure 33 It shows the manufacturing process. Figure 2 A cross-sectional view of the method for displaying the device.

[0200] refer to Figure 5 A first semiconductor layer S1 can be formed (or provided) on a first growth substrate SUB1. The first growth substrate SUB1 can be an epitaxial substrate. For example, the epitaxial substrate can include a silicon substrate, a silicon carbide substrate, and / or a sapphire substrate, etc. The first semiconductor layer S1 can be formed (or provided) by an epitaxial growth method.

[0201] In one or more embodiments, the first semiconductor layer S1 may include an n-type semiconductor layer. For example, the first semiconductor layer S1 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, the first semiconductor layer S1 may include a GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant.

[0202] An active layer S2 may be formed (or provided) on the first semiconductor layer S1. The active layer S2 may be formed (or provided) by an epitaxial growth method. For example, the active layer S2 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the active layer S2 may include a multi-quantum well structure. In one or more embodiments, the active layer S2 may include a structure in which well layers and barrier layers are alternately stacked. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but embodiments of this disclosure are not limited thereto.

[0203] A second semiconductor layer S3 may be formed (or provided) on the active layer S2. The second semiconductor layer S3 may be formed (or provided) by an epitaxial growth method. In one or more embodiments, the second semiconductor layer S3 may include a p-type semiconductor layer. For example, the second semiconductor layer S3 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, the second semiconductor layer S3 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant.

[0204] A preliminary metallized layer (PUE) may be formed (or provided) on the second semiconductor layer S3. For example, the preliminary metallized layer PUE may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the preliminary metallized layer PUE may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0205] refer to Figure 5 and Figure 6The first growth substrate SUB1 can be removed. For example, the first growth substrate SUB1 can be removed by laser ablation (LLO).

[0206] After removing the first growth substrate SUB1, a pre-constructed lower metal layer (PLE) may be formed (or provided) beneath the first semiconductor layer S1. For example, the pre-constructed lower metal layer (PLE) may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the pre-constructed lower metal layer (PLE) may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0207] A pre-adhesive layer PBM may be formed (or provided) below the pre-prepared lower metal layer PLE. In one or more embodiments, the pre-adhesive layer PBM may include solder bumps, solder balls, anisotropic conductive (e.g., electrically conductive) films and / or anisotropic conductive (e.g., electrically conductive) pastes, etc.

[0208] refer to Figure 7 and Figure 8 The pre-adhesive layer PBM, the pre-lower metal layer PLE, the first semiconductor layer S1, the active layer S2, the second semiconductor layer S3, and / or the pre-upper metal layer PUE can be attached to the circuit board 100. For example, the pre-lower metal layer PLE can be attached to the circuit board 100 via the pre-adhesive layer PBM.

[0209] The circuit board 100 may be formed (or provided) to include TFT, PMOS, NMOS, and / or CMOS structures, etc. A first electrode 110, a second electrode 120, a third electrode 130, a fourth electrode 140, and / or a fifth electrode 150 may be formed (or provided) in the circuit board 100. For example, each of the first electrode 110, the second electrode 120, the third electrode 130, the fourth electrode 140, and the fifth electrode 150 may include metals, alloys, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials, etc. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0210] refer to Figure 8 and Figure 9A portion of the pre-adhesive layer PBM, the pre-lower metal layer PLE, the first semiconductor layer S1, the active layer S2, the second semiconductor layer S3, and / or the pre-upper metal layer PUE can be removed to form (or provide) the first light-emitting unit 200 and / or the fourth light-emitting unit 500. For example, portions of the pre-adhesive layer PBM, the pre-lower metal layer PLE, the first semiconductor layer S1, the active layer S2, the second semiconductor layer S3, and / or the pre-upper metal layer PUE that do not overlap with the first pixel region PX1 and / or the second pixel region PX2 in a planar view can be removed to form (or provide) the first light-emitting unit 200 and / or the fourth light-emitting unit 500.

[0211] For example, portions of the prepared adhesive layer PBM that do not overlap with the first pixel region PX1 and / or the second pixel region PX2 in a planar view can be removed to form (or provide) a first adhesive layer BM1 and / or a second adhesive layer BM2. The first adhesive layer BM1 can be formed (or provided) in the first pixel region PX1, and the second adhesive layer BM2 can be formed (or provided) in the second pixel region PX2.

[0212] The portion of the prepared lower metal layer PLE that does not overlap with the first pixel region PX1 and / or the second pixel region PX2 in the planar view can be removed to form (or provide) a first lower metal layer LE1 and / or a second lower metal layer LE2. The first lower metal layer LE1 can be formed (or provided) in the first pixel region PX1, and the second lower metal layer LE2 can be formed (or provided) in the second pixel region PX2.

[0213] The portion of the first semiconductor layer S1 that does not overlap with the first pixel region PX1 and / or the second pixel region PX2 in the plan view can be removed to form (or provide) the first-1 semiconductor layer 210 and / or the fourth-1 semiconductor layer 510. The first-1 semiconductor layer 210 can be formed (or provided) in the first pixel region PX1, and the fourth-1 semiconductor layer 510 can be formed (or provided) in the second pixel region PX2.

[0214] The portion of the active layer S2 that does not overlap with the first pixel region PX1 and / or the second pixel region PX2 in the planar view can be removed to form (or provide) a first active layer 220 and / or a fourth active layer 520. The first active layer 220 can be formed (or provided) in the first pixel region PX1, and the fourth active layer 520 can be formed (or provided) in the second pixel region PX2.

[0215] The portion of the second semiconductor layer S3 that does not overlap with the first pixel region PX1 and / or the second pixel region PX2 in the plan view can be removed to form (or provide) the first-second semiconductor layer 230 and / or the fourth-second semiconductor layer 530. The first-second semiconductor layer 230 can be formed (or provided) in the first pixel region PX1, and the fourth-second semiconductor layer 530 can be formed (or provided) in the second pixel region PX2.

[0216] The portion of the prepared upper metal layer PUE that does not overlap with the first pixel region PX1 and / or the second pixel region PX2 in the plan view can be removed to form (or provide) a first upper metal layer UE1 and / or a fourth upper metal layer UE4. The first upper metal layer UE1 can be formed (or provided) in the first pixel region PX1, and the fourth upper metal layer UE4 can be formed (or provided) in the second pixel region PX2.

[0217] The first light-emitting unit 200 may include a first semiconductor layer 210, a first active layer 220, and / or a first semiconductor layer 230. The fourth light-emitting unit 500 may include a fourth semiconductor layer 510, a fourth active layer 520, and / or a fourth semiconductor layer 530.

[0218] refer to Figure 10 A first preliminary insulating layer PIL1 may be formed (or provided) on the circuit board 100. For example, the first preliminary insulating layer PIL1 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0219] refer to Figure 10 and Figure 11A portion of the first pre-insulating layer PIL1 can be removed. For example, a first hole H1 and / or a second hole H2 can be formed (or provided) in the first pre-insulating layer PIL1. In one or more embodiments, the first insulating layer PIL1 can be formed (or provided). The first hole H1 can be formed (or provided) to be spaced apart from and / or separated from the first pixel region PX1 in a direction opposite to the first direction DR1 (e.g., spaced apart or separated). The second hole H2 can be formed (or provided) between the first pixel region PX1 and the second pixel region PX2.

[0220] refer to Figure 12 A third connection electrode CE3 can be formed (or provided) in the first hole H1. For example, the third connection electrode CE3 can be formed (or provided) by an inlay process. For example, the third connection electrode CE3 can include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides and / or transparent conductive (e.g., electrically conductive) materials, etc. For example, the third connection electrode CE3 can include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium and / or copper, etc. These materials can be used alone or in combination with each other (e.g., in any suitable way).

[0221] A seventh connection electrode CE7 may be formed (or provided) in the second hole H2. For example, the seventh connection electrode CE7 may be formed (or provided) by an inlay process. For example, the seventh connection electrode CE7 may comprise metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the seventh connection electrode CE7 may comprise molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0222] A first conductive layer CL1 may be formed (or provided) on the first light-emitting unit 200, the fourth light-emitting unit 500, the first insulating layer IL1, the third connecting electrode CE3, and / or the seventh connecting electrode CE7. For example, the first conductive layer CL1 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used individually or in combination with each other (e.g., in any suitable combination). For example, the first conductive layer CL1 may include ITO, IZO, and / or IGO. These materials may be used individually or in combination with each other (e.g., in any suitable combination).

[0223] refer to Figure 13A portion of the first conductive layer CL1, the first upper metal layer UE1, the first light-emitting unit 200, the first lower metal layer LE1, and / or the first adhesive layer BM1 can be removed. For example, a portion of the first conductive layer CL1, the first upper metal layer UE1, the first light-emitting unit 200, the first lower metal layer LE1, and / or the first adhesive layer BM1 can be removed to form (or provide) a third hole H3. The third hole H3 can at least partially overlap with the first pixel region PX1 in a planar view. Additionally, a portion of the first conductive layer CL1, the fourth upper metal layer UE4, the fourth light-emitting unit 500, the second lower metal layer LE2, and / or the second adhesive layer BM2 can be removed to form (or provide) a fourth hole H4. The fourth hole H4 can at least partially overlap with the second pixel region PX2 in a planar view.

[0224] refer to Figure 13 and Figure 14 A second preliminary insulating layer PIL2 may be formed (or provided) on the first conductive layer CL1. The second preliminary insulating layer PIL2 may be formed (or provided) in the third hole H3 and / or the fourth hole H4. For example, the second preliminary insulating layer PIL2 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0225] refer to Figure 14 and Figure 15 A portion of the second pre-insulating layer PIL2 can be removed. For example, a fifth hole H5, a sixth hole H6, and / or a seventh hole H7 can be formed (or provided) in the second pre-insulating layer PIL2. In one or more embodiments, the second insulating layer IL2 can be formed (or provided). The fifth hole H5 can at least partially overlap with the third connecting electrode CE3 in a plan view. The sixth hole H6 can overlap with the third electrode 130 in a plan view. The seventh hole H7 can overlap with the fifth electrode 150 in a plan view. The sixth hole H6 and Figure 2 The first opening OP1 can be essentially the same. The seventh hole H7 and... Figure 2 The fourth opening OP4 can be basically the same.

[0226] refer to Figure 15 and Figure 16 It can be done in the third hole (e.g., Figure 13 The first-1 connecting electrode CE1-1 is formed (or provided) in the third hole H3 and / or the sixth hole H6. For example, the first-1 connecting electrode CE1-1 can be formed (or provided) by an inlay process. For example, the first-1 connecting electrode CE1-1 can be formed (or provided) to penetrate at least a portion of the first light-emitting unit 200.

[0227] For example, the first-1 connecting electrode CE1-1 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the first-1 connecting electrode CE1-1 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0228] It can be done in the fourth hole (e.g., Figure 13 The second-2 connecting electrode CE2-2 is formed (or provided) in the fourth hole H4 and / or the seventh hole H7. For example, the second-2 connecting electrode CE2-2 can be formed (or provided) by an inlay process. For example, the second-2 connecting electrode CE2-2 can be formed (or provided) to penetrate at least a portion of the fourth light-emitting unit 500.

[0229] For example, the second-2 connecting electrode CE2-2 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the second-2 connecting electrode CE2-2 may include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0230] A fourth connection electrode CE4 may be formed (or provided) in the fifth hole H5. For example, the fourth connection electrode CE4 may be formed (or provided) by an inlay process. For example, the fourth connection electrode CE4 may comprise metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the fourth connection electrode CE4 may comprise molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used individually or in combination with each other (e.g., in any suitable manner).

[0231] For example, the first-1 connecting electrode CE1-1, the second-2 connecting electrode CE2-2 and / or the fourth connecting electrode CE4 can be formed concurrently (e.g., simultaneously) and can comprise substantially the same material.

[0232] A second conductive layer CL2 may be formed (or provided) on the second insulating layer IL2, the fourth connecting electrode CE4, the first-1 connecting electrode CE1-1, and / or the second-2 connecting electrode CE2-2. For example, the second conductive layer CL2 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the second conductive layer CL2 may include ITO, IZO, and / or IGO. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0233] In one or more embodiments, a lower display unit (LSUB) may be formed (or provided). For example, Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a cross-sectional view illustrating a series of processes that can form (or provide) a lower display unit (LSUB). The lower display unit (LSUB) may include a circuit board 100, a first light-emitting unit 200, a fourth light-emitting unit 500, a first insulating layer IL1, a second insulating layer IL2, a first-1 connecting electrode CE1-1, a second-2 connecting electrode CE2-2, a third connecting electrode CE3, a fourth connecting electrode CE4, a seventh connecting electrode CE7, a first conductive layer CL1, and / or a second conductive layer CL2.

[0234] Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This illustrates that display units can be formed (or provided) on top (e.g., Figure 24 A cross-sectional view of a series of processes of the upper display unit (USUB).

[0235] refer to Figure 17 A third semiconductor layer S4 can be formed (or provided) on a second growth substrate SUB2. The second growth substrate SUB2 can be an epitaxial substrate. For example, the epitaxial substrate can include a silicon substrate, a silicon carbide substrate, and / or a sapphire substrate, etc. The third semiconductor layer S4 can be formed (or provided) by an epitaxial growth method.

[0236] In one or more embodiments, the third semiconductor layer S4 may include an n-type semiconductor layer. For example, the third semiconductor layer S4 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, the third semiconductor layer S4 may include a GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant.

[0237] A fourth pre-insulating layer PIL4 may be formed (or provided) on the third semiconductor layer S4. For example, the fourth pre-insulating layer PIL4 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0238] refer to Figure 17 and Figure 18 A portion of the fourth pre-insulating layer PIL4 can be removed. For example, an eighth hole H8 and / or a ninth hole H9 can be formed (or provided) in the fourth pre-insulating layer PIL4. In one or more embodiments, the fourth insulating layer PIL4 can be formed (or provided). The eighth hole H8 can overlap with the first pixel region PX1 in a planar view. The ninth hole H9 can overlap with the second pixel region PX2 in a planar view.

[0239] refer to Figure 18 and Figure 19 A second-second semiconductor layer 330 may be formed (or provided) in the first pixel region PX1. The second-second semiconductor layer 330 may have a shape that grows vertically on the third semiconductor layer S4. Depending on the cross-sectional shape of the eighth hole H8, the second-second semiconductor layer 330 may have one or more suitable shapes. For example, in a cross-sectional view, the second-second semiconductor layer 330 may have a shape in which rectangles (e.g., substantially rectangular) and triangles (e.g., substantially triangular) are sequentially stacked on the third direction DR3.

[0240] A third-second semiconductor layer 430 may be formed (or provided) in the second pixel region PX2. The third-second semiconductor layer 430 may have a shape that grows vertically on the third semiconductor layer S4. Depending on the cross-sectional shape of the ninth hole H9, the third-second semiconductor layer 430 may have one or more suitable shapes. For example, in a cross-sectional view, the third-second semiconductor layer 430 may have a shape in which rectangles (e.g., substantially rectangular) and trapezoids (e.g., substantially trapezoidal) are sequentially stacked on the third direction DR3.

[0241] refer to Figure 20 A second active layer 320 may be formed (or provided) on the second-second semiconductor layer 330. For example, the second active layer 320 may be formed (or provided) in the first pixel region PX1. For example, the second active layer 320 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the second active layer 320 may include a multi-quantum well structure. In one or more embodiments, the second active layer 320 may include a structure in which well layers and barrier layers are stacked alternately. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but the embodiments of this disclosure are not limited thereto.

[0242] A second-first semiconductor layer 310 may be formed (or provided) on the second active layer 320. For example, the second-first semiconductor layer 310 may be formed (or provided) in the first pixel region PX1. In one or more embodiments, the second-first semiconductor layer 310 may include a p-type semiconductor layer. For example, the second-first semiconductor layer 310 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, the second-first semiconductor layer 310 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant.

[0243] A third active layer 420 may be formed (or provided) on the third-second semiconductor layer 430. For example, the third active layer 420 may be formed (or provided) in the second pixel region PX2. For example, the third active layer 420 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the third active layer 420 may include a multi-quantum well structure. In one or more embodiments, the third active layer 420 may include a structure in which well layers and barrier layers are stacked alternately.

[0244] A third-first semiconductor layer 410 may be formed (or provided) on the third active layer 420. For example, the third-first semiconductor layer 410 may be formed (or provided) in the second pixel region PX2. In one or more embodiments, the third-first semiconductor layer 410 may include a p-type semiconductor layer. For example, the third-first semiconductor layer 410 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, the third-first semiconductor layer 410 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant.

[0245] refer to Figure 21 A fourth conductive layer CL4 may be formed (or provided) on the fourth insulating layer IL4, the second-first semiconductor layer 310, and / or the third-first semiconductor layer 410. For example, the fourth conductive layer CL4 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the fourth conductive layer CL4 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0246] refer to Figure 22 A third preliminary insulating layer PIL3 may be formed (or provided) on the fourth conductive layer CL4. For example, the third preliminary insulating layer PIL3 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0247] refer to Figure 22 and Figure 23A portion of the third pre-insulating layer PIL3 can be removed. For example, a tenth hole H10 and an eleventh hole H11 can be formed (or provided) in the third pre-insulating layer PIL3. In one or more embodiments, the third insulating layer IL3 can be formed (or provided). The tenth hole H10 can be spaced apart from and / or separated from the first pixel region PX1 in a direction opposite to the first direction DR1 (e.g., spaced apart or separated). The eleventh hole H11 can be formed (or provided) between the first pixel region PX1 and the second pixel region PX2.

[0248] refer to Figure 23 and Figure 24 A fifth connection electrode CE5 can be formed (or provided) in the tenth hole H10. For example, the fifth connection electrode CE5 can be formed (or provided) by an inlay process. For example, the fifth connection electrode CE5 can include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the fifth connection electrode CE5 can include molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials can be used alone or in combination with each other (e.g., in any suitable manner).

[0249] A sixth connection electrode CE6 may be formed (or provided) in the eleventh hole H11. For example, the sixth connection electrode CE6 may be formed (or provided) by an inlay process. For example, the sixth connection electrode CE6 may comprise metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. For example, the sixth connection electrode CE6 may comprise molybdenum, aluminum, chromium, titanium, gold, nickel, neodymium, and / or copper. These materials may be used alone or in combination with each other (e.g., in any suitable manner).

[0250] In one or more embodiments, the fifth connecting electrode CE5 and / or the sixth connecting electrode CE6 may be formed concurrently (e.g., simultaneously) and may comprise substantially the same material.

[0251] A third conductive layer CL3 may be formed (or provided) on the third insulating layer IL3, the fifth connecting electrode CE5, and / or the sixth connecting electrode CE6. For example, the third conductive layer CL3 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the third conductive layer CL3 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0252] In one or more embodiments, an upper display unit USUB may be formed (or provided). The upper display unit USUB may include a second growth substrate SUB2, a third semiconductor layer S4, a fourth insulating layer IL4, a second light-emitting unit 300, a third light-emitting unit 400, a fourth conductive layer CL4, a third insulating layer IL3, a fifth connecting electrode CE5, a sixth connecting electrode CE6, and / or a third conductive layer CL3.

[0253] refer to Figure 25 and Figure 26 The upper display unit (e.g., Figure 24 The upper display unit (USUB) is attached to the lower display unit (e.g., Figure 16 The upper display unit (LSUB) is attached to the lower display unit. For example, the upper display unit can be attached to the lower display unit in an inverted state, such that the third conductive layer CL3 faces the lower display unit.

[0254] After attaching the upper display unit to the lower display unit, the second growth substrate SUB2 and / or the third semiconductor layer S4 can be removed.

[0255] refer to Figure 27 A portion of the fourth insulating layer IL4, the second light-emitting unit 300, the fourth conductive layer CL4, the third insulating layer IL3, the third conductive layer CL3, and / or the second conductive layer CL2 can be removed to form (or provide) the twelfth hole H12. For example, the twelfth hole H12 can at least partially overlap with the first pixel region PX1 in a planar view. For example, the twelfth hole H12 can overlap with the first connecting electrode CE1-1 in a planar view.

[0256] A portion of the fourth insulating layer IL4, the third light-emitting unit 400, the fourth conductive layer CL4, the third insulating layer IL3, the third conductive layer CL3, and / or the second conductive layer CL2 can be removed to form (or provide) a thirteenth hole H13. For example, the thirteenth hole H13 may at least partially overlap with the second pixel region PX2 in a planar view. For example, the thirteenth hole H13 may at least partially overlap with the second-second connecting electrode CE2-2 in a planar view.

[0257] refer to Figure 27 and Figure 28 A fifth pre-insulating layer PIL5 may be formed (or provided) on the fourth insulating layer IL4, the second-second semiconductor layer 330, and / or the third-second semiconductor layer 430. The fifth pre-insulating layer PIL5 may be formed (or provided) in the twelfth hole H12 and / or the thirteenth hole H13. For example, the fifth pre-insulating layer PIL5 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x Ny ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0258] refer to Figure 28 and Figure 29 A portion of the fifth pre-insulating layer PIL5 can be removed. For example, a fourteenth hole H14 and / or a fifteenth hole H15 can be formed (or provided) in the fifth pre-insulating layer PIL5. In one or more embodiments, the fifth insulating layer IL5 can be formed (or provided). The fourteenth hole H14 and Figure 2 The second opening OP2 can be essentially the same. The fifteenth hole H15 and... Figure 2 The third opening OP3 can be basically the same.

[0259] refer to Figure 29 and Figure 30 It can be done in the twelfth hole (for example, Figure 27 A first-second connecting electrode CE1-2 is formed (or provided) in the twelfth hole (H12) and / or the fourteenth hole (H14). The first-second connecting electrode CE1-2 may be formed (or provided) to overlap with the first-first connecting electrode CE1-1 in a plan view. For example, the first-second connecting electrode CE1-2 may be formed (or provided) to penetrate at least a portion of the second light-emitting unit 300.

[0260] For example, the first-second connecting electrode CE1-2 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the first-second connecting electrode CE1-2 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0261] It can be done in the thirteenth hole (for example, Figure 27 A second-first connecting electrode CE2-1 is formed (or provided) in the thirteenth hole (H13) and / or the fifteenth hole (H15). The second-first connecting electrode CE2-1 may be formed (or provided) to overlap with the second-second connecting electrode CE2-2 in a plan view. For example, the second-first connecting electrode CE2-1 may be formed (or provided) to penetrate at least a portion of the third light-emitting unit 400.

[0262] For example, the second-first connecting electrode CE2-1 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the second-first connecting electrode CE2-1 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0263] refer to Figure 31 A portion of the fourth insulating layer IL4, the fifth insulating layer IL5, the second-second semiconductor layer 330, and / or the third-second semiconductor layer 430 can be removed. For example, a sixteenth hole H16 and / or a seventeenth hole H17 can be formed (or provided) in the fourth insulating layer IL4, the fifth insulating layer IL5, the second-second semiconductor layer 330, and / or the third-second semiconductor layer 430. The sixteenth hole H16 can overlap with the first pixel region PX1 in a planar view. If viewed in a planar view (e.g., when viewed in a planar view), the seventeenth hole H17 can overlap with the second pixel region PX2.

[0264] refer to Figure 31 and Figure 32 A second upper metal layer UE2 may be formed (or provided) in the sixteenth hole H16. For example, the second upper metal layer UE2 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the second upper metal layer UE2 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0265] A third upper metal layer UE3 may be formed (or provided) in the seventeenth hole H17. For example, the third upper metal layer UE3 may include metals, metal nitrides, conductive (e.g., electrically conductive) metal oxides, and / or transparent conductive (e.g., electrically conductive) materials. These materials may be used alone or in combination with each other (e.g., in any suitable combination). For example, the third upper metal layer UE3 may include ITO, IZO, and / or IGO, etc. These materials may be used alone or in combination with each other (e.g., in any suitable combination).

[0266] refer to Figure 33 A sixth insulating layer IL6 may be formed (or provided) on the fifth insulating layer IL5, the second upper metal layer UE2, and / or the third upper metal layer UE3. For example, the sixth insulating layer IL6 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), Hafnium oxide (HfO) x ) and / or titanium dioxide (TiO2) x These materials can be used individually or in combination with each other (e.g., in any suitable way).

[0267] A method of manufacturing a display device DD according to one or more embodiments may include attaching an upper display unit (e.g., ...) to a display device DD. Figure 24 The upper display unit (USUB) is integrally attached to the lower display unit (e.g., Figure 16 The steps (e.g., actions or tasks) on the lower display unit (LSUB). The process of attaching the upper display unit to the lower display unit can be referred to as a wafer-to-wafer (W2W) process. A method of manufacturing a display device DD according to one or more embodiments may include a single wafer-to-wafer bonding process. For example, a second light-emitting unit 300 and / or a third light-emitting unit 400 may be attached to a first light-emitting unit 200 and / or a fourth light-emitting unit 500 by a single wafer-to-wafer bonding process, and in one or more embodiments, the display device DD may be manufactured. In one or more embodiments, the manufacturing process of the display device DD may be appropriately simplified or modified. As described above, the first light-emitting unit 200 may be used to emit a first light, the second light-emitting unit 300 may be used to emit a second light, and the third light-emitting unit 400 may be used to emit a third light. For example, the first light-emitting unit 200 may be used to emit red light, the second light-emitting unit 300 may be used to emit blue light, and the third light-emitting unit 400 may be used to emit green light. According to one or more embodiments, the display device DD that implements an RGB full-color system may be manufactured by a single wafer-to-wafer process.

[0268] Figure 34 This is a cross-sectional view showing a display device according to one or more embodiments.

[0269] In addition to the configuration or arrangement of the first light-emitting unit 200', the first lower metal layer LE1', the first adhesive layer BM1' and / or the first upper metal layer UE1', refer to Figure 34 The described display device DD' can be compared with the reference. Figure 2 The described display devices DD are substantially the same or substantially similar. Therefore, duplicate descriptions will not be provided or will be appropriately simplified or modified.

[0270] refer to Figure 34The first light-emitting unit 200' may be disposed (or provided) on the circuit board 100. The first light-emitting unit 200' may include a first-1 semiconductor layer 210', a first active layer 220', and / or a first-2 semiconductor layer 230'. The first active layer 220' may be disposed (or provided) on the first-1 semiconductor layer 210'. The first-2 semiconductor layer 230' may be disposed (or provided) on the first active layer 220'. For example, the first light-emitting unit 200' may be used to emit first light. In one or more embodiments, the first light may be red light.

[0271] In one or more embodiments, the first light-emitting unit 200' may be arranged (or provided) continuously (e.g., substantially continuously) throughout the first pixel region PX1 and / or the second pixel region PX2. For example, except for the portion in which the first-1 connecting electrode CE1-1 is arranged (or provided) and / or the portion in which the second-2 connecting electrode CE2-2 is arranged (or provided), the first light-emitting unit 200' may be arranged (or provided) continuously (e.g., substantially continuously) throughout the first pixel region PX1 and / or the second pixel region PX2.

[0272] A first lower metal layer LE1' may be disposed (or provided) below the first light-emitting unit 200'. The first lower metal layer LE1' may be disposed (or provided) continuously (e.g., substantially continuously) across the first pixel region PX1 and / or the second pixel region PX2. For example, except for the portion in which the first-1 connecting electrode CE1-1 is disposed (or provided) and / or the portion in which the second-2 connecting electrode CE2-2 is disposed (or provided), the first lower metal layer LE1' may be disposed (or provided) continuously (e.g., substantially continuously) across the first pixel region PX1 and / or the second pixel region PX2.

[0273] The first adhesive layer BM1' may be disposed (or provided) below the first lower metal layer LE1'. The first adhesive layer BM1' may be disposed (or provided) continuously (e.g., substantially continuously) over the first pixel region PX1 and / or the second pixel region PX2. For example, except for the portion in which the first-1 connecting electrode CE1-1 is disposed (or provided) and / or the portion in which the second-2 connecting electrode CE2-2 is disposed (or provided), the first adhesive layer BM1' may be disposed (or provided) continuously (e.g., substantially continuously) over the first pixel region PX1 and / or the second pixel region PX2.

[0274] A first upper metal layer UE1' may be disposed (or provided) on the first light-emitting unit 200'. The first upper metal layer UE1' may be disposed (or provided) continuously (e.g., substantially continuously) over the first pixel region PX1 and / or the second pixel region PX2. For example, except for the portion in which the first-1 connecting electrode CE1-1 is disposed (or provided) and / or the portion in which the second-2 connecting electrode CE2-2 is disposed (or provided), the first upper metal layer UE1' may be disposed (or provided) continuously (e.g., substantially continuously) over the first pixel region PX1 and / or the second pixel region PX2.

[0275] The first-1 semiconductor layer 210' may be electrically connected to (or coupled to) the second electrode 120. For example, the first-1 semiconductor layer 210' may be electrically connected to (or coupled to) the second electrode 120 via a first lower metal layer LE1' and / or a first adhesive layer BM1'. The display device DD' according to one or more embodiments may not include (e.g., may be excluded). Figure 2 The display device DD includes a fourth electrode 140 and / or a seventh connection electrode CE7.

[0276] Figure 35 This is a cross-sectional view showing a display device according to one or more embodiments.

[0277] In addition to the configuration or arrangement of the first light-emitting unit 200", the second light-emitting unit 300', the third light-emitting unit 400' and / or the fourth light-emitting unit 500', refer to Figure 35 The described display device "DD" can be compared with the reference. Figure 2 The described display devices DD are substantially the same or substantially similar. In one or more embodiments, repeated descriptions will not be provided or will be appropriately simplified or modified.

[0278] refer to Figure 35 The first light-emitting unit 200 may include a first-1 semiconductor layer 210, a first active layer 220, and / or a first-2 semiconductor layer 230. For example, the first active layer 220 may be disposed on (or provided on) the first-2 semiconductor layer 230. In addition, the first-1 semiconductor layer 210 may be disposed on (or provided on) the first active layer 220.

[0279] The first and second semiconductor layers 230 may include a p-type semiconductor layer. For example, the first and second semiconductor layers 230 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, the first and second semiconductor layers 230 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant.

[0280] The first active layer 220 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the first active layer 220 may include a multi-quantum well structure. In one or more embodiments, the first active layer 220 may include a structure in which well layers and barrier layers are stacked alternately. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but embodiments of this disclosure are not limited thereto.

[0281] Semiconductor layer 210 1-1 may include an n-type semiconductor layer. For example, semiconductor layer 210 1-1 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, semiconductor layer 210 1-1 may include GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant.

[0282] The second light-emitting unit 300' may include a second-first semiconductor layer 310, a second active layer 320, and / or a second-second semiconductor layer 330. For example, the second active layer 320 may be disposed on (or provided on) the second-second semiconductor layer 330. In addition, the second-first semiconductor layer 310 may be disposed on (or provided on) the second active layer 320.

[0283] The second-second semiconductor layer 330 may include an n-type semiconductor layer. For example, the second-second semiconductor layer 330 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, the second-second semiconductor layer 330 may include a GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant.

[0284] The second active layer 320 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the second active layer 320 may include a multi-quantum well structure. In one or more embodiments, the second active layer 320 may include a structure in which well layers and barrier layers are stacked alternately. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but the embodiments of this disclosure are not limited thereto.

[0285] Semiconductor layer 310 2-1 may include a p-type semiconductor layer. For example, semiconductor layer 310 2-1 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, semiconductor layer 310 2-1 may include GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant.

[0286] The third light-emitting unit 400' may include a third-first semiconductor layer 410, a third active layer 420, and / or a third-second semiconductor layer 430. For example, the third active layer 420 may be disposed on (or provided on) the third-second semiconductor layer 430. Alternatively, the third-first semiconductor layer 410 may be disposed on (or provided on) the third active layer 420.

[0287] The third-second semiconductor layer 430 may include an n-type semiconductor layer. For example, the third-second semiconductor layer 430 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, the third-second semiconductor layer 430 may include a GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant.

[0288] The third active layer 420 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the third active layer 420 may include a multi-quantum well structure. In one or more embodiments, the third active layer 420 may include a structure in which well layers and barrier layers are stacked alternately. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but the embodiments of this disclosure are not limited thereto.

[0289] Semiconductor layer 410 3-1 may include a p-type semiconductor layer. For example, semiconductor layer 410 3-1 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, semiconductor layer 410 3-1 may include GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant.

[0290] The fourth light-emitting unit 500' may include a fourth-first semiconductor layer 510, a fourth active layer 520, and / or a fourth-second semiconductor layer 530. For example, the fourth active layer 520 may be disposed on (or provided on) the fourth-second semiconductor layer 530. Alternatively, the fourth-first semiconductor layer 510 may be disposed on (or provided on) the fourth active layer 520.

[0291] The fourth-second semiconductor layer 530 may include a p-type semiconductor layer. For example, the fourth-second semiconductor layer 530 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include a p-type semiconductor layer doped with a second conductive (e.g., electrically conductive) dopant (e.g., a p-type dopant) such as Zn, Mg, Be, Cd, Ag, Hg, Li, and / or Ca. For example, the fourth-second semiconductor layer 530 may include a GaN semiconductor material doped with a second conductive (e.g., electrically conductive) dopant.

[0292] The fourth active layer 520 may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well structure, a quantum dot structure, and / or a quantum wire structure. For example, the fourth active layer 520 may include a multi-quantum well structure. In one or more embodiments, the fourth active layer 520 may include a structure in which well layers and barrier layers are stacked alternately. The well layers may include InGaN, and the barrier layers may include GaN and / or AlGaN, but the embodiments disclosed herein are not limited thereto.

[0293] Semiconductor layer 510 4-1 may include an n-type semiconductor layer. For example, semiconductor layer 510 4-1 may include semiconductor materials such as GaN, InAlGaN, AlGaN, InGaN, AlN, and / or InN, and may include an n-type semiconductor layer doped with a first conductive (e.g., electrically conductive) dopant (e.g., an n-type dopant) such as Si, Sn, Te, Se, S, O, and / or Ge. For example, semiconductor layer 510 4-1 may include GaN semiconductor material doped with a first conductive (e.g., electrically conductive) dopant.

[0294] A fourth insulating layer IL4 may be disposed on (or provided) the second conductive layer CL2. A fourth conductive layer CL4 may be disposed on (or provided) the fourth insulating layer IL4, the second light-emitting unit 300', and / or the third light-emitting unit 400'. A third conductive layer CL3 may be disposed on (or provided) the third insulating layer IL3. A fifth insulating layer IL5 may be disposed on (or provided) the third conductive layer CL3. A sixth insulating layer IL6 may be disposed on (or provided) the fifth insulating layer IL5.

[0295] The first and second semiconductor layers 230 can be electrically connected to (or coupled to) the second electrode 120 through the first lower metal layer LE1 and / or the first adhesive layer BM1. In one or more embodiments, the second electrode 120 may be the anode of the first light-emitting unit 200".

[0296] The second-first semiconductor layer 310 can be electrically connected to (or coupled to) the third electrode 130 through the fourth conductive layer CL4, the fifth connecting electrode CE5, the third conductive layer CL3, the second upper metal layer UE2, and / or the first connecting electrode CE1. In one or more embodiments, the third electrode 130 can be the anode of the second light-emitting unit 300'.

[0297] The third-first semiconductor layer 410 can be electrically connected to (or coupled to) the fifth electrode 150 via the fourth conductive layer CL4, the sixth connecting electrode CE6, the third conductive layer CL3, the third upper metal layer UE3, and / or the second connecting electrode CE2. In one or more embodiments, the fifth electrode 150 may be the anode of the third light-emitting unit 400'.

[0298] The fourth-second semiconductor layer 530 may be electrically connected to (or coupled to) the fourth electrode 140 via the second lower metal layer LE2 and / or the second adhesive layer BM2. In one or more embodiments, the fourth electrode 140 may be the anode of the fourth light-emitting unit 500'.

[0299] Semiconductor layer 210 (1-1) can be connected to (or coupled to) the first electrode 110 via the third connecting electrode CE3, the first conductive layer CL1, and / or the first upper metal layer UE1. Semiconductor layer 330 (2-2) can be electrically connected to (or coupled to) the first electrode 110 via the second conductive layer CL2, the fourth connecting electrode CE4, the first conductive layer CL1, and / or the third connecting electrode CE3. Semiconductor layer 430 (3-2) can be electrically connected to (or coupled to) the first electrode 110 via the second conductive layer CL2, the fourth connecting electrode CE4, the first conductive layer CL1, and / or the third connecting electrode CE3. Semiconductor layer 510 (4-1) can be electrically connected to (or coupled to) the first electrode 110 via the fourth upper metal layer UE4, the first conductive layer CL1, and / or the third connecting electrode CE3.

[0300] In one or more embodiments, the first electrode 110 may be the cathode electrode of each of the first light-emitting unit 200", the second light-emitting unit 300', the third light-emitting unit 400', and the fourth light-emitting unit 500'.

[0301] Figure 36 This is a block diagram illustrating an electronic device according to an embodiment. Figure 37 It is shown Figure 36 The diagram shows an example of an electronic device implemented as a smartphone.

[0302] refer to Figure 36 and Figure 37 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device (I / O device) 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be... Figure 1 The display device DD. In addition, the electronic device 1000 may also include several ports capable of communicating with video cards, sound cards, memory cards and / or Universal Serial Bus (USB) devices.

[0303] According to the embodiments, such as Figure 37 As shown, the electronic device 1000 can be implemented as a smartphone. However, this is exemplary, and the electronic device 1000 can be implemented as various devices according to the embodiments. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation device, computer monitor, laptop computer, and / or head-mounted display device, etc.

[0304] Processor 1010 may be a microprocessor, a central processing unit, and / or an application processor, etc. Processor 1010 may be connected to other components via address buses, control buses, and / or data buses, etc. In embodiments, processor 1010 may also be connected to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0305] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device and / or a volatile memory device. Examples of non-volatile memory devices may include erasable programmable read-only memory (“EPROM”) devices, electrically erasable programmable read-only memory (“EEPROM”) devices, flash memory devices, phase-change random access memory (“PRAM”) devices, resistive random access memory (“RRAM”) devices, nanofloating gate memory (“NFGM”) devices, polymer random access memory (“PoRAM”) devices, magnetic random access memory (“MRAM”) devices, and / or ferroelectric random access memory (“FRAM”) devices, etc. Examples of volatile memory devices may include dynamic random access memory (“DRAM”) devices, static random access memory (“SRAM”) devices, and / or mobile DRAM devices, etc.

[0306] Storage device 1030 may include solid-state drives (“SSDs”), hard disk drives (“HDDs”), and / or optical disc read-only memory (CD-ROMs), etc.

[0307] Input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, and output devices such as a speaker and printer. In an embodiment, display device 1060 may be included in input / output device 1040.

[0308] Power supply 1050 can supply the power required for the operation of electronic device 1000. For example, power supply 1050 can supply the power required for the operation of display device 1060.

[0309] The display device 1060 can be connected to other components via a bus or other communication link.

[0310] This disclosure can be applied to one or more suitable display devices. For example, this disclosure can be applied to one or more suitable display devices, such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for exhibitions or information transmission and / or medical display devices, etc.

[0311] In view of the whole of this disclosure, those skilled in the art will understand that, unless otherwise stated or implied, each suitable feature of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole and may be technically associated with and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0312] The display device, the means for manufacturing the display device, and / or any other related means or components according to embodiments of the invention described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on a single integrated circuit (IC) chip or on separate IC chips. Furthermore, various components of the device can be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of the device can be processes or threads running in one or more processors, executing computer program instructions and interacting with other system components in one or more computing devices to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices (e.g., random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., CD-ROMs or flash drives, for example). Furthermore, those skilled in the art will recognize that, without departing from the scope of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0313] The foregoing is illustrative of one or more embodiments of this disclosure and should not be construed as limiting the disclosure. Although specific embodiments of this disclosure have been described, those skilled in the art will readily recognize that one or more suitable modifications may be made to one or more embodiments without substantially departing from the novel teachings and features of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as claimed in the claims. It should be understood that the foregoing is illustrative of one or more suitable embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and one or more embodiments are intended to be included within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting element, wherein, The light-emitting element includes: A first light-emitting unit is located in a first pixel region, wherein the first light-emitting unit is used to emit first light; A second light-emitting unit is located on top of the first light-emitting unit in the first pixel region, wherein the second light-emitting unit is used to emit second light having a wavelength different from that of the first light; and A third light-emitting unit is located in a second pixel region separated from the first pixel region in the planar view, wherein the third light-emitting unit is used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

2. The light-emitting element according to claim 1, wherein, The third light-emitting unit is located on the first light-emitting unit.

3. The light-emitting element according to claim 2, wherein, The light-emitting element also includes: A fourth light-emitting unit is located in the second pixel region and below the third light-emitting unit, wherein the fourth light-emitting unit is used to emit the first light.

4. The light-emitting element according to claim 1, wherein, The first light-emitting unit includes: Semiconductor layer 1-1; A first active layer is disposed on the first-1 semiconductor layer; and The first and second semiconductor layers are on the first active layer.

5. The light-emitting element according to claim 4, wherein, The second light-emitting unit includes: Semiconductor layer 2-1; A second active layer is disposed on the second-first semiconductor layer; and The second-second semiconductor layer is on the second active layer.

6. The light-emitting element according to claim 5, wherein: Each of the first-1 semiconductor layer and the second-2 semiconductor layer includes an n-type semiconductor layer, and Each of the first-2 semiconductor layers and the second-1 semiconductor layer includes a p-type semiconductor layer.

7. The light-emitting element according to claim 6, wherein, The light-emitting element also includes: Connecting electrodes are electrically connected to each of the first-2 semiconductor layer and the second-1 semiconductor layer.

8. A light-emitting element, wherein, The light-emitting element includes: A first light-emitting unit, in a first pixel region, is used to emit first light, wherein the first light-emitting unit includes: The first-1 semiconductor layer includes an n-type semiconductor layer; A first active layer is disposed on the first-1 semiconductor layer; and The first and second semiconductor layers are located on the first active layer, and the first and second semiconductor layers include a p-type semiconductor layer; A second light-emitting unit is located on top of the first light-emitting unit in the first pixel region. The second light-emitting unit is used to emit second light having a wavelength different from that of the first light. The second light-emitting unit includes: The second-1 semiconductor layer includes a p-type semiconductor layer; A second active layer is disposed on the second-first semiconductor layer; and The second-2 semiconductor layer, on the second active layer, includes an n-type semiconductor layer; and A third light-emitting unit is located in a second pixel region separated from the first pixel region in the planar view. The third light-emitting unit is used to emit third light having a wavelength different from each of the wavelengths of the first light and the second light. The third light-emitting unit includes: The third-first semiconductor layer includes a p-type semiconductor layer; A third active layer is disposed on the third-1st semiconductor layer; and The third-second semiconductor layer, on the third active layer, includes an n-type semiconductor layer.

9. The light-emitting element according to claim 8, wherein, The third light-emitting unit is located on the first light-emitting unit.

10. The light-emitting element according to claim 8, wherein, The light-emitting element also includes: Connecting electrodes are electrically connected to each of the first-2 semiconductor layer and the second-1 semiconductor layer.

11. The light-emitting element according to claim 8, wherein, The light-emitting element also includes: A fourth light-emitting unit is located in the second pixel region and below the third light-emitting unit, wherein the fourth light-emitting unit is used to emit the first light.

12. The light-emitting element according to claim 11, wherein, The fourth light-emitting unit includes: The fourth-1 semiconductor layer includes an n-type semiconductor layer; The fourth active layer is on the fourth-1st semiconductor layer; and The fourth active layer includes a p-type semiconductor layer.

13. The light-emitting element according to claim 8, wherein, The first light-emitting unit is continuously disposed throughout the first pixel area and the second pixel area.

14. A light-emitting element, wherein, The light-emitting element includes: A first light-emitting unit, in a first pixel region, is used to emit first light, wherein the first light-emitting unit includes: The first-1 semiconductor layer includes a p-type semiconductor layer; A first active layer is disposed on the first-1 semiconductor layer; and The first and second semiconductor layers are on the first active layer, and the first and second semiconductor layers include an n-type semiconductor layer; A second light-emitting unit is located on top of the first light-emitting unit in the first pixel region. The second light-emitting unit is used to emit second light having a wavelength different from that of the first light. The second light-emitting unit includes: The second-1 semiconductor layer includes an n-type semiconductor layer; A second active layer is disposed on the second-first semiconductor layer; and The second-2 semiconductor layer, on the second active layer, includes a p-type semiconductor layer; and A third light-emitting unit is located in a second pixel region separated from the first pixel region in the planar view. The third light-emitting unit is used to emit third light having a wavelength different from each of the wavelengths of the first light and the second light. The third light-emitting unit includes: The third-first semiconductor layer includes an n-type semiconductor layer; A third active layer is disposed on the third-1st semiconductor layer; and The third-second semiconductor layer, on the third active layer, includes a p-type semiconductor layer.

15. The light-emitting element according to claim 14, wherein, The third light-emitting unit is located on the first light-emitting unit.

16. The light-emitting element according to claim 15, wherein, The light-emitting element also includes: Connecting electrodes are electrically connected to each of the first-2 semiconductor layer and the second-1 semiconductor layer.

17. The light-emitting element according to claim 14, wherein, The light-emitting element also includes: A fourth light-emitting unit is located in the second pixel region and below the third light-emitting unit, wherein the fourth light-emitting unit is used to emit the first light.

18. The light-emitting element according to claim 17, wherein, The fourth light-emitting unit includes: The fourth-1 semiconductor layer includes a p-type semiconductor layer; The fourth active layer is on the fourth-1st semiconductor layer; and The fourth active layer is a semiconductor layer comprising an n-type semiconductor layer.

19. A display device, wherein, The display device includes: Circuit boards; and The light-emitting element is on the circuit board. The light-emitting element includes: In the first pixel region, the first light-emitting unit is used to emit first light; A second light-emitting unit is located on top of the first light-emitting unit in the first pixel region, and the second light-emitting unit is used to emit second light having a wavelength different from that of the first light; and A third light-emitting unit is located in a second pixel region separated from the first pixel region in the planar view. The third light-emitting unit is used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

20. The display device according to claim 19, wherein, The third light-emitting unit is located on the first light-emitting unit.

21. The display device according to claim 19, wherein, The first light-emitting unit includes: Semiconductor layer 1-1; A first active layer is disposed on the first-1 semiconductor layer; and The first and second semiconductor layers are on the first active layer.

22. The display device according to claim 21, wherein, The second light-emitting unit includes: Semiconductor layer 2-1; A second active layer is disposed on the second-first semiconductor layer; and The second-second semiconductor layer is on the second active layer.

23. The display device according to claim 22, wherein: Each of the first-1 semiconductor layer and the second-2 semiconductor layer includes an n-type semiconductor layer, and Each of the first-2 semiconductor layers and the second-1 semiconductor layer includes a p-type semiconductor layer.

24. The display device according to claim 23, wherein, The circuit board includes a first electrode, a second electrode, and a third electrode, and The first-2 semiconductor layer and the second-1 semiconductor layer are electrically connected to the first electrode.

25. The display device according to claim 24, wherein: The first semiconductor layer is electrically connected to the second electrode, and The second-second semiconductor layer is electrically connected to the third electrode.

26. The display device according to claim 25, wherein, The second-second semiconductor layer is electrically connected to the third electrode through a connection electrode that penetrates at least a portion of each of the first and second light-emitting units.

27. A method for manufacturing a display device, wherein, The method includes: A first light-emitting unit is formed on the circuit board in the first pixel region, wherein the first light-emitting unit is used to emit first light; A second light-emitting unit is formed on a first growth substrate in the first pixel region, wherein the second light-emitting unit is used to emit a second light having a wavelength different from that of the first light; A third light-emitting unit is formed on the first growth substrate in a second pixel region, the second pixel region being separated from the first pixel region in a planar view, wherein the third light-emitting unit is configured to emit third light having a wavelength different from each of the wavelengths of the first light and the second light; and The second light-emitting unit and the third light-emitting unit are attached to the first light-emitting unit.

28. The method according to claim 27, wherein, The formation of the first light-emitting unit includes: A first semiconductor layer is formed on a second growth substrate; An active layer is formed on the first semiconductor layer; A second semiconductor layer is formed on the active layer; Remove the second growth substrate; and Remove the portions of the first semiconductor layer, the active layer, and the second semiconductor layer from the circuit board that do not overlap with the first pixel region in the plan view.

29. The method according to claim 27, wherein, The method further includes: A first connection electrode is formed, the first connection electrode penetrating at least a portion of the first light-emitting unit and electrically connected to an electrode in the circuit board; and A second connecting electrode is formed, which penetrates at least a portion of the second light-emitting unit and is electrically connected to the first connecting electrode.

30. The method according to claim 29, wherein, The formation of the second light-emitting unit includes: A pre-insulating layer is formed on the first growth substrate; An insulating layer is formed by removing the portion of the prepared insulating layer that overlaps with the first pixel region and the second pixel region. A first semiconductor layer is formed in the first pixel region on the first growth substrate; An active layer is formed on the first semiconductor layer; and A second semiconductor layer is formed on the active layer.

31. The method according to claim 30, wherein, The second semiconductor layer is electrically connected to the second connection electrode.

32. An electronic device, wherein, The electronic device includes: Circuit board; Light-emitting elements, on the circuit board; and Memory device, configured to store data, The light-emitting element includes: In the first pixel region, the first light-emitting unit is used to emit first light; A second light-emitting unit is located on top of the first light-emitting unit in the first pixel region, and the second light-emitting unit is used to emit second light having a wavelength different from that of the first light; and A third light-emitting unit is located in a second pixel region spaced apart from the first pixel region in the planar view. The third light-emitting unit is used to emit a third light having a wavelength different from each of the wavelengths of the first light and the second light.

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