Display device

Abstract

There is provided a display device including: a lower substrate; a bonding electrode disposed on the lower substrate; and a light emitting element disposed on the bonding electrode. The bonding electrode includes: a first bonding metal layer and a second bonding metal layer sequentially disposed on the lower substrate, each including a bonding metal; a third bonding metal layer disposed between the first bonding metal layer and the second bonding metal layer and including a bonding metal; a first thin film layer disposed between the first bonding metal layer and the third bonding metal layer; and a second thin film layer disposed between the second bonding metal layer and the third bonding metal layer, and the first thin film layer and the second thin film layer include a material having an atomic volume greater than or equal to about 80% of an atomic volume of the bonding metal.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0061324, filed on May 9, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device, a method for manufacturing the display device, and an electronic device for providing images. Background Technology

[0003] As society becomes increasingly information-driven, there is a growing demand for display devices that can display images in various ways. In response to this trend, various types of display devices, including light-emitting display devices, are being developed. Light-emitting display devices can include pixels containing light-emitting elements. Summary of the Invention

[0004] The disclosed aspects provide a display device that can enhance manufacturing efficiency, a method for manufacturing the display device, and an electronic device for providing images.

[0005] According to the disclosed aspects, a display device is provided, comprising: a lower substrate; a bonding electrode disposed on the lower substrate; and a light-emitting element disposed on the bonding electrode. The bonding electrode may include: a first bonding metal layer and a second bonding metal layer sequentially disposed on the lower substrate, both comprising bonding metal; a third bonding metal layer disposed between the first and second bonding metal layers, also comprising bonding metal; a first thin film layer disposed between the first and third bonding metal layers; and a second thin film layer disposed between the second and third bonding metal layers. The first and second thin film layers may comprise a material having an atomic volume greater than or equal to about 80% of the atomic volume of the bonding metal.

[0006] In an embodiment, the first bonding metal layer, the second bonding metal layer, and the third bonding metal layer may include at least one of titanium (Ti), zirconium (Zr), nickel (Ni), and chromium (Cr).

[0007] In the embodiments, the first thin film layer and the second thin film layer may include at least one of gold (Au), zirconium (Zr), silver (Ag), hafnium (Hf), palladium (Pd) and platinum (Pt).

[0008] In an embodiment, the first bonding metal layer, the second bonding metal layer, and the third bonding metal layer may comprise titanium (Ti), and the first thin film layer and the second thin film layer may comprise at least one of gold (Au) and zirconium (Zr).

[0009] In an embodiment, each of the first bonding metal layer and the second bonding metal layer may have a thickness in the range of about 100 nm to about 300 nm.

[0010] In an embodiment, the thickness of the third bonding metal layer may be less than or equal to the thickness of each of the first and second bonding metal layers.

[0011] In an embodiment, each of the first and second thin film layers may have a thickness in the range of about 1 nm to about 50 nm.

[0012] In an embodiment, the bonding electrode may further include a bonding layer disposed between the lower substrate and the first bonding metal layer.

[0013] In an embodiment, the bonding electrode may further include a reflective layer disposed between the second bonding metal layer and the light-emitting element.

[0014] In an embodiment, the lower substrate may further include a semiconductor circuit substrate containing pixel circuits, a connection electrode connecting the pixel circuits to a bonding electrode, and a first insulating layer disposed on the semiconductor circuit substrate and surrounding the connection electrode.

[0015] In an embodiment, the light-emitting element may include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially disposed on a bonding electrode.

[0016] In an embodiment, the display device may further include a second insulating layer surrounding the side surface of the light-emitting element and a common electrode disposed on the light-emitting element.

[0017] In an embodiment, the display device may further include a reflective film surrounding the side surface of the light-emitting element.

[0018] According to the disclosed aspects, a method for manufacturing a display device is provided, the method comprising the steps of: preparing a first substrate including a semiconductor circuit substrate, wherein a first bonding metal layer and a first thin film layer are sequentially disposed on the semiconductor circuit substrate; preparing a second substrate including the semiconductor substrate, wherein an epitaxial layer, a second bonding metal layer, and a second thin film layer are sequentially disposed on the semiconductor substrate; disposing the second substrate on the first substrate such that the first thin film layer and the second thin film layer face each other, and bonding the first substrate to the second substrate; separating the semiconductor substrate from the epitaxial layer; and forming a bonding electrode and a light-emitting element by etching a lower bonding layer including the first bonding metal layer and the first thin film layer, the epitaxial layer, and an upper bonding layer including the second bonding metal layer and the second thin film layer. The first bonding metal layer and the second bonding metal layer may include a bonding metal, and the first thin film layer and the second thin film layer may include a material having an atomic volume greater than or equal to about 80% of the atomic volume of the bonding metal.

[0019] In an embodiment, the first bonding metal layer and the second bonding metal layer may include at least one of titanium (Ti), zirconium (Zr), nickel (Ni) and chromium (Cr).

[0020] In the embodiments, the first thin film layer and the second thin film layer may include at least one of gold (Au), zirconium (Zr), silver (Ag), hafnium (Hf), palladium (Pd) and platinum (Pt).

[0021] In an embodiment, the first bonding metal layer and the second bonding metal layer may comprise titanium (Ti), and the first thin film layer and the second thin film layer may comprise at least one of gold (Au) and zirconium (Zr).

[0022] In one embodiment, bonding the first substrate to the second substrate may include forming a third bonding metal layer comprising a bonding metal between the first thin film layer and the second thin film layer.

[0023] In an embodiment, each of the first bonding metal layer and the second bonding metal layer may have a thickness in the range of about 100 nm to about 300 nm.

[0024] In an embodiment, each of the first and second thin film layers may have a thickness in the range of about 1 nm to about 50 nm.

[0025] According to the disclosed aspect, an electronic device for providing an image is provided, the electronic device including a display device. The display device may include: a lower substrate; a bonding electrode disposed on the lower substrate; and a light-emitting element disposed on the bonding electrode. The bonding electrode may include: a first bonding metal layer and a second bonding metal layer sequentially disposed on the lower substrate, both including bonding metal; a third bonding metal layer disposed between the first and second bonding metal layers, also including bonding metal; a first thin film layer disposed between the first and third bonding metal layers; and a second thin film layer disposed between the second and third bonding metal layers. The first and second thin film layers may include a material having an atomic volume greater than or equal to about 80% of the atomic volume of the bonding metal.

[0026] According to the display device and the method of manufacturing the display device, the diffusion of the bonding metal can be facilitated by forming a thin film layer on the bonding metal layer of the first substrate and the second substrate. Therefore, the first substrate and the second substrate can be smoothly bonded without the need for a planarization process for the bonding metal layer. In embodiments, the manufacturing efficiency of the display device formed from the first substrate and the second substrate can be enhanced.

[0027] However, the effects of the disclosed embodiments are not limited to those described above, and various other effects are also anticipated. Attached Figure Description

[0028] The above and other aspects, features, and advantages of the disclosed embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic perspective view showing a display device according to an embodiment; Figure 2 It is shown Figure 1 A schematic plan view of an example of area A1; Figure 3 This is a schematic cross-sectional view showing the display panel according to an embodiment; Figure 4 It is shown Figure 3 A schematic cross-sectional view of an example of area A2; Figures 5 to 10 This is a schematic perspective view illustrating a method for manufacturing a display device according to an embodiment; Figures 11 to 18 This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment; Figure 19 This is a schematic diagram illustrating a smartwatch including a display device according to an embodiment; Figure 20 and Figure 21 This is a schematic diagram illustrating a virtual reality device including a display device according to an embodiment; Figure 22 This is a schematic diagram illustrating a virtual reality device including a display device according to another embodiment; Figure 23 This is a schematic diagram illustrating a car dashboard and a central instrument panel, both of which include display devices according to an embodiment; and Figure 24 This is a car diagram illustrating a transparent display device including a display apparatus according to an embodiment. Detailed Implementation

[0029] The disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The various embodiments are not necessarily exclusive, nor are they intended to limit the disclosure. For example, the specific shape, construction, and characteristics of an embodiment may be used or implemented in another embodiment.

[0030] In the accompanying drawings, the size, thickness, ratio, and dimensions of the elements may be exaggerated for ease of description and clarity. The same reference numerals and / or figure marks always refer to the same elements.

[0031] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0032] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0033] As used herein, the terms “about” or “approximately” include the stated value and mean: within an acceptable deviation of the particular value, taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system), as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0034] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood as equivalent to "and / or".

[0035] In the specification and claims, the phrase "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. Furthermore, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0036] When the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0037] The phrase "in a plan view" means viewing the object from top, while the phrase "in a schematic sectional view" means viewing the object from the side as a vertically cut section. Therefore, the expression "in a plan view" as used herein can mean viewing the object from top in the third z-direction DR3. The phrase "in a schematic sectional view" means viewing the object from the side as a vertically cut section in either the first z-direction DR1 or the second z-direction DR2. The third z-direction can also be referred to as the "thickness direction."

[0038] When an element (such as a layer, region, portion, etc.) is referred to as being "on" another element or layer, "connected to," or "bonded to" another element or layer, the element may be directly on, directly connected to, or directly bonded to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly bonded to" another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection and / or electrical connection with or without an intermediary element.

[0039] For ease of description, the spatial relative terms “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device located “below” or “under” another device may be placed “above” another device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be positioned in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0040] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which they pertain. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0041] The features of the various disclosed embodiments can be combined partially or completely, and can interact in different technical ways. Each embodiment can be implemented independently or in combination with other embodiments.

[0042] Figure 1 This is a schematic perspective view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 A schematic plan view of an example of area A1.

[0043] Reference Figure 1 and Figure 2 The display device 10 according to an embodiment may include a display panel DPN comprising a display area DA and a non-display area NDA. In an embodiment, the display device 10 may be included in or provided with electronic devices. For example, the display device 10 may be included in or provided with one of various types of electronic devices for providing images. Optionally, the display device 10 may be provided separately.

[0044] The display panel DPN can have a quadrilateral planar shape with a long side in the first direction DR1 and a short side in the second direction DR2. Figure 1 and Figure 2 In the diagram, the first direction DR1 can refer to the horizontal (or vertical) direction of the display panel DPN, while the second direction DR2 can refer to the vertical (or horizontal) direction of the display panel DPN. The third direction DR3 can refer to the thickness or height direction of the display panel DPN. However, the planar shape of the display panel DPN is not limited to a quadrilateral shape; the display panel DPN can have different shapes. For example, the display panel DPN can include polygonal shapes, circular shapes, elliptical shapes, or irregular shapes in the planar view, in addition to quadrilateral shapes.

[0045] The display area DA can be an area where an image is displayed, while the non-display area NDA can be an area where no image is displayed. In an embodiment, the planar shape of the display area DA can follow the planar shape of the display panel DPN. Figure 1 An embodiment is shown in which the display area DA has a quadrilateral planar shape. The display area DA can be located in the central area of ​​the display panel DPN, while the non-display area NDA can be located around the display area DA. For example, the non-display area NDA can surround the display area DA.

[0046] The display panel DPN may include a plurality of pixels PX arranged in the display area DA. For example, the display panel DPN may include a first pixel PX1 that emits light of a first color, a second pixel PX2 that emits light of a second color, and a third pixel PX3 that emits light of a third color. In an embodiment, the first color may be red, the second color may be green, and the third color may be blue, but they are not limited to these colors. At least one first pixel PX1, at least one second pixel PX2, and at least one third pixel PX3 adjacent to each other may form a unit pixel UPX capable of emitting light of various colors. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 arranged adjacent to each other in the Kth row (K is a positive integer) of the display area DA may form a unit pixel UPX. The number, type, and / or arrangement of pixels PX forming a unit pixel UPX may vary depending on the embodiment.

[0047] Each pixel PX may include at least one light-emitting element LE. For example, each pixel PX may include a single light-emitting element LE or may include multiple light-emitting elements LE.

[0048] The light-emitting element LE can have a circular shape, a quadrilateral shape, or another planar shape. For example, the shape of the light-emitting element LE can vary depending on the embodiment.

[0049] In an embodiment, the light-emitting element LE can be a microlight-emitting diode (microLED) with a small size in the micrometer (μm) range. For example, each light-emitting element LE can be a microLED having a length (e.g., horizontal length) in a first direction DR1, a length (e.g., vertical length) in a second direction DR2, and a length (e.g., thickness or height) in a third direction DR3, each dimension being from a few micrometers to several hundred micrometers. In an embodiment, the lengths of the light-emitting element LE in the first direction DR1, the second direction DR2, and the third direction DR3 can be approximately less than or equal to 100 μm, but are not limited to this size.

[0050] In one embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may each include a light-emitting element LE that emits light of a first color, a light-emitting element LE that emits light of a second color, and a light-emitting element LE that emits light of a third color, respectively. In another embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may each include a light-emitting element LE that emits light of the same color, and a light conversion pattern (e.g., a wavelength conversion pattern including quantum dots) and / or a color filter may be disposed in the emission region of the first pixel PX1, the second pixel PX2, and / or the third pixel PX3 to convert or control the color of the light emitted from the light-emitting element LE disposed in each pixel PX.

[0051] In this embodiment, pixels PX may be arranged in a matrix, strip, or any other form in the display area DA. The sizes of pixels PX (or the emission areas of pixels PX) may be substantially the same or different from each other.

[0052] In embodiments, pixel PX may have a quadrilateral planar shape (such as a rectangular or rhomboid shape), but the disclosure is not limited thereto. For example, pixel PX may have another polygonal shape (e.g., a hexagonal shape), a circular shape, an elliptical shape, or other planar shapes.

[0053] The non-display area NDA may include a first common voltage supply area CVA1, a second common voltage supply area CVA2, a first pad (also known as a "solder pad") area PDA1, a second pad area PDA2, and a peripheral area PHA.

[0054] A first common voltage supply region CVA1 can be located between a first pad region PDA1 and a display region DA. A second common voltage supply region CVA2 can be located between a second pad region PDA2 and a display region DA. Each of the first common voltage supply region CVA1 and the second common voltage supply region CVA2 may include a common electrode connection portion CVS electrically connected to a common electrode of pixel PX, a second pixel power line, etc. The second pixel voltage (e.g., common voltage) can be supplied to pixel PX through the common electrode connection portion CVS.

[0055] The common electrode connection portion CVS can be disposed in the common voltage supply region of the non-display area NDA (e.g., the first common voltage supply region CVA1 and / or the second common voltage supply region CVA2). The common electrode connection portion CVS may include a conductive material (e.g., a metallic material such as aluminum (Al)). Figure 1 and Figure 2 The illustration shows a display device 10 in which the common electrode connection portion CVS is located in the non-display area NDA, but the embodiment is not limited thereto. For example, the common electrode connection portion CVS may be located in the display area DA.

[0056] The common electrode connection portion CVS of the first common voltage supply region CVA1 can be electrically connected to any one of the first pads PD1 in the first pad region PDA1. For example, the common electrode connection portion CVS of the first common voltage supply region CVA1 can receive a second pixel voltage (e.g., common voltage) from any one of the first pads PD1 in the first pad region PDA1.

[0057] The first pad PD1 can be disposed in the first pad area PDA1. The first pad PD1 can be connected to the circuit board (not shown) via conductive connection members. For example, the first pad PD1 can be electrically connected to the circuit pad disposed on the circuit board via wiring.

[0058] The common electrode connection portion CVS of the second common voltage supply region CVA2 can be electrically connected to any one of the second pads in the second pad region PDA2. For example, the common electrode connection portion CVS of the second common voltage supply region CVA2 can receive a second pixel voltage (e.g., common voltage) from any one of the second pads in the second pad region PDA2. In an embodiment, the display panel DPN may not include the second common voltage supply region CVA2.

[0059] The first pad area PDA1 can be located on one side (e.g., the top side) of the display panel DPN. The first pad area PDA1 may include a first pad PD1 connected to an external circuit board.

[0060] The second pad region PDA2 can be located on one side (e.g., the lower side) of the display panel DPN. The second pad region PDA2 may include a second pad connected to an external circuit board. In an embodiment, the display panel DPN may not include the second pad region PDA2.

[0061] The second pad can be disposed in the second pad area PDA2 of the non-display area NDA. The second pad can be connected to a circuit board (not shown) via conductive connection members. For example, the second pad can be electrically connected to a circuit pad disposed on the circuit board via wiring.

[0062] The peripheral area PHA can be the remaining portion of the non-display area NDA, excluding the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. The peripheral area PHA can surround not only the display area DA, but also the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2.

[0063] Figure 3 This is a schematic cross-sectional view showing a display panel according to an embodiment. For example, Figure 3 The display panel DPN is shown with Figure 2 An embodiment of the cross section corresponding to line X1-X1', which is a schematic cross section of the first pixel PX1, the second pixel PX2 and the third pixel PX3 in the unit pixel area UPA of the display area DA.

[0064] Figure 3An embodiment is shown in which the display device 10 is a light-emitting diode (LEDoS) with a light-emitting element LE disposed on a semiconductor circuit substrate PCL formed using a semiconductor process on a silicon wafer. However, the device including the light-emitting element LE according to the embodiment is not limited to this configuration. For example, the light-emitting element LE manufactured according to the embodiment can be applied to display devices of various types and / or structures or can be applied to devices of different types and / or structures (such as lighting devices).

[0065] Reference Figures 1 to 3 The display panel DPN may include a semiconductor circuit substrate PCL (or a thin-film transistor substrate), a connection electrode CNE and a first insulating layer INS1 disposed on the semiconductor circuit substrate PCL, a bonding electrode BDE disposed on the connection electrode CNE and the first insulating layer INS1, and a light-emitting element LE disposed on the bonding electrode BDE. In an embodiment, the display panel DPN may further include contact electrodes CTE1 and CTE2 disposed on at least one surface of the light-emitting element LE, a second insulating layer INS2 surrounding a side surface or other area of ​​the light-emitting element LE, a reflective film RFL and a third insulating layer INS3, and at least one of a common electrode CME and a passivation layer PSV disposed on the light-emitting element LE. In an embodiment, the display panel DPN may further include an optical structure (or emission structure) disposed on the passivation layer PSV, for example, a lens-type optical structure LS. Although not explicitly stated in the original text... Figure 3 As shown, the display panel DPN may also include a protective layer covering a lens-type optical structure LS, etc.

[0066] A semiconductor circuit substrate PCL may include a display area DA in which pixel circuits PXC having pixels PX are formed. The semiconductor circuit substrate PCL may also include, for example... Figure 1 and Figure 2 The non-display area NDA is shown in the figure. For example, the semiconductor circuit substrate PCL may include a common electrode connection portion CVS, a first pad PD1, and / or a second pad disposed in the non-display area NDA.

[0067] A semiconductor circuit substrate (PCL) may include a substrate SB, pixel circuits PXC disposed or formed in the substrate SB, and pixel electrodes PXE (or connecting lines) connected to the respective pixel circuits PXC. The PCL may also include wiring connected to the pixels PXC. For example, the PCL may further include signal lines and power lines connected to the pixel circuits PXC (e.g., a first pixel power line to which a first pixel voltage is applied and a second pixel power line for applying a second pixel voltage). In describing embodiments, the term "connection" may refer to both electrical connection and / or physical connection.

[0068] In this embodiment, the semiconductor circuit substrate PCL can be formed using semiconductor processes employing silicon wafers. For example, the substrate SB can be a silicon wafer. In this embodiment, the substrate SB can be made of single-crystal silicon.

[0069] Pixel circuits (PXCs) can be disposed in a semiconductor circuit substrate (PCL) to correspond to the corresponding unit pixel region (UPA) where a corresponding pixel (PX) is disposed. In an embodiment, each of the pixel circuits (PXCs) may include complementary metal-oxide-semiconductor (CMOS) circuitry formed using semiconductor processes. In another embodiment, each of the pixel circuits (PXCs) may include at least one transistor and at least one capacitor, both formed using semiconductor processes. Figure 3 The schematic locations of pixel circuits PXC in the first pixel PX1, the second pixel PX2, and the third pixel PX3 are shown as examples of elements disposed in a semiconductor circuit substrate PCL.

[0070] Pixel electrodes PXE can be disposed on corresponding pixel circuits PXC. Pixel electrodes PXE can be connected to corresponding pixel circuits PXC. For example, the pixel circuit PXC of each pixel PX can be electrically connected to the pixel electrode PXE of the corresponding pixel PX. Pixel electrodes PXE can receive a first pixel voltage or anode voltage from the pixel circuit PXC.

[0071] In an embodiment, the pixel electrode PXE may be integrally formed with the corresponding pixel circuit PXC. For example, the pixel electrode PXE may be an exposed electrode (or wiring) protruding from the top surface of the corresponding pixel circuit PXC.

[0072] The pixel electrode (PXE) may include at least one conductive material. For example, the pixel electrode (PXE) may include, but is not limited to, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof.

[0073] Pixel electrodes PXE can be connected to light-emitting elements LE via connection electrodes CNE and bonding electrodes BDE. As an example, the pixel electrode PXE of each pixel PX can be electrically connected to the light-emitting element LE on the bonding electrode BDE via the corresponding pixel PX's connection electrode CNE and bonding electrode BDE.

[0074] A first insulating layer INS1 may be disposed on the pixel circuit PXC and the pixel electrode PXE. The first insulating layer INS1 may include an opening (e.g., a contact hole or via) that partially exposes the pixel electrode PXE. The opening may be filled with the connection electrode CNE. For example, the first insulating layer INS1 may surround the connection electrode CNE.

[0075] The first insulating layer INS1 may include at least one insulating material and may have a single-layer or multi-layer structure. In an embodiment, the first insulating layer INS1 may include an inorganic insulating material (e.g., silicon oxide (SiO2)). x Silicon nitride (SiN) x ), aluminum oxide (Al) x O y ), titanium dioxide (Ti x O y ), hafnium oxide (HfO) x (or other inorganic insulating materials), but not limited to these.

[0076] The connection electrode CNE can connect the semiconductor circuit substrate PCL to the bonding electrode BDE. For example, the connection electrode CNE can connect (e.g., electrically connect) the pixel circuit PXC of each pixel PX to the bonding electrode BDE. As an example, the connection electrode CNE can connect the pixel electrode PXE of each pixel in pixel PX to the bonding electrode BDE.

[0077] The connecting electrode CNE may include a conductive metal. For example, the connecting electrode CNE may include at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag).

[0078] The semiconductor circuit substrate PCL, the connection electrode CNE, and the first insulating layer INS1 can form the lower substrate 110 (e.g., a backplane substrate) of the display panel DPN. The bonding electrode BDE, the light-emitting element LE, etc. can be disposed on the lower substrate 110.

[0079] The bonding electrodes BDE can be disposed on the first insulating layer INS1. The bonding electrodes BDE can be separated from each other in the corresponding unit pixel region UPA where pixel PX is disposed. Therefore, the light-emitting element LE of pixel PX can be controlled individually. Each of the bonding electrodes BDE can be connected to the connection electrode CNE of the corresponding pixel PX. In an embodiment, the bonding electrodes BDE can be used as the anode electrode (or cathode electrode) of the light-emitting element LE or pixel PX.

[0080] The bonding electrode BDE may include multiple metal layers. For example, the bonding electrode BDE may include multiple bonding metal layers and a thin film layer disposed between the bonding metal layers. See below for further details. Figure 4 Description of embodiments related to the structure, materials, etc. of the bonding electrode BDE.

[0081] In an embodiment, the first contact electrode CTE1 may be disposed on each of the bonding electrodes BDE, and the light-emitting element LE may be disposed on the first contact electrode CTE1. Figure 3In the illustration, the first contact electrode CTE1 is shown as a component separate from the light-emitting element LE, but the embodiment is not limited thereto. For example, the first contact electrode CTE1 can be considered as a component included in the light-emitting element LE. The first contact electrode CTE1 can be formed or etched together with the light-emitting element LE, or it can be formed or etched separately from the light-emitting element LE.

[0082] In another embodiment, the light-emitting element LE or pixel PX may not include the first contact electrode CTE1. The light-emitting element LE may be directly disposed on the bonding electrode BDE of the pixel PX.

[0083] The first contact electrode CTE1 can be disposed on the surface (e.g., the bottom surface) of the first semiconductor layer SEM1. The first contact electrode CTE1 can protect the first semiconductor layer SEM1 and can smoothly connect the light-emitting element LE to the bonding electrode BDE.

[0084] In an embodiment, the first contact electrode CTE1 may be disposed entirely on the surface of the first semiconductor layer SEM1. For example, the first contact electrode CTE1 may be disposed entirely on the bottom surface of the first semiconductor layer SEM1. Therefore, the first semiconductor layer SEM1 can be appropriately or stably protected. However, the embodiment is not limited to this, and the first contact electrode CTE1 may be disposed only on a portion of the first semiconductor layer SEM1.

[0085] The first contact electrode CTE1 may include a metal, a metal oxide, or other conductive material. In embodiments, the first contact electrode CTE1 may be formed of a transparent electrode layer comprising a transparent conductive material (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), or another transparent conductive material), but is not limited thereto.

[0086] Each of the light-emitting elements LE can be disposed on the first contact electrode CTE1 (or bonding electrode BDE) of the corresponding pixel PX.

[0087] Each of the light-emitting elements (LEs) may include a first semiconductor layer SEM1, a light-emitting layer EML, and a second semiconductor layer SEM2 sequentially disposed on a first contact electrode CTE1. For example, the first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2 may be sequentially disposed or stacked on the first contact electrode CTE1 along a third direction DR3. The first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2 may include the same semiconductor material and may be formed by a semiconductor thin film layer (semiconductor epitaxial stack) or an epitaxial layer formed by epitaxial growth on a semiconductor substrate.

[0088] The first semiconductor layer SEM1 may include a semiconductor material doped with a first conductivity type dopant. For example, the first semiconductor layer SEM1 may be a semiconductor layer of the first conductivity type, including a nitride-based semiconductor material, a phosphide-based semiconductor material, or another semiconductor material, and may also include a dopant of the first conductivity type. In an embodiment, the first semiconductor layer SEM1 may be a p-type semiconductor layer (e.g., p-GaN) doped with p-type dopants (such as Mg, Zn, Ca, Sr, and Ba), but is not limited thereto.

[0089] The light-emitting layer EML can be disposed on the first semiconductor layer SEM1. For example, the light-emitting layer EML can be disposed between the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The light-emitting layer EML can emit light in response to the recombination of electron-hole pairs generated by an electrical signal applied via the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0090] The light-emitting layer (EML) may comprise a nitride-based semiconductor material, a phosphide-based semiconductor material, or another semiconductor material, and may have a single quantum well structure or a multi-quantum well structure. In embodiments, the EML may have a multi-quantum well structure, which includes, but is not limited to, a quantum well layer comprising InGaN and a barrier layer comprising GaN, AlGaN, or GaAlN. In embodiments where the EML comprises InGaN, the color of the light emitted from the EML can be adjusted by changing the indium (In) content.

[0091] In embodiments, the emissive layer EML can emit light in the visible light spectrum (e.g., light in the band approximately 400 nm to 900 nm). For example, the emissive layer EML can emit blue light with a peak wavelength in the range of approximately 440 nm to 480 nm, green light with a peak wavelength in the range of approximately 510 nm to 550 nm, or red light with a peak wavelength in the range of approximately 610 nm to 650 nm. The emissive layer EML can also emit light of a different color or wavelength than those described above.

[0092] The second semiconductor layer SEM2 may include a semiconductor material doped with a dopant of a second conductivity type. For example, the second semiconductor layer SEM2 may be a semiconductor layer of a second conductivity type, including a nitride-based semiconductor material, a phosphide-based semiconductor material, or another semiconductor material, and may also include a dopant of a second conductivity type. In an embodiment, the second semiconductor layer SEM2 may be an n-type semiconductor layer (e.g., n-GaN) doped with an n-type dopant (such as Si, Ge, Se, and Sn), but is not limited thereto.

[0093] In an embodiment, the second contact electrode CTE2 can be disposed on each of the light-emitting elements LE, and the common electrode CME can be disposed on the second contact electrode CTE2. For example, the second semiconductor layer SEM2 of the light-emitting element LE can be electrically connected to the common electrode CME through the second contact electrode CTE2.

[0094] exist Figure 3 In the illustration, the second contact electrode CTE2 is shown as a component separate from the light-emitting element LE, but the embodiment is not limited thereto. For example, the second contact electrode CTE2 can be considered as a component included in the light-emitting element LE. The second contact electrode CTE2 can be formed or etched together with the light-emitting element LE, or it can be formed or etched separately from the light-emitting element LE.

[0095] In another embodiment, the light-emitting element LE or pixel PX may not include the second contact electrode CTE2. The common electrode CME can be directly disposed on the light-emitting element LE. For example, if the light-emitting element LE or pixel PX does not include the second contact electrode CTE2, the second semiconductor layer SEM2 of the light-emitting element LE can directly contact the common electrode CME.

[0096] The second contact electrode CTE2 can be disposed on the surface (e.g., the top surface) of the second semiconductor layer SEM2. The second contact electrode CTE2 can protect the second semiconductor layer SEM2 and can smoothly connect the light-emitting element LE to the common electrode CME.

[0097] In an embodiment, the second contact electrode CTE2 may be disposed entirely on the surface of the second semiconductor layer SEM2. For example, the second contact electrode CTE2 may be disposed entirely on the top surface of the second semiconductor layer SEM2. Therefore, the second semiconductor layer SEM2 can be appropriately or stably protected. However, the embodiment is not limited to this, and the second contact electrode CTE2 may be disposed only on a portion of the second semiconductor layer SEM2.

[0098] The second contact electrode CTE2 may include a metal, a metal oxide, or other conductive material. In an embodiment, the second contact electrode CTE2 may be formed of a transparent electrode layer comprising a transparent conductive material (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), or another transparent conductive material). Therefore, light generated in the light-emitting element LE can pass through the second contact electrode CTE2 and be emitted onto the upper side of the light-emitting element LE.

[0099] The light-emitting element LE can be surrounded by a second insulating layer INS2, etc. For example, the side surface of each of the light-emitting elements LE can be surrounded by the second insulating layer INS2 and the reflective film RFL.

[0100] The second insulating layer INS2 may surround the side surface of the light-emitting element LE. In an embodiment, the second insulating layer INS2 may further surround the side surface of at least one of the bonding electrode BDE, the first contact electrode CTE1, and the second contact electrode CTE2. As an example, the second insulating layer INS2 may be disposed entirely in the display area DA to surround the side surfaces of the light-emitting element LE, the bonding electrode BDE, the first contact electrode CTE1, and the second contact electrode CTE2, and may include openings that expose a portion (e.g., a portion of the top surface) of each of the light-emitting element LE or the second contact electrode CTE2. In the opening portion of the second insulating layer INS2, the light-emitting element LE or the second contact electrode CTE2 may be connected to the common electrode CME.

[0101] The second insulating layer INS2 may include, for example, silicon oxide (SiO2). x (e.g., SiO2), silicon nitride (SiN) x (e.g., Si3N4), aluminum oxide (Al) x O y (e.g., Al2O3), titanium dioxide (Ti) x O y (e.g., TiO2) and hafnium oxide (HfO) x The second insulating layer INS2 can protect the light-emitting element LE, etc., and can ensure or improve the electrical characteristics of the light-emitting element LE by preventing short-circuit defects in the light-emitting element LE.

[0102] A reflective film RFL may be disposed on the second insulating layer INS2. The reflective film RFL may surround the side surface of each of the light-emitting elements LE. In an embodiment, the reflective film RFL may further surround the side surface of at least one of the bonding electrode BDE, the first contact electrode CTE1, and the second contact electrode CTE2. The reflective film RFL may be disposed individually in each unit pixel region UPA or may cover the entire display region DA, and may include openings that expose a portion (e.g., at least a portion of the top surface) of each of the light-emitting elements LE or the second contact electrode CTE2.

[0103] A reflective film RFL can be formed in each of the light-emitting elements LE, and can reflect and recycle light guided in the lateral direction, etc. The luminous efficiency of each of the light-emitting elements LE can be increased by the reflective film RFL (e.g., the ratio of light transmitted through the second contact electrode CTE2, the common electrode CME, etc., and emitted from the upper side of the light-emitting element LE).

[0104] The reflective film RFL can comprise a metallic material with high reflectivity (such as aluminum (Al)). In another embodiment, the reflective film RFL can comprise at least one pair (e.g., two or more pairs) of first and second layers with different refractive indices, arranged alternately, and thus can be used as a distributed Bragg reflector (DBR). The first and second layers can be formed of inorganic materials (such as silicon nitride (SiN)). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x ), titanium dioxide (Ti x O y ), aluminum oxide (Al) x O y )wait).

[0105] A third insulating layer INS3 can be disposed around the light-emitting element LE. As an example, the third insulating layer INS3 can fill the space between the light-emitting elements LE to surround the emitting area where the light-emitting elements LE are positioned. For instance, the third insulating layer INS3 can act as a filler to fill or occupy the gaps between the light-emitting elements LE.

[0106] The third insulating layer INS3 may be a single layer or multiple layers comprising at least one insulating material. In an embodiment, the third insulating layer INS3 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al) x O y ), titanium dioxide (Ti x O y ), hafnium oxide (HfO) x (or other inorganic insulating materials). In an embodiment, the third insulating layer INS3 may have a thickness sufficient to have a substantially flat top surface, or may have a substantially flat top surface by a planarization process performed after film formation. In another embodiment, the third insulating layer INS3 may include at least one organic insulating layer comprising an organic material, and the top surface of the third insulating layer INS3 may be substantially flat. For example, the third insulating layer INS3 may be a single-layer or multi-layer organic insulating layer comprising acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin or other organic insulating materials.

[0107] The third insulating layer INS3 can expose a portion (e.g., the top surface) of the light-emitting element LE. In one embodiment, the third insulating layer INS3 may have a height greater than or equal to the height of the light-emitting element LE, and may have an opening at the top of each of the light-emitting elements LE. In another embodiment, the third insulating layer INS3 may have a height less than or equal to the height of the light-emitting element LE. In another embodiment, the third insulating layer INS3 may have a height similar to the height of the light-emitting element LE. Therefore, the stepped portion of the common electrode CME can be mitigated, preventing the common electrode CME from disconnecting.

[0108] The common electrode CME can be disposed on both the light-emitting element LE and the third insulating layer INS3. For example, the common electrode CME can cover the entire display area DA. The common electrode CME can contact the second contact electrode CTE2 (or the light-emitting element LE) at the opening of the third insulating layer INS3. For example, the common electrode CME can be a common layer formed and / or connected to the light-emitting element LE and the pixels PX including the light-emitting element LE in the display area DA.

[0109] The common electrode CME can be electrically connected to a setting Figure 1 and Figure 2 The common electrode connection portion CVS is located in the first common voltage supply region CVA1 and / or the second common voltage supply region CVA2. Therefore, the common electrode CME can receive the common voltage through the common electrode connection portion CVS. In an embodiment, the common electrode CME can be connected within and / or around the display region DA to a power line (e.g., a second pixel power line) formed in the semiconductor circuit substrate PCL. The connection structure between the common electrode CME and the common electrode connection portion CVS can vary depending on the embodiment.

[0110] The common electrode CME can include a transparent conductive material capable of transmitting light. For example, the common electrode CME can be made of indium tin oxide (ITO), indium zinc oxide (IZO), or other transparent conductive materials. In embodiments, it can be used as the cathode electrode (or anode electrode) of a light-emitting element (LE) or a pixel (PX).

[0111] A passivation layer PSV can be disposed on the common electrode CME. In an embodiment, the passivation layer PSV may include a capping layer covering the entire display area DA to protect the common electrode CME. The capping layer may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al) x O yThe passivation layer PSV may be an inorganic insulating material or other insulating material, such as aluminum nitride (AlN). In another embodiment, the passivation layer PSV may also include an outer coating covering the overlay layer. The outer coating may include a material that provides appropriate protection for the display panel DPN (e.g., a material that absorbs or mitigates physical impacts on the display panel DPN). Additionally, the outer coating may planarize the top surface of the passivation layer PSV.

[0112] A lens-type optical structure LS can be disposed in the emission region of each pixel PX to be superimposed on the light-emitting element LE. In an embodiment, the lens-type optical structure LS can be an optical structure in the form of a convex lens disposed above the light-emitting element LE, but the type and / or form of the optical structure is not limited to this. By disposing the lens-type optical structure LS above the light-emitting element LE, the light-emitting characteristics of the pixel PX can be adjusted and / or improved.

[0113] The lens-type optical structure LS can be formed of a transparent material to transmit light emitted from the light-emitting element LE. As an example, the lens-type optical structure LS can be formed of glass, plastic, ceramic or other materials, and can be formed of an optical material with a high refractive index.

[0114] In an embodiment, the display panel DPN may include a protective layer covering the lens-type optical structure LS. As an example, the display panel DPN covering the entire display area DA may also include a protective layer extending across the lens-type optical structure LS. The protective layer may be formed of a transparent and durable material (e.g., plastic, plexiglass, optical glass, ceramic, etc.), and there are no specific limitations on the material, as long as it is suitable for protecting the lens-type optical structure LS, etc.

[0115] In embodiments, the display panel DPN or the display device 10 including the display panel DPN may further include additional components. For example, the display panel DPN or the display device 10 may include a light conversion layer disposed above the pixels PX (e.g., a light conversion layer containing a light conversion pattern of light-emitting elements LE distributed over the first pixel PX1, the second pixel PX2 and / or the third pixel PX3) or a color filter, etc.

[0116] Figure 4 It is shown Figure 3 A schematic cross-sectional view of an example of area A2. For example, Figure 4 The detailed structure of the bonding electrode BDE in the embodiment is shown.

[0117] Reference Figure 4 The bonding electrode BDE may include multiple layers comprising multiple bonding metal layers BMT. Each layer forming the bonding electrode BDE may include a conductive material to provide conductivity.

[0118] In an embodiment, the bonding metal layer BMT may include a first bonding metal layer BMT1 and a second bonding metal layer BMT2 sequentially disposed along a third direction DR3, and a third bonding metal layer BMT3 disposed between the first bonding metal layer BMT1 and the second bonding metal layer BMT2. A thin film layer DMT may be disposed between the bonding metal layers BMT. For example, the bonding electrode BDE may include a first thin film layer DMT1 disposed between the first bonding metal layer BMT1 and the third bonding metal layer BMT3, and a second thin film layer DMT2 disposed between the second bonding metal layer BMT2 and the third bonding metal layer BMT3.

[0119] In embodiments, the bonding electrode BDE may further include additional layers. As an example, the bonding electrode BDE may include a bonding layer AMT (also referred to as an "adhesive layer") disposed between the connecting electrode CNE and the first bonding metal layer BMT1, and a reflective layer RMT disposed on the second bonding metal layer BMT2. In embodiments, the bonding electrode BDE may further include at least one barrier layer BR. As an example, the bonding electrode BDE may include a first barrier layer BR1 disposed between the bonding layer AMT and the first bonding metal layer BMT1, and a second barrier layer BR2 and a third barrier layer BR3 disposed on both surfaces of the reflective layer RMT.

[0120] The first bonding metal layer BMT1, the second bonding metal layer BMT2, and the third bonding metal layer BMT3 may include conductive materials suitable for bonding. For example, the first bonding metal layer BMT1, the second bonding metal layer BMT2, and the third bonding metal layer BMT3 may include a metal or metal alloy having excellent electrical and thermal conductivity.

[0121] In embodiments, the bonding metal layer (BMT) may comprise a metal or alloy having properties suitable for bonding and exhibiting a low risk of foreign matter generation during processes such as etching. As an example, the bonding metal layer (BMT) may comprise titanium (Ti). For instance, the lower substrate 110 and the semiconductor substrate including the epitaxial layer (or light-emitting element LE) for forming the light-emitting element LE can be bonded by thermocompression bonding using titanium (Ti).

[0122] Titanium (Ti) exhibits relatively high reactivity, which reduces the risk of foreign matter formation during etching processes (e.g., wet etching processes), and due to its corrosion resistance, titanium (Ti) can serve as a highly reliable conductive material. In the case of using titanium (Ti) to form the bonding metal layer (BMT), the reliability of the bonding electrode (BDE) can be improved. However, the material of the bonding metal layer (BMT) is not limited to titanium (Ti). For example, the bonding metal layer (BMT) can include other highly reliable bonding metals such as zirconium (Zr), nickel (Ni), or chromium (Cr).

[0123] In an embodiment, the bonding metal layer BMT may comprise the same material. As an example, the first bonding metal layer BMT1, the second bonding metal layer BMT2, and the third bonding metal layer BMT3 may be metal layers comprising titanium (Ti) (e.g., made of titanium (Ti)).

[0124] In an embodiment, the first bonding metal layer BMT1 and the second bonding metal layer BMT2 may have thicknesses suitable for bonding. For example, the thickness of each of the first bonding metal layer BMT1 and the second bonding metal layer BMT2 may be in the range of about 100 nm to about 300 nm (e.g., about 200 nm), but is not limited to this range.

[0125] In an embodiment, the third bonding metal layer BMT3 can be bonded in the bonding process via a junction from the first bonding metal layer BMT1 and the second bonding metal layer BMT2 (or... Figure 9 and Figure 10 The third bonding metal layer BMT3 is formed by diffusion of bonding metals in the first bonding metal layer 140 and the second bonding metal layer 270. The thickness of the third bonding metal layer BMT3 may be less than or equal to the thickness of each of the first bonding metal layer BMT1 and the second bonding metal layer BMT2. For example, the thickness of the third bonding metal layer BMT3 may be less than the thickness of each of the first bonding metal layer BMT1 and the second bonding metal layer BMT2.

[0126] A first thin film layer DMT1 and a second thin film layer DMT2 may be disposed between a bonding metal layer BMT. The first thin film layer DMT1 and the second thin film layer DMT2 may have a material and / or thickness that promotes the diffusion of the bonding metal (e.g., titanium (Ti)) included in the first bonding metal layer BMT1 and the second bonding metal layer BMT2 during the bonding process. For example, the first thin film layer DMT1 and the second thin film layer DMT2 may be used as diffusion promoting layers (or capping layers) comprising a material that enhances the diffusion of atoms included in the bonding metal layer BMT during the bonding process for manufacturing a display panel DPN. The thicknesses of the first thin film layer DMT1 and the second thin film layer DMT2 can be selected to allow the bonding metal from the first bonding metal layer BMT1 and the second bonding metal layer BMT2 to diffuse effectively. The first thin film layer DMT1 and the second thin film layer DMT2 may also be referred to as the "first diffusion promoting layer" and the "second diffusion promoting layer," respectively.

[0127] In embodiments, the first thin film layer DMT1 and the second thin film layer DMT2 can be made of a material whose diffusion coefficient is enhanced due to high concentrations of grain boundaries and vacancies. For example, the first thin film layer DMT1 and the second thin film layer DMT2 can be made of a material having an atomic volume similar to, or greater than or equal to, about 80% of the atomic volume of the bonding metal (such as titanium (Ti)) included in the bonding metal layer BMT. As an example, each of the first thin film layer DMT1 and the second thin film layer DMT2 may include a material having an atomic volume greater than or equal to about 80% of the atomic volume of the bonding metal included in the bonding metal layer BMT. By using a material having an atomic volume greater than or equal to about 80% of the atomic volume of the bonding metal, the diffusion of the bonding metal can be effectively promoted.

[0128] Table 1 below shows the calculated equilibrium atomic volumes for several metals, including titanium (Ti). Table 1 is expressed in Ω... The calculated equilibrium atomic volume, Ω, is shown for each metal. This represents the equilibrium atomic volume calculated in a face-centered cubic (FCC) structure.

[0129] [Table 1]

[0130] In an embodiment, where the bonding metal layer BMT comprises titanium (Ti), the first thin film layer DMT1 and the second thin film layer DMT2 may comprise a material having an atomic volume greater than or equal to about 80% of the atomic volume of titanium (Ti). For example, each of the first thin film layer DMT1 and the second thin film layer DMT2 comprises at least one of gold (Au), zirconium (Zr), silver (Ag), hafnium (Hf), palladium (Pd), and platinum (Pt).

[0131] Because the dimensions (e.g., atomic volumes) of the materials included in the first thin film layer DMT1 and the second thin film layer DMT2 are larger than the dimensions of the bonding metal, they can promote diffusion. For example, the bonding metal layer BMT can be formed of titanium (Ti), while the first thin film layer DMT1 and the second thin film layer DMT2 can be formed of gold (Au), zirconium (Zr), or hafnium (Hf). This can enhance the diffusion-promoting effect, leading to an increase in the diffusion length of the bonding metal. Therefore, the roughness margin of the bonding metal layer BMT can be larger, and the bonding process can be performed smoothly even at low temperatures.

[0132] In an embodiment, where the bonding metal layer BMT includes zirconium (Zr), the first thin film layer DMT1 and the second thin film layer DMT2 may be made of a material having an atomic volume greater than or equal to about 80% of the atomic volume of zirconium (Zr). For example, each of the first thin film layer DMT1 and the second thin film layer DMT2 may be made of zirconium (Zr) or hafnium (Hf).

[0133] In this embodiment, the bonding metal layer BMT, the first thin film layer DMT1, and the second thin film layer DMT2 can all be made of the same material. For example, all of the bonding metal layer BMT, the first thin film layer DMT1, and the second thin film layer DMT2 can be formed of zirconium (Zr). However, the bonding metal layer BMT, the first thin film layer DMT1, and the second thin film layer DMT2 may not be deposited simultaneously, but may be deposited or formed sequentially, so that the bonding metal layer BMT, the first thin film layer DMT1, and the second thin film layer DMT2 can be formed from separate individual films with distinguishable boundaries.

[0134] Because the diffusion coefficient of the bonding metal increases due to the first thin film layer DMT1 and the second thin film layer DMT2, the diffusion length of the bonding metal can be increased. Therefore, the bonding process can proceed smoothly, allowing the atoms of the bonding metal to diffuse uniformly and / or appropriately without the need for separate planarization processes (such as chemical mechanical polishing (CMP)) to reduce the roughness of the bonding metal layer BMT. For example, by promoting the diffusion of the bonding metal via the first thin film layer DMT1 and the second thin film layer DMT2, the diffusion length of the bonding metal can be increased to an amount exceeding or equal to the initial roughness of the bonding metal layer BMT. For example, this process can increase the roughness margin of the bonding metal layer BMT, adapting to the initial roughness conditions of the bonding metal layer BMT by the enhanced diffusion provided by the first thin film layer DMT1 and the second thin film layer DMT2. As an example, by promoting the diffusion of the bonding metal via the first thin film layer DMT1 and the second thin film layer DMT2, the diffusion length of the bonding metal can be increased to a roughness greater than or equal to approximately 2 nm to approximately 4 nm (e.g., approximately 3 nm) (corresponding to the initial roughness without performing a planarization process after depositing the bonding metal layer BMT). Therefore, the bonding process can be performed immediately after depositing the bonding metal layer BMT without performing a planarization process on the bonding metal layer BMT.

[0135] In an embodiment, to facilitate the diffusion of the bonding metal through the first thin film layer DMT1 and the second thin film layer DMT2, the first thin film layer DMT1 and the second thin film layer DMT2 may be formed of thin films having a defined thickness. For example, each of the first thin film layer DMT1 and the second thin film layer DMT2 may have a thickness less than or equal to the diffusion length of the bonding metal included in the first bonding metal layer BMT1 or the second bonding metal layer BMT2.

[0136] In an embodiment, each of the first thin film layer DMT1 and the second thin film layer DMT2 may have a thickness in the range of about 1 nm to about 50 nm. As an example, each of the first thin film layer DMT1 and the second thin film layer DMT2 may have a thickness of approximately 10 nm to 20 nm. Therefore, since the bonding metal can pass through the first thin film layer DMT1 and the second thin film layer DMT2 and move or diffuse to the interface between the first thin film layer DMT1 and the second thin film layer DMT2, wafer-to-wafer bonding and the like can be suitably performed.

[0137] By promoting the diffusion of the bonding metal via the first thin film layer DMT1 and the second thin film layer DMT2, the temperature required for the bonding process can be reduced. For example, since the diffusion length of the bonding metal is increased due to the first thin film layer DMT1 and the second thin film layer DMT2, the bonding process (e.g., thermoforming wafer bonding) can be performed at a low temperature of approximately 200°C or lower without performing a separate planarization process on the bonding metal layers. Promoting the diffusion of the bonding metal via the first thin film layer DMT1 and the second thin film layer DMT2 can shorten the time required for the bonding process. For example, the time required for the bonding process can be shortened, such as from approximately 2 hours to approximately 1 hour.

[0138] By omitting the planarization process used for bonding the metal layer BMT, damage to the reflective layer RMT caused by chemicals in the planarization process, etc., can be prevented (e.g., corrosion or peeling of reflective layer RMTs, including those with weak chemical resistance such as aluminum (Al)). Therefore, the reliability of the reflective layer RMT and the bonding electrode BDE including the reflective layer RMT can be improved without requiring a shielding process to protect the reflective layer RMT. Since the bonding process temperature is lowered, the risk of degradation of surrounding components during the bonding process can be minimized.

[0139] Therefore, the manufacturing process of the display device 10, including the bonding process for bonding the light-emitting element LE (or an epitaxial layer including a semiconductor layer forming the light-emitting element LE) to the lower substrate 110, can be simplified or streamlined, reducing manufacturing costs. Furthermore, the overall reliability of the display device 10 can be enhanced by improving the reliability of the bonding electrode BDE.

[0140] In description Figure 3 and Figure 4 In the embodiments described, based on the bonding electrode BDE included in the display panel DPN, the simplification effect of the bonding process has been described in conjunction with the materials and / or thicknesses of the bonding metal layer BMT and the thin film layer DMT included in the bonding electrode BDE of the display panel DPN. This effect can be achieved in the manufacturing process of the display panel DPN. For example, Figure 4The first bonding metal layer BMT1, the second bonding metal layer BMT2, and the third bonding metal layer BMT3 can respectively correspond to Figure 10 The first bonding metal layer 140, the second bonding metal layer 270, and the third bonding metal layer 300. Similarly, Figure 4 The first thin film layer DMT1 and the second thin film layer DMT2 can be respectively with Figure 10 The first thin film layer 150 and the second thin film layer 280 correspond to each other. Figure 10 During the bonding process shown, diffusion of bonding metal from the first bonding metal layer BMT1 and the second bonding metal layer BMT2 can be promoted through the first thin film layer DMT1 and the second thin film layer DMT2, so that the third bonding metal layer BMT3 can be properly formed without performing a planarization process for planarizing the first bonding metal layer BMT1 and the second bonding metal layer BMT2.

[0141] A bonding layer AMT can be disposed on the connection electrode CNE. The bonding layer AMT may include a conductive material that enhances the adhesion between the connection electrode CNE and the bonding electrode BDE. In embodiments, the bonding layer AMT and the bonding metal layer BMT may include the same material (such as titanium (Ti)), but are not limited thereto. For example, the bonding layer AMT may include other metals (such as chromium (Cr)). The bonding electrode BDE and the connection electrode CNE can be stably bonded or connected through the bonding layer AMT.

[0142] The first barrier layer BR1 can be disposed on the bonding layer AMT. The second barrier layer BR2 and the third barrier layer BR3 can be disposed on two surfaces of the reflective layer RMT. For example, the second barrier layer BR2 can be disposed on the bottom surface of the reflective layer RMT, while the third barrier layer BR3 can be disposed on the top surface of the reflective layer RMT.

[0143] Each of the first barrier layer BR1, the second barrier layer BR2, and the third barrier layer BR3 may include a material suitable for preventing diffusion (e.g., preventing intermetallic diffusion) (e.g., a conductive material), and may include the same or different materials. Each of the first barrier layer BR1, the second barrier layer BR2, and the third barrier layer BR3 may be formed of a material that ensures the conductivity of the bonding electrode BDE and / or has a thickness that ensures the conductivity of the bonding electrode BDE. In an embodiment, each of the first barrier layer BR1, the second barrier layer BR2, and the third barrier layer BR3 may include a material with a high intermetallic diffusion prevention effect (such as titanium nitride (TiN)) and may be formed as a thin film with a defined thickness (e.g., less than or equal to about 20 nm). However, the materials of the first barrier layer BR1, the second barrier layer BR2, and the third barrier layer BR3 are not limited thereto. For example, the first barrier layer BR1, the second barrier layer BR2, and the third barrier layer BR3 may include a metal such as nickel (Ni).

[0144] The reflective layer RMT can be disposed on the second bonding metal layer BMT2. The bottom and top surfaces of the reflective layer RMT can be covered by the second barrier layer BR2 and the third barrier layer BR3, respectively.

[0145] The reflective RMT can include a metal with high light reflectivity. As an example, the reflective RMT can be made of aluminum (Al). However, the material of the reflective RMT is not limited to this. For example, the reflective RMT can also include other metals with high reflectivity, such as molybdenum (Mo), titanium (Ti), copper (Cu), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), or chromium (Cr)).

[0146] Figures 5 to 10 This is a schematic perspective view illustrating a method for manufacturing a display device according to an embodiment. For example, Figures 5 to 10 The illustration shows the manufacturing steps for preparing a first substrate 100 and a second substrate 200 for manufacturing a display panel DPN, and for bonding the first substrate 100 and the second substrate 200, according to an embodiment.

[0147] In an embodiment, Figures 5 to 10 The first substrate 100 and the second substrate 200 may include multiple unit regions for simultaneously manufacturing multiple display panel DPNs. However, the embodiments are not limited thereto. For example, the first substrate 100 and the second substrate 200 may be prepared in a size suitable for manufacturing a single display panel DPN.

[0148] Reference Figure 5 and Figure 6 A first substrate 100, including a lower substrate 110 of a display panel DPN, can be fabricated. In an embodiment, the lower substrate 110 may include, for example, Figure 3 The semiconductor circuit substrate PCL shown is illustrated. The lower substrate 110 may further include a connection electrode CNE and a first insulating layer INS1 on the semiconductor circuit substrate PCL. For example, as shown... Figure 3 As shown, the lower substrate 110 can be fabricated by forming a semiconductor circuit substrate PCL including a substrate SB, pixel circuits PXC, and pixel electrodes PXE, and by forming a first insulating layer INS1 and a connection electrode CNE on the semiconductor circuit substrate PCL. The lower substrate 110 may include cell regions for forming at least one display panel DPN. As an example, it can be fabricated with dimensions and shapes including multiple cell regions for simultaneously manufacturing multiple display panel DPNs. Figure 5 The lower base 110.

[0149] After that, as Figure 6As shown, multiple layers of lower bonding layers 120, 130, 140 and 150 may be formed on the lower substrate 110. For example, bonding material layer 120, first barrier material layer 130, first bonding metal layer 140 (also referred to as "first bonding material layer") and first thin film layer 150 (also referred to as "first thin film material layer") may be sequentially formed (e.g., deposited) on the lower substrate 110.

[0150] Lower bonding layers 120, 130, 140, and 150 can be used to form the bonding electrode BDE of pixel PX, and the lower layer of each of the bonding electrodes BDEs can be formed by lower bonding layers 120, 130, 140, and 150. As an example, Figure 4 The bonding layer AMT, the first barrier layer BR1, the first bonding metal layer BMT1, and the first thin film layer DMT1 can be formed from the lower bonding layers 120, 130, 140, and 150.

[0151] The bonding material layer 120 can be used to form a bonding layer AMT for each of the bonding electrodes BDEs, and can be formed using materials such as those previously described as suitable for bonding layer AMTs. The bonding material layer 120 can be patterned into a bonding layer AMT for each of the bonding electrodes BDEs by an etching process performed after the bonding process.

[0152] The first barrier material layer 130 can be used to form the first barrier layer BR1 of each of the bonding electrodes BDE, and can be formed using materials such as those previously described as the material of the first barrier layer BR1. The first barrier material layer 130 can be patterned into the first barrier layer BR1 of each of the bonding electrodes BDE by an etching process performed after the bonding process.

[0153] The first bonding metal layer 140 can be used to form the first bonding metal layer BMT1 of each of the bonding electrodes BDEs, and can be formed using materials such as those previously described as materials for the first bonding metal layer BMT1. For example, the first bonding metal layer 140 can be formed of titanium (Ti), or it can be formed of zirconium (Zr), nickel (Ni), chromium (Cr), etc. The first bonding metal layer 140 can have a thickness suitable for bonding processes (e.g., wafer-to-wafer bonding via hot pressing). For example, the first bonding metal layer 140 can have a thickness in the range of about 100 nm to about 300 nm (e.g., about 200 nm), but is not limited thereto. The first bonding metal layer 140 can be patterned into the first bonding metal layer BMT1 of each of the bonding electrodes BDEs by an etching process performed after the bonding process.

[0154] The first thin film layer 150 can be used to form the first thin film layer DMT1 of each of the bonding electrodes BDE, and can be formed using materials such as those previously described as materials for the first thin film layer DMT1. For example, the first thin film layer 150 can be formed of gold (Au) or zirconium (Zr), or it can be formed of silver (Ag), hafnium (Hf), palladium (Pd), platinum (Pt), etc. The first thin film layer 150 can have a thickness suitable for promoting the diffusion of the bonding metal (e.g., titanium (Ti)). For example, the first thin film layer 150 can have a thickness in the range of about 1 nm to about 50 nm (e.g., about 10 nm to about 20 nm), but is not limited thereto. The first thin film layer 150 can be patterned into the first thin film layer DMT1 of each of the bonding electrodes BDE by an etching process performed after the bonding process.

[0155] Reference Figure 7 and Figure 8 A second substrate 200 can be fabricated for forming the light-emitting element LE of the display panel DPN. For example, such as Figure 7 As shown, an epitaxial layer 220 can be formed on a semiconductor substrate 210.

[0156] Semiconductor substrate 210 can be a manufacturing substrate used to manufacture light-emitting elements LE. For example, semiconductor substrate 210 can be a growth substrate suitable for epitaxial growth.

[0157] In embodiments, the semiconductor substrate 210 may include materials such as GaAs, silicon (Si), sapphire, SiC, GaN, or ZnO. As an example, the semiconductor substrate 210 may be a silicon substrate or a sapphire substrate. The type or material of the semiconductor substrate 210 is not particularly limited provided that epitaxial growth of the epitaxial layer 220 for fabricating the light-emitting element LE can be successfully achieved.

[0158] Epitaxial layer 220 can be used to form the semiconductor layer of each of the light-emitting elements LE. For example, Figure 3 and Figure 4The first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2 of each of the light-emitting elements LE shown can be formed by an epitaxial layer 220. The epitaxial layer 220 may include a first epitaxial layer 221 (e.g., an n-type semiconductor layer) for forming the second semiconductor layer SEM2 of the light-emitting element LE, a second epitaxial layer 222 (e.g., a multi-quantum-well layer including a quantum well layer and a barrier layer) for forming the light-emitting layer EML of the light-emitting element LE, and a third epitaxial layer 223 (e.g., a p-type semiconductor layer) for forming the first semiconductor layer SEM1 of the light-emitting element LE. For example, the first epitaxial layer 221, the second epitaxial layer 222, and the third epitaxial layer 223 can be sequentially formed (e.g., deposited) on a semiconductor substrate 210 using the materials previously described as materials for the second semiconductor layer SEM2, the light-emitting layer EML, and the first semiconductor layer SEM1 of the light-emitting element LE.

[0159] After that, as Figure 8 As shown, multiple bonding layers 230, 240, 250, 260, 270, and 280 can be formed on the epitaxial layer 220. For example, a first contact material layer 230, a second barrier material layer 240, a reflective material layer 250, a third barrier material layer 260, a second bonding metal layer 270 (also referred to as the "second bonding material layer"), and a second thin film layer 280 (also referred to as the "second thin film material layer") can be sequentially formed (e.g., deposited) on the epitaxial layer 220.

[0160] Upper bonding layers 230, 240, 250, 260, 270, and 280 can be used to form the bonding electrode BDE and the first contact electrode CTE1 of the pixel PX. For example, the first contact electrode CTE1 can be formed by the first contact material layer 230. The upper layer of each of the bonding electrodes BDE (e.g., Figure 4 The third barrier layer BR3, the reflective layer RMT, the second barrier layer BR2, the second bonding metal layer BMT2, and the second thin film layer DMT2 can be formed from the second barrier material layer 240, the reflective material layer 250, the third barrier material layer 260, the second bonding metal layer 270, and the second thin film layer 280 of the second substrate 200, respectively.

[0161] The first contact material layer 230 can be used to form the first contact electrode CTE1 of the pixel PX, and can be formed using a material previously described as the material for the first contact electrode CTE1 (e.g., ITO, etc.). In embodiments, the first contact material layer 230 can have a thickness suitable for use as a contact electrode for smoothly connecting the light-emitting element LE to the corresponding bonding electrode BDE. As an example, the first contact material layer 230 can have a thickness of approximately 100 nm, but is not limited thereto. The first contact material layer 230 can be patterned into the first contact electrode CTE1 of each of the pixels PX by an etching process performed after the bonding process.

[0162] The second barrier material layer 240 can be used to form the third barrier layer BR3 of each of the bonding electrodes BDE, and can be formed using materials previously described as materials for the third barrier layer BR3 (e.g., TiN, etc.). In embodiments, the second barrier material layer 240 can be a thin film formed with a defined thickness (e.g., less than or equal to about 20 nm), but is not limited thereto. The second barrier material layer 240 can be patterned into the third barrier layer BR3 of each of the bonding electrodes BDE by an etching process performed after the bonding process.

[0163] The reflective material layer 250 can be used to form the reflective layer RMT of each of the bonding electrodes BDEs, and can be formed using materials previously described as materials for the reflective layer RMT (e.g., Al, etc.). In embodiments, the reflective material layer 250 can have a thickness that appropriately reflects light emitted from the light-emitting element LE (e.g., a thickness that ensures a target reflectivity). As an example, the reflective material layer 250 can have a thickness in the range of about 100 nm to about 200 nm, but is not limited thereto. The reflective material layer 250 can be patterned into the reflective layer RMT of each of the bonding electrodes BDEs by an etching process performed after the bonding process.

[0164] The third barrier material layer 260 can be used to form the second barrier layer BR2 in each of the bonding electrodes BDE, and can be formed using materials previously described as materials for the second barrier layer BR2 (e.g., TiN, etc.). In embodiments, the third barrier material layer 260 can be a thin film formed with a defined thickness (e.g., less than or equal to about 20 nm), but is not limited thereto. The third barrier material layer 260 can be patterned into the second barrier layer BR2 in each of the bonding electrodes BDE by an etching process performed after the bonding process.

[0165] The second bonding metal layer 270 can be used to form the second bonding metal layer BMT2 of each of the bonding electrodes BDE, and can be formed using the materials previously described as the materials for the second bonding metal layer BMT2. For example, the second bonding metal layer 270 can be formed of titanium (Ti), or it can be formed of zirconium (Zr), nickel (Ni), chromium (Cr), etc. The second bonding metal layer 270 can have a thickness suitable for bonding processes (e.g., wafer-to-wafer bonding via hot pressing). For example, the second bonding metal layer 270 can have a thickness in the range of about 100 nm to about 300 nm (e.g., about 200 nm), but is not limited thereto. The second bonding metal layer 270 can be patterned into the second bonding metal layer BMT2 of each of the bonding electrodes BDE by an etching process performed after the bonding process.

[0166] The second thin film layer 280 can be used to form the second thin film layer DMT2 of each of the bonding electrodes BDE, and can be formed using the materials previously described as the materials for the second thin film layer DMT2. For example, the second thin film layer 280 can be formed of gold (Au) or zirconium (Zr), or it can be formed of silver (Ag), hafnium (Hf), palladium (Pd), platinum (Pt), etc. The second thin film layer 280 can have a thickness suitable for promoting the diffusion of the bonding metal (e.g., titanium (Ti)). For example, the second thin film layer 280 can have a thickness in the range of about 1 nm to about 50 nm (e.g., about 10 nm to about 20 nm), but is not limited thereto. The second thin film layer 280 can be patterned into the second thin film layer DMT2 of each of the bonding electrodes BDE by an etching process performed after the bonding process.

[0167] Reference Figure 9 and Figure 10 The first substrate 100 and the second substrate 200 can be positioned facing each other, and a bonding process can be performed. For example, after the second substrate 200 is disposed on the first substrate 100 such that the first thin film layer 150 of the first substrate 100 and the second thin film layer 280 of the second substrate 200 face each other, heat and pressure can be applied to bond the first substrate 100 and the second substrate 200. For example, a wafer-to-wafer bonding method can be used to bond the first substrate 100 and the second substrate 200. In embodiments, the bonding process can be performed at a process temperature of about 200°C or lower for approximately 1 hour, but is not limited thereto.

[0168] The diffusion of bonding metal from the first bonding metal layer 140 and the second bonding metal layer 270 can be facilitated by the first thin film layer 150 and the second thin film layer 280. For example, the bonding metal from the first bonding metal layer 140 and the second bonding metal layer 270 can diffuse to the interface between the first substrate 100 and the second substrate 200 to form a third bonding metal layer 300 (also referred to as a "third bonding material layer"). As an example, the step of bonding the first substrate 100 and the second substrate 200 may include the step of forming a third bonding metal layer 300 comprising bonding metal (e.g., bonding metal diffused from the first bonding metal layer 140 and the second bonding metal layer 270) between the first thin film layer 150 and the second thin film layer 280. Thus, the first substrate 100 and the second substrate 200 can be suitably bonded.

[0169] The first bonding metal layer 140, the second bonding metal layer 270, and the third bonding metal layer 300 may comprise the same material. For example, the third bonding metal layer 300 may comprise the bonding metal contained in the first bonding metal layer 140 and the second bonding metal layer 270. The third bonding metal layer 300 may be patterned as the third bonding metal layer BMT3 of each of the bonding electrodes BDEs by an etching process performed after the bonding process.

[0170] Figures 11 to 18 This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment. For example, Figures 11 to 18 The pixel process is illustrated after the first substrate 100 and the second substrate 200 are bonded. The pixel process may include forming a pixel PX, comprising a light-emitting element LE, in each cell region on the first substrate 100. Figures 11 to 18 Only a portion of a cell region is shown (e.g., the cell pixel region UPA located within a cell region). Figures 11 to 18 The unit pixel region UPA can correspond to Figure 3 The unit pixel area UPA.

[0171] Apart from Figure 10 In addition, refer to Figure 11 and Figure 12 In such Figure 10 and Figure 11 In the state shown where the second substrate 200 is bonded to the first substrate 100, the semiconductor substrate 210 can be separated from the epitaxial layer 220. Therefore, as Figure 12 As shown, the semiconductor substrate 210 can be removed over the epitaxial layer 220.

[0172] Reference Figure 13A second contact material layer 400 can be formed (e.g., deposited) on the epitaxial layer 220. The second contact material layer 400 can be used to form the second contact electrode CTE2 of the pixel PX, and can be formed using materials previously described as materials for the second contact electrode CTE2 (e.g., ITO, etc.). In embodiments, the second contact material layer 400 can have a thickness suitable for use as a contact electrode for smoothly connecting the light-emitting element LE to the common electrode CME. The second contact material layer 400 can allow the transmission of light emitted from the light-emitting element LE. As an example, the second contact material layer 400 can have a thickness of approximately 100 nm, but is not limited thereto. The second contact material layer 400 can be patterned into the second contact electrode CTE2 of each of the pixels PX by a subsequent etching process. In embodiments, when manufacturing a display panel DPN without the second contact electrode CTE2 (e.g., a display panel DPN in which the common electrode CME is directly disposed on the light-emitting element LE), the process steps for forming the second contact material layer 400 can be omitted.

[0173] Apart from Figure 13 In addition, refer to Figure 14 The bonding electrode BDE, the first contact electrode CTE1, the light-emitting element LE, and the second contact electrode CTE2 can be formed in each pixel PX by etching the lower bonding layers 120, 130, 140, and 150, the third bonding metal layer 300, the upper bonding layers 230, 240, 250, 260, 270, and 280, the epitaxial layer 220, and the second contact material layer 400. In embodiments, one or more masking processes can be used to etch the lower bonding layers 120, 130, 140, and 150, the third bonding metal layer 300, the upper bonding layers 230, 240, 250, 260, 270, and 280, the epitaxial layer 220, and the second contact material layer 400 into the desired shape and size.

[0174] Reference Figure 15 A second insulating layer INS2 and a reflective film RFL can be formed around the side surface of the light-emitting element LE, etc. The second insulating layer INS2 and the reflective film RFL can be formed using the materials described above. An opening can be made in the second insulating layer INS2 and the reflective film RFL at the top of each of the light-emitting elements LE. Figure 15 An embodiment is shown in which the second insulating layer INS2 and the reflective film RFL are opened before the formation of the third insulating layer INS3, etc., but the embodiment is not limited thereto. For example, after the formation of the third insulating layer INS3, the second insulating layer INS2 and the reflective film RFL can be opened together with the third insulating layer INS3 at the top of each of the light-emitting elements LE.

[0175] Reference Figure 16A third insulating layer INS3 can be formed on the second insulating layer INS2 and the reflective film RFL. The third insulating layer INS3 can be formed entirely on the lower substrate 110, etc., using the materials described above to fill the space between the light-emitting elements LE. An opening in the third insulating layer INS3 can be made at the top of each of the light-emitting elements LE by an etching process, etc.

[0176] Reference Figure 17 A common electrode CME can be formed on the third insulating layer INS3. The aforementioned material can be used to form the entire common electrode CME on the light-emitting element LE.

[0177] Reference Figure 18 A passivation layer PSV can be formed on the common electrode CME. The above-described material can be used to form the passivation layer PSV entirely on the common electrode CME.

[0178] In an embodiment, where the display panel DPN includes additional elements disposed on the passivation layer PSV, processes for forming or disposing of those elements can subsequently be performed. For example, in manufacturing processes including... Figure 3 In the case of the display panel DPN (or display device 10) with the lens-type optical structure LS shown, the lens-type optical structure LS can be formed or disposed on the passivation layer PSV. Therefore, it is possible to complete... Figure 3 The display panel DPN.

[0179] As described above, in the display device 10 and the method of manufacturing the display device 10 according to the embodiment, the diffusion of the bonding metal can be facilitated by forming a first thin film layer 150 on a first bonding metal layer 140 of a first substrate 100 and a second thin film layer 280 on a second bonding metal layer 270 of a second substrate 200. The first substrate 100 includes a lower substrate 110 of a display panel DPN, and the second substrate 200 includes an epitaxial layer 220 for forming a light-emitting element LE. Therefore, the first substrate 100 and the second substrate 200 can be smoothly bonded without performing a planarization process for planarizing the first bonding metal layer 140 and / or the second bonding metal layer 270.

[0180] According to the embodiments, the manufacturing efficiency of the display device 10 can be improved. For example, the manufacturing process of the display device 10 formed from the first substrate 100 and the second substrate 200 can be simplified or streamlined, thereby reducing manufacturing costs.

[0181] Figure 19 This is a schematic diagram illustrating a smartwatch including a display device according to an embodiment. (Refer to...) Figure 19 The display device 10_1 according to the embodiment can be applied to a smartwatch 1000_1, which is an example of a smart device.

[0182] Figure 20 and Figure 21 This is a schematic diagram illustrating a virtual reality device including a display device according to an embodiment.

[0183] Reference Figure 20 and Figure 21 According to an embodiment, the head-mounted display 1000_2 may include a first display device 10_2, a second display device 10_3, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0184] The first display device 10_2 provides an image to the user's left eye, and the second display device 10_3 provides an image to the user's right eye. Because each of the first display device 10_2 and the second display device 10_3 is combined... Figure 1 and Figure 2 The display devices 10 described are substantially the same, so the descriptions of the first display device 10_2 and the second display device 10_3 will be omitted.

[0185] The first optical component 1510 may be disposed between the first display device 10_2 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_3 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0186] The intermediate frame 1400 can be disposed between the first display device 10_2 and the control circuit board 1600, and between the second display device 10_3 and the control circuit board 1600. The intermediate frame 1400 can be used to support and fix the first display device 10_2, the second display device 10_3, and the control circuit board 1600.

[0187] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_2 and the second display device 10_3 via connectors. The control circuit board 1600 can convert image sources input from external sources into video data and transmit the video data to the first display device 10_2 and the second display device 10_3 via connectors.

[0188] The control circuit board 1600 can transmit video data corresponding to a left-eye image optimized for the user's left eye to the first display device 10_2, and can transmit video data corresponding to a right-eye image optimized for the user's right eye to the second display device 10_3. In another embodiment, the control circuit board 1600 can transmit the same video data to both the first display device 10_2 and the second display device 10_3.

[0189] The display device housing 1100 can accommodate a first display device 10_2, a second display device 10_3, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 can cover one opening surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Although... Figure 20 and Figure 21 The first eyepiece 1210 and the second eyepiece 1220 are shown as separate components, but the disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may also be combined into one.

[0190] The first eyepiece 1210 can be aligned with the first display device 10_2 and the first optical component 1510, while the second eyepiece 1220 can be aligned with the second display device 10_3 and the second optical component 1520. Therefore, a user can view an image magnified into a virtual image by the first optical component 1510 from the first display device 10_2 through the first eyepiece 1210, and can view an image magnified into a virtual image by the second optical component 1520 from the second display device 10_3 through the second eyepiece 1220.

[0191] The headband 1300 secures the display device housing 1100 to the user's head, ensuring that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are aligned with the user's left and right eyes, respectively. In a lightweight and compact manner, the head-mounted display 1000_2 can replace the headband 1300 as... Figure 22 The eyeglass frames shown are provided.

[0192] The head-mounted display 1000_2 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal. The wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0193] Figure 22This is a schematic diagram illustrating a virtual reality device including a display device according to another embodiment. Figure 22 A virtual reality device 1000_3 is shown, in which a display device 10_4 is applied according to an embodiment.

[0194] Reference Figure 22 According to the embodiment, the virtual reality device 1000_3 can be an eyeglasses-type device. The virtual reality device 1000_3 may include a display device 10_4, a left eye lens 10a, a right eye lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0195] Figure 22 The virtual reality device 1000_3 is shown to be an eyeglass-type display device including temples 30a and 30b. The virtual reality device 1000_3 is not limited to... Figure 22 It takes the form shown and can be applied in various forms to different electronic devices.

[0196] The display device housing 50 may include a display device 10_4 and a reflective member 40. The image displayed on the display device 10_4 can be reflected by the reflective member 40 and provided to the user's right eye through the right eye lens 10b. Therefore, the user can view the virtual reality image displayed on the display device 10_4 with their right eye.

[0197] although Figure 22 The display device housing 50 is shown positioned at the right end of the support frame 20, but the disclosure is not limited thereto. For example, the display device housing 50 may be positioned at the left end of the support frame 20, and the image displayed on the display device 10_4 may be reflected by the reflective member 40 and provided to the user's left eye through the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10_4 with their left eye. In another embodiment, the display device housing 50 may be positioned at both the left and right ends of the support frame 20, allowing the user to view the virtual reality image displayed on the display device 10_4 with both their left and right eyes.

[0198] Figure 23 This is a schematic diagram illustrating a car dashboard and central instrument panel including a display device according to an embodiment. Figure 23 The vehicle in which the display devices 10_a, 10_b, 10_c, 10_d and 10_e are applied according to embodiments is shown.

[0199] Reference Figure 23The display devices 10_a, 10_b, and 10_c according to the embodiments can be applied to the dashboard, central instrument panel, or central information display (CID) of a car. Furthermore, the display devices 10_d and 10_e according to the embodiments can be applied to interior mirror displays that replace the side mirrors of a car.

[0200] Figure 24 This is a schematic diagram illustrating a transparent display device including a display apparatus according to an embodiment.

[0201] Reference Figure 24 The display device 10_5 according to the embodiment can be applied to a transparent display device. The transparent display device can display an image IM while also transmitting light. Therefore, a user located in front of the transparent display device can see not only the image IM displayed on the display device 10_5, but also the object RS or background behind the transparent display device. When the display device 10_5 is applied to a transparent display device, the substrate of the display device 10_5 may include a light-transmitting portion or may be made of a light-transmitting material.

[0202] Embodiments have been disclosed herein, and although terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, unless specifically stated otherwise, features, characteristics, and / or elements described in connection with the embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the disclosure set forth in the claims.

Claims

1. A display device, the display device comprising: Lower base; A bonding electrode is disposed on the lower substrate; as well as A light-emitting element is disposed on the bonding electrode, wherein, The bonding electrode includes: a first bonding metal layer and a second bonding metal layer, sequentially disposed on the lower substrate, each of the first and second bonding metal layers including a bonding metal; a third bonding metal layer disposed between the first and second bonding metal layers and including the bonding metal; a first thin film layer disposed between the first and third bonding metal layers; and a second thin film layer disposed between the second and third bonding metal layers. The first and second thin film layers comprise materials having an atomic volume greater than or equal to 80% of the atomic volume of the bonding metal.

2. The display device according to claim 1, wherein, The first bonding metal layer, the second bonding metal layer and the third bonding metal layer comprise at least one of titanium, zirconium, nickel and chromium.

3. The display device according to claim 2, wherein, The first thin film layer and the second thin film layer comprise at least one of gold, zirconium, silver, hafnium, palladium and platinum.

4. The display device according to claim 2, wherein, The first bonding metal layer, the second bonding metal layer, and the third bonding metal layer comprise titanium, and The first thin film layer and the second thin film layer comprise at least one of gold and zirconium.

5. The display device according to claim 1, wherein, Each of the first bonding metal layer and the second bonding metal layer has a thickness in the range of 100 nm to 300 nm.

6. The display device according to claim 5, wherein, The thickness of the third bonding metal layer is less than or equal to the thickness of each of the first bonding metal layer and the second bonding metal layer.

7. The display device according to claim 1, wherein, Each of the first and second thin film layers has a thickness in the range of 1 nm to 50 nm.

8. The display device according to claim 1, wherein, The bonding electrode further includes at least one of the following: A bonding layer is disposed between the lower substrate and the first bonding metal layer; and A reflective layer is disposed between the second bonding metal layer and the light-emitting element.

9. The display device according to claim 1, wherein, The light-emitting element includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially disposed on the bonding electrode.

10. The display device according to claim 9, further comprising: A second insulating layer surrounds the side surface of the light-emitting element; A common electrode is disposed on the light-emitting element; as well as A reflective film surrounds the side surface of the light-emitting element.

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