Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a manufacturing method of the display device. According to one embodiment, a display device includes: a substrate; a lower electrode disposed above the substrate in a display region in which an image is displayed; an insulating layer formed of an inorganic insulating material and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light emitting layer; an upper electrode disposed on the organic layer; a cap layer disposed on the upper electrode; a partition wall which has a lower portion that is disposed on the insulating layer, is in contact with the upper electrode, and is formed of a conductive material, and an upper portion that is disposed on the lower portion, and which surrounds the organic layer, the upper electrode, and the cap layer; a first sealing layer that is formed of an inorganic insulating material, is disposed on the cap layer surrounded by the partition walls, is in contact with the side surfaces of the partition walls, extends above the partition walls, and is separated from the upper portions of the partition walls; and a second sealing layer formed of an inorganic insulating material and directly covering the first sealing layer.

Description

[0001] Cross-referencing of related applications

[0002] This application claims priority based on Japanese Patent Application No. 2024-075934, filed on May 8, 2024, and invokes all the contents set forth in that Japanese application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing a display device. Background Technology

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. These display elements include pixel circuits comprising thin-film transistors, a lower electrode connected to the pixel circuits, an organic layer covering the lower electrode, and a top electrode covering the organic layer. The organic layer includes a light-emitting layer, as well as functional layers such as a hole transport layer and an electron transport layer.

[0005] The demand is to reduce the manufacturing cost of display devices. Summary of the Invention

[0006] The purpose of this implementation is to provide a display device and a method for manufacturing the display device that can reduce manufacturing costs.

[0007] According to one embodiment, a display device includes: a substrate; a lower electrode disposed above the substrate in a display area for displaying an image; an insulating layer formed of an inorganic insulating material and covering the periphery of the lower electrode; an organic layer disposed above the lower electrode and including a light-emitting layer; an upper electrode disposed above the organic layer; a cover layer disposed above the upper electrode; a partition wall having a lower portion disposed above the insulating layer and in contact with the upper electrode and formed of a conductive material, and an upper portion disposed above the lower portion, and surrounding the organic layer, the upper electrode, and the cover layer; a first sealing layer formed of an inorganic insulating material disposed above the cover layer surrounded by the partition wall, in contact with the side of the partition wall, extending upward toward the partition wall, and separated from the upper portion of the partition wall; and a second sealing layer formed of an inorganic insulating material and directly covering the first sealing layer.

[0008] According to one embodiment, a display device includes: a substrate; a lower electrode disposed above the substrate in a display area for displaying an image; an insulating layer formed of an inorganic insulating material covering a peripheral portion of the lower electrode; an organic layer disposed above the lower electrode and including a light-emitting layer; an upper electrode disposed above the organic layer; a cover layer disposed above the upper electrode; a partition wall having a lower portion disposed above the insulating layer and in contact with the upper electrode and formed of a conductive material, and an upper portion disposed above the lower portion, and surrounding the organic layer, the upper electrode, and the cover layer; a first sealing layer formed of an inorganic insulating material disposed above the cover layer surrounded by the partition wall, in contact with the side of the partition wall, extending upward toward the partition wall, and separated from the upper portion of the partition wall; and a resin layer directly covering the first sealing layer, wherein the resin layer is not covered by the inorganic insulating layer.

[0009] According to one embodiment, in a method for manufacturing a display device, a processing substrate is prepared having a lower electrode formed on top of a substrate, an insulating layer formed covering the periphery of the lower electrode, and a partition wall having a lower portion located above the insulating layer and an upper portion located above the lower portion. An organic layer including a light-emitting layer is formed on the lower electrode, an upper electrode is formed on the organic layer, a capping layer is formed on the upper electrode, a first sealing layer covering the capping layer and the partition wall is formed using an inorganic insulating material, a second sealing layer directly covering the first sealing layer is formed using an inorganic insulating material, and a resin layer covering the second sealing layer is formed.

[0010] According to the embodiments, a display device and a method for manufacturing the display device that can reduce manufacturing costs can be provided. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating an example of the configuration of a display device DSP.

[0012] Figure 2 This is a diagram showing an example of the layout of subpixels SP1, SP2, and SP3.

[0013] Figure 3 It means along Figure 2 A schematic cross-sectional view of a component example of a DSP display device with AB lines.

[0014] Figure 4 It means along Figure 1 A schematic cross-sectional view of a component example of a DSP display device with I-I' lines.

[0015] Figure 5 It is a magnified cross-sectional view of the gap GP.

[0016] Figure 6This is a diagram showing an example of the configuration of a display element DE.

[0017] Figure 7 It is a diagram used to illustrate the outline of the manufacturing apparatus.

[0018] Figure 8A It means Figure 7 A diagram showing an example configuration of the vapor deposition apparatus 100.

[0019] Figure 8B It means Figure 7 A diagram showing other configuration examples of the vapor deposition apparatus 100.

[0020] Figure 9 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0021] Figure 10 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0022] Figure 11 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0023] Figure 12 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0024] Figure 13 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0025] Figure 14 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0026] Figure 15 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0027] Figure 16 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0028] Figure 17 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0029] Figure 18 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0030] Figure 19 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0031] Figure 20 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0032] Figure 21 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0033] Figure 22 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0034] Figure 23 It means along Figure 2 A schematic cross-sectional view of other components of the DSP display device with AB lines.

[0035] Figure 24 It means along Figure 1 A schematic cross-sectional view of other components of the display device DSP with the I-I' line in the diagram.

[0036] Figure 25 This is a diagram used to illustrate the manufacturing method of a display device DSP. Detailed Implementation

[0037] One embodiment will be described with reference to the accompanying drawings.

[0038] The disclosed content is merely one example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of this invention. Furthermore, regarding the accompanying drawings, to make the description clearer, the width, thickness, shape, etc., of various parts are sometimes schematically shown compared to the actual form; however, this is merely an example and does not limit the interpretation of the invention. Additionally, in this specification and the various figures, the same reference numerals are used for constituent elements that perform the same or similar functions as those described with respect to previously presented figures, and sometimes repeated detailed descriptions are appropriately omitted.

[0039] It should be noted that the accompanying drawings include mutually orthogonal X-axis, Y-axis, and Z-axis for ease of understanding. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis as the second direction Y, and the direction along the Z-axis as the third direction Z. The method of observing various elements parallel to the third direction Z is called a top-down view. It should be noted that terms such as "above," "above," "between," and "opposite," which refer to the positional relationship between two or more constituent elements, include not only cases where the two or more constituent elements are directly connected, but also cases where they are separated by gaps or other constituent elements. Furthermore, the positive direction of the Z-axis is referred to as "above" or "above," and the negative direction of the Z-axis is referred to as "below" or "below."

[0040] The display device involved in this embodiment is an organic electroluminescent display device that uses organic light-emitting diodes (OLEDs) as display elements, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, portable telephone terminals, etc.

[0041] Figure 1 This is a diagram illustrating an example of the configuration of a display device DSP.

[0042] The display device DSP includes a display panel PNL having a display area DA for displaying images and a peripheral area SA located outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0043] In this embodiment, the substrate 10 is rectangular when viewed from above. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle; it can also be other shapes such as a square, a circle, or an ellipse.

[0044] The display area DA has multiple pixels PX arranged in a matrix along the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different from each other. It should be noted that pixel PX may also include sub-pixels SP of other colors such as white, either together with or replacing any one of sub-pixels SP1, SP2, and SP3.

[0045] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are, for example, switching elements composed of thin-film transistors.

[0046] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to the anode of display element DE.

[0047] It should be noted that the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may also have more thin-film transistors and capacitors.

[0048] Display element DE is an organic light-emitting diode (OLED) that acts as a light-emitting element, sometimes referred to as an organic EL element.

[0049] The peripheral area SA has multiple terminals TE arranged along one direction. In the illustrated example, the multiple terminals TE are arranged along the first direction X. Each terminal TE extends in a second direction Y, but is not limited thereto. Such multiple terminals TE can be electrically connected to signal sources such as flexible printed circuit boards, IC chips, etc. In addition, these terminals TE are electrically connected to various wirings (scan lines, signal lines, power lines, wiring for touch sensors, etc.) in the display area DA.

[0050] Figure 2 This is a diagram showing an example of the layout of subpixels SP1, SP2, and SP3.

[0051] In the illustrated example, sub-pixels SP2 and SP3 are arranged along the second direction Y. Sub-pixels SP1 and SP2 are arranged along the first direction X, and sub-pixels SP1 and SP3 are arranged along the first direction X.

[0052] With subpixels SP1, SP2, and SP3 arranged in this manner, the display area DA contains columns of subpixels SP2 and SP3 alternately arranged in the second direction Y, as well as columns of multiple subpixels SP1 arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0053] It should be noted that the layout of sub-pixels SP1, SP2, and SP3 is not limited to... Figure 2 For example, the sub-pixels SP1, SP2, and SP3 in each pixel PX can also be arranged sequentially in the first direction X.

[0054] An insulating layer 5 and a partition 6 are disposed in the display area DA. The insulating layer 5 has openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. The insulating layer 5 with these openings AP1, AP2, and AP3 is sometimes referred to as a rib.

[0055] When viewed from above, partition 6 overlaps with insulating layer 5. Partition 6 is formed in a lattice shape surrounding openings AP1, AP2, and AP3. Partition 6, like insulating layer 5, can also have openings in sub-pixels SP1, SP2, and SP3. Partition 6 is conductive and... Figure 1 The terminal TE with the common potential among the multiple terminals TE shown is electrically connected.

[0056] Subpixels SP1, SP2, and SP3 each have display elements DE1, DE2, and DE3 respectively as display elements DE.

[0057] The display element DE1 of sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with the opening AP1. The periphery of the lower electrode LE1 is covered by an insulating layer 5. The display element DE1, including the lower electrode LE1, the organic layer OR1, and the upper electrode UE1, is surrounded by a partition 6 when viewed from above. The peripheries of the organic layer OR1 and the upper electrode UE1 overlap with the insulating layer 5 when viewed from above. The organic layer OR1 includes a light-emitting layer that emits light, for example, in the blue wavelength region.

[0058] The display element DE2 of sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with the opening AP2. The periphery of the lower electrode LE2 is covered by an insulating layer 5. The display element DE2, including the lower electrode LE2, the organic layer OR2, and the upper electrode UE2, is surrounded by a partition 6 when viewed from above. The peripheries of the organic layer OR2 and the upper electrode UE2 overlap with the insulating layer 5 when viewed from above. The organic layer OR2 includes a light-emitting layer that emits light in, for example, the green wavelength region.

[0059] The display element DE3 of sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with the opening AP3. The periphery of the lower electrode LE3 is covered by an insulating layer 5. The display element DE3, including the lower electrode LE3, the organic layer OR3, and the upper electrode UE3, is surrounded by a partition 6 when viewed from above. The peripheries of the organic layer OR3 and the upper electrode UE3 overlap with the insulating layer 5 when viewed from above. The organic layer OR3 includes a light-emitting layer that emits light in the red wavelength region, for example.

[0060] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are represented by dashed lines, while the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are represented by single-dotted lines. It should be noted that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the illustration may not accurately reflect their shapes.

[0061] The lower electrodes LE1, LE2, and LE3 correspond to the anode of the display element, for example. The upper electrodes UE1, UE2, and UE3 correspond to the cathode or common electrode of the display element and are in contact with the partition 6.

[0062] Pixel circuit 1 of lower electrode LE1 and sub-pixel SP1 (see) Figure 1 Electrical connections are established. The lower electrode LE2 is electrically connected to pixel circuit 1 of sub-pixel SP2. The lower electrode LE3 is electrically connected to pixel circuit 1 of sub-pixel SP3.

[0063] In the illustrated example, the areas of openings AP1, AP2, and AP3 are different from each other. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. In other words, the area of ​​the lower electrode LE1 exposed through opening AP1 is larger than the area of ​​the lower electrode LE2 exposed through opening AP2, and the area of ​​the lower electrode LE2 exposed through opening AP2 is larger than the area of ​​the lower electrode LE3 exposed through opening AP3.

[0064] Figure 3 It means along Figure 2 A schematic cross-sectional view of a component example of a DSP display device with AB lines.

[0065] A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes... Figure 1 The diagram shows various circuits such as pixel circuit 1, scan lines GL, signal lines SL, and power lines PL. Circuit layer 11 is covered by insulating layer 12. Insulating layer 12 is an organic insulating layer that flattens the surface created by circuit layer 11.

[0066] Lower electrodes LE1, LE2, and LE3 are disposed on insulating layer 12 and are separated from each other. Insulating layer 5 is disposed on insulating layer 12 and lower electrodes LE1, LE2, and LE3. Opening AP1 of insulating layer 5 overlaps with lower electrode LE1, opening AP2 overlaps with lower electrode LE2, and opening AP3 overlaps with lower electrode LE3. The periphery of lower electrodes LE1, LE2, and LE3 is covered by insulating layer 5. Lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of sub-pixels SP1, SP2, and SP3 through contact holes provided in insulating layer 12. It should be noted that the contact holes of insulating layer 12 are located in... Figure 3 omitted.

[0067] The partition 6 has a conductive lower part 61 disposed on the insulating layer 5 and an upper part 62 disposed on the lower part 61.

[0068] In the illustrated example, the lower portion 61 has a bottom layer 63 disposed on the insulating layer 5 and a shaft layer 64 disposed between the bottom layer 63 and the upper portion 62. The bottom layer 63 is thinner than the shaft layer 64. The bottom layer 63 has a wider width than the shaft layer 64. Both ends of the bottom layer 63 protrude from the sides of the shaft layer 64.

[0069] The upper portion 62 has a thin film 65 disposed on the shaft layer 64 and a thin film 66 disposed on the thin film 65. The upper portion 62 has a width greater than that of the shaft layer 64. Both ends of the upper portion 62 protrude from the side surfaces of the shaft layer 64. In this specification, the side surfaces of the shaft layer 64 are defined as surfaces extending throughout the shaft layer 64 between the bottom layer 63 and the upper portion 62.

[0070] Additionally, in the illustrated example, the upper part 62 has a wider width than the lower part 63. It should be noted that the lower part 63 can also have a wider width than the upper part 62.

[0071] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and the periphery of the organic layer OR1 is located above the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower part 61.

[0072] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and the periphery of the organic layer OR2 is located above the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower part 61.

[0073] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and the periphery of the organic layer OR3 is located above the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and contacts the lower part 61.

[0074] It should be noted that the contact between the upper electrodes UE1, UE2, and UE3 and the lower part 61 includes the case where the upper electrodes UE1, UE2, and UE3 are in direct contact with the upper surface of the bottom layer 63, and the case where the upper electrodes UE1, UE2, and UE3 are in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side of the shaft layer 64. In this specification, the upper surface of the bottom layer 63 is defined as the surface that is in direct contact with the shaft layer 64 in the bottom layer 63 and the surface that protrudes from the shaft layer 64 and faces the upper part 62.

[0075] In the illustrated example, sub-pixel SP1 has a capping layer CP1 and a sealing layer SE1, sub-pixel SP2 has a capping layer CP2 and a sealing layer SE2, and sub-pixel SP3 has a capping layer CP3 and a sealing layer SE3. The capping layers CP1, CP2, and CP3 serve as optical adjustment layers, respectively, to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. It should be noted that the capping layers CP1, CP2, and CP3 can also be omitted.

[0076] The capping layer CP1 is disposed on the upper electrode UE1.

[0077] The capping layer CP2 is configured on the upper electrode UE2.

[0078] The capping layer CP3 is disposed on the upper electrode UE3.

[0079] The sealing layer SE1 is disposed on top of the cover layer CP1, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP1. That is, the sealing layer SE1 contacts the axial layer 64 and the upper part 62 of the partition wall 6 surrounding the display element DE1.

[0080] The sealing layer SE2 is disposed on top of the cover layer CP2, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP2. That is, the sealing layer SE2 contacts the axial layer 64 and the upper part 62 of the partition wall 6 surrounding the display element DE2.

[0081] The sealing layer SE3 is disposed on top of the cover layer CP3, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP3. That is, the sealing layer SE3 contacts the axial layer 64 and the upper part 62 of the partition wall 6 surrounding the display element DE3.

[0082] In the following description, the multilayer comprising organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer comprising organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer comprising organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0083] Sealing layers SE1, SE2, and SE3 all extend upwards from the partition wall 6 and are separated from the upper part 62 of the partition wall 6. That is, a gap GP is formed between the sealing layers SE1, SE2, and SE3 and the upper part 62. The ends of the sealing layers SE1, SE2, and SE3 are separated from the upper part 62.

[0084] The ends of sealing layers SE1, SE2, and SE3 are located above partition 6. In the illustrated example, the ends of sealing layers SE1 and SE2 located above partition 6 between sub-pixels SP1 and SP2 are separated from each other, and the ends of sealing layers SE1 and SE3 located above partition 6 between sub-pixels SP1 and SP3 are separated from each other.

[0085] The sealing layer SEL directly covers the sealing layers SE1, SE2, and SE3. Furthermore, the sealing layer SEL continuously overlaps the sealing layers SE1, SE2, and SE3 directly and uninterruptedly on top of the display elements DE1, DE2, and DE3 and the partition 6. That is, there is no resin layer between the sealing layers SE1, SE2, and SE3 and the sealing layer SEL.

[0086] Furthermore, the sealing layer SEL covers the ends of each of the sealing layers SE1, SE2, and SE3. That is, the ends of the sealing layers SE1 and SE2 located above the partition 6 between sub-pixels SP1 and SP2 are separated from each other, and the sealing layer SEL is configured to fill the gap. Similarly, the ends of the sealing layers SE2 and SE3 located above the partition 6 between sub-pixels SP2 and SP3 are separated from each other, and the sealing layer SEL is configured to fill the gap. Therefore, the gap GP is an airtight space surrounded by the upper part 62, the sealing layers SE1, SE2, SE3, and the sealing layer SEL, and does not open to the outside. For example, the gap GP located between display element DE1 and display element DE2 is surrounded by the upper part 62 of the partition 6, the sealing layers SE1, SE2, and the sealing layer SEL.

[0087] The resin layer RL covers the sealing layer SEL. The cover plate CV or polarizing plate POL is bonded to the resin layer RL. The cover plate CV is a transparent glass substrate or a transparent resin substrate. It should be noted that, alternatively, the polarizing plate POL can be bonded to the resin layer RL, and the cover plate CV can be bonded to the polarizing plate POL.

[0088] The insulating layer 5, sealing layers SE1, SE2, SE3, and sealing layer SEL are formed, for example, of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and alumina (Al2O3). In one example, the insulating layer 5 is formed of silicon oxynitride, and the sealing layers SE1, SE2, SE3, and sealing layer SEL are formed of silicon nitride.

[0089] The lower part 61 of the partition 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed, for example, of a titanium-based material such as titanium or a titanium compound. The axial layer 64 is formed of a material different from the bottom layer 63 and the upper part 62, for example, of an aluminum-based material such as aluminum or an aluminum compound.

[0090] The upper portion 62 of the partition 6 is formed, for example, of a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a different material than the lower portion 61. The thin film 65 is formed, for example, of a titanium-based material such as titanium or a titanium compound. The thin film 66 is formed, for example, of an oxide conductive material such as indium tin oxide (ITO).

[0091] The lower electrodes LE1, LE2, and LE3 are, for example, multilayer bodies comprising a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metallic material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer bodies comprising a reflective layer between a pair of transparent layers.

[0092] Organic layer OR1 includes light-emitting layer EM1. Organic layer OR2 includes light-emitting layer EM2. Organic layer OR3 includes light-emitting layer EM3. Light-emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, light-emitting layer EM1 is formed of a material that emits light in the blue wavelength region, light-emitting layer EM2 is formed of a material that emits light in the green wavelength region, and light-emitting layer EM3 is formed of a material that emits light in the red wavelength region.

[0093] In addition, the organic layers OR1, OR2, and OR3 include multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0094] The upper electrodes UE1, UE2, and UE3 are formed, for example, from metallic materials such as an alloy of magnesium and silver (MgAg).

[0095] The capping layers CP1, CP2, and CP3 are multilayers of multiple thin films. All the films are transparent and have different refractive indices.

[0096] The circuit layer 11, insulating layer 12, and insulating layer 5 shown in the diagram are arranged around the display area DA and the surrounding area SA.

[0097] Figure 4It means along Figure 1 A schematic cross-sectional view of a component example of a DSP display device with I-I' lines.

[0098] Here, the PNL panel is simplified and shown. The laminated film FL in the diagram corresponds to... Figure 3 The laminated films FL1, FL2, and FL3 shown have a sealing layer SE equivalent to... Figure 3 The sealing layers SE1, SE2, and SE3 are shown. Sealing layer SE, as described above, covers the laminated film FL and has an end point directly above the partition wall 6. Sealing layer SEL is continuously disposed throughout the entire display area DA, covering sealing layer SE and extending outwards from the display area DA. A gap GP is formed directly above the partition wall 6. Resin layer RL is continuously disposed throughout the entire display area DA, covering sealing layer SEL. Cover plate CV or polarizing plate POL is bonded to the upper surface of resin layer RL in display area DA. Terminal TE is exposed from sealing layer SEL and resin layer RL. The ends of sealing layer SEL and resin layer RL are located between terminal TE and display area DA. In the illustrated example, the end point of resin layer RL overlaps with the end point of sealing layer SEL.

[0099] Figure 5 It is a magnified cross-sectional view of the gap GP.

[0100] Here, the gap GP formed between display element DE1 and display element DE2 is shown. In the illustrated example, the gap GP located directly above partition 6 is a single gap. It should be noted that the sealing layer SEL between sealing layer SE1 and sealing layer SE2 can also be formed in connection with the upper part 62. In this case, the gap GP located directly above partition 6 is divided into two gaps: the gap between sealing layer SE1 and the upper part 62, and the gap between sealing layer SE2 and the upper part 62.

[0101] Sealing layer SE1 has a thickness T1 equal to that of sealing layer SE2 in the third direction Z. Sealing layer SEL has a thickness T2 in the third direction Z. From the viewpoint that sealing layer SEL fills the gap between sealing layer SE1 and sealing layer SE2 to form a closed void GP, it is desirable that the thickness T2 of sealing layer SEL is equal to or greater than the thickness T1 of sealing layer SE1. In one example, the thicknesses T1 and T2 are 2 to 3 μm.

[0102] The resin layer RL has a thickness T3 in the third direction Z. Thickness T3 is greater than both thickness T1 and thickness T2. In one example, thickness T3 is approximately 10 μm.

[0103] In a structure where a void GP is formed directly above the adjacent 6, the following effect can be achieved.

[0104] That is, when the light L1 emitted from the display element DE1 or the light L1 reflected by the stacked film FL1 or the lower electrode LE1 in the incident light from the outside travels toward the adjacent sub-pixel, it reaches the gap GP, thereby confining the light L1 in the gap GP and suppressing the degradation of display quality.

[0105] In addition, when light L2 incident from the outside is reflected by the upper part 62 of the partition 6, the reflected light L2 is also confined in the gap GP, which can suppress the degradation of display quality caused by unwanted reflected light.

[0106] Next, an example of the configuration of the display element DE will be explained.

[0107] Figure 6 This is a diagram showing an example of the configuration of a display element DE.

[0108] The display element DE shown in the diagram can be equivalent to any of the display elements DE1, DE2, and DE3 mentioned above.

[0109] It should be noted that this explanation will be based on the case where the lower electrode LE is equivalent to the anode and the upper electrode UE is equivalent to the cathode.

[0110] The display element DE has an organic layer OR (OR1, OR2, OR3) between the lower electrode LE (LE1, LE2, LE3) and the upper electrode UE (UE1, UE2, UE3).

[0111] In the organic layer OR, along the third direction Z, the hole injection layer HIL, the hole transport layer HTL, the electron blocking layer EBL, the light emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL are stacked sequentially.

[0112] It should be noted that, in addition to the functional layers mentioned above, the organic layer OR may also include other functional layers such as a carrier generation layer as needed, and at least one of the functional layers mentioned above may be omitted.

[0113] The light-emitting layer EML is equivalent to Figure 3 Any one of the light-emitting layers EM1, EM2, and EM3 shown.

[0114] The capping layers CP (CP1, CP2, CP3) include a first transparent layer TL1 and a second transparent layer TL2. The first transparent layer TL1 is disposed above the upper electrode UE. The first transparent layer TL1 is a high-refractive-index layer with a higher refractive index than the upper electrode UE. The second transparent layer TL2 is disposed above the first transparent layer TL1. The second transparent layer TL2 is a low-refractive-index layer with a lower refractive index than the first transparent layer TL1. The sealing layers SE (SE1, SE2, SE3) are disposed above the second transparent layer TL2.

[0115] It should be noted that the composition of the organic layer OR is not limited to the configuration shown in the figure, where the organic layer OR has a single light-emitting layer EML. It can also be a configuration where the organic layer OR has multiple light-emitting layers connected in series.

[0116] Next, the apparatus used to manufacture the display device DSP will be described in general terms.

[0117] Figure 7 It is a diagram used to illustrate the outline of the manufacturing apparatus.

[0118] It should be noted that the dot patterns in the figure represent the atmosphere of each device. The sparsest dot pattern V1 represents a high vacuum environment with a first vacuum level. The densest dot pattern AT represents an atmospheric atmosphere. The dot pattern V2, with a density between dot pattern V1 and dot pattern AT, represents a vacuum environment with a second vacuum level lower than the first vacuum level.

[0119] The substrate storage 200 houses multiple processing substrates in an atmospheric environment. Here, the processing substrate refers to a motherboard substrate for a display device, which has multiple panel sections on a large substrate. Each panel section is removed by cutting through the processing substrate. Each removed panel section corresponds to... Figure 1 The display panel PNL shown has a display area DA and a peripheral area SA.

[0120] The inline vapor deposition apparatus 100 includes a pretreatment section 101, a heating section 102, and a vapor deposition section 103. The vapor deposition apparatus 100 will be described in detail later. It is configured to form a vapor deposition layer on a substrate under a high vacuum environment with a first vacuum degree.

[0121] The CVD (Chemical-Vapor Deposition) apparatus 210 is configured to deposit inorganic insulating materials on a processing substrate under a vacuum environment of a second vacuum level to form sealing layers SE1, SE2, SE3 and sealing layer SEL.

[0122] The resist forming apparatus 220 is configured to form a resist with a predetermined shape on the sealing layers SE1, SE2, and SE3 under atmospheric conditions.

[0123] The wet etching apparatus 230 is configured to remove a portion of the laminated films FL1, FL2, and FL3 by using a photoresist as a mask in an atmospheric atmosphere.

[0124] The dry etching apparatus 240 is configured to remove a portion of the laminated films FL1, FL2, FL3, a portion of the sealing layers SE1, SE2, SE3, and a portion of the sealing layer SEL by using a photoresist as a mask in a vacuum environment with a second vacuum degree.

[0125] The resin forming apparatus 250 is configured to form a resin layer RL. The resin forming apparatus 250 includes a coating apparatus 251, a drying apparatus 252, and a curing apparatus 253. The coating apparatus 251 is configured to coat the resin material in an atmospheric atmosphere. The drying apparatus 252 is configured to dry the resin material in a low vacuum (second vacuum degree) environment with reduced pressure compared to atmospheric atmosphere. It should be noted that the drying apparatus 252 may be omitted. The curing apparatus 253 is configured to cure the resin material in an atmospheric atmosphere. As an example, when the resin material is an ultraviolet-curable resin material, the curing apparatus 253 is configured to irradiate the resin material with ultraviolet light.

[0126] The vapor deposition apparatus 100, CVD apparatus 210, resist forming apparatus 220, wet etching apparatus 230, dry etching apparatus 240 and resin forming apparatus 250 are connected to the substrate storage unit 200 via a transport mechanism not described in detail.

[0127] Figure 8A It means Figure 7 A diagram showing an example configuration of the vapor deposition apparatus 100.

[0128] Evaporation apparatus 100, for example, in continuous forming Figure 6 This is applicable to the processes of the organic layer OR, the upper electrode UE, and the capping layer CP shown. The processing substrate SUB, which is fed into the vapor deposition apparatus 100, has a circuit layer 11, an insulating layer 12, lower electrodes LE1, LE2, LE3, an insulating layer 5, and a partition 6 on the substrate 10.

[0129] The vapor deposition apparatus 100 includes a pretreatment unit 101, a heating unit 102, and a vapor deposition unit 103. Although not described in detail, the vapor deposition apparatus 100 is connected to the substrate storage unit 200 via a transport mechanism. In addition, the vapor deposition apparatus 100 includes a posture changing unit 104 as part of the transport mechanism.

[0130] The pretreatment unit 101 is equipped with a mechanism for performing various pretreatments, such as plasma treatment, on the processed substrate SUB that is being transported in. The heating unit 102 is equipped with a mechanism for heating the processed substrate SUB.

[0131] The attitude transformation unit 104 includes a mechanism for changing the attitude of the processing substrate SUB, a mechanism for fixing the processing substrate SUB to a dedicated bracket using an electrostatic chuck, and a mechanism for releasing the electrostatic chuck and removing the processing substrate SUB from the bracket. In one example, the processing substrate SUB being moved into the front processing unit 101 and the heating unit 102 is in a horizontal attitude. The attitude of the processing substrate SUB being moved out of the front processing unit 101 and the heating unit 102 is changed from a horizontal attitude to a vertical attitude in the attitude transformation unit 104. The processing substrate SUB being moved into the vapor deposition unit 103 is in a vertical attitude. The attitude of the processing substrate SUB being moved out of the vapor deposition unit 103 is changed from a vertical attitude to a horizontal attitude in the attitude transformation unit 104.

[0132] The vapor deposition unit 103 includes multiple vapor deposition chambers EV11 to EV20 and a rotating chamber R11. The pretreatment unit 101, the heating unit 102, the attitude change unit 104, the multiple vapor deposition chambers EV11 to EV20 and the rotating chamber R11 are connected to each other and maintained at a high vacuum (first vacuum level).

[0133] Vapor deposition chambers EV11 to EV15 are arranged in a row. Vapor deposition chamber EV11 is connected to the attitude change unit 104. Vapor deposition chamber EV15 is connected to the rotating chamber R11. The transport path T11 is provided throughout vapor deposition chambers EV11 to EV15.

[0134] Vapor deposition chambers EV16 to EV20 are arranged in a row. Vapor deposition chamber EV16 is connected to the rotating chamber R11. Vapor deposition chamber EV20 is connected to the attitude change unit 104. The transport path T12 is provided throughout vapor deposition chambers EV16 to EV20.

[0135] The vapor deposition chamber EV11 has a vapor deposition source S11. The vapor deposition source S11 is configured to emit material for forming the hole injection layer HIL toward the transport path T11.

[0136] The vapor deposition chamber EV12 has a vapor deposition source S12. The vapor deposition source S12 is configured to emit material for forming the hole transport layer HTL toward the transport path T11.

[0137] The vapor deposition chamber EV13 has a vapor deposition source S13. The vapor deposition source S13 is configured to radiate material for forming the electron blocking layer EBL toward the transport path T11.

[0138] The evaporation chamber EV14 includes an evaporation source S14. The evaporation source S14 is configured to emit material for forming the light-emitting layer EML towards the transport path T11. Here, the light-emitting layer EML is... Figure 3 Any one of the light-emitting layers EM1, EM2, and EM3 shown.

[0139] The vapor deposition chamber EV15 includes a vapor deposition source S15. The vapor deposition source S15 is configured to radiate material for forming the hole blocking layer HBL toward the transport path T11.

[0140] The vapor deposition chamber EV16 has a vapor deposition source S16. The vapor deposition source S16 is configured to radiate material for forming the electron transport layer (ETL) toward the transport path T12.

[0141] The vapor deposition chamber EV17 is equipped with a vapor deposition source S17. The vapor deposition source S17 is configured to emit material for forming the electron injection layer EIL toward the transport path T12.

[0142] The vapor deposition chamber EV18 has a vapor deposition source S18. The vapor deposition source S18 is configured to radiate material for forming the upper electrode UE toward the transport path T12.

[0143] The vapor deposition chamber EV19 has a vapor deposition source S19. The vapor deposition source S19 is configured to radiate material for forming the first transparent layer TL1 toward the transport path T12.

[0144] The vapor deposition chamber EV20 is equipped with a vapor deposition source S20. The vapor deposition source S20 is configured to radiate material for forming the second transparent layer TL2 toward the transport path T12.

[0145] The rotating chamber R11 is configured to move the processing substrate SUB that is moved out of the transport path T11 to the transport path T12. The rotating chamber R11 has a rotating mechanism RM11. The rotating mechanism RM11 is configured to hold the processing substrate SUB that is moved in via the transport path T11 and can rotate about the rotation axis A11.

[0146] It should be noted that the configuration of the vapor deposition apparatus 100 is not limited to the example shown in the figure.

[0147] Figure 8B It means Figure 7 A diagram showing other configuration examples of the vapor deposition apparatus 100.

[0148] Figure 8B The example shown is similar to Figure 8A The difference between the configuration shown and the one shown is that it has vapor deposition chambers for forming the light-emitting layers EM1, EM2, and EM3 respectively.

[0149] In the vapor deposition unit 103 of the vapor deposition apparatus 100, vapor deposition chambers EV11, EV12, EV13, EV141, EV142, and EV143 are arranged in a row. Vapor deposition chamber EV11 is connected to the attitude change unit 104. Vapor deposition chamber EV143 is connected to the rotating chamber R11.

[0150] Vapor deposition chambers EV15 to EV20 are arranged in a row. Vapor deposition chamber EV15 is connected to the rotating chamber R11. Vapor deposition chamber EV20 is connected to the attitude transformation unit 104.

[0151] The vapor deposition source S11 of the vapor deposition chamber EV11 is configured to emit material for forming the hole injection layer HIL.

[0152] The vapor deposition source S12 of the vapor deposition chamber EV12 is configured to emit material for forming the hole transport layer HTL.

[0153] The vapor deposition source S13 of the vapor deposition chamber EV13 is configured to emit material for forming the electron blocking layer EBL.

[0154] The vapor deposition source S141 of the vapor deposition chamber EV141 is configured to emit material for forming the light-emitting layer EM1.

[0155] The vapor deposition source S142 of the vapor deposition chamber EV142 is configured to emit material for forming the light-emitting layer EM2.

[0156] The vapor deposition source S143 of the vapor deposition chamber EV143 is configured to emit material for forming the light-emitting layer EM3.

[0157] The materials emitted from the vapor deposition sources S141, S142, and S143 are luminescent materials that emit light of different colors from each other.

[0158] The vapor deposition source S15 of the vapor deposition chamber EV15 is configured to emit material for forming the hole blocking layer HBL.

[0159] The vapor deposition source S16 of the vapor deposition chamber EV16 is configured to radiate material used to form the electron transport layer ETL.

[0160] The vapor deposition source S17 of the vapor deposition chamber EV17 is configured to radiate material used to form the electron injection layer EIL.

[0161] The vapor deposition source S18 of the vapor deposition chamber EV18 is configured to radiate material used to form the upper electrode UE.

[0162] The vapor deposition source S19 of the vapor deposition chamber EV19 is configured to radiate material used to form the first transparent layer TL1.

[0163] The vapor deposition source S20 of the vapor deposition chamber EV20 is configured to emit material for forming the second transparent layer TL2.

[0164] In this vapor deposition apparatus 100, when forming the display element DE1, the processing substrate SUB is transported in a vertical orientation while materials are sequentially vapor-deposited in vapor deposition chambers EV11, EV12, EV13, and EV141. Then, the processing substrate SUB is transported in vapor deposition chambers EV142 and EV143 without material deposition. Finally, materials are sequentially vapor-deposited in vapor deposition chambers EV15 to EV20.

[0165] In the process of forming the display element DE2, the processing substrate SUB is transported in a vertical orientation while materials are sequentially deposited in evaporation chambers EV11, EV12, and EV13. Then, the processing substrate SUB is transported in evaporation chamber EV141 without material deposition. Next, materials are deposited in evaporation chamber EV142. Then, the processing substrate SUB is transported in evaporation chamber EV143 without material deposition. Finally, materials are sequentially deposited in evaporation chambers EV15 to EV20.

[0166] In the process of forming the display element DE3, the processing substrate SUB is transported in a vertical orientation while materials are sequentially deposited in evaporation chambers EV11, EV12, and EV13. Then, the processing substrate SUB is transported in evaporation chambers EV141 and EV142 without material deposition. Next, materials are sequentially deposited in evaporation chambers EV143, EV15 to EV20.

[0167] exist Figure 8A and Figure 8B In each of the configuration examples shown, the vapor deposition section 103 has a rotating chamber R11, configured to transport the processing substrate SUB in a folding manner, but is not limited to this.

[0168] The vapor deposition section 103 can also be configured such that the rotating chamber R11 is omitted, and the processed substrate SUB is transported in one direction. In this case, for example in Figure 8A In the illustrated configuration example, the vapor deposition chambers EV11, EV12, EV13, EV14, EV15, EV16, EV17, EV18, EV19, and EV20 are arranged sequentially along one direction. Furthermore, in... Figure 8B In the configuration example shown, the vapor deposition chambers EV11, EV12, EV13, EV141, EV142, EV143, EV15, EV16, EV17, EV18, EV19, and EV20 are arranged sequentially along one direction.

[0169] Next, the manufacturing method of the display device DSP will be explained. It should be noted that... Figures 9-14 The diagram below the insulating layer 12 is omitted.

[0170] First, such as Figure 9As shown, a processing substrate SUB is prepared. The process for preparing the processing substrate SUB includes: forming a lower electrode LE1 of sub-pixel SP1, a lower electrode LE2 of sub-pixel SP2, and a lower electrode LE3 of sub-pixel SP3 on an insulating layer 12; forming an insulating layer 5 having openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3 respectively; and forming a partition 6 having a lower portion 61 located on the insulating layer 5 and an upper portion 62 located on the lower portion 61 and protruding from the side of the lower portion 61. It should be noted that the partition 6 can be formed after the insulating layer 5 with openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 can be formed after the partition 6 is formed.

[0171] Next, the display element DE1 is formed.

[0172] First, for example, to Figure 8A The vapor deposition apparatus 100 shown introduces a processing substrate SUB, and performs a prescribed pretreatment on the processing substrate SUB in the pretreatment unit 101. Then, as needed, the processing substrate SUB is heated in the heating unit 102, and the processing substrate SUB is converted to a vertical position in the posture changing unit 104, and then introduced into the vapor deposition unit 103.

[0173] Then, in the evaporation unit 103, evaporation is performed using the partition wall 6 as a mask to form a laminated film FL1 on the processing substrate SUB. Specifically, in the evaporation chamber EV11, a hole injection layer HIL is formed on the lower electrode LE1; in the evaporation chamber EV12, a hole transport layer HTL is formed on the hole injection layer HIL; in the evaporation chamber EV13, an electron blocking layer EBL is formed on the hole transport layer HTL; in the evaporation chamber EV14, a light-emitting layer EM1 is formed on the electron blocking layer EBL; in the evaporation chamber EV15, a hole blocking layer HBL is formed on the light-emitting layer EM1; in the evaporation chamber EV16, an electron transport layer ETL is formed on the hole blocking layer HBL; and in the evaporation chamber EV17, an electron injection layer EIL is formed on the electron transport layer ETL. Thus, an organic layer OR1 including the light-emitting layer EM1 is formed on the lower electrode LE1. Then, in the vapor deposition chamber EV18, the upper electrode UE is formed on the electron injection layer EIL. This forms the upper electrode UE1 on the organic layer OR1. Next, in the vapor deposition chamber EV19, a first transparent layer TL1 is formed on the upper electrode UE, and in the vapor deposition chamber EV20, a second transparent layer TL2 is formed on the first transparent layer TL1. This forms the capping layer CP1 on the upper electrode UE1.

[0174] The organic layer OR1, the upper electrode UE1, and the capping layer CP1 included in the laminated film FL1 are continuously formed in the vapor deposition apparatus 100 under a vacuum environment of the first vacuum degree, using the partition wall 6 as a mask (vapor deposition process).

[0175] Then, as Figure 10 As shown, a sealing layer SE1 is formed on the laminated film FL1. Specifically, the processing substrate SUB is removed from the evaporation unit 103, its orientation is changed to a horizontal position in the orientation change unit 104, and then it is moved into the CVD apparatus 210 with a second vacuum level. In the CVD apparatus 210, an inorganic insulating material (e.g., silicon nitride) is deposited on the processing substrate SUB. This forms a sealing layer SE1 that continuously covers the laminated film FL1 and the spacer 6.

[0176] The laminated film FL1 and the sealing layer SE1 are formed at least in the entire display area DA, and are disposed not only in sub-pixels SP1 but also in sub-pixels SP2 and SP3. The laminated film FL1 is separated by cantilevered partitions 6.

[0177] When the organic layer OR1, the upper electrode UE1, and the capping layer CP1 constituting the laminated film FL1 are formed by vapor deposition, the material emitted from the vapor deposition source is blocked by the upper part 62. Therefore, a portion of the laminated film FL1 is laminated on the upper part 62. The laminated film FL1 located on the upper part 62 is separated from the laminated film FL1 located directly above the lower electrode LE1.

[0178] The sealing layer SE1 covers the laminated film FL1 directly above the partition wall 6 and the laminated film FL1 directly above the lower electrode LE1, and is in contact with the partition wall 6.

[0179] Next, as Figure 11 As shown, a resist RS1 patterned into a prescribed shape is formed on the sealing layer SE1. The resist RS1 is formed by the resist forming apparatus 220. The resist RS1 overlaps with a portion of the sub-pixel SP1 and the surrounding partition 6.

[0180] Next, as Figure 12 As shown, the resist RS1 is used as a mask to pattern the sealing layer SE1 and the laminated film FL1. The patterning is performed by a wet etching apparatus 230 and a dry etching apparatus 240. Various etching processes are performed by using the resist RS1 as a mask, thereby sequentially removing the sealing layer SE1 and the laminated film FL1 (capping layer CP1, upper electrode UE1, and organic layer OR1) exposed from the resist RS1.

[0181] This patterning exposes the lower electrode LE2 of sub-pixel SP2 and the lower electrode LE3 of sub-pixel SP3.

[0182] Next, the resist RS1 is removed. Thus, the display element DE1 is formed on the sub-pixel SP1. Furthermore, in the illustrated example, the laminated film FL1 stacked on the partition 6 is removed before the patterning of the laminated film FL1 and the removal of the resist RS1. Therefore, a gap GP is formed between the sealing layer SE1 and the partition 6.

[0183] Next, as Figure 13 As shown, display element DE2 is formed. The steps for forming display element DE2 are the same as those for forming display element DE1. That is, pretreatment is performed on the processing substrate SUB on which display element DE1 is formed. Then, a laminated film FL2 is formed on the lower electrode LE2. The laminated film FL2 has an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2, and a capping layer CP2. Then, a sealing layer SE2 is formed. Then, a photoresist is formed on the sealing layer SE2. Then, patterning is performed using the photoresist as a mask. As a result, the sealing layer SE2 and the laminated film FL2 exposed from the photoresist are removed sequentially. Then, the photoresist is removed.

[0184] Thus, a display element DE2 is formed on sub-pixel SP2, exposing the lower electrode LE3 of sub-pixel SP3. Furthermore, in the illustrated example, the laminated film FL2 above partition 6 is removed during patterning, thus creating a gap GP between the sealing layer SE2 and partition 6.

[0185] Next, as Figure 14 As shown, display element DE3 is formed. The steps for forming display element DE3 are the same as those for forming display element DE1. That is, pretreatment is performed on the processing substrate SUB on which display elements DE1 and DE2 are formed. Then, a laminated film FL3 is formed on the lower electrode LE3. The laminated film FL3 has an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3, and a capping layer CP3. Then, a sealing layer SE3 is formed. Then, a resist is formed on the sealing layer SE3. Then, patterning is performed using the resist as a mask. As a result, the sealing layer SE3 and the laminated film FL3 exposed from the resist are removed sequentially. Then, the resist is removed.

[0186] Thus, a display element DE3 is formed on the sub-pixel SP3. Furthermore, in the illustrated example, since the laminated film FL3 above the partition 6 is removed during patterning, a gap GP is formed between the sealing layer SE3 and the partition 6.

[0187] It should be noted that in the above manufacturing process, the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the formation order of display elements DE1, DE2, and DE3 is not limited to this example.

[0188] Thus, a processing substrate SUB containing display elements DE1, DE2, and DE3 is formed, as shown below. Figure 15 The film is shown to be removed under atmospheric conditions. Each of the laminated films FL is sealed by a sealing layer SE. Terminals TE are formed during the formation of circuit layer 11.

[0189] Next, as Figure 16 As shown, a sealing layer SEL is formed on the entire surface of the processing substrate SUB. Specifically, the processing substrate SUB is fed into a CVD apparatus 210 with a second vacuum level. In the CVD apparatus 210, an inorganic insulating material (e.g., silicon nitride) is deposited. This forms a sealing layer SEL that directly covers each of the sealing layers SE1, SE2, and SE3 and also covers the terminal TE. At this time, a void GP exists directly above the partition wall 6. The void GP is surrounded by the upper portion 62, the sealing layers SE1, SE2, SE3, and the sealing layer SEL.

[0190] Next, as Figure 17 As shown, a resin layer RL is formed over the entire display area DA. Specifically, the processing substrate SUB is first fed into the coating apparatus 251 of the resin forming apparatus 250. In the coating apparatus 251, resin material is coated onto the sealing layer SEL under atmospheric conditions. At this time, the resin material is coated in a manner that does not overlap with the terminals TE.

[0191] Then, the processing substrate SUB is moved into the drying apparatus 252. The drying apparatus 252 maintains an environment with a pressure reduction compared to atmospheric pressure. By placing the processing substrate SUB in this reduced-pressure environment, moisture is dissipated from the resin material, thereby drying the resin material.

[0192] Next, the processing substrate SUB is fed into the curing apparatus 253. In the curing apparatus 253, the resin material is irradiated with ultraviolet light, for example, in an atmospheric atmosphere. The resin material is thus cured. Through this process, a resin layer RL is formed on the sealing layer SEL, and the resin layer RL does not overlap with the terminal TE. It should be noted that the drying process can be omitted after the resin coating process, by irradiating the resin material with ultraviolet light.

[0193] Next, as Figure 18 As shown, the resin layer RL is used as a mask to pattern the sealing layer SEL. Specifically, the processing substrate SUB is fed into the dry etching apparatus 240. In the dry etching apparatus 240, under a vacuum environment of a second vacuum degree, the sealing layer SEL is removed by etching, using the resin layer RL as a mask. Therefore, the ends of the resin layer RL overlap with the ends of the sealing layer SEL. Through this patterning of the sealing layer SEL, the terminal TE is exposed from the sealing layer SEL.

[0194] Next, the cover plate CV or polarizing plate POL is bonded to the upper surface of the resin layer RL.

[0195] After the above processes, the display device DSP is completed.

[0196] Next, other manufacturing methods for the display device DSP will be described.

[0197] from Figure 9 The process shown is the preparation of the substrate SUB. Figure 16 The process for forming the sealing layer SEL shown up to the point is the same as the manufacturing method previously described.

[0198] After the SEL sealing layer is formed, such as Figure 19 As shown, a resist RS2 is formed on the sealing layer SEL over the entire display area DA. This resist RS2, for example, can pass through a reference... Figure 17 The resin layer RL described is formed using the same process. The resist RS2 overlaps with the display area DA but not with the terminal TE.

[0199] Next, as Figure 20 As shown, the resist RS2 is used as a mask to pattern the sealing layer SEL. Specifically, the processing substrate SUB is fed into the dry etching apparatus 240. In the dry etching apparatus 240, under a vacuum environment with a second vacuum level, the resist RS2 is used as a mask to remove the sealing layer SEL through etching. By patterning the sealing layer SEL, the terminal TE is exposed from the sealing layer SEL. Afterwards, the resist RS2 is removed.

[0200] Next, as Figure 21 As shown, a resin layer RL is formed over the entire display area DA. This resin layer RL can be compared with a reference... Figure 17 The resin layer RL described is formed using the same process. However, in Figure 21 In the example shown, the resin layer RL was not used as a mask for dry etching. That is, in Figure 17 In the example shown, the resin layer RL is used as a mask for dry etching, therefore a relatively thick resin layer RL needs to be formed. On the other hand, in Figure 21 In the example shown, with Figure 17 Compared to the example shown, the thickness of the resin layer RL can be reduced. Therefore, it is possible to achieve a thinner display device DSP.

[0201] In addition, Figure 21 In the example shown, since the resin layer RL is formed on the patterned sealing layer SEL, the end of the resin layer RL may not overlap with the end of the sealing layer SEL. Both the end of the resin layer RL and the end of the sealing layer SEL are located between the display area DA and the terminal TE. In the illustrated example, the end of the resin layer RL is located between the end of the sealing layer SEL and the terminal TE.

[0202] Next, as Figure 22 As shown, the cover plate CV or polarizing plate POL is bonded to the upper surface of the resin layer RL.

[0203] After the above processes, the display device DSP is completed.

[0204] Next, other examples of the composition will be explained.

[0205] Figure 23 It means along Figure 2 A schematic cross-sectional view of other components of the DSP display device with AB lines.

[0206] Figure 23 The example shown is similar to Figure 3 The configuration shown differs from the example shown in that the sealing layer SEL is omitted. The void GP is surrounded by the individual sealing layers SE1, SE2, and SE3 and the upper part 62. The resin layer RL directly covers the sealing layers SE1, SE2, and SE3 and fills the void GP. The cover plate CV or polarizing plate POL is bonded to the upper surface of the resin layer RL.

[0207] Figure 24 It means along Figure 1 A schematic cross-sectional view of other components of the display device DSP with the I-I' line in the diagram.

[0208] Figure 24 The example shown is similar to Figure 4 The configuration shown differs from the example shown in that the sealing layer SEL is omitted. The resin layer RL is continuously arranged across the entire display area DA. The resin layer RL is not covered by an inorganic insulating layer. The cover plate CV or polarizing plate POL is bonded to the upper surface of the resin layer RL in the display area DA. The terminal TE protrudes from the resin layer RL. In the illustrated example, the end of the resin layer RL overlaps with the sealing layer SE.

[0209] Next, regarding Figure 23 and Figure 24 The manufacturing method of the DSP display device shown will be explained.

[0210] from Figure 9 The process shown is the preparation of the substrate SUB. Figure 14 The process for forming the display element DE3 shown up to the point is the same as the manufacturing method previously described.

[0211] Thus, a processing substrate SUB containing display elements DE1, DE2, and DE3 is formed, as shown below. Figure 25 As shown in the upper section, it is removed under atmospheric conditions. The laminated films FL are each sealed by a sealing layer SE. The terminals TE are formed during the formation of circuit layer 11.

[0212] Next, as Figure 25 As shown in the lower section, a resin layer RL is formed over the entire display area DA. This resin layer RL can be compared with a reference... Figure 17 The resin layer RL described herein is formed using the same process.

[0213] However, in Figure 25 In the example shown, because the sealing layer SEL is omitted, the resin layer RL is not used as a mask for dry etching. Therefore, in Figure 25 In the example shown, with Figure 17 Compared to the example shown, the thickness of the resin layer RL can be reduced. Therefore, it is possible to achieve a thinner display device DSP.

[0214] Next, the cover plate CV or polarizing plate POL is bonded to the upper surface of the resin layer RL.

[0215] After the above processes, the display device DSP is completed.

[0216] According to this embodiment, partition walls 6 are provided at the boundaries of sub-pixels SP1, SP2, and SP3. These partition walls 6 surround the organic layers OR1, OR2, and OR3, the upper electrodes UE1, UE2, and UE3, and the capping layers CP1, CP2, and CP3, all formed by vapor deposition. Furthermore, the display element DE1 of sub-pixel SP1, the display element DE2 of sub-pixel SP2, and the display element DE3 of sub-pixel SP3 are each independently separated by the partition walls 6. The separated display elements DE1, DE2, and DE3 are then independently sealed by sealing layers SE1, SE2, and SE3. Therefore, even if a defect occurs in any display element due to moisture intrusion, the diffusion of intruded moisture to adjacent display elements can be suppressed.

[0217] Furthermore, in a structure that can suppress the diffusion of moisture to adjacent display elements as described above, the allowable moisture content of the resin layer RL can be increased compared to a structure in which the organic layer is not isolated in adjacent display elements (comparative example).

[0218] That is, in the comparative example, when cracks or other defects appeared in the sealing layer, moisture seeped in through the cracks and diffused throughout multiple display elements, causing damage to many display elements. Therefore, it is necessary to minimize the moisture content of the resin layer covering the sealing layer. Thus, it is necessary to form the resin layer in a nitrogen atmosphere or a clean, dry air atmosphere with extremely low moisture concentration. Therefore, in the comparative example, equipment for generating a nitrogen atmosphere or clean, dry air is required.

[0219] On the other hand, in this embodiment, a high moisture content is permissible for the resin layer RL disposed on the sealing layer SEL or on the sealing layers SE1, SE2, and SE3. Therefore, the process of applying resin material to form the resin layer RL can be performed in an atmospheric atmosphere. In one example, the resin material application process can be performed in a cleanroom atmosphere adjusted to a temperature range of 20°C to 30°C, a humidity range of 40% to 70%, and an oxygen concentration of 20% or higher. Therefore, equipment for generating an atmosphere with extremely low moisture concentration is not required.

[0220] Furthermore, compared to a comparative example where a resin layer is disposed between the sealing layers SE1, SE2, SE3 and the sealing layer SEL, the manufacturing process can be simplified and manufacturing costs can be reduced. Additionally, it enables the display device DSP to be made thinner.

[0221] Additionally, according to reference Figures 23-25 The described configuration example can omit the sealing layer SEL, thereby simplifying the manufacturing process and further reducing manufacturing costs.

[0222] In addition, with the simplification of manufacturing processes, it is possible to reduce some of the manufacturing equipment, miniaturize the manufacturing equipment, and reduce the installation area of ​​the manufacturing equipment.

[0223] In the above embodiments, for example, sealing layers SE1, SE2, and SE3 correspond to the first sealing layer, and sealing layer SEL corresponds to the second sealing layer. Resist RS1 corresponds to the first resist, and resist RS2 corresponds to the second resist.

[0224] As explained above, according to this embodiment, a display device and a method for manufacturing the display device that can reduce manufacturing costs can be provided.

[0225] Any display device and manufacturing method that can be implemented by those skilled in the art by making appropriate design modifications based on the display device and manufacturing method described above as embodiments of the present invention, as long as it contains the spirit of the present invention, is also within the scope of the present invention.

[0226] Within the scope of the present invention, various modifications will be conceived by those skilled in the art, and these modifications should also be understood to fall within the scope of the present invention. For example, solutions obtained by appropriately adding, deleting, or designing the constituent elements of the above-described embodiments, or solutions obtained by adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention as long as they possess the spirit of the present invention.

[0227] Furthermore, any other effects resulting from the solutions described in the above embodiments, effects that are clearly known from the description in this specification or that can be reasonably conceived by those skilled in the art, should of course be understood as effects resulting from the present invention.

Claims

1. A display device, comprising: substrate; The lower electrode is disposed above the substrate in the display area for displaying images; An insulating layer, formed of an inorganic insulating material, covers the periphery of the lower electrode; An organic layer disposed above the lower electrode, and including a light-emitting layer; The upper electrode is disposed on the organic layer; A capping layer disposed on the upper electrode; The partition has a lower portion formed of a conductive material disposed on the insulating layer and in contact with the upper electrode, and an upper portion disposed on the lower portion, and surrounds the organic layer, the upper electrode and the capping layer; A first sealing layer, formed of an inorganic insulating material, is disposed on the cover layer surrounded by the partition wall, contacts the side of the partition wall, extends upward toward the partition wall, and is separated from the upper part of the partition wall; and The second sealing layer is formed of inorganic insulating material and directly covers the first sealing layer.

2. The display device according to claim 1, further comprising a resin layer covering the second sealing layer.

3. The display device according to claim 2, further comprising a terminal electrically connected to a signal source on the outer side of the display area. The end of the second sealing layer and the end of the resin layer are located between the terminal and the display area.

4. The display device according to claim 3, wherein, The end of the resin layer overlaps with the end of the second sealing layer.

5. The display device according to claim 3, wherein, The end of the resin layer is located between the end of the terminal and the end of the second sealing layer.

6. The display device according to claim 1, further comprising a gap surrounded by the upper portion, the first sealing layer and the second sealing layer.

7. The display device according to claim 1, wherein, The first sealing layer and the second sealing layer are formed of silicon nitride.

8. A display device, comprising: substrate; The lower electrode is disposed above the substrate in the display area for displaying images; An insulating layer, formed of an inorganic insulating material, covers the periphery of the lower electrode; An organic layer disposed above the lower electrode, and including a light-emitting layer; The upper electrode is disposed on the organic layer; A capping layer disposed on the upper electrode; The partition has a lower portion formed of a conductive material disposed on the insulating layer and in contact with the upper electrode, and an upper portion disposed on the lower portion, and surrounds the organic layer, the upper electrode and the capping layer; A first sealing layer, formed of an inorganic insulating material, is disposed on the cover layer surrounded by the partition wall, contacts the side of the partition wall, extends upward toward the partition wall, and is separated from the upper part of the partition wall; and A resin layer that directly covers the first sealing layer. The resin layer was not covered by an inorganic insulating layer.

9. The display device according to claim 8, wherein, The resin layer fills the voids surrounded by the upper part and the first sealing layer.

10. The display device according to claim 2 or 8, further comprising a cover plate or polarizing plate bonded to the resin layer.

11. The display device according to claim 1 or 8, wherein, The lower portion has a bottom layer disposed on the insulating layer and a shaft layer disposed between the bottom layer and the upper portion. The bottom layer and the top layer protrude from the side of the shaft layer.

12. A method for manufacturing a display device, wherein, A processing substrate is prepared in which a lower electrode is formed on top of a substrate, an insulating layer is formed covering the periphery of the lower electrode, and a partition wall is formed having a lower portion located above the insulating layer and an upper portion located above the lower portion. A laminated film comprising an organic layer including a light-emitting layer, an upper electrode, and a capping layer is formed on the lower electrode. An inorganic insulating material is used to form a first sealing layer covering the laminated film and the partition wall. A second sealing layer is formed by using inorganic insulating materials to directly cover the first sealing layer. A resin layer is formed on top of the second sealing layer.

13. The method of manufacturing a display device according to claim 12, wherein, The process of forming the laminated film is a vapor deposition process in a vacuum environment with the partition wall as a mask. The process of forming the resin layer includes the process of coating a resin material in an atmospheric atmosphere.

14. The method of manufacturing a display device according to claim 13, wherein, The process of forming the resin layer, after the process of coating the resin material, further includes the following steps: The resin material is dried in an environment with reduced pressure than atmospheric pressure. The resin material is cured in an atmospheric atmosphere.

15. The method of manufacturing a display device according to claim 12, wherein, Before forming the second sealing layer, the following is also performed: In an atmospheric atmosphere, a patterned first resist is formed on top of the first sealing layer. The first resist is used as a mask to pattern the first sealing layer and the laminated film.

16. The method of manufacturing a display device according to claim 15, wherein, A gap is also formed between the upper part and the first sealing layer.

17. The method of manufacturing a display device according to claim 16, wherein, After the second sealing layer is formed, the gap is surrounded by the upper part, the first sealing layer and the second sealing layer.

18. The method of manufacturing a display device according to claim 12, wherein, The second sealing layer is formed in such a way that it covers the terminals that are electrically connected to the signal source. The resin layer is formed in a manner that does not overlap with the terminal. After the resin layer is formed, the resin layer is further used as a mask to pattern the second sealing layer.

19. The method of manufacturing a display device according to claim 12, wherein, The second sealing layer is formed in such a way that it covers the terminals that are electrically connected to the signal source. Before the formation of the resin layer, the following is also performed: In an atmospheric atmosphere, a second resist is formed on top of the second sealing layer. The second resist is used as a mask to pattern the second sealing layer, exposing the terminals. The resin layer is formed in a manner that does not overlap with the terminal.

20. The method of manufacturing a display device according to claim 13, wherein, The processes for the first sealing layer and the second sealing layer are each carried out in a vacuum environment with a second vacuum level that is lower than the first vacuum level.

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