Display device

Abstract

A display device is provided. The display device includes: a substrate; a first buffer layer disposed on the substrate; a thin film transistor including a semiconductor layer disposed on the first buffer layer and a gate electrode insulated from the first semiconductor layer; and a first inorganic insulating layer disposed between the semiconductor layer and the gate electrode. A concentration of H in the first inorganic insulating layer is about 7.55 * 1020 atoms per cubic centimeter (atoms / cm3) or less, and a content of a compound including a nitrogen-hydrogen (N-H) bond in the first buffer layer is about 0.1% or less based on a total weight of the first buffer layer.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2024-0062186, filed on May 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to display devices. Background Technology

[0003] Display devices visually display data. They can provide images using light-emitting diodes (LEDs). Display devices have a variety of uses, and various designs have been explored to improve their quality. Summary of the Invention

[0004] The embodiments include a display device.

[0005] Additional features will be set forth in part in the description below, and in part will be apparent from the description, or may be learned by practicing the disclosed embodiments presented.

[0006] In the disclosed embodiments, the display device includes: a substrate; a first buffer layer disposed on the substrate; a thin-film transistor including a semiconductor layer disposed on the first buffer layer and a gate electrode insulated from the semiconductor layer; and a first inorganic insulating layer disposed between the semiconductor layer and the gate electrode, wherein the concentration of H in the first inorganic insulating layer is approximately 7.55 × 10⁻⁶. 20 Atoms per cubic centimeter (atoms / cm) 3 (or less) and, based on the total weight of the first buffer layer, the content of compounds comprising nitrogen-hydrogen (NH) bonds or composed of NH bonds in the first buffer layer is about 0.1% or less.

[0007] In this embodiment, the concentration of H in the first buffer layer can be 8.5 × 10⁻⁶. 20 atoms / cm 3 Or smaller.

[0008] In an embodiment, the first buffer layer may include silicon oxide (SiO2). x ).

[0009] In one embodiment, the display device may further include a second buffer layer disposed below the first buffer layer.

[0010] In this embodiment, the second buffer layer may include SiN. x .

[0011] In this embodiment, the first inorganic insulating layer may include SiO2. x .

[0012] In an embodiment, the fluorine content at the interface between the first buffer layer and the semiconductor layer can be six times or more the minimum fluorine content in the lower part of the first buffer layer.

[0013] In this embodiment, the semiconductor layer may include a silicon semiconductor material.

[0014] In one embodiment, the display device may further include a metal layer disposed on a substrate.

[0015] In one embodiment, the thin-film transistor may include a driving thin-film transistor.

[0016] In this embodiment, the substrate may include a glass material.

[0017] In one embodiment, the substrate may include an inorganic layer disposed between adjacent plastic substrates.

[0018] In the embodiments, the plastic substrates may each comprise polyimide.

[0019] In this embodiment, the inorganic layer may include SiO2. x .

[0020] In an embodiment, the display device may further include an organic insulating layer disposed on the first inorganic insulating layer.

[0021] In some embodiments, the display device may further include an organic light-emitting diode disposed on an organic insulating layer.

[0022] In an embodiment, an organic light-emitting diode may include a pixel electrode, an emitter layer, and a counter electrode.

[0023] In some embodiments, the display device may further include an encapsulation layer disposed on an organic light-emitting diode.

[0024] In this embodiment, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0025] In some embodiments, the display device may further include a storage capacitor disposed on a thin-film transistor. Attached Figure Description

[0026] The above and other features and advantages of the disclosed exemplary embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic perspective view of an embodiment of the display device; Figure 2 This is a schematic plan view of an embodiment of the display device; Figure 3 and Figure 4 This is an equivalent circuit diagram of an embodiment of pixels in a display device; Figure 5 It is along Figure 1 A schematic cross-sectional view of the pixels captured by line I-I'; and Figure 6 It is a schematic graph showing the fluorine content in the first buffer layer, semiconductor layer and first inorganic insulating layer. Detailed Implementation

[0027] Referring now to embodiments, exemplary embodiments of the embodiments are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, the illustrated embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain the described features. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0028] Various modifications can be applied to the illustrated embodiments, and specific embodiments will be shown in the accompanying drawings and described in the detailed description. The effects and features of the illustrated embodiments, as well as methods of implementing them, will become clearer with reference to the following detailed description taken in conjunction with the accompanying drawings. However, the illustrated embodiments can be implemented in various forms and are not limited to those presented below.

[0029] In the following description, embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same or corresponding components are indicated by the same reference numerals, and redundant descriptions thereof are omitted.

[0030] In the embodiments described below, it will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These elements are used only to distinguish one element from another.

[0031] In the embodiments described below, as used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms.

[0032] In the embodiments described below, it will also be understood that the terms “comprising” and / or “including” as used herein indicate the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0033] In the following embodiments, it will be understood that when an element such as a layer, film, region, or plate is referred to as being "on" another element, the element may be directly on the other element or an intervening element may be on the other element.

[0034] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated. For example, since the dimensions and thicknesses of the elements in the accompanying drawings are arbitrarily shown for ease of explanation, the following disclosure is not limited thereto.

[0035] When exemplary embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of the described sequence.

[0036] In the specification, expressions such as "A and / or B" may include A, B, or A and B. Expressions such as "at least one of A and B (species / man)" may include A, B, or A and B.

[0037] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, the term “about” may mean within one or more standard deviations, or, for example, within ±30%, ±20%, ±10%, ±5% of the stated value.

[0038] In the following embodiments, it will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, that layer, region, or component may be directly connected to the other layer, region, or component, or indirectly connected to the other layer, region, or component via an intermediary layer, region, or component. For example, in the specification, when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, that layer, region, or component may be directly electrically connected to the other layer, region, or component, or indirectly electrically connected to the other layer, region, or component via an intermediary layer, region, or component.

[0039] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0040] Figure 1 This is a schematic perspective view of an embodiment of the display device.

[0041] Reference Figure 1 The display device 1 may include a display area DA and a peripheral area PA arranged around the display area DA. The peripheral area PA may surround the display area DA. The display device 1 may provide an image using light emitted from pixels P arranged in the display area DA, and the peripheral area PA may be a non-display area in which no image is displayed.

[0042] In the following description, an organic light-emitting display device is described in an embodiment of display device 1, but the disclosure is not limited thereto. In embodiments, display device 1 may include a display device such as an inorganic light-emitting display device (or an inorganic electroluminescent (“EL”) display) or a quantum dot light-emitting display device. In embodiments, for example, the emitting layer of the display element in display device 1 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0043] although Figure 1 The display device 1 shown has a flat display surface, but the disclosure is not limited thereto. In embodiments, the display device 1 may have a three-dimensional display surface or a curved display surface.

[0044] Figure 1 A display device 1 applicable to a mobile phone terminal is shown. Although not shown, electronic modules, camera modules, power modules, etc., set (e.g., mounted) on a motherboard can be mounted together with the display device 1 on a bracket / casing or the like to form a mobile phone terminal. Specifically, the display device 1 can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as tablet computers, vehicle navigation devices, game consoles, and smartwatches.

[0045] although Figure 1 The illustration shows a case where the display area DA of the display device 1 is a quadrilateral, but the shape of the display area DA can be a circle, an ellipse, or a polygon such as a triangle or a pentagon.

[0046] Display device 1 may include pixels P arranged in display area DA. Each of pixels P may include an organic light-emitting diode (“OLED”). Each of pixels P can be represented by an organic light-emitting diode OLED (see [link to OLED display]). Figure 3 A pixel P can be understood as a pixel that emits light of any color, such as red, green, blue, or white. As mentioned above, a pixel P can be understood as a pixel that emits light of any color, such as red, green, blue, or white.

[0047] Figure 2 This is a schematic plan view of an embodiment of the display device.

[0048] Reference Figure 2 The display device 1 may include pixels P arranged in the display area DA. Each pixel P may be electrically connected to external circuitry arranged in the peripheral area PA. A first scan drive circuit 110, a transmit drive circuit 117, a second scan drive circuit 120, a terminal 140, a data drive circuit 150, a first power supply wiring 160, and a second power supply wiring 170 may be disposed in the peripheral area PA.

[0049] The first scan driving circuit 110 provides a scan signal to each pixel P via a scan line SL. The emission driving circuit 117 provides an emission control signal to each pixel P via an emission control line EL. The second scan driving circuit 120 can be configured parallel to the first scan driving circuit 110, and the display area DA is located between the second scan driving circuit 120 and the first scan driving circuit 110. In an embodiment, some pixels P arranged in the display area DA can be electrically connected to the first scan driving circuit 110, and other pixels P can be electrically connected to the second scan driving circuit 120. In an embodiment, the second scan driving circuit 120 can be omitted.

[0050] The transmit drive circuit 117 can be disposed in the peripheral region PA at a distance from the first scan drive circuit 110 in the x-direction. Furthermore, the transmit drive circuit 117 can be arranged alternately with the first scan drive circuit 110 in the x-direction.

[0051] Terminal 140 may be disposed on one side of substrate 100. Terminal 140 may be electrically connected to printed circuit board (PCB) while being exposed without being covered by an insulating layer. Terminal PCB-P of printed circuit board PCB may be electrically connected to terminal 140 of display device 1. Printed circuit board PCB may transmit signals or power from controller (not shown) to display device 1. Control signals generated from controller may be transmitted via printed circuit board PCB to each of the first scan drive circuit 110, the transmit drive circuit 117, and the second scan drive circuit 120. Controller may transmit a first power voltage ( ) via first connection wiring 161 and second connection wiring 171. Figure 3 and Figure 4 ELVDD, also known as drive voltage) and second power voltage ( Figure 3 and Figure 4 The ELVSS (also known as the common voltage) is provided to the first power line 160 and the second power line 170, respectively. The first power voltage ELVDD can be provided to each pixel P through the drive voltage line PL connected to the first power line 160, and the second power voltage ELVSS can be provided to the counter electrode of each pixel P connected to the second power line 170.

[0052] The data drive circuit 150 can be electrically connected to the data line DL. The data signal of the data drive circuit 150 can be provided to each pixel P through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151.

[0053] although Figure 2The data driving circuit 150 is shown disposed on a printed circuit board (PCB), but in an embodiment, the data driving circuit 150 may be disposed on a substrate 100. In an embodiment, for example, the data driving circuit 150 may be disposed between terminal 140 and the first power supply wiring 160.

[0054] The first power supply cabling 160 may include a first sub-cabling 162 and a second sub-cabling 163 extending parallel in the x-direction and with the display area DA located therebetween. The second power supply cabling 170 may have an annular shape with an open side and partially surround the display area DA.

[0055] Figure 3 and Figure 4 This is an equivalent circuit diagram of an embodiment of pixels in a display device.

[0056] Reference Figure 3 Each pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL, and an organic light-emitting diode (OLED) connected to the pixel circuit PC.

[0057] The pixel circuit PC may include a driving thin-film transistor (driving TFT; T1), a switching thin-film transistor (switching TFT; T2), and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and can transmit the data signal Dm input through the data line DL to the driving thin-film transistor T1 in response to a first scan signal Sn input through the scan line SL.

[0058] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and can store the charge corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the drive voltage ELVDD supplied through the drive voltage line PL.

[0059] The driving thin-film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) in response to the value of the charge stored in the storage capacitor Cst. The OLED can emit light with a predetermined brightness according to the driving current.

[0060] although Figure 3 The illustration shows a scenario where the pixel circuit PC includes two thin-film transistors and one storage capacitor, but the disclosure is not limited thereto. In embodiments, for example, the pixel circuit PC may include three or more thin-film transistors and / or two or more storage capacitors. In another embodiment, the pixel circuit PC may include seven thin-film transistors and one storage capacitor. In an alternative embodiment, the pixel circuit PC may include seven thin-film transistors and two storage capacitors.

[0061] Reference Figure 4 A pixel P may include a pixel circuit PC and an organic light-emitting diode (OLED) electrically connected to the pixel circuit PC.

[0062] In an embodiment, such as Figure 4 As shown, the pixel circuit PC may include multiple thin-film transistors T1 to T7 and a storage capacitor Cst. The thin-film transistors T1 to T7 and the storage capacitor Cst may be connected to signal lines SL1, SL2, SLp, SLn, EL and DL, the initialization voltage line VIL, and the drive voltage line PL. In an embodiment, at least one of the signal lines SL1, SL2, SLp, SLn, EL and DL, the initialization voltage line VIL, and the drive voltage line PL may be shared by adjacent pixels P.

[0063] Thin-film transistors T1 to T7 may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0064] Some of the thin-film transistors T1 to T7 can be configured as n-channel MOSFETs (“NMOS”) transistors, while the others can be configured as p-channel MOSFETs (“PMOS”) transistors.

[0065] In an embodiment, such as Figure 4 As shown, for example, among the thin-film transistors T1 to T7, the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 can be configured as NMOS transistors, and the other thin-film transistors can be configured as PMOS transistors.

[0066] In one embodiment, among the thin-film transistors T1 to T7, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, and the second initialization thin-film transistor T7 can be configured as NMOS transistors, while the other thin-film transistors can be configured as PMOS transistors. In an alternative embodiment, although only one of the thin-film transistors T1 to T7 can be configured as an NMOS transistor, the other thin-film transistors can be configured as PMOS transistors. In an alternative embodiment, all of the thin-film transistors T1 to T7 can be configured as NMOS transistors.

[0067] Signal lines SL1, SL2, SLp, SLn, EL, and DL may include a first scan line SL1 for transmitting a first scan signal Sn, a second scan line SL2 for transmitting a second scan signal Sn', a previous scan line SLp for transmitting a previous scan signal Sn-1 to a first initialization thin-film transistor T4, an emitt control line EL for transmitting an emitt control signal En to an operation control thin-film transistor T5 and an emitt control thin-film transistor T6, a next scan line SLn for transmitting a next scan signal Sn+1 to a second initialization thin-film transistor T7, and a data line DL that intersects with the first scan line SL1 and transmits a data signal Dm.

[0068] The driving voltage line PL can transmit the driving voltage ELVDD to the driving thin-film transistor T1, and the initialization voltage line VIL can transmit the initialization voltage Vint to initialize the driving thin-film transistor T1 and the pixel electrode.

[0069] The driving gate electrode of driving thin-film transistor T1 is connected to the storage capacitor Cst. The driving source region of driving thin-film transistor T1 is connected to the driving voltage line PL via operation control thin-film transistor T5. The driving drain region of driving thin-film transistor T1 is electrically connected to the pixel electrode of organic light-emitting diode (OLED) via emitter control thin-film transistor T6. Driving thin-film transistor T1 can receive the data signal Dm according to the switching operation of switching thin-film transistor T2, and transmit the driving current I... OLED Supply to organic light-emitting diodes (OLEDs).

[0070] The switching gate electrode of the switching thin-film transistor T2 is connected to the first scan line SL1, the switching source region of the switching thin-film transistor T2 is connected to the data line DL, and the switching drain region of the switching thin-film transistor T2 is connected to the driving source region of the driving thin-film transistor T1 and is connected to the driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on in response to the first scan signal Sn received through the first scan line SL1 to perform a switching operation that transmits the data signal Dm transmitted through the data line DL to the driving source region of the driving thin-film transistor T1.

[0071] The compensation gate electrode of the compensation thin-film transistor T3 can be connected to the second scan line SL2. The compensation drain region of the compensation thin-film transistor T3 is connected to the driving drain region of the driving thin-film transistor T1 and is connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The compensation source region of the compensation thin-film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin-film transistor T1. Furthermore, the compensation source region of the compensation thin-film transistor T3 is connected to the first initialization drain region of the first initialization thin-film transistor T4.

[0072] The compensation thin-film transistor T3 is turned on in response to the second scan signal Sn' received through the second scan line SL2, so as to electrically connect the driving gate electrode and the driving drain region of the driving thin-film transistor T1 to each other, thereby allowing the driving thin-film transistor T1 to be diode connected.

[0073] The first initialization gate electrode of the first initialization thin-film transistor T4 is connected to the previous scan line SLp. The first initialization source region of the first initialization thin-film transistor T4 is connected to the second initialization source region of the second initialization thin-film transistor T7 and the initialization voltage line VIL. The first initialization drain region of the first initialization thin-film transistor T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensation source region of the compensation thin-film transistor T3, and the driving gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on in response to the previous scan signal Sn-1 received through the previous scan line SLp to transmit the initialization voltage Vint to the driving gate electrode of the driving thin-film transistor T1, thereby performing an initialization operation to initialize the voltage of the driving gate electrode of the driving thin-film transistor T1.

[0074] The operation control gate electrode of the operation control thin film transistor T5 is connected to the emitter control line EL, the operation control source region of the operation control thin film transistor T5 is connected to the drive voltage line PL, and the operation control drain region of the operation control thin film transistor T5 is connected to the drive source region of the drive thin film transistor T1 and the switch drain region of the switch thin film transistor T2.

[0075] The emission control gate electrode of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source region of the emission control thin film transistor T6 is connected to the driving drain region of the driving thin film transistor T1 and the compensation drain region of the compensation thin film transistor T3. The emission control drain region of the emission control thin film transistor T6 is electrically connected to the second initialization drain region of the second initialization thin film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0076] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are simultaneously turned on in response to the emission control signal En received through the emission control line EL, so as to transfer the driving voltage ELVDD to the organic light-emitting diode OLED, thereby allowing the driving current I... OLED It flows within an organic light-emitting diode (OLED).

[0077] The second initialization gate electrode of the second initialization thin-film transistor T7 is connected to the next scan line SLn. The second initialization drain region of the second initialization thin-film transistor T7 is connected to the emission control drain region of the emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode (OLED). The second initialization source region of the second initialization thin-film transistor T7 is connected to the first initialization source region of the first initialization thin-film transistor T4 and the initialization voltage line VIL. The second initialization thin-film transistor T7 is turned on in response to the next scan signal Sn+1 received through the next scan line SLn, thereby initializing the pixel electrode of the organic light-emitting diode (OLED).

[0078] like Figure 4 As shown, the second initialization thin-film transistor T7 can be connected to the next scan line SLn. In an embodiment, the second initialization thin-film transistor T7 can be connected to the emitter control line EL to be driven according to the emitter control signal En. The positions of the source and drain regions can be switched between each other depending on the type of transistor (p-type or n-type).

[0079] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst is connected to the driving gate electrode of the driving thin-film transistor T1, and the upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst can store the charge corresponding to the difference between the voltage of the driving gate electrode of the driving thin-film transistor T1 and the driving voltage ELVDD.

[0080] In this embodiment, the detailed operation of each pixel P is as follows.

[0081] During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line SLp, the first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1, and the driving thin film transistor T1 is initialized by the initialization voltage Vint supplied to the driving thin film transistor T1 through the initialization voltage line VIL.

[0082] During the data programming period, when the first scan signal Sn and the second scan signal Sn' are supplied through the first scan line SL1 and the second scan line SL2 respectively, the switching thin-film transistor T2 and the compensation thin-film transistor T3 are turned on in response to the first scan signal Sn and the second scan signal Sn'. In this state, the driving thin-film transistor T1 is connected to the diode of the turned-on compensation thin-film transistor T3 and is biased in the forward direction.

[0083] Then, a compensation voltage (Dm+Vth) (where Vth is a negative (-) value) is applied to the driving gate electrode of the driving thin film transistor T1. The compensation voltage (Dm+Vth) is equal to the voltage obtained by subtracting the threshold voltage (Vth) of the driving thin film transistor T1 from the data signal Dm supplied through the data line DL.

[0084] The driving voltage ELVDD and the compensation voltage (Dm+Vth) are applied to the opposite terminals of the storage capacitor Cst, and the charge corresponding to the voltage difference between the opposite terminals is stored in the storage capacitor Cst.

[0085] During the light-emitting period, the operation control thin-film transistor T5 and the emission control thin-film transistor T6 are turned on by the emission control signal En supplied through the emission control line EL. A drive current I is generated based on the difference between the voltage at the drive gate electrode of the driving thin-film transistor T1 and the drive voltage ELVDD. OLED And drive current I OLED The emission control thin-film transistor T6 supplies power to the organic light-emitting diode (OLED).

[0086] In an embodiment, at least one of the thin-film transistors T1 to T7 may include a semiconductor layer comprising an oxide semiconductor, and the other thin-film transistors may include a semiconductor layer comprising a silicon semiconductor.

[0087] In detail, the driving thin-film transistor T1, which directly affects the brightness of the display device, includes a semiconductor layer comprising or composed of polycrystalline silicon with relatively high reliability, and through which a display device with relatively high resolution can be realized.

[0088] Because oxide semiconductors have relatively high carrier mobility and relatively low leakage current, the voltage drop is not large even during long drive times. In other words, even during relatively low-frequency drive, relatively low-frequency drive is possible because the color change in the voltage drop profile is minimal.

[0089] Thus, since oxide semiconductors have the advantage of relatively low leakage current, using oxide semiconductors as at least one of the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 connected to the drive gate electrode of the drive thin film transistor T1 can prevent leakage current that may flow to the drive gate electrode of the drive thin film transistor T1, and at the same time reduce power consumption.

[0090] In this embodiment, the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the emission control thin-film transistor T6, and the second initialization thin-film transistor T7 can be configured as a semiconductor layer including silicon semiconductor, and the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 can be configured as a semiconductor layer including oxide semiconductor. However, the disclosure is not limited thereto.

[0091] Figure 5 It is along Figure 1 A schematic cross-sectional view of the pixels captured by line I-I'. Figure 6 It is a graph schematically showing the content (e.g., weight percentage) of fluorine (F) in the first buffer layer, semiconductor layer and first inorganic insulating layer.

[0092] Reference Figure 5 The display panel 10 of the display device 1 may include a substrate 100, an inorganic insulating layer 118, an organic insulating layer 119, a pixel circuit PC, a connecting electrode CM, an organic light-emitting diode OLED, a pixel defining layer 118, a spacer 119, and an encapsulation layer 300. In other words, the substrate 100, the inorganic insulating layer 118, the organic insulating layer 119, the pixel circuit PC, the connecting electrode CM, the organic light-emitting diode OLED, the pixel defining layer 118, the spacer 119, and the encapsulation layer 300 may be disposed in the display area DA of the display panel 10.

[0093] The substrate 100 may include or be composed of various materials (such as glass, metal, plastic, etc.). When the substrate 100 is a flexible substrate, the substrate 100 may include, for example, polymer resins such as polyethersulfone (“PES”), polyacrylate (“PAR”), polyetherimide (“PEI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), polyphenylene sulfide (“PPS”), polyarylate, polyimide (“PI”), polycarbonate (“PC”), or cellulose acetate propionate (“CAP”)).

[0094] As an optional embodiment, substrate 100 may have a structure comprising two adjacent plastic substrates and an inorganic layer between the two plastic substrates. The two plastic substrates may comprise the aforementioned polymer resin and may have the same or different thicknesses. In an embodiment, both plastic substrates may both comprise polyimide and may have a thickness, for example, from 3 micrometers (μm) to 20 μm. The inorganic layer, serving as a barrier layer to prevent the penetration of external foreign matter, may comprise inorganic materials such as silicon nitride (SiN). x ) and / or silicon dioxide (SiO2) xThe inorganic layer may be a single layer or multiple layers. The inorganic layer may have a thickness of about 6000 angstroms (Å), but is not limited thereto.

[0095] A bottom metal layer (also called a metal layer) BML can be disposed on the substrate 100. The bottom metal layer BML may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The bottom metal layer BML can be a single layer or multiple layers of the above materials.

[0096] A buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 may include a first buffer layer 111a and a second buffer layer 111b. The second buffer layer 111b may be disposed below the first buffer layer 111a. The first buffer layer 111a may include SiO2. x The second buffer layer 111b may include SiN x .

[0097] The inorganic insulating layer IIL can be disposed on the buffer layer 111. The inorganic insulating layer IIL may include a first inorganic insulating layer 112, a second inorganic insulating layer 113, and a third inorganic insulating layer 114.

[0098] The pixel circuit PC can be disposed in the display area DA. The pixel circuit PC may include a thin-film transistor (TFT) and a storage capacitor Cst. The thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0099] The semiconductor layer Act may be disposed on the buffer layer 111. The semiconductor layer Act may include polysilicon. In an alternative embodiment, the semiconductor layer Act may include amorphous silicon. The semiconductor layer Act may include a channel region and drain and source regions disposed on opposite sides of the channel region.

[0100] The gate electrode GE can be disposed on the semiconductor layer Act. The gate electrode GE can be stacked with the channel region. The gate electrode GE can include a relatively low-resistance metallic material. The gate electrode GE can include conductive materials containing Mo, Al, Cu, titanium (Ti), etc., and can be formed as a multilayer or a single layer including the above materials.

[0101] The first inorganic insulating layer 112 can be disposed between the semiconductor layer Act and the gate electrode GE. The first inorganic insulating layer 112 may include inorganic insulating materials (such as silicon oxide (SiO2), SiN...). x Silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), ZnOx etc., including ZnO x It can be ZnO or ZnO2.

[0102] Figure 5 The thin-film transistor (TFT) shown in the figure can be Figure 4 The pixel circuit PC shown in the figure has a driving thin-film transistor T1.

[0103] When white-color stress is applied to the driving thin-film transistor TFT, a negative bias voltage is applied to the driving thin-film transistor TFT, which can reduce the driving range of the driving thin-film transistor TFT. Furthermore, as the amount of current flowing in the driving thin-film transistor TFT at the same voltage decreases, the brightness of the display device 1 can be reduced.

[0104] In this embodiment, based on the total weight of the first inorganic insulating layer 112, the content of compounds comprising SiO-H bonds or composed of SiO-H bonds in the first inorganic insulating layer 112 can be 0.9% or less. In this case, the concentration of hydrogen (H) in the first inorganic insulating layer 112 can be 7.55 × 10⁻⁶. 20 Atoms per cubic centimeter (atoms / cm) 3 (or less). When the content of compounds comprising SiO-H bonds or composed of SiO-H bonds in the first inorganic insulating layer 112 is 0.9% or less based on the total weight of the first inorganic insulating layer 112, this content can prevent the SiO-H bonds from acting as trap sites for electrons as they break at the interface between the first inorganic insulating layer 112 and the semiconductor layer Act. When the number of trap sites for electrons at the interface between the first inorganic insulating layer 112 and the semiconductor layer Act decreases, the driving range of the driving thin-film transistor TFT increases, and the amount of current flowing when the same voltage is applied to the driving thin-film transistor TFT can increase, thereby preventing a decrease in the brightness of the display device 1.

[0105] In this embodiment, based on the total weight of the first buffer layer 111a, the content of compounds comprising nitrogen-hydrogen (NH) bonds or composed of nitrogen-hydrogen (NH) bonds in the first buffer layer 111a can be 0.1% or less. In this case, the concentration of H in the first buffer layer 111a can be 8.5 × 10⁻⁶. 20 atoms / cm 3Or even less. When the content of NH bonds or compounds composed of NH bonds in the first buffer layer 111a is 0.1% or less based on the total weight of the first buffer layer 111a, this content can prevent the NH bonds from acting as trap sites for electrons as they break at the interface between the first buffer layer 111a and the semiconductor layer Act. When the number of trap sites for electrons at the interface between the first buffer layer 111a and the semiconductor layer Act decreases, the driving range of the driving thin-film transistor TFT increases, and the amount of current flowing when the same voltage is applied to the driving thin-film transistor TFT can increase, thereby preventing a decrease in the brightness of the display device 1.

[0106] When the semiconductor layer Act is set in SiO x When the first buffer layer 111a is applied, the threshold voltage of the driving thin-film transistor TFT may have a negative offset. By injecting fluorine (F) into the first buffer layer 111a and the semiconductor layer Act, the fluorine content at the interface between the first buffer layer 111a and the semiconductor layer Act can be increased, thus preventing the negative offset of the threshold voltage of the driving thin-film transistor TFT.

[0107] Reference Figure 6 The intensity indicated on the y-axis of the graph can be the fluorine content. In an embodiment, the fluorine content at the interface between the first buffer layer 111a and the semiconductor layer Act can be six times or more the minimum fluorine content in the lower part of the first buffer layer 111a. When the fluorine content at the interface between the first buffer layer 111a and the semiconductor layer Act is six times or more the minimum fluorine content in the lower part of the first buffer layer 111a, a negative shift in the threshold voltage of the driving thin-film transistor TFT can be prevented. Furthermore, since fluorine bonds with dangling bonds present at the interface between the first buffer layer 111a and the semiconductor layer Act, the amount of dangling bonds that can act as trap sites for electrons can be reduced, and the amount of current flowing when the same voltage is applied to the driving thin-film transistor TFT increases, thereby preventing a decrease in the brightness of the display device 1.

[0108] The second inorganic insulating layer 113 can be disposed on the gate electrode GE. The second inorganic insulating layer 113 can be configured to cover the gate electrode GE. The second inorganic insulating layer 113 may include materials such as SiO2 and SiN. x , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO x (Among them, ZnO) x It can be an inorganic insulating material such as ZnO or ZnO2.

[0109] The upper electrode CE2 of the storage capacitor Cst can be disposed on the second inorganic insulating layer 113. The upper electrode CE2 can be stacked with the gate electrode GE disposed below it. In this state, the gate electrode GE and the upper electrode CE2, which are stacked on top of each other and with the second inorganic insulating layer 113 located therebetween, can form the storage capacitor Cst. In other words, the gate electrode GE can be used as the lower electrode CE1 of the storage capacitor Cst.

[0110] Thus, the storage capacitor Cst and the thin-film transistor TFT can be formed to be stacked on top of each other. However, the disclosure is not limited thereto. In embodiments, for example, the storage capacitor Cst can be formed not to be stacked with the thin-film transistor TFT. In other words, the lower electrode CE1 of the storage capacitor Cst can be configured to be spaced apart from the gate electrode GE of the thin-film transistor TFT as a separate component from the gate electrode GE of the thin-film transistor TFT.

[0111] The upper electrode CE2 may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W and / or Cu, and may be a single layer or multiple layers of the above materials.

[0112] The third inorganic insulating layer 114 can be disposed on the upper electrode CE2. The third inorganic insulating layer 114 can cover the upper electrode CE2. The third inorganic insulating layer 114 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO x (Among them, ZnO) x It can be ZnO or ZnO2, etc. The third inorganic insulating layer 114 can be a single layer or multiple layers including the above-mentioned inorganic insulating materials.

[0113] The drain electrode DE and the source electrode SE can each be disposed on the third inorganic insulating layer 114. The drain electrode DE and the source electrode SE can each be connected to the semiconductor layer Act through contact holes in the first inorganic insulating layer 112, the second inorganic insulating layer 113, and the third inorganic insulating layer 114. The drain electrode DE and the source electrode SE can comprise materials with good conductivity. The drain electrode DE and the source electrode SE can each comprise a conductive material containing Mo, Al, Cu, Ti, etc., and can be formed as a multilayer or a single layer containing the aforementioned materials. In an embodiment, for example, the drain electrode DE and the source electrode SE can each have a Ti / Al / Ti multilayer structure.

[0114] An organic insulating layer (OIL) can be disposed on an inorganic insulating layer (IIL). The organic insulating layer (OIL) may include a first organic insulating layer (115) and a second organic insulating layer (116). Although... Figure 6The diagram shows an organic insulating layer (OIL) comprising two organic insulating layers, but the disclosure is not limited thereto. An organic insulating layer (OIL) may comprise three or four organic insulating layers.

[0115] The first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include organic insulating materials such as general-purpose polymers (such as polymethyl methacrylate (“PMMA” or polystyrene (“PS”)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and mixtures thereof.

[0116] A connecting electrode CM can be disposed on the first organic insulating layer 115. In this state, the connecting electrode CM can be connected to the drain electrode DE or the source electrode SE through contact holes in the first organic insulating layer 115. The connecting electrode CM can include a material with good conductivity. The connecting electrode CM can include conductive materials containing Mo, Al, Cu, Ti, etc., and can be formed as a multilayer or a single layer including the above materials. In an embodiment, for example, the connecting electrode CM can have a Ti / Al / Ti multilayer structure.

[0117] The second organic insulating layer 116 may be disposed on the connecting electrode CM. The second organic insulating layer 116 may cover the connecting electrode CM. The second organic insulating layer 116 may include the same material as the first organic insulating layer 115 or a different material.

[0118] A light-emitting diode (LED) can be disposed on the second organic insulating layer 116. In an embodiment, for example, an organic light-emitting diode (OLED) can be disposed on the second organic insulating layer 116. In an alternative embodiment, although not shown, an inorganic light-emitting diode or the like can be disposed on the second organic insulating layer 116.

[0119] Organic light-emitting diodes (OLEDs) can emit red, green, or blue light, or a combination of these colors or white light. An OLED may include a pixel electrode 211, an emitting layer 212b, a functional layer 212f, a counter electrode 213, and a capping layer 215.

[0120] Pixel electrode 211 may be disposed on the second organic insulating layer 116. Pixel electrode 211 may be electrically connected to connection electrode CM through contact holes defined in the second organic insulating layer 116. Pixel electrode 211 may include a conductive oxide such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or zinc aluminum oxide (“AZO”). In embodiments, pixel electrode 211 may include a reflective film comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds or mixtures thereof. In embodiments, pixel electrode 211 may also include a film comprising ITO, IZO, ZnO, or In2O3, or composed of ITO, IZO, ZnO, or In2O3, above / below the aforementioned reflective film. In embodiments, for example, pixel electrode 211 may have a multilayer structure of ITO / Ag / ITO.

[0121] A pixel defining layer 118 may be disposed on the pixel electrode 211, and an opening is defined in the pixel defining layer 118 to expose at least a portion of the pixel electrode 211. The emission region of light emitted from the organic light-emitting diode (OLED) may be defined by the opening defined in the pixel defining layer 118. In an embodiment, for example, the width of the opening may correspond to the width of the emission region.

[0122] Pixel defining layer 118 may include an organic insulating material. In an alternative embodiment, pixel defining layer 118 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. In an alternative embodiment, pixel defining layer 118 may include both organic and inorganic insulating materials. In an embodiment, pixel defining layer 118 may include a light-blocking material. The light-blocking material may include a resin or paste containing a black dye, carbon black, carbon nanotubes, metal particles (e.g., nickel, aluminum, molybdenum, and alloys thereof), metal oxide particles (e.g., chromium oxide), metal nitride particles (e.g., chromium nitride), etc. When pixel defining layer 118 includes a light-blocking material, reflection of external light caused by the metal structure disposed beneath pixel defining layer 118 can be reduced.

[0123] Spacer 119 may be disposed on pixel defining layer 118. Spacer 119 may include an organic insulating material such as polyimide. In an alternative embodiment, spacer 119 may include an inorganic insulating material such as SiN. x (or SiO2) or organic insulating materials and inorganic insulating materials.

[0124] In one embodiment, the spacer 119 may comprise the same material as the pixel defining layer 118. In this case, the pixel defining layer 118 and the spacer 119 may be formed together in a masking process using a halftone mask or the like. In an alternative embodiment, the spacer 119 and the pixel defining layer 118 may comprise different materials from each other.

[0125] The emitting layer 212b may be disposed in the opening of the pixel defining layer 118. The emitting layer 212b may comprise a polymer or a relatively low molecular weight organic material that emits light of a predetermined color.

[0126] Functional layer 212f may include a first functional layer 212a and a second functional layer 212c. The first functional layer 212a may be disposed between the pixel electrode 211 and the emitter layer 212b, and the second functional layer 212c may be disposed between the emitter layer 212b and the counter electrode 213. However, at least one of the first functional layer 212a and the second functional layer 212c may be omitted. In the following description, the case in which each of the first functional layer 212a and the second functional layer 212c is arranged is described in detail.

[0127] The first functional layer 212a may include a hole transport layer (“HTL”) and / or a hole injection layer (“HIL”). The second functional layer 212c may include an electron transport layer (“ETL”) and / or an electron injection layer (“EIL”). The first functional layer 212a and / or the second functional layer 212c may each be formed as a common layer covering the entire substrate 100, as described below for the counter electrode 213.

[0128] Counter electrode 213 may be disposed on functional layer 212f. Counter electrode 213 may comprise a conductive material having a relatively low work function. In embodiments, for example, counter electrode 213 may comprise a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, alloys thereof, etc. In alternative embodiments, counter electrode 213 may further comprise a layer comprising ITO, IZO, ZnO, or In2O3 on a (semi-)transparent layer comprising the aforementioned material.

[0129] In an embodiment, a capping layer 215 may be disposed on the counter electrode 213. The capping layer 215 may comprise inorganic materials (such as LiF) and / or organic materials.

[0130] The encapsulation layer 300 can be disposed on the organic light-emitting diode (OLED). The encapsulation layer 300 can cover the OLED. The encapsulation layer 300 can be disposed on the counter electrode 213 and / or the capping layer 215. In an embodiment, the encapsulation layer 300 may include at least one inorganic film layer and at least one organic film layer. Figure 5The encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 stacked sequentially.

[0131] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each comprise one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each be a single layer or multiple layers comprising the aforementioned materials. The organic encapsulation layer 320 may comprise polymeric materials. Polymeric materials may include acrylic resins, epoxy resins, polyimides, polyethylene, etc. In an embodiment, the organic encapsulation layer 320 may comprise acrylates.

[0132] The touch sensor layer 400 can be disposed on the encapsulation layer 300. The touch sensor layer 400 may include a first touch insulating layer 410, a second touch insulating layer 420, a first conductive layer 430, a third touch insulating layer 440, a second conductive layer 450, and a planarization layer 460.

[0133] In an embodiment, a first touch insulating layer 410 may be disposed on a second inorganic encapsulation layer 330, and a second touch insulating layer 420 may be disposed on a first touch insulating layer 410. In an embodiment, the first touch insulating layer 410 and the second touch insulating layer 420 may each comprise an inorganic insulating material and / or an organic insulating material. In an embodiment, for example, the first touch insulating layer 410 and the second touch insulating layer 420 may each comprise an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0134] In this embodiment, at least one of the first touch insulating layer 410 and the second touch insulating layer 420 may be omitted. For example, the first touch insulating layer 410 may be omitted. In this case, the second touch insulating layer 420 may be disposed on the second inorganic encapsulation layer 330, and the first conductive layer 430 may be disposed on the second touch insulating layer 420.

[0135] A first conductive layer 430 may be disposed on a second touch insulating layer 420, and a third touch insulating layer 440 may be disposed on a first conductive layer 430. In an embodiment, the third touch insulating layer 440 may include an inorganic insulating material and / or an organic insulating material. In an embodiment, for example, the third touch insulating layer 440 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0136] The second conductive layer 450 may be disposed on the third touch insulating layer 440. The touch electrode TE of the touch sensor layer 400 may have a structure in which the first conductive layer 430 and the second conductive layer 450 are connected to each other. In an alternative embodiment, the touch electrode TE may be formed on either the first conductive layer 430 or the second conductive layer 450, and may include metal wires on the respective conductive layers. The first conductive layer 430 and the second conductive layer 450 may each include at least one of Al, Cu, Ti, Mo, and ITO, and may include a single layer or multiple layers containing the above materials. In an embodiment, for example, the first conductive layer 430 and the second conductive layer 450 may each have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0137] In one embodiment, the planarization layer 460 may cover the second conductive layer 450. The planarization layer 460 may include an organic insulating material.

[0138] In this embodiment, the concentration of H in the first inorganic insulating layer 112 disposed above the driving thin-film transistor TFT, which comprises silicon semiconductor material, is 7.55 × 10⁻⁶. 20 atoms / cm 3 Or even less, based on the total weight of the first buffer layer 111a, the content of compounds comprising NH bonds or composed of NH bonds in the first buffer layer 111a disposed below the driving thin-film transistor TFT is 0.1% or less, and the concentration of H in the first buffer layer 111a is 8.5 × 10⁻⁶. 20 atoms / cm 3 Or even smaller. Therefore, the number of trap sites for electrons can be reduced at the upper and lower interfaces of the semiconductor layer Act of the driving thin-film transistor TFT, thereby increasing the amount of current flowing when the same voltage is applied to the driving thin-film transistor TFT, and during white light stress, a negative bias is applied to the driving thin-film transistor TFT, thereby preventing the brightness of the display device 1 from decreasing.

[0139] As described above, in the embodiments, a display device with improved reliability and quality can be achieved. The scope of the disclosure is not limited to the above effects.

[0140] It should be understood that the embodiments described herein should be considered descriptively only and not for limiting purposes. The description of features or advantages within each embodiment should generally be considered applicable to other similar features or advantages in other embodiments. Although embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims.

Claims

1. A display device, the display device comprising: Base; A first buffer layer is disposed on the substrate; A thin-film transistor includes: a semiconductor layer disposed on a first buffer layer; and a gate electrode insulated from the semiconductor layer; and A first inorganic insulating layer is disposed between the semiconductor layer and the gate electrode. The hydrogen concentration in the first inorganic insulating layer is 7.55 × 10⁻⁶. 20 Atoms per cubic centimeter or smaller, and Based on the total weight of the first buffer layer, the content of compounds including nitrogen-hydrogen bonds in the first buffer layer is 0.1% or less.

2. The display device according to claim 1, wherein, The hydrogen concentration in the first buffer layer is 8.5 × 10⁻⁶. 20 Atoms per cubic centimeter or smaller.

3. The display device according to claim 1, wherein, The first buffer layer comprises silicon oxide.

4. The display device according to claim 1, wherein the display device further comprises a second buffer layer disposed below the first buffer layer.

5. The display device according to claim 4, wherein, The second buffer layer comprises silicon nitride.

6. The display device according to claim 1, wherein, The first inorganic insulating layer comprises silicon oxide.

7. The display device according to claim 1, wherein, The fluorine content at the interface between the first buffer layer and the semiconductor layer is six times or more the minimum fluorine content in the lower part of the first buffer layer.

8. The display device according to claim 1, wherein, The semiconductor layer comprises silicon semiconductor material.

9. The display device according to claim 1, wherein the display device further comprises a metal layer disposed on the substrate.

10. The display device according to claim 1, wherein, The thin-film transistor includes a driving thin-film transistor.

11. The display device according to claim 1, wherein, The substrate includes a glass material.

12. The display device according to claim 1, wherein, The substrate includes an inorganic layer disposed between adjacent plastic substrates.

13. The display device according to claim 12, wherein, Each of the plastic substrates comprises polyimide.

14. The display device according to claim 12, wherein, The inorganic layer includes silicon oxide.

15. The display device according to claim 1, wherein the display device further comprises an organic insulating layer disposed on the first inorganic insulating layer.

16. The display device according to claim 15, further comprising an organic light-emitting diode disposed on the organic insulating layer.

17. The display device according to claim 16, wherein, The organic light-emitting diode includes a pixel electrode, an emitter layer, and a counter electrode.

18. The display device according to claim 17, further comprising an encapsulation layer disposed on the organic light-emitting diode.

19. The display device according to claim 18, wherein, The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

20. The display device according to claim 1, further comprising a storage capacitor disposed on the thin-film transistor.

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