Display device, electronic device, and method of manufacturing display device

Abstract

The invention provides a display device, an electronic device and a method of manufacturing the display device. The display device includes: a first sub-pixel; a second sub-pixel; the pixel circuit layer comprises a pixel circuit; a first sub-pixel region formed by the first sub-pixels; a second sub-pixel region formed by a second sub-pixel; a 1-1 light-emitting element on the pixel circuit layer, a 1-2 light-emitting element on the 1-1 light-emitting element, and a 1-3 light-emitting element on the 1-2 light-emitting element, where the 1-1 light-emitting element, the 1-2 light-emitting element, and the 1-3 light-emitting element are in the first sub-pixel region; and a 2-1 light-emitting element on the pixel circuit layer, a 2-2 light-emitting element on the 2-1 light-emitting element, and a 2-3 light-emitting element on the 2-2 light-emitting element, where the 2-1 light-emitting element, the 2-2 light-emitting element, and the 2-3 light-emitting element are in the second sub-pixel region, where the 1-3 light-emitting element is not electrically connected to the pixel circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0060795, filed on May 8, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Some aspects of embodiments of this disclosure relate to display devices, electronic devices, and methods of manufacturing display devices. Background Technology

[0004] With the development of information technology, the importance of display devices as the connection medium between users and information has become increasingly prominent. Therefore, research and development of display devices are constantly being carried out.

[0005] Display devices may need to have high resolution to display high-quality images (or videos).

[0006] The information disclosed in this "Background Art" section is only intended to enhance the understanding of the background, and therefore the information discussed in this "Background Art" section does not necessarily constitute prior art. Summary of the Invention

[0007] Some aspects of embodiments of this disclosure include a display device capable of displaying images with relatively high resolution and a method of manufacturing the display device.

[0008] Some aspects of embodiments of this disclosure include a display device capable of improving light efficiency and relatively simplifying the manufacturing process, and a method of manufacturing the display device.

[0009] According to some embodiments of the present disclosure, a display device includes: a first sub-pixel; a second sub-pixel; a pixel circuit layer including a pixel circuit; a 1-1 light-emitting element on the pixel circuit layer, a 1-2 light-emitting element on the 1-1 light-emitting element, and a 1-3 light-emitting element on the 1-2 light-emitting element, wherein the 1-1 light-emitting element, the 1-2 light-emitting element, and the 1-3 light-emitting element are located in a first sub-pixel region formed by the first sub-pixel; and a 2-1 light-emitting element on the pixel circuit layer, a 2-2 light-emitting element on the 2-1 light-emitting element, and a 2-3 light-emitting element on the 2-2 light-emitting element, wherein the 2-1 light-emitting element, the 2-2 light-emitting element, and the 2-3 light-emitting element are located in a second sub-pixel region formed by the second sub-pixel, wherein the 1-3 light-emitting element may not be electrically connected to the pixel circuit.

[0010] According to some embodiments, the 2-2 light-emitting element may not be electrically connected to the pixel circuit, and the 1-1 light-emitting element, 1-2 light-emitting element, 2-1 light-emitting element and 2-3 light-emitting element may be electrically connected to the pixel circuit.

[0011] According to some embodiments, the display device may further include: a 1-1 electrode configured to electrically connect the pixel circuit to the 1-1 light-emitting element; a 1-2 electrode configured to electrically connect the pixel circuit to the 1-2 light-emitting element; a 2-1 electrode configured to electrically connect the pixel circuit to the 2-1 light-emitting element; and a 2-2 electrode configured to electrically connect the pixel circuit to the 2-3 light-emitting element, wherein the 1-2 electrode may not overlap with the 1-1 light-emitting element in a planar view.

[0012] According to some embodiments, the display device may further include: a first interlayer insulating layer, at least a portion of which is between light-emitting element 1-1 and light-emitting element 1-2 and between light-emitting element 2-1 and light-emitting element 2-2; and a second interlayer insulating layer, at least a portion of which is between light-emitting element 1-2 and light-emitting element 1-3 and between light-emitting element 2-2 and light-emitting element 2-3, wherein the second interlayer insulating layer may completely cover the lower surface of light-emitting element 1-3 and may expose at least a portion of the lower surface of light-emitting element 2-3.

[0013] According to some embodiments, the display device may further include: a first insulating layer surrounding light-emitting elements 1-1 and 2-1; a second insulating layer surrounding light-emitting elements 1-2 and 2-2; and a third insulating layer surrounding light-emitting elements 1-3 and 2-3, wherein electrodes 1-2 can pass through the first insulating layer, and electrodes 2-2 can pass through the first and second insulating layers.

[0014] According to some embodiments, the display device may further include a first electrode and a second electrode electrically connected to the pixel circuit, wherein the second electrode may not overlap with the 1-1 light-emitting element and the 2-1 light-emitting element in a planar view, the first electrode may be an anode, and the second electrode may be a cathode.

[0015] According to some embodiments, the display device may further include: a first insulating layer configured to surround 1-1 light-emitting element and 2-1 light-emitting element; a second insulating layer configured to surround 1-2 light-emitting element and 2-2 light-emitting element; and a third insulating layer configured to surround 1-3 light-emitting element and 2-3 light-emitting element, wherein the second electrode may pass through the first insulating layer, the second insulating layer and the third insulating layer.

[0016] According to some embodiments, the display device may further include: a first conductive layer configured to electrically connect the second electrode to a 1-1 light-emitting element; a second conductive layer configured to electrically connect the second electrode to a 1-2 light-emitting element; and a third conductive layer configured to electrically connect the second electrode to a 1-3 light-emitting element, wherein each of the first conductive layer, the second conductive layer, and the third conductive layer may include at least a portion of the same material as the second electrode.

[0017] According to some embodiments, each of the first conductive layer, the second conductive layer, and the third conductive layer can be integrally connected to the second electrode, and the first conductive layer, the second conductive layer, the third conductive layer, and the second electrode can have a mesh pattern shape in a planar view.

[0018] According to some embodiments, the first conductive layer and the second electrode may be located outside the area in the plan view where light-emitting elements 1-1 and 2-1 are located.

[0019] According to some embodiments, the display device may further include: a first connecting electrode on a first conductive layer; a second connecting electrode on a second conductive layer; and a third connecting electrode on a third conductive layer, wherein the first connecting electrode may cover the upper surface of the 1-1 light-emitting element, the second connecting electrode may cover the upper surface of the 1-2 light-emitting element, and the third connecting electrode may cover the upper surface of the 1-3 light-emitting element.

[0020] According to some embodiments, light-emitting elements 1-1 and 2-1 can emit a first light, light-emitting elements 1-2 and 2-2 can emit a second light, and light-emitting elements 1-3 and 2-3 can emit a third light, wherein the first light, the second light, and the third light can be light of different colors.

[0021] According to some embodiments of the present disclosure, a display device is provided, comprising: a pixel circuit layer including pixel circuits; a 1-1 light-emitting element on the pixel circuit layer; a 1-2 light-emitting element on the 1-1 light-emitting element; a 1-3 light-emitting element on the 1-2 light-emitting element; a 2-1 light-emitting element on the same layer as the 1-1 light-emitting element; a 2-2 light-emitting element on the same layer as the 1-2 light-emitting element; and a 2-3 light-emitting element on the same layer as the 1-3 light-emitting element, wherein the 1-3 light-emitting element and the 2-2 light-emitting element may not be electrically connected to the pixel circuit.

[0022] According to some embodiments, the display device may further include: a first insulating layer surrounding 1-1 light-emitting element and 2-1 light-emitting element; a second insulating layer surrounding 1-2 light-emitting element and 2-2 light-emitting element; a third insulating layer surrounding 1-3 light-emitting element and 2-3 light-emitting element; a 1-1 electrode configured to electrically connect a pixel circuit to the 1-1 light-emitting element; a 1-2 electrode configured to electrically connect a pixel circuit to the 1-2 light-emitting element; a 2-1 electrode configured to electrically connect a pixel circuit to the 2-1 light-emitting element; and a 2-2 electrode configured to electrically connect a pixel circuit to the 2-3 light-emitting element, wherein the 1-2 electrode can pass through the first insulating layer, and the 2-2 electrode can pass through the first insulating layer and the second insulating layer.

[0023] According to some embodiments, the display device may further include: a first interlayer insulating layer, at least a portion of which is between light-emitting element 1-1 and light-emitting element 1-2 and between light-emitting element 2-1 and light-emitting element 2-2; and a second interlayer insulating layer, at least a portion of which is between light-emitting element 1-2 and light-emitting element 1-3 and between light-emitting element 2-2 and light-emitting element 2-3, wherein the second interlayer insulating layer may completely cover the lower surface of light-emitting element 1-3.

[0024] According to some embodiments, the display device may further include: a first electrode and a second electrode electrically connected to the pixel circuit, wherein the second electrode may not overlap with the 1-1 light-emitting element and the 2-1 light-emitting element in a planar view.

[0025] According to some embodiments, the first electrode may include: electrode 1-1 configured to electrically connect the pixel circuit to the light-emitting element 1-1; electrode 1-2 configured to electrically connect the pixel circuit to the light-emitting element 1-2; electrode 2-1 configured to electrically connect the pixel circuit to the light-emitting element 2-1; and electrode 2-2 configured to electrically connect the pixel circuit to the light-emitting element 2-3, wherein the light-emitting elements 1-3 and 2-2 may not be electrically connected to the first electrode.

[0026] According to some embodiments of this disclosure, in a method of manufacturing a display device, the display device includes a first sub-pixel region formed by a first sub-pixel and a second sub-pixel region formed by a second sub-pixel. The method includes: forming a pixel circuit layer including pixel circuitry; forming a 1-1 base electrode and a 1-2 base electrode electrically connected to the pixel circuitry in the first sub-pixel region; forming a 1-1 light-emitting element on the pixel circuit layer; forming a 1-2 light-emitting element on the 1-1 light-emitting element; and forming a 1-3 light-emitting element on the 1-2 light-emitting element; and in the second sub-pixel region... A base electrode 2-1 and a base electrode 2-2 are formed that are electrically connected to the pixel circuit. A light-emitting element 2-1 is formed on the pixel circuit layer. A light-emitting element 2-2 is formed on the light-emitting element 2-1. A light-emitting element 2-3 is formed on the light-emitting element 2-2. The base electrode 1-1 can be electrically connected to the light-emitting element 1-1. The base electrode 1-2 can be electrically connected to the light-emitting element 1-2. The base electrode 2-1 can be electrically connected to the light-emitting element 2-1. The base electrode 2-2 can be electrically connected to the light-emitting element 2-3. The light-emitting element 1-3 can be unconnected to the pixel circuit.

[0027] According to some embodiments, the method may further include: forming a base insulating layer on a pixel circuit layer; forming a first insulating layer on the base insulating layer; forming a first interlayer insulating layer on the first insulating layer; forming a second insulating layer on the first interlayer insulating layer; and forming a second interlayer insulating layer on the second insulating layer, wherein forming the first insulating layer may include depositing the first base insulating layer, etching the first base insulating layer to form a first contact opening exposing 1-2 base electrodes, and etching the first base insulating layer to form a second contact opening exposing 2-2 base electrodes, and forming the second insulating layer may include depositing the second base insulating layer and etching the second base insulating layer to form a third contact opening overlapping the second contact opening.

[0028] According to some embodiments, during the formation of the 2-2 light-emitting element, the 2-2 light-emitting element can be formed such that the lower surface of the 2-2 light-emitting element is in complete contact with the first interlayer insulating layer.

[0029] An electronic device includes: a processor for providing input image data; and a display device for displaying an image based on the input image data. The display device includes: a first sub-pixel; a second sub-pixel; a pixel circuit layer including pixel circuitry; a 1-1 light-emitting element, a 1-2 light-emitting element on the 1-1 light-emitting element, and a 1-3 light-emitting element on the 1-2 light-emitting element, and a 2-1 light-emitting element, a 2-2 light-emitting element on the 2-1 light-emitting element, and a 2-3 light-emitting element on the 2-2 light-emitting element, all on the pixel circuit layer. Light-emitting elements 1-1, 1-2, and 1-3 are located in a first sub-pixel region formed by the first sub-pixel. Light-emitting elements 2-1, 2-2, and 2-3 are located in a second sub-pixel region formed by the second sub-pixel. Light-emitting element 1-3 is not electrically connected to the pixel circuitry. Attached Figure Description

[0030] Figure 1 This is a schematic plan view of a display device according to some embodiments.

[0031] Figure 2 It is a schematic plan view of pixels according to some embodiments.

[0032] Figure 3 This is an equivalent circuit diagram of a pixel according to some embodiments.

[0033] Figure 4 and Figure 5 This is a schematic cross-sectional view of a display device according to some embodiments.

[0034] Figure 6 This is a schematic plan view of the second electrode according to some embodiments.

[0035] Figures 7 to 55This is a schematic diagram illustrating each process operation of a method for manufacturing a display device according to some embodiments of the present disclosure.

[0036] Figure 56 This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment.

[0037] Figure 57 It is shown Figure 56 The diagram illustrates an example of an electronic device, such as a smartphone.

[0038] Figure 58 It is shown Figure 56 The electronic device is a schematic diagram of an example of a tablet computer. Detailed Implementation

[0039] Because this disclosure can be applied in various forms and has various embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the "Detailed Description" section. However, it should be understood that this is not intended to limit this disclosure to the specific form disclosed, but rather to include all modifications, equivalents, and substitutions included within the technical scope of this disclosure.

[0040] The terms "first," "second," etc., may be used only to describe various constituent elements, but their meanings are not limited to the specific meanings. The above terms are used only to distinguish one constituent element from other constituent elements. For example, within the scope of the appended claims, a first constituent element may be referred to as a second constituent element, and similarly, a second constituent element may be referred to as a first constituent element. Singular expressions include plural expressions, provided they can be clearly and distinctly interpreted.

[0041] In this specification, the terms "comprising" or "having" are used to specify the presence of features, values, processes, operations, constituent elements, components, or combinations thereof, and it will be understood that this does not preclude the possibility of the presence or addition of one or more other features, values, processes, operations, constituent elements, components, or combinations thereof. Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intervening elements. Additionally, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being located "on" another element, the arrangement direction is not limited to the upper direction and includes the lateral or lower direction. Conversely, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "below" another element, the element may be directly below the other element or there may be intervening elements.

[0042] Some aspects of embodiments of this disclosure relate to display devices and methods of manufacturing display devices. Hereinafter, display devices and methods of manufacturing display devices according to embodiments will be described with reference to the accompanying drawings.

[0043] Figure 1 This is a schematic plan view of a display device DD according to some embodiments. Figure 2 This is a schematic plan view of pixel PXL according to some embodiments.

[0044] refer to Figure 1 The display device DD is configured to emit light. The display device DD includes a light-emitting element LD (see [link to DD]). Figure 3 According to some embodiments, the display device DD can be a device for displaying moving or still images. The display device DD can be used as a display screen for various products such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), as well as for devices such as televisions, laptops, monitors, billboards, and devices for the Internet of Things (IoT). However, the application areas of the display device DD are not limited to the specific examples.

[0045] The display device DD can be formed as a rectangular planar shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corner where the short side in the first direction DR1 intersects the long side in the second direction DR2 can be rounded to have a certain curvature, or it can be formed at a right angle. The planar shape of the display device DD is not limited to a quadrilateral shape, and can be formed as other shapes such as another polygon, a circle, an ellipse, or an irregular shape. Furthermore, in various embodiments, the corners of the display device DD can be rounded or curved. The display device DD can be formed as a flat shape, but the embodiments are not limited to this. For example, the display device DD can include curved portions formed at each of the left and right ends and having a constant or variable curvature. Moreover, the display device DD can be flexibly formed as flexible, bendable, foldable, or rollable without damaging the display device DD. For example, according to some embodiments, the display device DD can be a flexible display device.

[0046] In this disclosure, the first direction DR1 can be a "horizontal" direction that is the row direction of pixel PXL. The second direction DR2 can be the column direction of pixel PXL. The third direction DR3 can be the display direction of the display device DD or the normal direction of the plane on which the base layer BSL is located.

[0047] The base layer (BSL) can form the base surface of the display device (DD). The base layer (BSL) can be a rigid or flexible substrate or film. For example, the base layer (BSL) can be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal, or at least one insulating layer. The material and / or physical properties of the base layer (BSL) are not particularly limited. According to some embodiments, the base layer (BSL) can be transparent (or substantially transparent). Here, the term "substantially transparent" can mean that light can be transmitted at a certain level of transmittance or a higher level of transmittance. In other embodiments, the base layer (BSL) can be translucent or opaque. Furthermore, according to some embodiments, the base layer (BSL) may include a reflective material.

[0048] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may refer to an area other than the display area DA. The non-display area NDA may surround at least a portion of the display area DA.

[0049] The display area DA can refer to the area where pixel PXL is located. The non-display area NDA can refer to the area where pixel PXL is not located. The driving circuit units, lines, and pads of pixel PXL connected to the display area DA can be located in the non-display area NDA.

[0050] According to some embodiments, a pixel PXL (or sub-pixel SPX) may include a first sub-pixel SPX1 and a second sub-pixel SPX2. At least one first sub-pixel SPX1 and at least one second sub-pixel SPX2 may form a pixel unit PXU capable of emitting light in various colors. Figure 1 The illustration shows that each pixel PXL comprises two sub-pixels (i.e., a first sub-pixel SPX1 and a second sub-pixel SPX2), but the embodiments in this specification are not limited thereto.

[0051] The first sub-pixel SPX1 can emit at least one of a first light and a second light, and the second sub-pixel SPX2 can emit at least one of a first light and a third light. For example, the first sub-pixel SPX1 can emit only the first light, only the second light, or light that includes both the first and second light (e.g., light that includes light components of both the first and second light). Similarly, the second sub-pixel SPX2 can emit only the first light, only the third light, or light that includes both the first and third light (e.g., light that includes light components of both the first and third light). Accordingly, the first sub-pixel SPX1 and the second sub-pixel SPX2 can form a pixel unit PXU, and the display device DD can form a pixel structure capable of displaying a full-color image.

[0052] The first, second, and third lights can be various lights of different colors. Here, the first light can be light in the red band, the second light can be light in the green band, and the third light can be light in the blue band. The red band can be from 600 nanometers (nm) (or about 600 nm) to 750 nm (or about 750 nm), the green band can be from 480 nm (or about 480 nm) to 560 nm (or about 560 nm), and the blue band can be from 370 nm (or about 370 nm) to 460 nm (or about 460 nm), but the embodiments according to this disclosure are not limited thereto. For example, the first light can be light in the blue band, the second light can be light in the green band, and the third light can be light in the red band. For example, the first light can be light in the blue band, the second light can be light in the red band, and the third light can be light in the green band.

[0053] According to some embodiments, the pixel PXL (or sub-pixel SPX) can be arranged according to various arrangement structures, and is not particularly limited thereto according to embodiments of this disclosure.

[0054] refer to Figure 2 The display device DD may include a first pixel PXL1 and a second pixel PXL2. Pixel PXL may include the first pixel PXL1 and the second pixel PXL2. According to some embodiments, the first pixel PXL1 and the second pixel PXL2 may be adjacent to each other in the second direction DR2.

[0055] The first pixel PXL1 may include a first sub-pixel SPX1 and a second sub-pixel SPX2. The first sub-pixel SPX1 and the second sub-pixel SPX2 may be arranged in a first direction DR1 (e.g., a horizontal direction). However, embodiments according to this disclosure are not limited thereto, and the first sub-pixel SPX1 and the second sub-pixel SPX2 may be arranged in a second direction DR2 (e.g., a column direction).

[0056] In the following description, for ease of description, an embodiment based on the first sub-pixel SPX1 and the second sub-pixel SPX2 being adjacent to each other in the first direction DR1 will be provided.

[0057] The second pixel PXL2 may include a first sub-pixel SPX1' and a second sub-pixel SPX2'. The first sub-pixel SPX1' and the second sub-pixel SPX2' may be arranged in a first direction DR1 (e.g., the horizontal direction). However, embodiments according to this disclosure are not limited thereto, and the first sub-pixel SPX1' and the second sub-pixel SPX2' may be arranged in a second direction DR2 (e.g., the column direction).

[0058] In the following description, for ease of description, an embodiment based on the first sub-pixel SPX1' and the second sub-pixel SPX2' being adjacent to each other in the first direction DR1 will be described.

[0059] The first sub-pixel SPX1 of the first pixel PXL1 and the first sub-pixel SPX1' of the second pixel PXL2 can be arranged diagonally. The second sub-pixel SPX2 of the first pixel PXL1 and the second sub-pixel SPX2' of the second pixel PXL2 can also be arranged diagonally.

[0060] In this specification, the diagonal direction can be the direction extending between the first direction DR1 and the second direction DR2.

[0061] Accordingly, the sub-pixels SPX1, SPX1', SPX2, and SPX2' of the first pixel PXL1 and the second pixel PXL2 can be arranged in various configurations. For example, the sub-pixels SPX1, SPX1', SPX2, and SPX2' of the first pixel PXL1 and the second pixel PXL2 can be arranged in hexagonal, rectangular, or square configurations.

[0062] Each of the first sub-pixel SPX1 and the second sub-pixel SPX2 may include an inorganic light-emitting element as a light-emitting element, wherein the inorganic light-emitting element includes an inorganic semiconductor. For example, each of the first sub-pixel SPX1 and the second sub-pixel SPX2 may include an inorganic light-emitting element... Figure 4 and Figure 5 The light-emitting element LD is shown in the figure.

[0063] Figure 3 This is an equivalent circuit diagram of pixel PXL according to some embodiments. Although Figure 3 Various components in a pixel circuit PXC according to some embodiments are shown, but embodiments of the present disclosure are not limited thereto, and in some embodiments the pixel circuit PXC may include additional components without departing from the spirit and scope of embodiments of the present disclosure.

[0064] Figure 3 The electrical connections of components included in a pixel PXL, which can be applied to an active display device, are shown. However, the types of components included in the pixel PXL are not necessarily limited to this. According to some embodiments, Figure 3 The pixel PXL shown can be included in Figure 1 One of the first sub-pixel SPX1 and the second sub-pixel SPX2 in the display device DD.

[0065] refer to Figure 3Each pixel PXL may include a light-emitting element LD that generates light with a brightness corresponding to the data signal. Pixel PXL may include pixel circuitry PXC configured to drive the light-emitting element LD.

[0066] According to some embodiments, a pixel PXL may include at least one light-emitting element LD electrically connected between a first power line PL1 to which a first power voltage ELVDD is applied and a second power line PL2 to which a second power voltage ELVSS is applied. For example, the light-emitting element LD may include a first electrode ET1 connected (e.g., electrically connected) to the pixel circuit PXC and the first power line PL1, and a second electrode ET2 connected (e.g., electrically connected) to the second power line PL2. According to some embodiments, the first electrode ET1 may be an anode, and the second electrode ET2 may be a cathode. The light-emitting element LD may also include a light-emitting structure LS that emits light by receiving voltage via the first electrode ET1 and the second electrode ET2 (see [link to LS]). Figure 4 The light-emitting structure LS will subsequently pass through... Figure 4 The accompanying figures and diagrams will provide a more detailed description.

[0067] The first power voltage ELVDD and the second power voltage ELVSS can have different potentials. In this case, the potential difference between the first power voltage ELVDD and the second power voltage ELVSS can be set to be greater than or equal to the threshold voltage of the light-emitting element LD during the emission cycle of pixel PXL.

[0068] A light-emitting element (LD) can be used as the light source for a pixel PXL. The LD can emit light with a brightness corresponding to the drive current supplied through the pixel circuit PXC. For example, within each frame period, the pixel circuit PXC can supply a drive current corresponding to the grayscale value of the corresponding frame data. Accordingly, the LD can emit light with a brightness corresponding to the drive current.

[0069] The pixel circuit PXC can be connected (e.g., electrically connected) to the scan line SLi and data line DLj of the pixel PXL. As an example, when the pixel PXL is placed in the display area DA (see...), Figure 1 When the pixel circuit PXC of pixel PXL is in the i-th row and j-th column of the display area DA (where i and j are each integers greater than or equal to 1), the pixel circuit PXC of pixel PXL can be connected to the i-th scan line SL1 and the j-th data line DLj of the display area DA. According to some embodiments, the pixel circuit PXC may include a first transistor TR1 and a second transistor TR2, as well as a storage capacitor Cstg. However, the structure of the pixel circuit PXC according to some embodiments of this disclosure is not limited to... Figure 3 The embodiment shown.

[0070] The first transistor TR1 may include a gate electrode connected (e.g., electrically connected) to a first node N1. The first transistor TR1 may include a first electrode connected (e.g., electrically connected) to a second node N2. The first transistor TR1 may include a second electrode connected (e.g., electrically connected) to a first power line PL1. The first electrode may be either a source electrode or a drain electrode (e.g., a drain electrode). The second electrode may be the other of the source electrode and drain electrode (e.g., a source electrode). A current (e.g., a drive current) corresponding to the voltage applied to the first node N1 may flow in the first transistor TR1. The first transistor TR1 may be referred to as a drive transistor.

[0071] The second transistor TR2 can be configured to write the data voltage Vdata into the pixel circuit PXC. The second transistor TR2 may include a gate electrode connected (e.g., electrically connected) to the i-th scan line SLi. In response to a scan signal SCAN (e.g., a scan signal SCAN with an on / off level) input to the i-th scan line SLi, the second transistor TR2 can be configured to input the data voltage Vdata into the pixel circuit PXC. The second transistor TR2 can be configured to switch the electrical connection between the j-th data line DLj and the first node N1. The second transistor TR2 can be referred to as a switching transistor.

[0072] The storage capacitor Cstg may include one electrode connected (e.g., electrically connected) to a first node N1 and another electrode connected (e.g., electrically connected) to a second node N2. The storage capacitor Cstg may be configured to maintain a voltage difference between the first node N1 and the second node N2. For example, the storage capacitor Cstg may be configured to maintain a data voltage Vdata applied to the first node N1 during a certain period (e.g., one frame period).

[0073] Figure 3 A pixel circuit PXC is shown, comprising a second transistor TR2 configured to write a data voltage Vdata to a pixel PXL, a storage capacitor Cstg for storing the data voltage Vdata, and a first transistor TR1 configured to supply a drive current corresponding to the data voltage Vdata to a light-emitting element LD. However, embodiments of this disclosure are not limited thereto, and the structure of the pixel circuit PXC can be modified in various ways. As an example, the pixel circuit PXC may include transistor elements configured to compensate for changes in the threshold voltage of the first transistor TR1, transistor elements configured to initialize the voltage of a first node N1, and / or transistor elements configured to control the length of time for the light-emitting element LD (or multiple light-emitting elements LD) to emit light. According to some embodiments, the pixel circuit PXC may also include circuit elements such as a boost capacitor for boosting the voltage of the first node N1.

[0074] Figure 3 An embodiment of a pixel circuit PXC according to some embodiments of the present disclosure is shown, comprising a first transistor TR1 and a second transistor TR2, each of the first transistor TR1 and the second transistor TR2 including a P-type semiconductor layer (e.g., implemented as a P-channel metal-oxide-semiconductor (PMOS)). However, embodiments of the present disclosure are not limited thereto, and at least one of the first transistor TR1 and the second transistor TR2 may be configured as a transistor including an N-type semiconductor layer (e.g., an N-channel metal-oxide-semiconductor (NMOS)). For example, the P-type semiconductor layer may comprise a metal-oxide-semiconductor. For example, the N-type semiconductor layer may comprise a polysilicon semiconductor.

[0075] Figure 4 and Figure 5 This is a schematic cross-sectional view of a display device DD according to some embodiments. Figure 6 This is a schematic plan view of the second electrode ET2 according to some embodiments. Figure 4 It is along Figure 2 A schematic cross-sectional view of the display device DD taken by line A-A'. Figure 5 It is along Figure 2 A schematic cross-sectional view of the display device DD taken by line B-B'.

[0076] refer to Figure 4 and Figure 5 The display device DD may include a subpixel region SPXA in which subpixels SPX1 and SPX2 are located.

[0077] The subpixel region SPXA can be a region formed by subpixels SPX, and can be a region that provides light with a certain color.

[0078] The sub-pixel region SPXA may include a first sub-pixel region SPXA1 formed by a first sub-pixel SPX1 and a second sub-pixel region SPXA2 formed by a second sub-pixel SPX2.

[0079] According to some embodiments, a first color light, a second color light, or a mixture of the first and second color lights can be provided in the first sub-pixel region SPXA1. A first color light, a third color light, or a mixture of the first and third color lights can be provided in the second sub-pixel region SPXA2.

[0080] The display device DD may include a pixel circuit layer (PCL) and a display element layer (LEL). The PCL and LEL may be located on the base layer (BSL) (see [link to base layer]). Figure 1 On the ), and can be arranged to cover the entire sub-pixel region SPXA.

[0081] The pixel circuit layer PCL may include a second power line PL2 and a circuit unit C for driving the light-emitting element LD. For example, the pixel circuit layer PCL may include a circuit unit C for supplying an anode signal (e.g., a signal supplied from a first power voltage ELVDD) to the light-emitting element LD and a second power line PL2 for supplying a cathode signal (e.g., a signal supplied from a second power voltage ELVSS).

[0082] Circuit unit C can be with Figure 3 At least one circuit in the pixel circuit PXC shown corresponds to this. For example, circuit unit C may be part of the pixel circuit PXC. For example, circuit unit C may be electrically connected to the pixel circuit PXC. Circuit unit C may include 1-1 pixel circuit unit C1_1, 1-2 pixel circuit unit C1_2, 2-1 pixel circuit unit C2_1, and 2-2 pixel circuit unit C2_2.

[0083] Pixel 1-1 circuit unit C1_1 and pixel 1-2 circuit unit C1_2 may be located in the first sub-pixel region SPXA1. Pixel 2-1 circuit unit C2_1 and pixel 2-2 circuit unit C2_2 may be located in the second sub-pixel region SPXA2. However, embodiments according to this disclosure are not limited thereto. Pixel 1-1 circuit unit C1_1 and pixel 1-2 circuit unit C1_2 may be located inside and outside the first sub-pixel region SPXA1. Pixel 2-1 circuit unit C2_1 and pixel 2-2 circuit unit C2_2 may be arranged to extend throughout the inside and outside of the second sub-pixel region SPXA2.

[0084] Pixel circuit unit C1_1 and pixel circuit unit C1_2 can be pixel circuits PXC used to drive the first sub-pixel SPX1 (or the light-emitting element LD formed in the first sub-pixel SPX1). Pixel circuit unit C2_1 and pixel circuit unit C2_2 can be pixel circuits PXC used to drive the second sub-pixel SPX2 (or the light-emitting element LD formed in the second sub-pixel SPX2).

[0085] The display element layer (LEL) may include a light-emitting element (LD), a first electrode (ET1), and a second electrode (ET2).

[0086] The light-emitting element LD includes 1-1 light-emitting element LD1, 1-2 light-emitting element LD2 and 1-3 light-emitting element LD3, each located in the first sub-pixel region SPXA1, and may include 2-1 light-emitting element LD1', 2-2 light-emitting element LD2' and 2-3 light-emitting element LD3', each located in the second sub-pixel region SPXA2.

[0087] 1-1 Light-emitting element LD1 and 2-1 Light-emitting element LD1' can be located on the same layer. 1-2 Light-emitting element LD2 and 2-2 Light-emitting element LD2' can be located on the same layer. 1-3 Light-emitting element LD3 and 2-3 Light-emitting element LD3' can be located on the same layer.

[0088] Light-emitting elements 1-1 (LD1) and 2-1 (LD1') can be formed using the same process. For example, LD1 and LD1' may contain the same material. Similarly, light-emitting elements 1-2 (LD2) and 2-2 (LD2') can be formed using the same process. For example, LD2 and LD2' may contain the same material. Likewise, light-emitting elements 1-3 (LD3) and 2-3 (LD3') can be formed using the same process. For example, LD3 and LD3' may contain the same material.

[0089] 1-1 Light-emitting element LD1 can be located at the bottom of 1-1 light-emitting element LD1, 1-2 light-emitting element LD2 and 1-3 light-emitting element LD3. 2-1 Light-emitting element LD1' can be located at the bottom of 2-1 light-emitting element LD1', 2-2 light-emitting element LD2' and 2-3 light-emitting element LD3'.

[0090] 1-2 Light-emitting element LD2 can be located between 1-1 light-emitting element LD1 and 1-3 light-emitting element LD3. 1-2 Light-emitting element LD2 can be located on 1-1 light-emitting element LD1. 2-2 Light-emitting element LD2' can be located between 2-1 light-emitting element LD1' and 2-3 light-emitting element LD3'. 2-2 Light-emitting element LD2' can be located on 2-1 light-emitting element LD1'.

[0091] 1-3 Light-emitting element LD3 can be located at the top among 1-1 light-emitting element LD1, 1-2 light-emitting element LD2, and 1-3 light-emitting element LD3. 1-3 Light-emitting element LD3 can be located on top of 1-2 light-emitting element LD2. 2-3 Light-emitting element LD3' can be located at the top among 2-1 light-emitting element LD1', 2-2 light-emitting element LD2', and 2-3 light-emitting element LD3'. 2-3 Light-emitting element LD3' can be located on top of 2-2 light-emitting element LD2'.

[0092] Each of the light-emitting elements (LDs) may include a bonding electrode (BDE), a lower electrode (LE), a light-emitting structure (LS), and an upper electrode (UE). The light-emitting structure (LS) may include a first semiconductor layer (SCL1), an active layer (AL), and a second semiconductor layer (SCL2).

[0093] The bonded electrode (BDE) may include a eutectic metal. According to some embodiments, the bonded electrode (BDE) may include multiple layers. For example, the bonded electrode (BDE) may include multiple layers, in which a first electrode layer comprising titanium (Ti), a second electrode layer comprising gold (Au) and / or tin (Sn), and a third electrode layer comprising titanium (Ti) are sequentially stacked. However, embodiments according to this disclosure are not limited thereto.

[0094] The lower electrode LE can be located on the bonding electrode BDE. When the light-emitting element LD is electrically connected to the circuit unit C, the lower electrode LE can receive an anode signal (e.g., a signal supplied from the first power voltage ELVDD). However, embodiments according to this disclosure are not limited thereto. For example, when the second electrode ET2 is located below the light-emitting element LD such that the lower surface of the light-emitting element LD is electrically connected to the second electrode ET2, the lower electrode LE can receive a cathode signal (e.g., a signal supplied from the second power voltage ELVSS).

[0095] The lower electrode LE can be made transparent (or substantially transparent) or translucent to meet transmittance requirements. According to some embodiments, the lower electrode LE may comprise materials selected from indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). x The lower electrode LE may be at least one of the conductive materials selected from indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, embodiments according to this disclosure are not limited thereto. According to some embodiments, the lower electrode LE may comprise a metal or a metal oxide. For example, the lower electrode LE may comprise at least one selected from copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and their oxides and alloys, but embodiments according to this disclosure are not limited thereto.

[0096] The first semiconductor layer SCL1 may be located on the lower electrode LE. The first semiconductor layer SCL1 may include either a P-type semiconductor layer or an N-type semiconductor layer. In the following description, for ease of description, an embodiment in which the first semiconductor layer SCL1 includes a P-type semiconductor layer will be described as an example, but the embodiments disclosed herein are not limited thereto. The first semiconductor layer SCL1 may include a P-type semiconductor layer comprising a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN and doped with a first conductive dopant (or P-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba).

[0097] The active layer AL can be located between the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The active layer AL can include any one of the following structures: single-well structure, multi-well structure, single quantum well structure, multiple quantum well (MQW) structure, quantum dot structure, and quantum wire structure, but the embodiments disclosed herein are not limited thereto. The active layer AL can include AlGaN, InGaN, or GaN, and various other materials can constitute the active layer AL.

[0098] The active layer AL of light-emitting elements (LDs) located on different layers can be configured to emit various types of light in different wavelength bands. For example, light-emitting elements LD1 (1-1), LD2 (1-2), and LD3 (1-3) can each have an active layer AL configured to emit various types of light in different wavelength bands. Similarly, light-emitting elements LD1' (2-1), LD2' (2-2), and LD3' (2-3) can each have an active layer AL configured to emit various types of light in different wavelength bands.

[0099] For example, the active layer AL of 1-1 light-emitting element LD1 and 2-1 light-emitting element LD1' can be configured to emit light in a wavelength band corresponding to the first light (e.g., light in the red wavelength band), the active layer AL of 1-2 light-emitting element LD2 and 2-2 light-emitting element LD2' can be configured to emit light in a wavelength band corresponding to the second light (e.g., light in the green wavelength band), and the active layer AL of 1-3 light-emitting element LD3 and 2-3 light-emitting element LD3' can be configured to emit light in a wavelength band corresponding to the third light (e.g., light in the blue wavelength band). However, embodiments according to this disclosure are not limited thereto.

[0100] The second semiconductor layer SCL2 may be located on the active layer AL. The second semiconductor layer SCL2 may include either a P-type semiconductor layer or an N-type semiconductor layer. In the following description, for ease of description, an embodiment in which the second semiconductor layer SCL2 includes an N-type semiconductor layer will be used as an example, but the embodiments disclosed herein are not limited thereto. The second semiconductor layer SCL2 may be an N-type semiconductor layer comprising a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN and doped with a second conductive dopant (or N-type dopant) such as germanium (Ge), selenium (Se), tellurium (Te), or tin (Sn). As an example, the second semiconductor layer SCL2 may include a GaN semiconductor material doped with a second conductive dopant (or N-type dopant). However, the materials constituting the second semiconductor layer SCL2 are not limited thereto, and the second semiconductor layer SCL2 may be made of various other materials.

[0101] The upper electrode UE can be located on the second semiconductor layer SCL2. When the light-emitting element LD is electrically connected to the second electrode ET2, the upper electrode UE can receive a cathode signal. However, embodiments according to this disclosure are not limited thereto. For example, when the light-emitting element LD is electrically connected to the first electrode ET1, the upper electrode UE can receive an anode signal.

[0102] The upper electrode UE can be made transparent (or substantially transparent) or translucent to meet a certain transmittance. According to some embodiments, the upper electrode UE may include materials selected from indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). x The upper electrode UE may be selected from at least one of the conductive materials indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, embodiments according to this disclosure are not limited thereto. According to some embodiments, the upper electrode UE may include a metal or a metal oxide. For example, the upper electrode UE may include at least one selected from copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and their oxides and alloys, but embodiments according to this disclosure are not limited thereto.

[0103] The first electrode ET1 may include electrode 1-1 ET1_1, electrode 1-2 ET1_2, electrode 2-1 ET1_1', and electrode 2-2 ET1_2'. Electrodes 1-1 ET1_1 and 1-2 ET1_2 may be located in the first sub-pixel region SPXA1. Electrodes 2-1 ET1_1' and 2-2 ET1_2' may be located in the second sub-pixel region SPXA2.

[0104] The 1-1 electrode ET1_1 can be connected to the 1-1 pixel circuit unit C1_1. For example, the 1-1 electrode ET1_1 can be electrically connected to the 1-1 pixel circuit unit C1_1. The 1-1 electrode ET1_1 can electrically connect the 1-1 pixel circuit unit C1_1 to the 1-1 light-emitting element LD1.

[0105] Electrode ET1_2 (1-2) can be connected to pixel circuit unit C1_2 (1-2). For example, electrode ET1_2 (1-2) can be electrically connected to pixel circuit unit C1_2 (1-2). Electrode ET1_2 (1-2) can electrically connect pixel circuit unit C1_2 (1-2) to light-emitting element LD2 (1-2).

[0106] Electrode ET1_1' can be connected to pixel circuit unit C2_1. For example, electrode ET1_1' can be electrically connected to pixel circuit unit C2_1. Electrode ET1_1' can also electrically connect pixel circuit unit C2_1 to light-emitting element LD1'.

[0107] The 2-2 electrode ET1_2' can be connected to the 2-2 pixel circuit unit C2_2. For example, the 2-2 electrode ET1_2' can be electrically connected to the 2-2 pixel circuit unit C2_2. The 2-2 electrode ET1_2' can also electrically connect the 2-2 pixel circuit unit C2_2 to the 2-3 light-emitting element LD3'.

[0108] At least a portion of the first electrode ET1 may not overlap with at least some of the light-emitting elements LD in a planar view (e.g., on the third-direction DR3). For example, electrode 1-2 ET1_2 may not overlap with light-emitting element 1-1 LD1 in a planar view. Electrode 2-2 ET1_2' may not overlap with light-emitting elements 2-1 LD1' and 2-2 LD2' in a planar view.

[0109] The second electrode ET2 can be connected to the second power line PL2. For example, the second electrode ET2 can be electrically connected to the second power line PL2. Accordingly, the second electrode ET2 can serve as a common electrode for the first sub-pixel SPX1 and the second sub-pixel SPX2.

[0110] The second electrode ET2 may not overlap with the light-emitting element LD in the planar view. The second electrode ET2 may be located outside the sub-pixel region SPXA. However, embodiments according to this disclosure are not limited thereto. For example, the second electrode ET2 may overlap with at least a portion of the light-emitting element LD in the planar view.

[0111] The second electrode ET2 can have a mesh structure in a planar view. (See below for reference.) Figure 6 This will be described.

[0112] The positions of the first electrode ET1 and the second electrode ET2 can be changed. For example, according to some embodiments, the second electrode ET2, located outside the sub-pixel region SPXA, can be changed to the first electrode ET1, and in this case, the second electric field line PL2 can be changed to the first electric field line PL1. In the following, the positions of the first electrode ET1 and the second electrode ET2 will be considered based on their location... Figure 4 and Figure 5 The embodiments shown in the diagram are described.

[0113] According to some embodiments, the display element layer LEL may include a base insulating layer BIL, an insulating layer IL, an interlayer insulating layer LIL, a conductive layer SL, and a connection electrode CNE.

[0114] The base insulating layer (BIL) may be located on the pixel circuit layer (PCL). At least a portion of the base insulating layer (BIL) may be located between the pixel circuit layer (PCL) and the 1-1 light-emitting element (LD1), and between the pixel circuit layer (PCL) and the 2-1 light-emitting element (LD1').

[0115] An opening through the base insulating layer (BIL) may be provided in at least a portion of the base insulating layer (BIL). The first electrode ET1 described above may pass through the opening in the base insulating layer (BIL). For example, electrodes 1-1 ET1_1, 1-2 ET1_2, 2-1 ET1_1', and 2-2 ET1_2' may pass through the base insulating layer (BIL).

[0116] The base insulating layer (BIL) may include silicon oxide (SiO2) x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x Aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), hafnium oxide (HfO) x ) or titanium dioxide (TiO) x Inorganic materials.

[0117] The insulating layer IL can be located on the base insulating layer BIL. The insulating layer IL can be located on the same layer as each of the light-emitting elements LD. The insulating layer IL can surround the light-emitting element LD.

[0118] The insulating layer IL may include silicon oxide (SiO2) x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x Aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), hafnium oxide (HfO) x ) or titanium dioxide (TiO) x Inorganic materials.

[0119] The insulating layer IL may include a first insulating layer IL1, a second insulating layer IL2, and a third insulating layer IL3.

[0120] The first insulating layer IL1 may be located on the base insulating layer BIL. The first insulating layer IL1 may be located on the same layer as the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'. The first insulating layer IL1 may surround the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'.

[0121] The second insulating layer IL2 may be located on the first insulating layer IL1. The second insulating layer IL2 may be located on the same layer as the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'. The second insulating layer IL2 may surround the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0122] The third insulating layer IL3 may be located on the second insulating layer IL2. The third insulating layer IL3 may be located on the same layer as the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'. The third insulating layer IL3 may surround the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'.

[0123] An interlayer insulating layer (LIL) may be located on an insulating layer (IL). The LIL may be positioned between a light-emitting element (LD) positioned on the LIL and a light-emitting element (LD) positioned below the LIL, such that the light-emitting elements (LDs) located in the same sub-pixel region (SPXA) are electrically insulated from each other. The LIL may expose at least a portion of the lower surface of the light-emitting element (LD).

[0124] Interlayer insulating layers (LILs) may include silicon oxide (SiO2) x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x C y ), aluminum oxide (AlO) x Aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), hafnium oxide (HfO) x ) or titanium dioxide (TiO) x Inorganic materials.

[0125] The interlayer insulation layer (LIL) may include a first interlayer insulation layer (LIL1) and a second interlayer insulation layer (LIL2).

[0126] The first interlayer insulating layer LIL1 may be located on the first insulating layer IL1. At least a portion of the first interlayer insulating layer LIL1 may be located between the 1-1 light-emitting element LD1 and the 1-2 light-emitting element LD2, and between the 2-1 light-emitting element LD1' and the 2-2 light-emitting element LD2'. The first interlayer insulating layer LIL1 may be located between the first insulating layer IL1 and the second insulating layer IL2.

[0127] The first interlayer insulating layer LIL1 may expose the lower surface of the 1-2 light-emitting elements LD2. For example, at least a portion of the 1-2 light-emitting elements LD2 (or the exposed lower surface of the 1-2 light-emitting elements LD2) may not overlap with the first interlayer insulating layer LIL1 in a plan view. In the following, in this disclosure, the downward direction is defined as the direction opposite to the third direction DR3.

[0128] The first interlayer insulating layer LIL1 can expose the lower surface of the 1-2 light-emitting elements LD2, and the exposed lower surface of the 1-2 light-emitting elements LD2 can serve as a contact portion through which the 1-2 light-emitting elements LD2 and the 1-2 electrodes ET1_2 can be electrically connected. For example, the 1-2 electrodes ET1_2 can be electrically connected to the 1-2 pixel circuit unit C1_2, and the 1-2 electrodes ET1_2 can be electrically connected to the 1-2 light-emitting elements LD2 through the first insulating layer IL1 and the first interlayer insulating layer LIL1.

[0129] The second interlayer insulating layer LIL2 may be located on the second insulating layer IL2. At least a portion of the second interlayer insulating layer LIL2 may be located between the 1-2 light-emitting elements LD2 and 1-3 light-emitting elements LD3, and between the 2-2 light-emitting elements LD2' and 2-3 light-emitting elements LD3'. The second interlayer insulating layer LIL2 may be located between the second insulating layer IL2 and the third insulating layer IL3.

[0130] The second interlayer insulating layer LIL2 can expose the lower surface of the 2-3 light-emitting element LD3'. For example, at least a portion of the 2-3 light-emitting element LD3' (or the exposed lower surface of the 2-3 light-emitting element LD3') may not overlap with the second interlayer insulating layer LIL2 in a plan view. The second interlayer insulating layer LIL2 can expose the lower surface of the 2-3 light-emitting element LD3', and the exposed lower surface of the 2-3 light-emitting element LD3' can serve as a contact portion through which the 2-3 light-emitting element LD3' and the 2-2 electrode ET1_2' can be electrically connected. For example, the 2-2 electrode ET1_2' can be electrically connected to the 2-2 pixel circuit unit C2_2, and the 2-2 electrode ET1_2' can be electrically connected to the 2-3 light-emitting element LD3' through the first insulating layer IL1 and the second insulating layer IL2, as well as the first interlayer insulating layer LIL1 and the second interlayer insulating layer LIL2.

[0131] The second interlayer insulating layer LIL2 may not expose the lower surface of the 1-3 light-emitting elements LD3. For example, the lower surface of the 1-3 light-emitting elements LD3 may be in complete contact with the second interlayer insulating layer LIL2. Accordingly, among the 1-1 light-emitting elements LD1, 1-2 light-emitting elements LD2 and 1-3 light-emitting elements LD3 located in the first sub-pixel region SPXA1, 1-1 light-emitting elements LD1 and 1-2 light-emitting elements LD2 may be electrically connected to the pixel circuit PXC, and 1-3 light-emitting element LD3 may not be electrically connected to the pixel circuit PXC. For example, 1-1 light-emitting element LD1 may be electrically connected to the pixel circuit PXC through the 1-1 electrode ET1_1, 1-2 light-emitting element LD2 may be electrically connected to the pixel circuit PXC through the 1-2 electrode ET1_2, and 1-3 light-emitting element LD3 may not be electrically connected to the pixel circuit PXC through the first electrode ET1.

[0132] The first interlayer insulating layer LIL1 may not expose the lower surface of the 2-2 light-emitting element LD2'. For example, the lower surface of the 2-2 light-emitting element LD2' may be in complete contact with the first interlayer insulating layer LIL1. Accordingly, among the 2-1 light-emitting elements LD1', 2-2 light-emitting elements LD2', and 2-3 light-emitting elements LD3' located in the second sub-pixel region SPXA2, 2-1 light-emitting elements LD1' and 2-3 light-emitting elements LD3' may be electrically connected to the pixel circuit PXC, while 2-2 light-emitting element LD2' may not be electrically connected to the pixel circuit PXC. For example, 2-1 light-emitting element LD1' may be electrically connected to the pixel circuit PXC via the 2-1 electrode ET1_1', 2-3 light-emitting element LD3' may be electrically connected to the pixel circuit PXC via the 2-2 electrode ET1_2', and 2-2 light-emitting element LD2' may not be electrically connected to the pixel circuit PXC via the first electrode ET1.

[0133] In other words, 1-1 light-emitting element LD1 and 1-2 light-emitting element LD2 located in the first sub-pixel region SPXA1 can be electrically connected to the pixel circuit PXC, while 1-3 light-emitting element LD3 can be de-connected to the pixel circuit PXC. 2-1 light-emitting element LD1' and 2-3 light-emitting element LD3' located in the second sub-pixel region SPXA2 can be electrically connected to the pixel circuit PXC, while 2-2 light-emitting element LD2' can be de-connected to the pixel circuit PXC.

[0134] Accordingly, light efficiency can be improved in high-resolution display devices (DDs). When all of the 1-1 light-emitting elements LD1, 1-2 light-emitting elements LD2, and 1-3 light-emitting elements LD3 are electrically connected to the pixel circuit PXC in a single sub-pixel region (e.g., the first sub-pixel region SPXA1), there is a risk of reduced light efficiency. For example, in a structure where 1-1 light-emitting elements LD1, 1-2 light-emitting elements LD2, and 1-3 light-emitting elements LD3 are vertically stacked, when all of them are electrically connected to the pixel circuit PXC, additional 1-3 electrodes are required to electrically connect the 1-3 light-emitting elements LD3 to the pixel circuit PXC. In this case, when forming the 1-3 electrodes, at least a portion of the 1-1 light-emitting elements LD1 and 1-2 light-emitting elements LD2 may be etched, thereby reducing light efficiency.

[0135] In the display device DD according to this disclosure, only two of the light-emitting elements LD are electrically connected to the pixel circuit PXC in a sub-pixel region SPXA, thereby reducing the number of electrodes. Accordingly, by reducing the need for further etching of some of the light-emitting elements LD, light efficiency can be improved.

[0136] The connecting electrode CNE can be located on each of the light-emitting elements LD. The connecting electrode CNE can be in contact with the upper surface of each of the light-emitting elements LD.

[0137] The connecting electrode CNE can be made transparent (or substantially transparent) or translucent to meet a certain transmittance. According to some embodiments, the connecting electrode CNE may include materials selected from indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). x It is at least one of the conductive materials of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).

[0138] The connecting electrode CNE can be electrically connected to the second electrode ET2 and the conductive layer SL, and can supply a cathode signal (e.g., a second power voltage ELVSS) to the light-emitting element LD. The connecting electrode CNE can include a first connecting electrode CNE1, a second connecting electrode CNE2, and a third connecting electrode CNE3.

[0139] The first connecting electrode CNE1 can be located on the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'. The first connecting electrode CNE1 can contact (or cover) the upper surface of the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'. The first connecting electrode CNE1 can supply a cathode signal to the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'.

[0140] The second connecting electrode CNE2 can be located on the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'. The second connecting electrode CNE2 can contact (or cover) the upper surface of the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'. The second connecting electrode CNE2 can supply a cathode signal to the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0141] The third connecting electrode CNE3 can be located on the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'. The third connecting electrode CNE3 can contact (or cover) the upper surface of the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'. The third connecting electrode CNE3 can supply a cathode signal to the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'.

[0142] The conductive layer SL can be located below the connecting electrode CNE. The conductive layer SL may include a first conductive layer SL1, a second conductive layer SL2, and a third conductive layer SL3.

[0143] refer to Figure 6 The conductive layer SL can be connected (or electrically connected) to the second electrode ET2. Each of the conductive layers SL (the first conductive layer SL1, the second conductive layer SL2, and the third conductive layer SL3) can be integrally connected to the second electrode ET2.

[0144] The conductive layer SL (each of the first conductive layer SL1, the second conductive layer SL2, and the third conductive layer SL3) and the second electrode ET2 can be located in a region outside the area where the light-emitting element LD is located in the plan view. For example, the first conductive layer SL1 and the second electrode ET2 can be located in a region outside the areas where light-emitting elements LD1 (1-1) and LD1' (2-1) are located. For example, the area where the first conductive layer SL1 and the second electrode ET2 are located can be non-overlapping with the areas where light-emitting elements LD1 (1-1) and LD1' (2-1) are located in the plan view.

[0145] The conductive layers SL (each of the first conductive layer SL1, the second conductive layer SL2, and the third conductive layer SL3) and the second electrode ET2 can be arranged to surround the light-emitting element LD in a planar view. For example, the conductive layers SL (each of the first conductive layer SL1, the second conductive layer SL2, and the third conductive layer SL3) and the second electrode ET2 can be integrally connected to each other in a planar view to form a mesh structure.

[0146] Each of the first conductive layer SL1, the second conductive layer SL2, and the third conductive layer SL3 can be formed using the same process as at least a portion of the second electrode ET2. Each of the first conductive layer SL1, the second conductive layer SL2, and the third conductive layer SL3 may comprise the same material as at least a portion of the second electrode ET2.

[0147] The conductive layer SL may include a conductive metal. For example, the conductive layer SL may include copper (Cu). However, embodiments according to this disclosure are not limited thereto. Accordingly, the conductive layer SL may receive a cathode signal from the second electrode ET2 and may supply the received cathode signal to each of the light-emitting elements LD.

[0148] The first conductive layer SL1 may be located below the first connecting electrode CNE1. The first conductive layer SL1 may be in contact with the first connecting electrode CNE1. The first conductive layer SL1 may be connected (or electrically connected) to the second electrode ET2, and may supply cathode signals to the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'.

[0149] The second conductive layer SL2 can be located below the second connecting electrode CNE2. The second conductive layer SL2 can be in contact with the second connecting electrode CNE2. The second conductive layer SL2 can be connected (or electrically connected) to the second electrode ET2, and can supply cathode signals to the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0150] The third conductive layer SL3 can be located below the third connecting electrode CNE3. The third conductive layer SL3 can be in contact with the third connecting electrode CNE3. The third conductive layer SL3 can be connected (or electrically connected) to the second electrode ET2, and can supply cathode signals to the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'.

[0151] In the following text, reference will be made to Figures 7 to 55 Describe the method for manufacturing the display device DD. Content that may overlap with the above will be briefly described or omitted.

[0152] Figures 7 to 55 This is a schematic diagram illustrating each process operation of a method for manufacturing a display device DD according to some embodiments of the present disclosure. Figures 7 to 55 Some of the accompanying drawings are schematic plan views of a region of the display device DD, some are schematic sectional views taken along line A-A' of the display device DD, and the remaining drawings are schematic sectional views taken along line B-B' of the display device DD.

[0153] refer to Figures 7 to 12The diagram illustrates an operation S100 for forming 1-1 light-emitting element LD1 and 2-1 light-emitting element LD1'. A method for manufacturing a display device DD may include the operation S100 for forming 1-1 light-emitting element LD1 and 2-1 light-emitting element LD1'.

[0154] Before forming 1-1 light-emitting element LD1 and 2-1 light-emitting element LD1', a pixel circuit layer PCL and a base insulating layer BIL may be formed. A method for manufacturing a display device DD may include forming the pixel circuit layer PCL and the base insulating layer BIL.

[0155] The pixel circuit layer PCL can include forming circuit units C and a second electric field line PL2. The forming circuit unit C can include forming 1-1 pixel circuit unit C1_1, 1-2 pixel circuit unit C1_2, 2-1 pixel circuit unit C2_1, and 2-2 pixel circuit unit C2_2. Circuit unit C can correspond to pixel circuits PXC, and in addition to... Figure 8 and Figure 9 In addition to the components shown, forming the pixel circuit layer PCL may also include forming Figure 3 The components of the equivalent circuit diagram shown.

[0156] A base insulating layer (BIL) can be formed on the pixel circuit layer (PCL). The base insulating layer (BIL) can be etched to expose at least a portion of the pixel circuit layer (PCL). At least a portion of the base insulating layer (BIL) can be etched to form an opening through the base insulating layer (BIL).

[0157] A base electrode layer B_ET can be formed in an opening in the base insulating layer BIL. For example, at least a portion of the base electrode layer B_ET can fill the opening in the base insulating layer BIL. A method of manufacturing a display device DD may include forming the base electrode layer B_ET.

[0158] Forming the base electrode layer B_ET may include forming a 1-1 base electrode 10, a 1-2 base electrode 20, a 2-1 base electrode 30, a 2-2 base electrode 40, and a second base electrode 50.

[0159] The base electrode layer B_ET may include a conductive material. For example, the base electrode layer B_ET may include copper (Cu). However, embodiments according to this disclosure are not limited thereto.

[0160] The 1-1 base electrode 10 and the 1-2 base electrode 20 can be formed in the first sub-pixel region SPXA1. The 1-1 base electrode 10 can correspond to the 1-1 electrode ET1_1. For example, the 1-1 base electrode 10 can be the 1-1 electrode ET1_1. The 1-2 base electrode 20 can correspond to a portion of the 1-2 electrode ET1_2. For example, the 1-2 base electrode 20 can constitute a portion of the 1-2 electrode ET1_2.

[0161] The 2-1 base electrode 30 and the 2-2 base electrode 40 can be formed in the second sub-pixel region SPXA2. The 2-1 base electrode 30 can correspond to the 2-1 electrode ET1_1'. For example, the 2-1 base electrode 30 can be the 2-1 electrode ET1_1'. The 2-2 base electrode 40 can correspond to a portion of the 2-2 electrode ET1_2'. For example, the 2-2 base electrode 40 can constitute a portion of the 2-2 electrode ET1_2'.

[0162] The second base electrode 50 can be formed outside the first sub-pixel region SPXA1 and the second sub-pixel region SPXA2. The second base electrode 50 can correspond to a portion of the second electrode ET2. For example, the second base electrode 50 can constitute a portion of the second electrode ET2.

[0163] The operation S100 of forming 1-1 light-emitting element LD1 and 2-1 light-emitting element LD1' may include forming a basic light-emitting element layer BLDL (or forming a first basic light-emitting element layer BLDL1). The basic light-emitting element layer BLDL may be formed to extend over the first sub-pixel region SPXA1 and the second sub-pixel region SPXA2 (e.g., over the entire surface of the display region DA).

[0164] Forming the first base light-emitting element layer BLDL1 (or forming the base light-emitting element layer BLDL) may include sequentially stacking (depositing) a base bonding electrode B_BDE, a base lower electrode B_LE, a base first semiconductor layer B_SCL1, a base active layer B_AL, a base second semiconductor layer B_SCL2, and a base upper electrode B_UE. In this disclosure, the base bonding electrode B_BDE, base lower electrode B_LE, base first semiconductor layer B_SCL1, base active layer B_AL, base second semiconductor layer B_SCL2, and base upper electrode B_UE may refer to the bonding electrode BDE, lower electrode LE, first semiconductor layer SCL1, active layer AL, second semiconductor layer SCL2, and upper electrode UE before etching.

[0165] refer to Figures 10 to 12 The operation S100, which forms 1-1 light-emitting element LD1 and 2-1 light-emitting element LD1', may include etching the first basic light-emitting element layer BLDL1.

[0166] In the etching of the first basic light-emitting element layer BLDL1, the first basic light-emitting element layer BLDL1 can be etched and formed in the first sub-pixel region SPXA1 and the second sub-pixel region SPXA2. The first basic light-emitting element layer BLDL1 can be etched to expose the 1-2 basic electrode 20 of the first sub-pixel SPX1, the 2-2 basic electrode 40 of the second sub-pixel SPX2, and the second basic electrode 50.

[0167] The first base light-emitting element layer BLDL1 can be etched to form light-emitting elements 1-1 LD1 and 2-1 LD1'. Light-emitting element 1-1 LD1 may not overlap with base electrode 20 1-2 in a planar view. Light-emitting element 2-1 LD1' may not overlap with base electrode 40 2-2 in a planar view.

[0168] refer to Figures 13 to 15 The diagram illustrates operation S110 for forming a first intermediate insulating layer M_IL1. A method for manufacturing a display device DD may include operation S110 for forming the first intermediate insulating layer M_IL1.

[0169] The operation S110 of forming the first intermediate insulating layer M_IL1 may include depositing a first base insulating layer to cover the base insulating layer BIL, and then etching the first base insulating layer to form the first intermediate insulating layer M_IL1. The first intermediate insulating layer M_IL1 may be an insulating layer formed by performing an etching process on the first base insulating layer, and may be an insulating layer prior to the formation of the first insulating layer IL1.

[0170] The first base insulating layer can be etched to form a first intermediate insulating layer M_IL1, and the first intermediate insulating layer M_IL1 (or the first insulating layer IL1) can have a first opening MP1. The first opening MP1 of the first intermediate insulating layer M_IL1 (or the first insulating layer IL1) can have a mesh pattern shape in a planar view.

[0171] The first intermediate insulating layer M_IL1 (or the first insulating layer IL1) may have a first opening MP1 that exposes at least a portion of the base insulating layer BIL. The first intermediate insulating layer M_IL1 (or the first insulating layer IL1) may expose at least a portion of the base insulating layer BIL and the second base electrode 50.

[0172] refer to Figures 16 to 18 The diagram illustrates operation S120 for forming the first conductive layer SL1. A method for manufacturing a display device DD may include operation S120 for forming the first conductive layer SL1.

[0173] The operation S120 of forming the first conductive layer SL1 may include forming the first conductive layer SL1 in the first opening MP1. The first conductive layer SL1 may fill the first opening MP1.

[0174] The first conductive layer SL1 can have a mesh pattern shape in the planar view. The first conductive layer SL1 can surround the light-emitting element LD1 (1-1) and the light-emitting element LD1' (2-1).

[0175] The portion of the first conductive layer SL1 that overlaps with the second base electrode 50 in the plan view can correspond to a portion of the second electrode ET2. The first conductive layer SL1 can supply the cathode signal supplied to the second electrode ET2 to the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'.

[0176] refer to Figures 19 to 21 The diagram illustrates operation S130 for forming the first connection electrode CNE1. A method for manufacturing a display device DD may include operation S130 for forming the first connection electrode CNE1.

[0177] The first connecting electrode CNE1 can be formed on the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'. The first connecting electrode CNE1 can be formed to contact the upper surface of the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'. The first connecting electrode CNE1 can cover the upper surface of the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'.

[0178] The first connecting electrode CNE1 can be formed to contact a portion of the first conductive layer SL1. For example, the first connecting electrode CNE1 can be formed to contact a portion of the first conductive layer SL1 that does not overlap with the second base electrode 50 in a plan view. The first connecting electrode CNE1 may not overlap with the second base electrode 50 in a plan view.

[0179] The first connecting electrode CNE1 can be connected to the 1-1 light-emitting element LD1, the 2-1 light-emitting element LD1', and a portion of the first conductive layer SL1. The first connecting electrode CNE1 can electrically connect the second electrode ET2 to the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'.

[0180] refer to Figures 22 to 24 The diagram illustrates operation S140 for forming a first contact opening H1 and a second contact opening H2. A method for manufacturing a display device DD may include operation S140 for forming the first contact opening H1 and the second contact opening H2.

[0181] Although Figure 22The diagram shows that a first contact opening H1 is formed at the upper right portion of the first sub-pixel region SPXA1, and a second contact opening H2 is formed at the lower left portion of the second sub-pixel region SPXA2, but the positions of the first contact opening H1 and the second contact opening H2 are not limited to these.

[0182] The operation S140 of forming the first contact opening H1 and the second contact opening H2 may include etching the first intermediate insulating layer M_IL1. The first intermediate insulating layer M_IL1 may be etched to form the first contact opening H1 and the second contact opening H2, and the first intermediate insulating layer M_IL1 may be etched to form the first insulating layer IL1.

[0183] A first contact opening H1 can be formed in a first sub-pixel region SPXA1. The first contact opening H1 can expose 1-2 base electrodes 20. A second contact opening H2 can be formed in a second sub-pixel region SPXA2. The second contact opening H2 can expose 2-2 base electrodes 40.

[0184] The first contact opening H1 and the second contact opening H2 may subsequently be filled with a conductive material to serve as contact portions for electrically connecting some of the light-emitting elements LD located on light-emitting elements LD1 (1-1) and LD1' (2-1) to the pixel circuit PXC. This will be described below with reference to the accompanying drawings.

[0185] refer to Figures 25 to 27 The diagram illustrates operation S150 for forming a first basic interlayer insulating layer B_LIL1. A method for manufacturing a display device DD may include operation S150 for forming the first basic interlayer insulating layer B_LIL1.

[0186] The operation S150 of forming the first basic interlayer insulating layer B_LIL1 may include forming the first basic interlayer insulating layer B_LIL1 to completely cover the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'. The first basic interlayer insulating layer B_LIL1 may completely cover the upper surfaces of the 1-1 light-emitting element LD1 and the 2-1 light-emitting element LD1'.

[0187] The first basic interlayer insulating layer B_LIL1 can completely cover the first connecting electrode CNE1 and the first conductive layer SL1. The first basic interlayer insulating layer B_LIL1 can cover the exposed 1-2 basic electrode 20, the exposed 2-2 basic electrode 40 and the exposed first conductive layer SL1 (e.g., a portion of the second electrode ET2).

[0188] The first basic interlayer insulating layer B_LIL1 can then be etched to form the first interlayer insulating layer LIL1.

[0189] refer to Figures 28 to 30 The diagram illustrates operation S160 of etching the first base interlayer insulating layer B_LIL1. A method for manufacturing a display device DD may include operation S160 of etching the first base interlayer insulating layer B_LIL1.

[0190] At least a portion of the first base interlayer insulating layer B_LIL1 can be etched, and the first base interlayer insulating layer B_LIL1 can form the first interlayer insulating layer LIL1. The first interlayer insulating layer LIL1 can cover the side surface of the first insulating layer IL1 that defines the first contact opening H1 and the second contact opening H2. The first base interlayer insulating layer B_LIL1 can be etched to expose the 1-2 base electrodes 20, the 2-2 base electrodes 40, and the first conductive layer SL1 (e.g., a portion of the second electrode ET2).

[0191] refer to Figures 31 to 33 The diagram illustrates operation S170 for forming the first cover electrode CVE1. A method for manufacturing a display device DD may include operation S170 for forming the first cover electrode CVE1.

[0192] The first cover electrode CVE1 can be formed in the region where the first base interlayer insulating layer B_LIL1 has been etched. For example, the first cover electrode CVE1 can be formed in a region that overlaps with the region where the first base interlayer insulating layer B_LIL1 has been etched in a plan view.

[0193] The first cover electrode CVE1 can be formed to cover the 1-2 base electrodes 20 and the first conductive layer SL1 (e.g., a portion of the second electrode ET2) overlapping the second base electrode 50. The first cover electrode CVE1 can be connected (or electrically connected) to the 1-2 base electrodes 20. The first cover electrode CVE1 can be connected (or electrically connected) to the first conductive layer SL1 (e.g., a portion of the second electrode ET2) overlapping the second base electrode 50.

[0194] The first cover electrode CVE1 can be connected to the 1-2 base electrode 20 to form the 1-2 electrode ET1_2. The 1-2 electrode ET1_2 can electrically connect the 1-2 pixel circuit unit C1_2 to the 1-2 light-emitting element LD2.

[0195] refer to Figures 34 to 36 The diagram illustrates an operation S200 for forming 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'. A method for manufacturing a display device DD may include the operation S200 for forming 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0196] The operation S200 of forming 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2' may include forming the above-mentioned basic light-emitting element layer BLDL and etching the basic light-emitting element layer BLDL.

[0197] For example, a second base light-emitting element layer with the same configuration as the base light-emitting element layer BLDL can be formed on the first interlayer insulating layer LIL1, and the second base light-emitting element layer can be etched to form 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0198] The 1-2 light-emitting element LD2 can be etched such that at least a portion of it contacts the 1-2 electrode ET1_2. The 2-2 light-emitting element LD2' can be formed such that its lower surface is in complete contact with the first interlayer insulating layer LIL1. The 2-2 light-emitting element LD2' can be etched so that it does not contact the portion of the first cover electrode CVE1 located in the second sub-pixel region SPXA2. For example, the second base light-emitting element layer can be etched such that it overlaps with the 1-2 electrode ET1_2 located in the first sub-pixel region SPXA1 in the planar view, and may not overlap with the portion of the first cover electrode CVE1 located in the second sub-pixel region SPXA2.

[0199] refer to Figure 37 and Figure 38 The diagram illustrates operation S210 for forming the second intermediate insulating layer M_IL2. A method for manufacturing a display device DD may include operation S210 for forming the second intermediate insulating layer M_IL2.

[0200] The operation S210 of forming the second intermediate insulating layer M_IL2 may include depositing a second base insulating layer to cover the first interlayer insulating layer LIL1, and then etching the second base insulating layer to form the second intermediate insulating layer M_IL2. The second intermediate insulating layer M_IL2 may be an insulating layer formed by performing an etching process on the second base insulating layer, and may be an insulating layer prior to the formation of the second insulating layer IL2.

[0201] The second base insulating layer can be etched to form a second intermediate insulating layer M_IL2, and the second intermediate insulating layer M_IL2 (or the second insulating layer IL2) can have a second opening MP2. The second opening MP2 of the second intermediate insulating layer M_IL2 (or the second insulating layer IL2) can have a shape corresponding to the first opening MP1. For example, the second opening MP2 of the second intermediate insulating layer M_IL2 (or the second insulating layer IL2) can have a mesh pattern shape in a planar view.

[0202] The second intermediate insulating layer M_IL2 (or the second insulating layer IL2) may have a second opening MP2 that exposes at least a portion of the first interlayer insulating layer LIL1 and the portion of the first cover electrode CVE1 that overlaps with the second base electrode 50 (e.g., a portion of the second electrode ET2). The second intermediate insulating layer M_IL2 (or the second insulating layer IL2) may expose the portion of the first interlayer insulating layer LIL1 that overlaps with the first conductive layer SL1 in a plan view and the portion of the first cover electrode CVE1 that overlaps with the second base electrode 50 (e.g., a portion of the second electrode ET2).

[0203] refer to Figures 39 to 41 The diagram illustrates operations S220 for forming the second conductive layer SL2 and S230 for forming the second connection electrode CNE2. A method for manufacturing a display device DD may include operations S220 for forming the second conductive layer SL2 and S230 for forming the second connection electrode CNE2.

[0204] The operation S220 of forming the second conductive layer SL2 may include forming the second conductive layer SL2 in the second opening MP2. The second conductive layer SL2 may fill the second opening MP2.

[0205] The second conductive layer SL2 can have a mesh pattern shape in the planar view. The second conductive layer SL2 can surround the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0206] In the plan view, the second conductive layer SL2, which overlaps with the second base electrode 50, can correspond to a portion of the second electrode ET2. The second conductive layer SL2 can supply the cathode signal supplied to the second electrode ET2 to the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0207] The second connecting electrode CNE2 can be formed on the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'. The second connecting electrode CNE2 can be formed to contact the upper surfaces of the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'. The second connecting electrode CNE2 can cover the upper surfaces of the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0208] The second connecting electrode CNE2 can be formed to contact a portion of the second conductive layer SL2. For example, the second connecting electrode CNE2 can be formed to contact a portion of the second conductive layer SL2 that does not overlap with the second base electrode 50 in a plan view. The second connecting electrode CNE2 may not overlap with the second base electrode 50 in a plan view.

[0209] The second connecting electrode CNE2 can be connected to the 1-2 light-emitting elements LD2, the 2-2 light-emitting element LD2', and a portion of the second conductive layer SL2. The second connecting electrode CNE2 can electrically connect the second electrode ET2 to the 1-2 light-emitting elements LD2 and the 2-2 light-emitting element LD2'.

[0210] refer to Figure 42 and Figure 43 The diagram illustrates operation S240 for forming the third contact opening H3. A method for manufacturing the display device DD may include operation S240 for forming the third contact opening H3.

[0211] The operation S240 of forming the third contact opening H3 may include etching the second intermediate insulating layer M_IL2. The second intermediate insulating layer M_IL2 may be etched to form the third contact opening H3, and the second intermediate insulating layer M_IL2 may be etched to form the second insulating layer IL2.

[0212] The third contact opening H3 can be formed in the second sub-pixel region SPXA2. The third contact opening H3 can overlap with the second contact opening H2 in the planar view. The third contact opening H3 can expose the portion of the first cover electrode CVE1 formed in the second contact opening H2.

[0213] The third contact opening H3 may subsequently be filled with a conductive material to serve as a contact portion for electrically connecting the 2-3 light-emitting element LD3' located on the 2-2 light-emitting element LD2' to the pixel circuit PXC. This will be described below with reference to the accompanying drawings.

[0214] refer to Figures 44 to 46 The diagram illustrates the formation of a second interlayer insulating layer, LIL2. A method for manufacturing a display device DD may include forming the second interlayer insulating layer, LIL2.

[0215] Forming the second interlayer insulating layer LIL2 may include the operation of forming the second base interlayer insulating layer S250 and the operation of etching the second base interlayer insulating layer S260.

[0216] The operation S250 of forming the second basic interlayer insulating layer may include forming the second basic interlayer insulating layer to completely cover the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'. The second basic interlayer insulating layer may completely cover the upper surfaces of the 1-2 light-emitting elements LD2 and 2-2 light-emitting elements LD2'.

[0217] The second base interlayer insulating layer can then be etched to form the second interlayer insulating layer LIL2.

[0218] At least a portion of the second base interlayer insulating layer may be etched, and the second base interlayer insulating layer may form a second interlayer insulating layer LIL2. The second base interlayer insulating layer may be etched to expose a first cover electrode CVE1 that overlaps with the 2-2 base electrode 40 in the plan view and a second conductive layer SL2 (e.g., a portion of the second electrode ET2) that overlaps with the second base electrode 50 in the plan view.

[0219] refer to Figures 47 to 49 The diagram illustrates operation S270 for forming the second cover electrode CVE2. A method for manufacturing a display device DD may include operation S270 for forming the second cover electrode CVE2.

[0220] The second cover electrode CVE2 can be formed in the region where the second base interlayer insulating layer has been etched. For example, the second cover electrode CVE2 can be formed in a region that overlaps with the region where the second base interlayer insulating layer has been etched in a plan view.

[0221] The second cover electrode CVE2 can be formed to cover the first cover electrode CVE1, which overlaps with the 2-2 base electrode 40 in the plan view, and the second conductive layer SL2 (e.g., a portion of the second electrode ET2), which overlaps with the second base electrode 50 in the plan view. The second cover electrode CVE2 can be connected (or electrically connected) to the 2-2 base electrode 40. The second cover electrode CVE2 can be connected (or electrically connected) to the second conductive layer SL2 (e.g., a portion of the second electrode ET2), which overlaps with the second base electrode 50.

[0222] The second cover electrode CVE2 can be connected to the 2-2 base electrode 40 to form the 2-2 electrode ET1_2'. The 2-2 electrode ET1_2' can electrically connect the 2-2 pixel circuit unit C2_2 to the 2-3 light-emitting element LD3'.

[0223] refer to Figure 50 and Figure 51 The diagram illustrates operation S300 for forming 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'. A method for manufacturing a display device DD may include operation S300 for forming 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'.

[0224] The operation S300 of forming 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3' may include forming the above-mentioned basic light-emitting element layer BLDL and etching the basic light-emitting element layer BLDL.

[0225] For example, a third basic light-emitting element layer with the same structure as the basic light-emitting element layer BLDL can be formed on the second interlayer insulating layer LIL2, and the third basic light-emitting element layer can be etched to form 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'.

[0226] The 2-3 light-emitting element LD3' can be etched to contact the 2-2 electrode ET1_2'. The 2-3 light-emitting element LD3' can be electrically connected to the 2-2 electrode ET1_2'. The 1-3 light-emitting element LD3 can be formed such that the lower surface of the 1-3 light-emitting element LD3 is in complete contact with the second interlayer insulating layer LIL2.

[0227] refer to Figure 52 and Figure 53 The diagram illustrates operation S310 for forming the third insulating layer IL3. A method for manufacturing a display device DD may include operation S310 for forming the third insulating layer IL3.

[0228] The operation S310 of forming the third insulating layer IL3 may include depositing a third base insulating layer to cover the second interlayer insulating layer LIL2, and then etching the third base insulating layer to form the third insulating layer IL3.

[0229] A third base insulating layer can be etched to form a third insulating layer IL3, and the third insulating layer IL3 can have a third opening MP3. The third opening MP3 can have a shape corresponding to the first opening MP1 and the second opening MP2. For example, the third opening MP3 can have a mesh pattern shape in a planar view.

[0230] refer to Figure 54 and Figure 55 The diagram illustrates operations S320 for forming a third conductive layer SL3 and operations S330 for forming a third connection electrode CNE3. A method for manufacturing a display device DD may include operations S320 for forming the third conductive layer SL3 and operations S330 for forming the third connection electrode CNE3.

[0231] The operation S320 of forming the third conductive layer SL3 may include forming the third conductive layer SL3 in the third opening MP3. The third conductive layer SL3 may fill the third opening MP3.

[0232] The third conductive layer SL3 can have a mesh pattern shape in the planar view. The third conductive layer SL3 can surround the 1-3 light-emitting elements LD3 and the 2-3 light-emitting elements LD3'.

[0233] In the plan view, the third conductive layer SL3, which overlaps with the second base electrode 50, can correspond to a portion of the second electrode ET2. The third conductive layer SL3 can supply the cathode signal supplied to the second electrode ET2 to the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'.

[0234] The third conductive layer SL3 can be connected to the second base electrode 50, the first conductive layer SL1, a portion of the first cover electrode CVE1, the second conductive layer SL2, and a portion of the second cover electrode CVE2 to form the second electrode ET2. The second electrode ET2 can be formed to pass through the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3.

[0235] The third connecting electrode CNE3 can be formed on the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'. The third connecting electrode CNE3 can be formed to contact the upper surface of the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'. The third connecting electrode CNE3 can cover the upper surface of the 1-3 light-emitting elements LD3 and 2-3 light-emitting elements LD3'.

[0236] The third connecting electrode CNE3 can be formed to contact a portion of the 1-3 light-emitting elements LD3, the 2-3 light-emitting elements LD3', and the third conductive layer SL3. For example, the third connecting electrode CNE3 can be formed to contact a portion of the third conductive layer SL3 that does not overlap with the second base electrode 50 in a planar view. The third connecting electrode CNE3 may not overlap with the second base electrode 50 in a planar view.

[0237] The third connecting electrode CNE3 can be connected to the 1-3 light-emitting elements LD3, the 2-3 light-emitting elements LD3', and a portion of the third conductive layer SL3. The third connecting electrode CNE3 can electrically connect the second electrode ET2 to the 1-3 light-emitting elements LD3 and the 2-3 light-emitting elements LD3'.

[0238] Subsequently, after the third connecting electrode CNE3 is formed, an insulating layer can be deposited to completely cover the third connecting electrode CNE3 and the third insulating layer IL3.

[0239] Figure 56 This is a schematic block diagram illustrating an electronic device 1000 including a display device 1060 according to an embodiment. Figure 57 It is shown Figure 56 The electronic device 1000 is a schematic diagram of an example of a smartphone. Figure 58 It is shown Figure 56 The electronic device 1000 is a schematic diagram of an example of a tablet computer.

[0240] refer to Figures 56 to 58 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1The display device DD. The electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, USB devices, or other systems. In embodiments, such as Figure 57 As shown, the electronic device 1000 can be a smartphone. In an embodiment, as... Figure 58 As shown, electronic device 1000 may be a tablet computer. However, the above examples are illustrative, and electronic device 1000 is not necessarily limited to the examples described above. For example, electronic device 1000 may be a cellular phone, video phone, smart pad, smartwatch, navigation device for a vehicle, computer monitor, portable computer, head-mounted display device, or the like.

[0241] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, a controller, etc. Processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In embodiments, processor 1010 may be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display images based on the input image data provided by processor 1010.

[0242] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can be used as working memory and / or buffer memory for the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0243] In response to control signals or data from processor 1010, storage device 1030 can store data. Storage device 1030 may include one or more non-volatile storage devices to retain data even if electronic device 1000 is powered off. In some embodiments, storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, or the like.

[0244] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In an embodiment, display device 1060 may be integrated with I / O device 1040.

[0245] Power supply 1050 can supply the power required to operate electronic device 1000. For example, power supply 1050 may include a power management integrated circuit (PMIC). In an embodiment, power supply 1050 can supply power to display device 1060.

[0246] In response to image data signals and / or control signals from processor 1010, display device 1060 can display an image. Display device 1060 can be connected to other components via a bus or other communication link.

[0247] According to some embodiments of this disclosure, a display device capable of displaying images with relatively high resolution and a method for manufacturing the display device are provided.

[0248] Some aspects of embodiments of this disclosure include a display device capable of improving light efficiency and relatively simplifying the manufacturing process, and a method of manufacturing the display device.

[0249] Although aspects of some embodiments of this disclosure have been described with reference to some embodiments thereof, it will be understood by those skilled in the art or of ordinary skill that various modifications and changes may be made to this disclosure without departing from the spirit and scope of the disclosure as described in the claims.

[0250] Therefore, the scope of the embodiments according to this disclosure is not limited to what is described in the “Detailed Description” of the specification, but should be defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: First sub-pixel; Second sub-pixel; Pixel circuit layer, including pixel circuits; A light-emitting element 1-1, a light-emitting element 1-2 on the light-emitting element 1-1, and a light-emitting element 1-3 on the light-emitting element 1-2, wherein the light-emitting element 1-1, the light-emitting element 1-2, and the light-emitting element 1-3 are located in a first sub-pixel region formed by the first sub-pixel; and The pixel circuit layer contains a 2-1 light-emitting element, a 2-2 light-emitting element on the 2-1 light-emitting element, and a 2-3 light-emitting element on the 2-2 light-emitting element, wherein the 2-1 light-emitting element, the 2-2 light-emitting element, and the 2-3 light-emitting element are located in the second sub-pixel region formed by the second sub-pixel. The 1-3 light-emitting elements are not electrically connected to the pixel circuit.

2. The display device according to claim 1, wherein, The 2-2 light-emitting elements are not electrically connected to the pixel circuit, and The light-emitting element 1-1, the light-emitting element 1-2, the light-emitting element 2-1, and the light-emitting element 2-3 are electrically connected to the pixel circuit.

3. The display device according to claim 1, further comprising: Electrode 1-1 is configured to electrically connect the pixel circuit to the light-emitting element 1-1; Electrodes 1-2 are configured to electrically connect the pixel circuit to the light-emitting elements 1-2; Electrode 2-1 is configured to electrically connect the pixel circuit to the light-emitting element 2-1; as well as Electrode 2-2 is configured to electrically connect the pixel circuit to the light-emitting element 2-3. In the plan view, the 1-2 electrodes do not overlap with the 1-1 light-emitting element.

4. The display device according to claim 1, further comprising: A first interlayer insulating layer, at least a portion of which is between the 1-1 light-emitting element and the 1-2 light-emitting element and between the 2-1 light-emitting element and the 2-2 light-emitting element; as well as A second interlayer insulating layer, at least a portion of which is between the 1-2 light-emitting element and the 1-3 light-emitting element, and between the 2-2 light-emitting element and the 2-3 light-emitting element. The second interlayer insulating layer completely covers the lower surface of the 1-3 light-emitting elements and exposes at least a portion of the lower surface of the 2-3 light-emitting elements.

5. The display device according to claim 3, further comprising: A first insulating layer surrounds the 1-1 light-emitting element and the 2-1 light-emitting element; A second insulating layer surrounds the 1-2 light-emitting elements and the 2-2 light-emitting elements; as well as A third insulating layer surrounds the 1-3 light-emitting elements and the 2-3 light-emitting elements. Wherein, electrodes 1-2 pass through the first insulating layer, and The 2-2 electrode passes through the first insulating layer and the second insulating layer.

6. The display device according to claim 1, further comprising a first electrode and a second electrode electrically connected to the pixel circuit. in, The second electrode does not overlap with light-emitting elements 1-1 and 2-1 in the plan view. The first electrode is the anode, and The second electrode is the cathode.

7. The display device according to claim 6, further comprising: A first insulating layer surrounds the 1-1 light-emitting element and the 2-1 light-emitting element; A second insulating layer surrounds the 1-2 light-emitting elements and the 2-2 light-emitting elements; as well as A third insulating layer surrounds the 1-3 light-emitting elements and the 2-3 light-emitting elements. The second electrode passes through the first insulating layer, the second insulating layer, and the third insulating layer.

8. The display device according to claim 6, further comprising: A first conductive layer is configured to electrically connect the second electrode to the 1-1 light-emitting element; The second conductive layer is configured to electrically connect the second electrode to the 1-2 light-emitting elements; as well as The third conductive layer is configured to electrically connect the second electrode to the 1-3 light-emitting elements. Each of the first conductive layer, the second conductive layer, and the third conductive layer comprises at least a portion of the same material as the second electrode.

9. The display device according to claim 8, wherein, Each of the first conductive layer, the second conductive layer, and the third conductive layer is integrally connected to the second electrode, and The first conductive layer, the second conductive layer, the third conductive layer, and the second electrode have a mesh pattern shape in the plan view.

10. The display device according to claim 8, wherein, The first conductive layer and the second electrode are located outside the area in the plan view where the 1-1 light-emitting element and the 2-1 light-emitting element are located.

11. The display device according to claim 8, further comprising: The first connecting electrode is on the first conductive layer; The second connecting electrode is located on the second conductive layer; as well as The third connecting electrode is located on the third conductive layer. The first connecting electrode covers the upper surface of the light-emitting element 1-1. The second connecting electrode covers the upper surface of the 1-2 light-emitting elements, and The third connecting electrode covers the upper surface of the 1-3 light-emitting elements.

12. The display device according to claim 1, wherein, The 1-1 light-emitting element and the 2-1 light-emitting element are configured to emit a first light. The 1-2 light-emitting elements and the 2-2 light-emitting elements are configured to emit a second light, and The 1-3 light-emitting elements and the 2-3 light-emitting elements are configured to emit a third light. The first light, the second light, and the third light are light of different colors.

13. A display device, comprising: Pixel circuit layer, including pixel circuits; 1-1 Light-emitting element, on the pixel circuit layer; 1-2 light-emitting elements, on the 1-1 light-emitting element; 1-3 light-emitting elements, on the 1-2 light-emitting elements; 2-1 Light-emitting element, located in the same layer as the 1-1 light-emitting element; 2-2 light-emitting elements, located in the same layer as the 1-2 light-emitting elements; as well as Light-emitting elements 2-3 are located on the same layer as light-emitting elements 1-3. The light-emitting elements 1-3 and 2-2 are not electrically connected to the pixel circuit.

14. The display device according to claim 13, further comprising: A first insulating layer surrounds the 1-1 light-emitting element and the 2-1 light-emitting element; A second insulating layer surrounds the 1-2 light-emitting elements and the 2-2 light-emitting elements; A third insulating layer surrounds the 1-3 light-emitting elements and the 2-3 light-emitting elements; Electrode 1-1 is configured to electrically connect the pixel circuit to the light-emitting element 1-1; Electrodes 1-2 are configured to electrically connect the pixel circuit to the light-emitting elements 1-2; Electrode 2-1 is configured to electrically connect the pixel circuit to the light-emitting element 2-1; as well as Electrode 2-2 is configured to electrically connect the pixel circuit to the light-emitting element 2-3. Wherein, electrodes 1-2 pass through the first insulating layer, and The 2-2 electrode passes through the first insulating layer and the second insulating layer.

15. The display device according to claim 13, further comprising: A first interlayer insulating layer, at least a portion of which is between the 1-1 light-emitting element and the 1-2 light-emitting element and between the 2-1 light-emitting element and the 2-2 light-emitting element; as well as A second interlayer insulating layer, at least a portion of which is between the 1-2 light-emitting element and the 1-3 light-emitting element, and between the 2-2 light-emitting element and the 2-3 light-emitting element. The second interlayer insulating layer completely covers the lower surface of the 1-3 light-emitting elements.

16. The display device according to claim 13, further comprising: The first and second electrodes are electrically connected to the pixel circuit. In the plan view, the second electrode does not overlap with the light-emitting element 1-1 and the light-emitting element 2-1.

17. The display device according to claim 16, wherein, The first electrode includes: Electrode 1-1 is configured to electrically connect the pixel circuit to the light-emitting element 1-1; Electrodes 1-2 are configured to electrically connect the pixel circuit to the light-emitting elements 1-2; Electrode 2-1, configured to electrically connect the pixel circuit to the light-emitting element 2-1; and Electrode 2-2 is configured to electrically connect the pixel circuit to the light-emitting element 2-3. The light-emitting elements 1-3 and 2-2 are not electrically connected to the first electrode.

18. A method of manufacturing a display device, the display device comprising a first sub-pixel region formed by a first sub-pixel and a second sub-pixel region formed by a second sub-pixel, the method comprising: Forming a pixel circuit layer that includes pixel circuits; In the first sub-pixel region, a base electrode 1-1 and a base electrode 1-2 electrically connected to the pixel circuit are formed, a light-emitting element 1-1 is formed on the pixel circuit layer, a light-emitting element 1-2 is formed on the light-emitting element 1-1, and a light-emitting element 1-3 is formed on the light-emitting element 1-2. as well as In the second sub-pixel region, a base electrode 2-1 and a base electrode 2-2 electrically connected to the pixel circuit are formed. A light-emitting element 2-1 is formed on the pixel circuit layer, a light-emitting element 2-2 is formed on the light-emitting element 2-1, and a light-emitting element 2-3 is formed on the light-emitting element 2-2. Wherein, the 1-1 base electrode is electrically connected to the 1-1 light-emitting element, The 1-2 base electrodes are electrically connected to the 1-2 light-emitting elements. The 2-1 base electrode is electrically connected to the 2-1 light-emitting element. The 2-2 base electrode is electrically connected to the 2-3 light-emitting element, and The 1-3 light-emitting elements are not electrically connected to the pixel circuit.

19. The method of claim 18, further comprising: A basic insulating layer is formed on the pixel circuit layer; A first insulating layer is formed on the basic insulating layer; A first interlayer insulating layer is formed on the first insulating layer; A second insulating layer is formed on the first interlayer insulating layer; as well as A second interlayer insulating layer is formed on the second insulating layer. The formation of the first insulating layer includes: depositing a first base insulating layer, etching the first base insulating layer to form a first contact opening exposing the 1-2 base electrodes, and etching the first base insulating layer to form a second contact opening exposing the 2-2 base electrodes. Forming the second insulating layer includes: depositing a second base insulating layer, and etching the second base insulating layer to form a third contact opening that overlaps with the second contact opening.

20. The method according to claim 19, wherein, During the formation of the 2-2 light-emitting element, the 2-2 light-emitting element is formed such that the lower surface of the 2-2 light-emitting element is in complete contact with the first interlayer insulating layer.

21. An electronic device comprising: A processor used to provide input image data; as well as A display device for displaying an image based on the input image. The display device includes: First sub-pixel; Second sub-pixel; Pixel circuit layer, including pixel circuits; A light-emitting element 1-1, a light-emitting element 1-2 on the light-emitting element 1-1, and a light-emitting element 1-3 on the light-emitting element 1-2, wherein the light-emitting element 1-1, the light-emitting element 1-2, and the light-emitting element 1-3 are located in a first sub-pixel region formed by the first sub-pixel; and The pixel circuit layer contains a 2-1 light-emitting element, a 2-2 light-emitting element on the 2-1 light-emitting element, and a 2-3 light-emitting element on the 2-2 light-emitting element, wherein the 2-1 light-emitting element, the 2-2 light-emitting element, and the 2-3 light-emitting element are located in the second sub-pixel region formed by the second sub-pixel. The 1-3 light-emitting elements are not electrically connected to the pixel circuit.

Images