Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises a driving circuit layer, an anode layer and at least one composite insulating layer. The composite insulating layer is arranged between the driving circuit layer and the anode layer, and a via is arranged on the composite insulating layer. The via penetrates the organic insulating layer and the inorganic insulating layer of the composite insulating layer so as to be passed by a conductive layer. Since the material resolution of the inorganic material is higher than that of the organic material, a smaller via can be formed in the inorganic insulating layer under the same process condition. Therefore, the space occupied by the via can be reduced, more space is left for placing pixels, and the pixel density of the array substrate can be improved without affecting the yield of products.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the development of display technology, a plethora of consumer electronics products relying on array substrates for display functions, such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, virtual reality display panels, and augmented reality display panels, have emerged. The rise of the "metaverse" concept has also brought virtual reality and augmented reality display panels to the attention of consumers, indicating broad market application prospects.

[0003] Virtual reality (VR) and augmented reality (AR) display panels are near-eye display panels, requiring high resolution from their array substrates. Under current pixel design architectures, the pixel density of the array substrates in VR and AR display panels can only reach 800ppi, which still cannot meet user needs. Further increasing the pixel density would lead to limited wiring space and compromised safety distances, reducing the product yield of the array substrate.

[0004] Therefore, it is necessary to provide an array substrate and a display panel to improve this defect. Summary of the Invention

[0005] This application provides an array substrate and a display panel that can balance high resolution and product yield.

[0006] To achieve the above objectives, according to a first aspect of this application, an array substrate is provided, comprising:

[0007] A driving circuit layer is disposed on the substrate;

[0008] An anode layer is disposed on the drive circuit layer; and

[0009] At least one composite insulating layer is disposed between the driving circuit layer and the anode layer;

[0010] At least one conductive layer is disposed on a corresponding composite insulating layer;

[0011] The composite insulating layer includes an inorganic insulating layer and an organic insulating layer disposed on the inorganic insulating layer. The composite insulating layer is provided with a via. The via penetrates the organic insulating layer and the inorganic insulating layer in the thickness direction of the array substrate to allow the conductive layer to pass through. The size of the portion of the via located in the inorganic insulating layer is smaller than the size of the portion of the via located in the organic insulating layer.

[0012] Optionally, the driving circuit layer includes a pixel driving circuit, and the array substrate includes at least two composite insulating layers, wherein the at least two composite insulating layers include:

[0013] A first composite insulating layer is disposed on the driving circuit layer and has a first via.

[0014] A second composite insulating layer is disposed on the first composite insulating layer and has a second through hole, which communicates with the first through hole;

[0015] The conductive layer includes a first conductive layer disposed on the second composite insulating layer, the pixel driving circuit includes a driving transistor, and the anode layer is electrically connected to the driving transistor in sequence through the first conductive layer, the second via, and the first via, wherein the size of the first via is smaller than the size of the second via.

[0016] Optionally, the conductive layer includes a second conductive layer, the second conductive layer includes a data line, and the pixel driving circuit includes a switching transistor connected in series between the data line and the driving transistor;

[0017] The second conductive layer is disposed between the first composite insulating layer and the second composite insulating layer.

[0018] Optionally, the first conductive layer is laid along the sidewalls of the first via and the second via, and a groove is formed at the first via and the second via;

[0019] The array substrate further includes a filling portion that fills the groove.

[0020] Optionally, the array substrate includes data lines, a first power signal line, a second power signal line, and a reset signal line; the driving circuit layer includes a pixel driving circuit, which includes:

[0021] A driving transistor is connected in series between the first power signal line and the second power signal line;

[0022] A switching transistor, wherein the second source of the switching transistor is electrically connected to the data line, and the second drain of the switching transistor is electrically connected to the driving transistor; and

[0023] A reset transistor, wherein the third source of the reset transistor is electrically connected to the reset signal line, and the third drain of the reset transistor is electrically connected to the driving transistor;

[0024] The second drain and the third drain are disposed in different layers.

[0025] Optionally, the array substrate is provided with a third via and a fourth via, the switching transistor includes a switching active part, the second drain is connected to the switching active part through the third via, and the reset transistor includes a reset active part, the third drain is connected to the reset active part through the fourth via.

[0026] The array substrate further includes scan lines, and the third via and the fourth via are arranged side by side at intervals along the extension direction of the scan lines.

[0027] Optionally, the orthographic projection of the second drain on the reference plane partially overlaps with the orthographic projection of the third drain on the reference plane, and the reference plane is parallel to the light-emitting surface of the array substrate.

[0028] Optionally, the second source electrode and the third source electrode are disposed in different layers.

[0029] Optionally, the array substrate is provided with a fifth via and a sixth via, the switching transistor includes a switching active part, the second source is connected to the switching active part through the fifth via, the reset transistor includes a reset active part, and the third source is connected to the reset active part through the sixth via;

[0030] The array substrate further includes multiple scan lines, and the fifth via and the sixth via are arranged side by side at intervals along the extension direction of the scan lines.

[0031] Optionally, the second drain and the third source are disposed on the same layer;

[0032] And / or, the second source and the third drain are disposed on the same layer.

[0033] Optionally, the array substrate includes:

[0034] The active layer includes the switching active part and the reset active part;

[0035] A first source-drain layer is disposed on the active layer and includes a second drain and a third source.

[0036] The second source-drain layer is disposed on the first source-drain layer and includes the second source and the third drain.

[0037] Optionally, the driving circuit layer includes a pixel driving circuit, the pixel driving circuit includes a storage capacitor, and the storage capacitor includes:

[0038] First electrode plate;

[0039] A second electrode plate is disposed on the first electrode plate; and

[0040] The third electrode plate is disposed on the second electrode plate;

[0041] The first electrode plate is electrically connected to the third electrode plate, and the orthographic projection of the first electrode plate on the reference plane partially overlaps with the orthographic projection of the second electrode plate on the reference plane and the orthographic projection of the third electrode plate on the reference plane to form the storage capacitor.

[0042] Optionally, the pixel driving circuit includes a driving transistor, a switching transistor, and a reset transistor, and the array substrate includes:

[0043] The first gate layer includes the driving gate of the driving transistor, the switching gate of the switching transistor, and the reset gate of the reset transistor.

[0044] A first source-drain layer is disposed on the first gate layer and includes the first electrode plate;

[0045] A second source / drain layer is disposed on the first source / drain layer and includes a second electrode plate; and

[0046] The second gate layer is disposed on the second source-drain layer and includes the third electrode plate.

[0047] Optionally, the first electrode plate and the second drain of the switching transistor are integrally formed.

[0048] And / or, the third electrode plate and the third drain of the reset transistor are integrally structured.

[0049] Optionally, the array substrate includes multiple data lines and multiple scan lines, the driving circuit layer includes a pixel driving circuit, the pixel driving circuit includes a switching transistor, the switching transistor includes a switching active part, the multiple scan lines include a first scan line and a second scan line adjacent to the first scan line, and the first scan line and the second scan line are spaced apart along the extension direction of the data lines;

[0050] Wherein, the orthographic projection of the active switch portion on the reference plane overlaps with the orthographic projection of the first scan line on the reference plane, and the orthographic projection of the active switch portion on the reference plane overlaps with the orthographic projection of the second scan line on the reference plane.

[0051] Optionally, the pixel driving circuit includes a reset transistor, and the reset transistor includes a reset active part;

[0052] Wherein, the orthographic projection of the reset active part on the reference plane overlaps with the orthographic projection of the first scan line on the reference plane, and the orthographic projection of the reset active part on the reference plane overlaps with the orthographic projection of the second scan line on the reference plane.

[0053] Optionally, the first scan line and the second scan line are disposed in the same layer and are made of the same material.

[0054] Optionally, the substrate is a glass substrate.

[0055] According to a second aspect of this application, a display panel is provided, comprising an array substrate as described above.

[0056] In the array substrate of this application embodiment, a composite insulating layer is provided between the driving circuit layer and the anode layer, and vias are provided on the composite insulating layer. The vias penetrate the organic insulating layer and the inorganic insulating layer of the composite insulating layer to facilitate the passage of the conductive layer. Since the material resolution of inorganic materials is higher than that of organic materials, smaller vias can be formed in the inorganic insulating layer under the same process conditions. Therefore, the space occupied by the vias can be reduced to free up more space for placing pixels, thereby increasing the pixel density of the array substrate without affecting the product yield.

[0057] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0060] Figure 1 A top view of an array substrate provided for an embodiment of this application;

[0061] Figure 2 A schematic diagram of the film layer structure of the array substrate provided for an embodiment of this application;

[0062] Figure 3 A schematic diagram of a pixel driving circuit provided for an embodiment of this application;

[0063] Figure 4 A partial film stack diagram of the pixel driving circuit in the array substrate provided for an embodiment of this application;

[0064] Figure 5 A schematic diagram of a display panel provided for an embodiment of this application. Detailed Implementation

[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0066] An embodiment of this application provides an array substrate, which includes a driving circuit layer, an anode layer, and at least one composite insulating layer. The anode layer is disposed on the driving circuit layer, and the composite insulating layer is disposed between the driving circuit layer and the anode layer. The composite insulating layer includes an inorganic insulating layer and an organic insulating layer disposed on the inorganic insulating layer. The composite insulating layer has a via, which penetrates the organic insulating layer and the inorganic insulating layer in the thickness direction of the display panel to allow the conductive layer to pass through. The size of the portion of the via located in the inorganic insulating layer is smaller than the size of the portion of the via located in the organic insulating layer.

[0067] In the embodiments of this application, a composite insulating layer is provided between the driving circuit layer and the anode layer, and vias are provided on the composite insulating layer. The vias penetrate the organic insulating layer and the inorganic insulating layer of the composite insulating layer to facilitate the passage of the conductive layer. The organic insulating layer in the composite insulating layer is located on the inorganic insulating layer. Since the material resolution of inorganic materials is higher than that of organic materials, smaller vias can be formed in the inorganic insulating layer under the same process conditions. Therefore, the space occupied by the vias can be reduced to free up more space for placing pixels, thereby increasing the pixel density of the array substrate without affecting the product yield.

[0068] It should be noted that the resolution in the embodiments of this application refers to the smallest feature size achievable in the etching process, that is, the finest line or smallest spacing that can be precisely fabricated on the material. Resolution directly reflects the fineness of the microstructure that the process technology can process. Under the same process conditions, because the resolution of inorganic insulating layers is higher than that of organic insulating layers, smaller vias can be formed in inorganic insulating layers.

[0069] Combination Figure 1 and Figure 2 As shown, Figure 1 A top view of the array substrate provided for an embodiment of this application. Figure 2 This is a schematic diagram of the film layer structure of the array substrate provided in an embodiment of this application. The array substrate includes a display area AA and a non-display area NA disposed around the display area AA. The display area AA is the area used to display images, and the non-display area NA is the area used to place peripheral circuits and traces.

[0070] The array substrate 100 includes a driving circuit layer 1 and an anode layer 21. The driving circuit layer 1 includes a plurality of pixel driving circuits 10. The anode layer 21 is disposed on the driving circuit layer 1 and includes a plurality of patterned anodes 211. Each anode 211 is electrically connected to a corresponding pixel driving circuit 10.

[0071] like Figure 1 As shown, the array substrate 100 further includes at least one composite insulating layer 4, which is disposed between the driving circuit layer 1 and the anode layer 21. The composite insulating layer 4 includes an inorganic insulating layer 401 and an organic insulating layer 402, with the organic insulating layer 402 disposed on the inorganic insulating layer 401. The composite insulating layer 4 has a via H0 that penetrates both the organic insulating layer 402 and the inorganic insulating layer 401 in the thickness direction of the array substrate, allowing the conductive layer to pass through. The size of the portion of the via H0 located in the inorganic insulating layer 401 is smaller than the size of the portion of the via H0 located in the organic insulating layer.

[0072] In this embodiment, the via H0 includes a first sub-part H01 located in the inorganic insulating layer 401 and a second sub-part H02 located in the organic insulating layer 402. The first sub-part H01 and the second sub-part H02 are connected to form the via H0. The first sub-part H01 has a first dimension d1, and the second sub-part H02 has a second dimension d2. The first dimension d1 is smaller than the second dimension d2. The orthographic projection of the first sub-part H01 on the reference plane lies within the orthographic projection of the second sub-part H02 on the reference plane. The reference plane is parallel to the light-emitting surface of the display panel. It should be noted that the first dimension d1 of the first sub-part H01 refers to the aperture of the bottom portion of the via H0 located in the inorganic insulating layer 401, and the second dimension d2 of the second sub-part H02 refers to the aperture of the bottom portion of the via H0 located in the organic insulating layer 402.

[0073] In the embodiments of this application, a composite insulating layer 4 is provided between the driving circuit layer 1 and the anode layer 21, and a via H0 is provided on the composite insulating layer 4. The via H0 penetrates the organic insulating layer 402 and the inorganic insulating layer 401 of the composite insulating layer 4 so that the conductive layer can pass through. The organic insulating layer 402 in the composite insulating layer 4 is located on the inorganic insulating layer 401. Since the material resolution of inorganic materials is higher than that of organic materials, under the same process conditions, a smaller via H0 can be formed in the inorganic insulating layer 401. Therefore, the space occupied by the via H0 can be reduced, so as to free up more space for placing pixels. Thus, the pixel density of the array substrate can be increased without affecting the product yield.

[0074] In some embodiments, combined with Figure 3 As shown, Figure 3This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application. The array substrate includes multiple data lines (Data), multiple scan lines (Scan), a first power signal line (Vdd), a second power signal line (Vss), and a reset signal line (Vi). The pixel driving circuit 10 includes a driving transistor T1, a switching transistor T2, a reset transistor T3, and a storage capacitor Cst. The driving transistor T1 and the light-emitting device 20 are connected in series between the first power signal line Vdd and the second power signal line Vss. The first source of the driving transistor T1 is electrically connected to the first power signal line Vdd, and the first drain of the driving transistor T1 is electrically connected to the anode of the light-emitting device 20. The second source of the switching transistor T2 is electrically connected to the data line Data, and the second drain of the switching transistor T2 is electrically connected to the driving gate of the driving transistor T1 and one of the plates of the storage capacitor Cst. The switching gate of the switching transistor T2 is electrically connected to the scan line. The third source of the reset transistor T3 is electrically connected to the reset signal line Vi, and the third drain of the reset transistor T3 is electrically connected to the first drain of the driving transistor T1 and the other plate of the storage capacitor Cst. The reset gate of the reset transistor T3 is electrically connected to the scan line.

[0075] In some embodiments, the array substrate includes at least two composite insulating layers 4, which include a first composite insulating layer 41 and a second composite insulating layer 42. Both the first composite insulating layer 41 and the second composite insulating layer 42 are stacked structures formed by stacking inorganic insulating layers and organic insulating layers.

[0076] like Figure 2 As shown, the first composite insulating layer 41 is disposed on the driving circuit layer 1. The plurality of vias H0 include the first via H1. The first via H1 is disposed on the first composite insulating layer 41. The first via H1 penetrates the inorganic insulating layer and the organic insulating layer of the first composite insulating layer 41 in the thickness direction. The size of the portion of the first via H1 located in the inorganic insulating layer is smaller than the size of the portion of the first via H1 located in the organic insulating layer. The second composite insulating layer 42 is disposed on the first composite insulating layer 41. The plurality of vias H0 also includes a second via H2. The second via H is disposed on the second composite insulating layer 42. The second via H2 penetrates the inorganic insulating layer and the organic insulating layer of the second composite insulating layer 42 in the thickness direction. The size of the portion of the second via H2 located in the inorganic insulating layer is smaller than the size of the portion of the second via H2 located in the organic insulating layer. The second via H2 is connected to the first via H1 so that the conductive layer 30 can pass through. The bottom of the first via H1 has a first dimension d1, and the bottom of the second via H2 has a third dimension d3. The first dimension d1 of the first via H1 refers to the aperture of the bottom of the first via H1, and the third dimension d3 of the second via H2 refers to the aperture of the bottom of the second via H2.

[0077] In this embodiment, the via H0 in the composite insulating layer 4 can refer to the first via H1 in the first composite insulating layer 41 and the second via H2 in the second composite insulating layer 42. The structure of the first via H1 and the second via H2 can be referred to the aforementioned via H0, and will not be repeated here.

[0078] In some embodiments, such as Figure 2 As shown, the cross-sectional shape of the first via H1 and the second via H2 is trapezoidal, that is, the aperture of the first via H1 and the second via H2 gradually increases from the end near the driving circuit layer 1 to the end near the anode layer 21, and the aperture at the bottom of the second via H2 is larger than the aperture at the top of the first via H1.

[0079] In some embodiments, such as Figure 2 As shown, the array substrate includes at least one conductive layer 30, which includes a first conductive layer 3. The first conductive layer 3 is disposed on the second composite insulating layer 42. The first conductive layer 3 is electrically connected to the first drain of the driving transistor T1 through a second via H2 and a first via H1 in sequence. The orthographic projection of the first via H1 on the reference plane lies within the orthographic projection of the second via H2 on the reference plane. The reference plane is parallel to the light-emitting surface of the array substrate. The first via H1 and the second via H2 form a deep hole, which can reduce the planar space occupied by the first via H1 and the second via H2, and is beneficial to increasing the pixel density of the array substrate.

[0080] In some embodiments, combined with Figure 2 and 3 As shown, the array substrate includes a second conductive layer 5, the second conductive layer 5 includes a data line Data, a switching transistor T2 is connected in series between the data line Data and the driving transistor T1, and the second conductive layer 5 is disposed between the first composite insulating layer 41 and the second composite insulating layer 42.

[0081] It should be noted that if the linewidth of the data line (Data) is too narrow, it will increase the impedance of the data line, causing uneven charging voltage between the far and near light-emitting devices, resulting in a decrease in the uniformity of the light emission brightness of the array substrate. Therefore, the data line (Data) needs to have a certain linewidth and spacing to improve the uniformity of the light emission brightness of the array substrate and reduce crosstalk between adjacent signal lines. In this embodiment, by setting the first conductive layer 3 and the second conductive layer 5 in different layers, not only can short circuits between the data lines (Data) of the first conductive layer 3 and the second conductive layer 5 be avoided and the signal crosstalk between the first conductive layer 3 and the data lines (Data) be improved, but the planar space occupied by the first conductive layer 3 and the second conductive layer 5 can also be reduced, thereby increasing the pixel density of the array substrate.

[0082] In some embodiments, such as Figure 2As shown, the first conductive layer 3 is laid along the sidewalls of the first via H1 and the second via H2, and a groove G1 is formed by recessing at the first via H1 and the second via H2. The array substrate 100 includes a filling portion 403, which is disposed in the groove G1 to fill the groove G1.

[0083] like Figure 2 As shown, the upper surface of the filling portion 403 is flush with the upper surface of the organic insulating layer 402 of the first composite insulating layer 41. The groove G1 is located directly below the light-emitting device 20. By filling the groove G1 with the filling portion 403, the flatness of the terrain below the light-emitting device 20 can be improved. This not only improves the luminous efficiency and lifespan of the light-emitting device 20, but also reduces the risk of short circuit between the anode and cathode of the light-emitting device 20 due to uneven terrain.

[0084] In some embodiments, combined with Figure 2 As shown, the array substrate further includes a passivation layer 7, a third conductive layer 6, and a third composite insulating layer 43. The array substrate includes multiple conductive layers 30, which also include a second conductive layer 5 and a third conductive layer 6. The passivation layer 7 is disposed on the first conductive layer 3, and the third conductive layer 6 is disposed on the passivation layer 7. The third conductive layer 6 includes a reset signal line and a first conductive portion 61. The passivation layer 7 has a seventh hole and an eighth hole. The seventh hole penetrates the passivation layer 7 and the first composite insulating layer 41. The reset signal line Vi is connected to the second conductive layer 5 through the seventh hole. The second conductive layer 5 is connected to the third source of the reset transistor T3 through a via. The eighth hole penetrates the passivation layer 7 to expose the first conductive layer 3, and the first conductive portion 61 is connected to the first conductive layer 3 through the eighth hole.

[0085] In some implementations, such as Figure 2 As shown, the third composite insulating layer 43 is disposed on the third conductive layer 6 and the passivation layer 7. The third composite insulating layer 43 includes an inorganic insulating layer 401 and an organic insulating layer 402.

[0086] In some embodiments, such as Figure 2 As shown, the array substrate also includes a pixel definition layer 22, an anode layer 21 disposed on a third composite insulating layer 43, the anode layer 21 including a plurality of patterned anodes 211, and the pixel definition layer 22 disposed on the anode layer 21 and the third composite insulating layer 43. The third composite insulating layer 43 has a ninth hole that penetrates the inorganic insulating layer 401 and the organic insulating layer 402. The anode layer 21 is connected to the first conductive part 61 through the ninth hole, thereby realizing the electrical connection between the first drain of the driving transistor T1 and the anode of the light-emitting device.

[0087] In some embodiments, such as Figure 2As shown, the array substrate 100 includes a substrate 101, a buffer layer 102, and a pixel driving circuit layer 1 disposed on the buffer layer 102. The pixel driving circuit layer 1 includes an active layer 11, a first gate insulating layer 12, a first gate layer 13, a first interlayer dielectric layer 14, a first source-drain layer 15, a second interlayer dielectric layer 16, a second source-drain layer 17, a third interlayer dielectric layer 18, and a second gate layer 19, which are sequentially stacked on the buffer layer 102.

[0088] In some embodiments, combined with Figure 2 and Figure 4 As shown, Figure 4 The image shows a partial film stack diagram of the pixel driving circuit in the array substrate provided in the embodiments of this application, wherein the second drain D2 of the switching transistor T2 and the third drain D3 of the reset transistor T3 are disposed in different layers.

[0089] In some embodiments, combined with Figure 2 and Figure 4 As shown, the array substrate 100 is provided with a third via H3 and a fourth via H4. The switching transistor T2 includes a switching active part 112, and the second drain D2 is connected to the first end of the switching active part 112 through the third via H3. The reset transistor T3 includes a reset active part 113, and the third drain D3 is connected to the first end of the reset active part 113 through the fourth via H4. In the extension direction of the scan line Scan, the third via H3 and the fourth via H4 are arranged side by side at intervals.

[0090] By placing the second drain D2 and the third drain D3 on different layers, the distance between the third via H3 and the fourth via H4 can be reduced, allowing the third via H3 and the fourth via H4 to be arranged side-by-side with intervals, without needing to misalign them. This reduces the planar space occupied by the third via H3 and the fourth via H4, which not only facilitates increasing the pixel density of the array substrate but also frees up space to increase the channel length of the driving transistor T1, the switching transistor T2, and the reset transistor T3, reducing the off-state leakage current of the driving transistor T1, the switching transistor T2, and the reset transistor T3, thus improving screen flicker. This, in turn, improves the uniformity of brightness on the array substrate and reduces its power consumption.

[0091] In some embodiments, combined with Figure 4 As shown, the orthographic projection of the second drain D2 on the reference plane partially overlaps with the orthographic projection of the third drain D3 on the reference plane. This can further reduce the distance between the third via H3 and the fourth via H4, thereby reducing the planar space occupied by the third via H3 and the fourth via H4, and thus further improving the pixel density of the array substrate.

[0092] In some embodiments, such as Figure 4As shown, the second source S2 and the third source S3 are configured in different layers.

[0093] In some embodiments, combined with Figure 2 and Figure 4 As shown, the array substrate is provided with a fifth via H5 and a sixth via H6. The second source S2 is connected to the second end of the active switch 112 through the fifth via H5, and the third source S3 is connected to the second end of the active reset 113 through the sixth via H6. In the extension direction of the scan line Scan, the fifth via H5 and the sixth via H6 are arranged side by side at intervals.

[0094] By placing the second source S2 and the third source S3 on different layers, the distance between the fifth via H5 and the sixth via H6 can be reduced, allowing the fifth via H5 and the sixth via H6 to be arranged side-by-side with intervals, without needing to misalign them. This reduces the planar space occupied by the fifth via H5 and the sixth via H6, which not only facilitates increasing the pixel density of the array substrate but also frees up space to further increase the channel length of the driving transistor T1, the switching transistor T2, and the reset transistor T3, reducing the off-state leakage current of the driving transistor T1, the switching transistor T2, and the reset transistor T3, improving screen flicker, thereby enhancing the uniformity of the array substrate's brightness and reducing its power consumption.

[0095] In some embodiments, combined with Figure 2 and Figure 4 As shown, the second drain D2 and the third source S3 are disposed in the same layer and are made of the same material. The second drain D2 and the third source S3 can be fabricated simultaneously using the same process.

[0096] In some embodiments, combined with Figure 2 and Figure 4 As shown, the active layer 11 includes a driving active portion 111 of driving transistor T1, a switching active portion 112 of switching transistor T2, and a reset active portion 113 of reset transistor T3. Both the switching active portion 112 and the reset active portion 113 are elongated strips extending along the second direction Y. The switching active portion 112 and the reset active portion 113 are parallel and spaced apart in the first direction X. The driving active portion 111 and the reset active portion 113 are connected as a single unit. The first direction X and the second direction Y are perpendicular to each other, and both directions X and Y are perpendicular to the thickness direction of the display panel.

[0097] In some embodiments, combined with Figure 2 and Figure 4 As shown, the first source-drain layer 15 is disposed on the active layer 11, and the first source-drain layer 15 includes a second drain D2 and a third source S3.

[0098] In some embodiments, combined with Figure 2 and Figure 4 As shown, the second source-drain layer 17 is disposed on the first source-drain layer 15, and the second source-drain layer 17 includes a second source S2 and a third drain D3.

[0099] In some embodiments, such as Figure 2 As shown, the storage capacitor Cst includes a first plate C1, a second plate C2, and a third plate C3. The first plate C1 is disposed on different film layers as the second plate C2 and the third plate C3. The second plate C2 is disposed on the first plate C1, and the third plate C3 is disposed on the second plate C2. The first plate C1 and the third plate C3 are electrically connected. The second plate C2 is insulated from the first plate C1 and the third plate C3 in the thickness direction.

[0100] In some embodiments, such as Figure 2 As shown, the orthographic projection of the first electrode C1 on the reference plane partially overlaps with the orthographic projections of the second electrode C2 and the third electrode C3 on the reference plane to form a storage capacitor Cst. By placing the first electrode C1, the second electrode C2, and the third electrode C3 on different film layers, and by placing the first electrode C1 and the third electrode C3 together to form a sandwich capacitor, the planar space occupied by the storage capacitor Cst can be reduced while keeping the capacitance of the storage capacitor Cst unchanged. This frees up more space for placing pixels, thereby further increasing the pixel density of the array substrate.

[0101] In some embodiments, such as Figure 2 As shown, a first source-drain layer 15 is disposed on a first gate layer 13, a second source-drain layer 17 is disposed on the first source-drain layer 15, and a second gate layer 19 is disposed on the second source-drain layer 17. The first source-drain layer 15 includes a first electrode C1, the second source-drain layer 17 includes a second electrode C2, and the second gate layer 19 includes a third electrode C3.

[0102] In some embodiments, combined with Figure 2 and Figure 4 As shown, the first source-drain layer 15 includes a second drain D2 and a first electrode C1. The first electrode C1 and the second drain D2 are an integral structure. The first electrode C1 and the second drain D2 are different parts of a patterned structure in the first source-drain layer 15.

[0103] In some embodiments, combined with Figure 2 and Figure 4As shown, the second source-drain layer 17 includes a third drain D3 and a second electrode C2. The second electrode C2 and the third drain D3 are an integral structure. The second electrode C2 and the third drain D3 are different parts of a patterned structure in the second source-drain layer 17.

[0104] In some embodiments, combined with Figures 2 to 4 As shown, the multiple scan lines Scan include a first scan line Scan1 and a second scan line Scan2 adjacent to the first scan line Scan1. The first scan line Scan1 and the second scan line Scan2 are spaced apart along the extension direction of the data line Data. The orthographic projection of the active switch portion 112 on the reference plane overlaps with the orthographic projection of the first scan line Scan1 on the reference plane, and the orthographic projection of the active switch portion 112 on the reference plane overlaps with the orthographic projection of the second scan line Scan2 on the reference plane. That is, the same active switch portion 112 overlaps with the first scan line Scan1 and the second scan line Scan2 respectively, so that the same active switch portion 112 has two channel portions. This can increase the channel length of the switching transistor T2, thereby reducing the leakage current of the switching transistor T2, thereby improving the screen flicker, improving the uniformity of the brightness of the display panel, and reducing the power consumption of the display panel.

[0105] In some embodiments, the orthographic projection of the reset active portion 113 on the reference plane partially overlaps with the orthographic projection of the first scan line Scan1 on the reference plane, and the orthographic projection of the reset active portion 113 on the reference plane partially overlaps with the orthographic projection of the second scan line Scan2 on the reference plane. That is, the same reset active portion 113 overlaps with the first scan line Scan1 and the second scan line Scan2 respectively, so that the reset active portion 113 has two channel portions. This can increase the channel length of the reset transistor T3, thereby reducing the leakage current of the reset transistor T3, thereby improving the screen flicker, thereby improving the uniformity of the brightness of the array substrate, and reducing the power consumption of the array substrate.

[0106] In some embodiments, the first scan line Scan1 and the second scan line Scan2 are disposed in the same layer and are made of the same material.

[0107] In some embodiments, combined with Figure 2 , Figure 4 As shown, the first gate layer 13 includes a first scan line Scan1 and a second scan line Scan2.

[0108] Based on the array substrate provided in the above embodiments of this application, embodiments of this application also provide a display panel; please refer to [link to relevant documentation]. Figure 5 , Figure 5This is a schematic diagram of a display panel provided in an embodiment of this application. The display panel 1000 includes an array substrate 100 and a light-emitting layer 200 disposed on the array substrate 100. The array substrate 100 can be any of the array substrates provided in the above embodiments. The display panel provided in the embodiments of this application can achieve the same technical effects as the array substrates provided in any of the above embodiments, and will not be described in detail here.

[0109] In some embodiments, the light-emitting layer 200 may include, but is not limited to, a hole injection layer, a hole transport layer, an organic light-emitting material layer, an electron transport layer, and an electron injection layer (not shown in the figure) stacked sequentially.

[0110] In some embodiments, the light-emitting layer 200 may also have film layer structures such as a cathode layer, an encapsulation layer, and a protective layer stacked on it (not shown in the figure).

[0111] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide an array substrate and a display panel. The array substrate includes a driving circuit layer, an anode layer, and at least one composite insulating layer. By setting a composite insulating layer between the driving circuit layer and the anode layer, and setting vias on the composite insulating layer, the vias penetrate the organic insulating layer and the inorganic insulating layer of the composite insulating layer to facilitate the passage of the conductive layer. The organic insulating layer in the composite insulating layer is located on the inorganic insulating layer. Since the material resolution of inorganic materials is higher than that of organic materials, under the same process conditions, smaller vias can be formed in the inorganic insulating layer. Therefore, the space occupied by the vias can be reduced to free up more space for placing pixels, thereby increasing the pixel density of the array substrate without affecting the product yield.

[0112] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0113] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0114] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0115] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, include: substrate; A driving circuit layer is disposed on the substrate; An anode layer is disposed on the drive circuit layer; as well as At least one composite insulating layer is disposed between the driving circuit layer and the anode layer; At least one conductive layer is disposed on a corresponding composite insulating layer; The composite insulating layer includes an inorganic insulating layer and an organic insulating layer disposed on the inorganic insulating layer. The composite insulating layer is provided with a via. The via penetrates the organic insulating layer and the inorganic insulating layer in the thickness direction of the array substrate so that the conductive layer can pass through. The size of the portion of the via located in the inorganic insulating layer is smaller than the size of the portion of the via located in the organic insulating layer. The driving circuit layer includes multiple pixel driving circuits, each pixel driving circuit including a switching transistor and a reset transistor. The array substrate is provided with a third via and a fourth via. The switching transistor includes a second drain and a switching active portion. The second drain is connected to the switching active portion through the third via. The reset transistor includes a third drain and a reset active portion. The third drain is connected to the reset active portion through the fourth via. The switching active portion and the reset active portion are adjacent to each other and spaced apart. The second drain and the third drain are disposed on different layers. The array substrate also includes scan lines. Multiple pixel driving circuits are repeatedly arranged along the extension direction of the scan lines. Multiple third vias and multiple fourth vias are alternately arranged on the same straight line along the extension direction of the scan lines.

2. The array substrate as described in claim 1, characterized in that, The driving circuit layer includes a pixel driving circuit, and the array substrate includes at least two composite insulating layers, wherein the at least two composite insulating layers include: A first composite insulating layer is disposed on the driving circuit layer and has a first via. A second composite insulating layer is disposed on the first composite insulating layer and has a second through hole, which communicates with the first through hole; The conductive layer includes a first conductive layer disposed on the second composite insulating layer, the pixel driving circuit includes a driving transistor, and the anode layer is electrically connected to the driving transistor in sequence through the first conductive layer, the second via, and the first via, wherein the size of the first via is smaller than the size of the second via.

3. The array substrate as described in claim 2, characterized in that, The conductive layer includes a second conductive layer, the second conductive layer includes a data line, and the pixel driving circuit includes a switching transistor connected in series between the data line and the driving transistor. The second conductive layer is disposed between the first composite insulating layer and the second composite insulating layer.

4. The array substrate as described in claim 2, characterized in that, The first conductive layer is laid along the sidewalls of the first via and the second via, and a groove is formed at the first via and the second via; The array substrate further includes a filling portion that fills the groove.

5. The array substrate as described in any one of claims 1 to 4, characterized in that, The array substrate includes data lines, a first power signal line, a second power signal line, and a reset signal line; the pixel driving circuit includes: A driving transistor is connected in series between the first power signal line and the second power signal line. The second source of the switching transistor is electrically connected to the data line, and the second drain of the switching transistor is electrically connected to the driving transistor. The third source of the reset transistor is electrically connected to the reset signal line, and the third drain of the reset transistor is electrically connected to the driving transistor.

6. The array substrate as described in claim 5, characterized in that, The orthographic projection of the second drain on the reference plane partially overlaps with the orthographic projection of the third drain on the reference plane, and the reference plane is parallel to the light-emitting surface of the array substrate.

7. The array substrate as described in claim 5, characterized in that, The second source electrode and the third source electrode are disposed in different layers.

8. The array substrate as claimed in claim 7, characterized in that, The array substrate is provided with a fifth via and a sixth via. The second source is connected to the active switch part through the fifth via, and the third source is connected to the active reset part through the sixth via. In the direction of the extension of the scan line, the fifth via and the sixth via are arranged side by side at intervals.

9. The array substrate as described in claim 5, characterized in that, The second drain and the third source are disposed on the same layer; And / or, the second source and the third drain are disposed on the same layer.

10. The array substrate as claimed in claim 9, characterized in that, The array substrate includes: The active layer includes the switching active part and the reset active part; A first source-drain layer is disposed on the active layer and includes a second drain and a third source. The second source-drain layer is disposed on the first source-drain layer and includes the second source and the third drain.

11. The array substrate as described in any one of claims 1 to 4, characterized in that, The driving circuit layer includes a pixel driving circuit, and the pixel driving circuit includes a storage capacitor, the storage capacitor comprising: First electrode plate; A second electrode plate is disposed on the first electrode plate; and The third electrode plate is disposed on the second electrode plate; The first electrode plate is electrically connected to the third electrode plate, and the orthographic projection of the first electrode plate on the reference plane partially overlaps with the orthographic projection of the second electrode plate on the reference plane and the orthographic projection of the third electrode plate on the reference plane to form the storage capacitor.

12. The array substrate as claimed in claim 11, characterized in that, The pixel driving circuit includes a driving transistor, and the array substrate includes: The first gate layer includes the driving gate of the driving transistor, the switching gate of the switching transistor, and the reset gate of the reset transistor. A first source-drain layer is disposed on the first gate layer and includes the first electrode plate; A second source / drain layer is disposed on the first source / drain layer and includes a second electrode plate; and The second gate layer is disposed on the second source-drain layer and includes the third electrode plate.

13. The array substrate as claimed in claim 12, characterized in that, The first electrode plate and the second drain of the switching transistor are integrally formed. And / or, the second electrode plate and the third drain of the reset transistor are integrally structured.

14. The array substrate as described in any one of claims 1 to 4, characterized in that, The array substrate includes multiple data lines and multiple scan lines. The multiple scan lines include a first scan line and a second scan line adjacent to the first scan line. The first scan line and the second scan line are spaced apart along the extension direction of the data lines. Wherein, the orthographic projection of the active switch portion on the reference plane overlaps with the orthographic projection of the first scan line on the reference plane, and the orthographic projection of the active switch portion on the reference plane overlaps with the orthographic projection of the second scan line on the reference plane.

15. The array substrate as claimed in claim 14, characterized in that, The orthographic projection of the reset active part on the reference plane overlaps with the orthographic projection of the first scan line on the reference plane, and the orthographic projection of the reset active part on the reference plane overlaps with the orthographic projection of the second scan line on the reference plane.

16. The array substrate as claimed in claim 14, characterized in that, The first scan line and the second scan line are arranged in the same layer and are made of the same material.

17. The array substrate as described in any one of claims 1 to 4, characterized in that, The substrate is a glass substrate.

18. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 17.

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