Array substrate and display device

Abstract

The invention provides an array substrate and a display device, and relates to the technical field of display. The array substrate comprises a first conducting layer, a second conducting layer and an insulating layer located between the first conducting layer and the second conducting layer, a plurality of first fan-out lines are arranged in the first conducting layer, a plurality of second fan-out lines are arranged in the second conducting layer, and the first fan-out lines and the second fan-out lines extend in the same direction; the plurality of first fan-out lines comprise a first line group, the first line group comprises a plurality of adjacent first fan-out lines, and the orthographic projection of the first line group on the second conductive layer is located in a gap range of two adjacent second fan-out lines. A novel fan-out line arrangement mode is provided.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] In related technologies, the wide bezels of display devices negatively impact the user experience. Summary of the Invention

[0003] Embodiments of this disclosure provide an array substrate and a display device.

[0004] On one hand, an array substrate is provided, the array substrate including a first conductive layer and a second conductive layer, the first conductive layer having a plurality of first fan-out lines, a first gap being formed between two adjacent first fan-out lines, the plurality of first fan-out lines forming a plurality of first gaps; the second conductive layer having a plurality of second fan-out lines, the plurality of second fan-out lines including a first line group, the first line group including a plurality of adjacent second fan-out lines, the orthographic projection of the first line group on the first conductive layer being located within the range of the first gap.

[0005] In some implementations, the linewidth of the second fan-out line is smaller than that of the first fan-out line.

[0006] In some embodiments, the gap between two adjacent second fan-out lines within the first line group is called the second gap, and the width of the second gap refers to the dimension of the second gap along the line width direction of the second fan-out line; the difference between the line width of the first fan-out line and the second fan-out line is greater than half the width of the second gap.

[0007] In some embodiments, the width of the second gap is greater than 0 micrometers and less than or equal to 10 micrometers.

[0008] In some embodiments, the linewidth of the first fan-out line is greater than 0 micrometers and less than or equal to 5 micrometers; and / or, the linewidth of the second fan-out line is greater than 0 micrometers and less than or equal to 3 micrometers.

[0009] In some embodiments, the width of the first gap is less than twice the width of the first fan-out line; the width of the first gap refers to the dimension of the first gap along the linewidth direction of the first fan-out line.

[0010] In some implementations, the first line group includes two second fan-out lines.

[0011] In some implementations, the first line group includes three or more second fan-out lines.

[0012] In some embodiments, the plurality of second fan-out lines include a plurality of first line groups, the plurality of first line groups being arranged at intervals, and the orthographic projection of the first fan-out line on the second conductive layer being located between two adjacent first line groups.

[0013] In some embodiments, the plurality of second fan-out lines further includes a second line group, wherein the number of second fan-out lines in the second line group is different from the number of second fan-out lines in the first line group, the orthographic projection of the second line group on the first conductive layer is located within the first gap range, and the first line group and the second line group are located in different first gaps.

[0014] In some implementations, the second line group includes a second fan-out line.

[0015] In some embodiments, the first gap includes a first gap and a second gap, the orthographic projection of the first line group onto the first conductive layer is located within the range of the first gap, the orthographic projection of the second line group onto the first conductive layer is located within the range of the second gap, and the width of the second gap is less than or equal to the width of the first gap.

[0016] In some embodiments, the first line group and the second line group are arranged alternately, and the orthogonal projection of the first fan-out line onto the second conductive layer is located between the first line group and the second line group.

[0017] In some embodiments, the array substrate further includes a substrate, wherein the first conductive layer, the second conductive layer and the insulating layer are stacked on the substrate, and the second conductive layer is closer to the substrate.

[0018] In some embodiments, the array substrate has a display area and a non-display area, the first fan-out line and the second fan-out line are located in the non-display area, the display area is provided with a plurality of transistors, at least some of the gates of the transistors are located in the second conductive layer, and at least some of the source and drain terminals of the transistors are located in the first conductive layer.

[0019] On the other hand, a display device is provided, including the aforementioned array substrate.

[0020] In some embodiments, the display device further includes a paper film layer disposed on the surface of the array substrate.

[0021] The array substrate and display device provided in this disclosure include multiple second fan-out lines in the first line group opposite to the first gap, resulting in a large number of fan-out lines in the second conductive layer. With a fixed fan-out area size, the more fan-out lines in the second conductive layer, the denser the arrangement of the fan-out lines. A denser arrangement of the fan-out lines results in smaller gaps between adjacent fan-out lines, lower surface roughness, and consequently, a lower surface roughness of the second conductive layer. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A front view structure of a display device provided in an embodiment of this disclosure;

[0024] Figure 2 for Figure 1 Partial structural cross-section of AA;

[0025] Figure 3 A front view of a display panel provided in an embodiment of this disclosure;

[0026] Figure 4 for Figure 3 A magnified view of the area at point I;

[0027] Figure 5 A front view of another display panel provided in an embodiment of this disclosure;

[0028] Figure 6 This is a diagram illustrating the arrangement of fan-out lines in a related technology.

[0029] Figure 7 This is a diagram illustrating the arrangement of fan-out lines in a related technology.

[0030] Figure 8 This refers to the relative positional relationship between two adjacent fan-out lines in related technologies;

[0031] Figure 9 This is a partial structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0032] Figure 10 This is a partial structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0033] Figure 11 This is a partial structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0034] Figure 12 This is a partial structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0035] Figure 13 This is a partial structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0036] Figure 14 This is a partial structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0037] Figure 15 This is a partial structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0038] Figure 16 This is a partial structural cross-sectional view of an array substrate provided in an embodiment of this disclosure.

[0039] Figure label:

[0040] 1000 - Display device; 100 - Display panel; 101 - Array substrate;

[0041] 110 - Substrate; 120 - Circuit layer; 130 - Paper film layer; 140 - Protective layer; 150 - Data driver chip; 160 - Gate driver chip;

[0042] 1-Data fan-out line; 2-Gate fan-out line;

[0043] 10 - First conductive layer; 20 - Second conductive layer; 30 - Insulating layer; 40 - Transistor;

[0044] 11-First sector outgoing line; 21-Second sector outgoing line; 31-Gate insulating layer; 32-Source-drain insulating layer; 41-Gate; 42-Source; 43-Drain;

[0045] 21a - First line group; 21b - Second line group. Detailed Implementation

[0046] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0047] In the embodiments of this disclosure, the terms "first," "second," "third," and "fourth" are used to distinguish identical or similar items with essentially the same function and effect, solely for the purpose of clearly describing the technical solutions of the embodiments of this disclosure, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0048] In embodiments of this disclosure, "a plurality of" means two or more, and "at least one" means one or more, unless otherwise expressly and specifically defined.

[0049] In the embodiments of this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0050] Figure 1 This is a front view structure of a display device provided in an embodiment of the present disclosure. For example... Figure 1 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device with display functionality. For example, the display device 1000 can be a mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, architectural structure, packaging and aesthetic structure (e.g., a display of an image of a piece of jewelry), etc. Figure 1 The following illustration uses a mobile phone as an example of a display device 1000. The display device 1000 includes a display panel 100, through which images are displayed.

[0051] The display panel 100 can be an electronic paper (ePaper) display panel, or a liquid crystal display (LCD), an electroluminescent display panel, or a photoluminescent display panel.

[0052] When the display panel 100 is a liquid crystal display panel, it can be either a horizontal electric field type liquid crystal display panel or a vertical electric field type liquid crystal display panel. When the display panel 100 is a horizontal electric field type liquid crystal display panel, it can be an in-plane switching (IPS) liquid crystal display panel or an advanced super-dimensional switching (ADS) liquid crystal display panel.

[0053] When the display panel 100 is an electroluminescent display panel, the display panel 100 can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel.

[0054] When the display panel 100 is a photoluminescent display panel, the display panel 100 can be a quantum dot photoluminescent display panel.

[0055] The following explanation uses display panel 100 as an example of an electronic paper display panel.

[0056] Figure 2 for Figure 1 Partial structural cross-sectional view of AA in the diagram. Figure 2 Only a portion of the film structure of the display panel is shown; the structure of the display device (e.g., the casing) is not included. Figure 2 As shown in the image. Figure 2 As shown, the display panel includes an array substrate 101, which may include a substrate 110 and a circuit layer 120 disposed on the surface of the substrate 110.

[0057] The substrate 110 is used to support and connect other film layer structures of the display panel 100. The substrate 110 can be a rigid substrate or a flexible substrate, and can be flexibly selected according to the needs of practical applications.

[0058] For example, substrate 110 is a rigid substrate. For instance, substrate 110 can be a glass substrate or a polymethyl methacrylate (PMMA) substrate, etc.

[0059] For example, substrate 110 is a flexible substrate. For instance, substrate 110 can be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate twoformic acid glycol ester (PEN) substrate, or a polyimide (PI) substrate, etc.

[0060] The substrate 110 can be a single-layer structure or a composite structure formed by stacking multiple layers. When the substrate 110 is a composite structure, the multiple layers in the substrate 110 can be any one or more of the rigid and flexible substrates mentioned above.

[0061] The circuit layer 120 is composed of multiple film layer structures stacked together. Circuits are provided in the circuit layer 120, such as pixel driving circuits, gate driving circuits, data lines, gate lines, pixel electrodes, etc.

[0062] Continue to refer to Figure 2 When the display panel 100 is an electronic paper display panel, the display panel 100 also includes a paper film layer 130 and a protective layer 140 that are sequentially stacked on the array substrate 101.

[0063] The paper film layer 130 covers the side of the circuit layer 120 away from the substrate 110 and is used to display images under the drive of the circuits within the circuit layer 120. Exemplarily, the paper film layer 130 includes an adhesive layer, an electronic paper layer, and a common electrode stacked sequentially, and the paper film layer 130 is bonded to the array substrate 101 by the adhesive layer.

[0064] The electronic paper layer contains charged particles that can display images when driven by a working voltage. Depending on the display principle, the electronic paper layer can be a microcapsule electronic paper layer, a microcup electronic paper layer, an electronic liquid powder electronic paper layer, a cholesterol liquid crystal electronic paper layer, a microelectromechanical system electronic paper layer, an electrowetting electronic paper layer, etc. The embodiments disclosed herein do not limit this type.

[0065] The adhesive layer can be either flexible or rigid. When the display panel 100 is a flexible display panel, the adhesive layer is flexible to facilitate bending of the display panel. For example, the adhesive layer is optically clear adhesive (OCA) or pressure-sensitive adhesive (PSA).

[0066] The array substrate 101 is provided with pixel electrodes, and an electric field is formed between the pixel electrodes and the common electrode to drive the movement of charged particles in the electronic paper layer, thereby displaying an image.

[0067] The protective layer 140 covers one side of the substrate of the paper film layer 130 and is used to protect the paper film layer 130.

[0068] When the display panel 100 is a liquid crystal display panel, the display panel 100 includes an array substrate 101 and a color filter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate 101 and the color filter substrate. The display panel may also include a backlight module disposed on the side of the array substrate 101 away from the color filter substrate.

[0069] When the display panel 100 is an organic light-emitting diode (OLED) display panel, the display panel 100 includes light-emitting devices disposed on the array substrate 101. The structural components of the display panel will not be listed individually here.

[0070] Continue to refer to Figure 2 The display panel 100 may have a display area AA and a non-display area NA connected to the display area AA. The non-display area NA may be located on one side, two sides, or three sides of the display area AA, or the non-display area NA may be arranged around the display area AA.

[0071] The pixel driving circuit, data lines, gate lines, etc., within the circuit layer 120 can be located within the display area AA. When a gate driving circuit is provided within the circuit layer 120, the gate driving circuit can be located within the non-display area NA.

[0072] For example, continue to refer to Figure 2 The paper film layer 130 covers the display area AA, and the edge of the paper film layer 130 is located in the non-display area NA. The protective layer 140 covers the paper film layer 130, and the edge of the protective layer 140 is located between the outer edge of the paper film layer 130 and the outer edge of the array substrate 101.

[0073] The width of the bezel of the display device 1000 is directly related to the size of the non-display area NA. Specifically, the non-display area NA extends along... Figure 2 The larger the horizontal dimension shown, the wider the bezel of the display device 1000. To reduce the width of the bezel of the display device 1000, the size of the non-display area NA needs to be reduced.

[0074] Figure 3 This is a front view of a display panel provided in an embodiment of the present disclosure. Figure 4 for Figure 3 A magnified view of the area at point I. (See image below.) Figure 3 and Figure 4 As shown, the non-display area NA is equipped with a fan-out line FL, which is used to lead the traces in the display area AA to the non-display area NA.

[0075] For example, such as Figure 3 and Figure 4As shown, the fan-out line FL may include a data fan-out line 1, one end of which is electrically connected to a data line DL, and the other end of which is electrically connected to a data driver chip 150. For example, the fan-out line FL may include multiple data fan-out lines 1, one end of which is electrically connected to a data line DL, and the other ends of the multiple data fan-out lines 1 converge and are electrically connected to the data driver chip 150.

[0076] The other end of the data fan-out line 1 can be directly electrically connected to the data driver chip 150, meaning that the display panel 100 adopts a COG (Chip on Glass) packaging solution. The display panel 100 can also adopt a COF (Chip on Film) packaging solution, meaning that the other end of the data fan-out line 1 extends to the bonding area, and the bonding area is bonded to the flip-chip film.

[0077] Continue to refer to Figure 3 The fan-out line FL may also include a gate fan-out line 2, one end of which is electrically connected to a gate line, and the other end of which is electrically connected to the gate driver chip 160. For example, the fan-out line FL may include multiple gate fan-out lines 2, one end of which is electrically connected to a gate line, and the other ends of the multiple gate fan-out lines 2 converge and are electrically connected to the gate driver chip 160.

[0078] For example, the other end of the gate fan-out line 2 can be directly electrically connected to the gate driver chip 160, that is, the display panel 100 adopts a COG (Chip on Glass) packaging scheme. The display panel 100 can also adopt a COF (Chip on Film) packaging scheme, that is, the other end of the gate fan-out line 2 extends to the bonding region, and the bonding region is bonded to the flip-chip film.

[0079] in, Figure 3 The diagram illustrates the arrangement of fan-out lines FL when the data driver chip 150 and the gate driver chip 160 are integrated into a single structure. In this case, the gate fan-out lines 2 can include a gate fan-out line 2 located on the left and a gate fan-out line 2 located on the right. The left and right gate fan-out lines 2 are electrically connected to different gate lines, respectively. This divides the gate fan-out lines 2 into two parts, one on the left and the other on the right, reducing the number of gate fan-out lines 2 located on the same side, thereby reducing the size of the left and right non-display areas NA.

[0080] Figure 5 A front view of another display panel provided in an embodiment of this disclosure, such as... Figure 5 As shown, when the data driver chip 150 and the gate driver chip 160 are separate structures, the gate fan-out line 2 is located on the same side of the display panel 100 (e.g., Figure 5 (As shown on the right).

[0081] Continue to refer to Figure 2 , Figure 2 In this context, the fanout area refers to the region where the fan-out line (FL) is located. For example... Figures 2 to 5 As shown, the fan-out area occupies a large proportion of the non-display area NA, so the size of the non-display area NA can be reduced by decreasing the size of the fan-out area.

[0082] It should be noted that when the following descriptions involve the interrelationships of position, size, etc. among multiple fan-out lines, they all refer to the interrelationships of position, size, etc. among multiple fan-out lines within the same type of fan-out line. For example, the interrelationships of position, size, etc. among multiple data fan-out lines 1, or the interrelationships of position, size, etc. among multiple left gate fan-out lines 2, or the interrelationships of position, size, etc. among multiple right gate fan-out lines 2.

[0083] Continue to refer to Figure 4 Multiple fan-out lines (FLs) can extend in the same direction, for example, multiple fan-out lines (FLs) can be arranged in parallel and spaced apart.

[0084] Figure 6 This is a diagram illustrating the arrangement of fan-out lines in related technologies, for example... Figure 6 for Figure 4 Cross-sectional view at point BB. (See diagram below.) Figure 6 As shown, one arrangement of related technologies is that each fan-out line is located on the same conductive layer, and there is a gap between two adjacent fan-out lines. In this way, the size of the fan-out area is relatively large.

[0085] Figure 7 This is a diagram illustrating the arrangement of fan-out lines in related technologies, for example... Figure 7 for Figure 4 Cross-sectional view at point BB. (See diagram below.) Figure 7 As shown, another arrangement of related technologies is that some fan-out lines are located in one fan-out line layer and other fan-out lines are located in another fan-out line layer. This can reduce the number of fan-out lines located in the same conductive layer, thereby reducing the size of the non-display area (NA).

[0086] Figure 8 This refers to the relative positional relationship between two adjacent fan-out lines in related technologies. For example... Figure 8 As shown, when there is an overlapping region between the fan-out lines of the two conductive layers, the overlapping region and the insulating layer between the overlapping regions form parasitic capacitance. When the fan-out line is gate fan-out line 2, the parasitic capacitance increases the gate line load, leading to an increase in Tr / Tf, which in turn reduces the pixel charging rate. Furthermore, the gate voltage of the next row of pixels will be pulled by the gate voltage of the previous row of pixels, causing the switching transistor to turn on prematurely, thus posing a risk of mischarging and crosstalk.

[0087] Therefore, the fan-out lines of the two conductive layers need to be staggered, such as... Figure 7 As shown, this arrangement makes it less likely for parasitic capacitance to form between adjacent fan-out lines. However, even when the fan-out lines are staggered, the size of the fan-out region is still relatively large.

[0088] In view of this, the present disclosure provides a fan-out line arrangement method that can reduce the size of the fan-out area, thereby reducing the bezel width of the display device 1000.

[0089] Figure 9 This is a partial structural diagram of an array substrate 101 provided in an embodiment of the present disclosure, for example... Figure 9 for Figure 4 A cross-sectional view of BB. (See attached image.) Figure 9 As shown, the array substrate 101 may include a first conductive layer 10, a second conductive layer 20, and an insulating layer 30 located between the first conductive layer 10 and the second conductive layer 20. The first conductive layer 10, the second conductive layer 20, and the insulating layer 30 may belong to the circuit layer 120. The first conductive layer 10 and the second conductive layer 20 may be metal layers such as copper or aluminum, and the materials of the first conductive layer 10 and the second conductive layer 20 may be the same or different. The insulating layer 30 is made of an insulating material to achieve insulation between the first conductive layer 10 and the second conductive layer 20. The insulating layer 30 may be a single-layer structure or composed of multiple layers stacked together.

[0090] Continue to refer to Figure 9 The first conductive layer 10 has multiple first fan-out lines 11, and a first gap D1 is formed between two adjacent first fan-out lines 11. Multiple first fan-out lines 11 form multiple first gaps D1.

[0091] For example, multiple first fan-out lines 11 within the first conductive layer 10 extend along a direction perpendicular to the XY plane, and the multiple first fan-out lines 11 are arranged parallel and spaced apart along the first direction X. A first gap D1 is formed between two adjacent first fan-out lines 11 along the first direction X, and multiple first fan-out lines 11 form multiple first gaps D1, with a first fan-out line 11 spaced apart between two adjacent first gaps D1.

[0092] The line width W1 of the first outgoing line 11 refers to the dimension of the first outgoing line 11 along the first direction X.

[0093] For example, the linewidth W1 of the first outgoing line 11 is greater than 0 micrometers and less than or equal to 5 micrometers. For instance, the linewidth W1 of the first outgoing line 11 is 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, etc.

[0094] Continue to refer to Figure 9 The second conductive layer 20 has multiple second fan-out lines 21, and there is a gap between two adjacent second fan-out lines 21.

[0095] For example, multiple second fan-out lines 21 within the second conductive layer 20 extend along a direction perpendicular to the XY plane, and the multiple second fan-out lines 21 are arranged parallel to and spaced apart along the first direction X. There is a gap between two adjacent second fan-out lines 21 along the first direction X, and the multiple second fan-out lines 21 form multiple gaps.

[0096] The line width W2 of the second outgoing line 21 refers to the dimension of the second outgoing line 21 along the first direction X.

[0097] For example, the linewidth W2 of the second fan-out line 21 is greater than 0 micrometers and less than or equal to 3 micrometers. For example, the linewidth W2 of the first fan-out line 11 is 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, etc.

[0098] Continue to refer to Figure 9 The multiple second-side outgoing lines 21 include a first line group 21a, and the first line group 21a includes multiple second-side outgoing lines 21, with the multiple second-side outgoing lines 21 in the first line group 21a being adjacent to each other in sequence.

[0099] A second gap D2 exists between two adjacent second fan-out lines 21 within the first line group 21a. Multiple second fan-out lines 21 within the first line group 21a can form one second gap D2 (e.g., when including two second fan-out lines 21), or multiple second gaps D2 (e.g., when including three or more second fan-out lines 21). When multiple second gaps D2 are formed, the widths of the multiple second gaps D2 can be the same or different.

[0100] The width of the second gap D2 refers to the dimension of the second gap D2 along the first direction X.

[0101] For example, the width of the second gap D2 is greater than 0 micrometers and less than or equal to 10 micrometers. For example, the width of the second gap D2 is 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, 10 micrometers, etc.

[0102] in, Figure 2 The diagram shows that the first line group 21a includes two second fan-out lines 21. In actual applications, the number of second fan-out lines 21 in the first line group 21a can also be three, four, five, etc.

[0103] The orthographic projection of the first line group 21a onto the first conductive layer 10 is located within the range of the first gap D1, that is, the first line group 21a is directly opposite the first gap D1, and the orthographic projection of the first line group 21a onto the first conductive layer 10 does not overlap with the first fan-out line 11, so as to prevent the first fan-out line 11 and the second fan-out line 21 from overlapping to form parasitic capacitance.

[0104] In practical applications, the distance between adjacent first fan-out line 11 and second fan-out line 21 can be minimized as much as possible, thereby reducing the size of the fan-out area.

[0105] Compared to the staggered arrangement of fan-out lines in the two conductive layers in related technologies, the first line group 21a opposite to the first gap D1 in this embodiment includes multiple second fan-out lines 21, resulting in a larger number of fan-out lines in the second conductive layer 20. With a fixed fan-out area size, the more fan-out lines in the second conductive layer 20, the denser the arrangement of the fan-out lines. A denser arrangement of fan-out lines results in smaller gaps between adjacent fan-out lines, lower surface roughness, and consequently, a lower surface roughness in the second conductive layer 20.

[0106] The second conductive layer 20 may include one first line group 21a or multiple first line groups 21a. When the second conductive layer 20 includes multiple first line groups 21a, the orthographic projection of each first line group 21a on the first conductive layer 10 is located within the first gap D1, and the orthographic projections of different first line groups 21a are located within different first gaps D1.

[0107] Figure 10 This is a partial structural diagram of an array substrate 101 provided in an embodiment of the present disclosure, for example... Figure 10 for Figure 4 A cross-sectional view of BB. (See attached image.) Figure 10 As shown, when the second conductive layer 20 includes a plurality of first line groups 21a, the plurality of first line groups 21a are arranged at intervals, and the orthographic projection of the first fan-out line 11 on the second conductive layer 20 is located between two adjacent first line groups 21a.

[0108] For example, such as Figure 10 As shown, along the first direction X, the first line group 21a and the first fan-out line 11 are arranged alternately. For example, a first fan-out line 11 and a first line group 21a adjacent to this first fan-out line 11 form an array unit, and the array unit is arranged in an array along the first direction X.

[0109] This allows for a greater number of fan-out lines within the second conductive layer 20. With a fixed fan-out area size, a larger number of fan-out lines within the second conductive layer 20 results in a denser arrangement of these lines. A denser arrangement of the fan-out lines leads to smaller gaps between adjacent lines, resulting in lower surface roughness and consequently, a lower surface roughness for the second conductive layer 20.

[0110] Continue to refer to Figure 9In some embodiments, the width of the first fan-out line 11 is W1, and the width of the second fan-out line 21 is W2. The linewidth of the second fan-out line 21 is smaller than that of the first fan-out line 11, i.e., W2 < W1. The smaller linewidth of the second fan-out line 21 allows for a more compact arrangement of the fan-out lines FL within the second conductive layer 20, thereby reducing the size of the fan-out region. For example, reducing the linewidth of the second fan-out line 21 can reduce the width of the array unit along the first direction X, thus reducing the size of the fan-out region.

[0111] In practical applications, the second fan-out line 21 can be fabricated using a phase-shift mask. Phase-shift masks (PSMs) utilize phase-shifting technology for imaging, which can improve image resolution. Phase-shifting mask technology improves lithographic resolution by changing the phase of the light beam. Its basic principle is to change the mask structure so that the light waves passing through adjacent transparent areas have a 180-degree phase difference. Two light waves with a 180-degree phase difference undergo destructive interference in a specific region on the imaging surface, reducing the light intensity in the dark area and increasing the light field in the bright area, thereby improving contrast and resolution.

[0112] When the second fan-out line 21 is fabricated using a phase-shifting mask, the first fan-out line 11 can be fabricated using a mask other than the phase-shifting mask (such as the mask used in the array substrate 101 in the related art) to reduce the fabrication cost of the array substrate 101.

[0113] For example, the linewidth of the first fan-out line 11 is 5 micrometers, and the linewidth of the second fan-out line 21 is 3 micrometers; the linewidth of the first fan-out line 11 is 5 micrometers, and the linewidth of the second fan-out line 21 is 2 micrometers; the linewidth of the first fan-out line 11 is 5 micrometers, and the linewidth of the second fan-out line 21 is 1 micrometer; the linewidth of the first fan-out line 11 is 4 micrometers, and the linewidth of the second fan-out line 21 is 3 micrometers; the linewidth of the first fan-out line 11 is 4 micrometers, and the linewidth of the second fan-out line 21 is 2 micrometers; the linewidth of the first fan-out line 11 is 4 micrometers, and the linewidth of the second fan-out line 21 is 1 micrometer; the linewidth of the first fan-out line 11 is 3 micrometers, and the linewidth of the second fan-out line 21 is 2 micrometers; the linewidth of the first fan-out line 11 is 3 micrometers, and the linewidth of the second fan-out line 21 is 1 micrometer; the linewidth of the first fan-out line 11 is 2 micrometers, and the linewidth of the second fan-out line 21 is 1 micrometer.

[0114] Continue to refer to Figure 9 and Figure 10 The width of the first fan-out line 11 is W1, the width of the second fan-out line 21 is W2, the width of the first gap D1 is D1, the width of the second gap D2 is D2, the spacing between the first fan-out line 11 and its adjacent second fan-out line 21 is Δ, and the width of the array unit along the first direction X is Wz = W1 + 2*W2 + D2 + 2*Δ.

[0115] Continue to refer to Figure 7 In related technologies, the width of the fan-out line FL is w, the spacing between two adjacent fan-out lines is d, and the array unit includes two fan-out lines. The width of the array unit along the first direction X is wz = 2*w + 2*d. In practical applications, Δ and d depend on the alignment accuracy between different film layers. It can be assumed that Δ and d are equal. The fabrication process of the first fan-out line 11 can be the same as the fabrication process of the fan-out line in related technologies. Therefore, the linewidth of the first fan-out line 11 can be equal to the linewidth of the fan-out line in related technologies, i.e., W1 = w. In this case, wz = 2*W1 + 2*Δ.

[0116] Assume that the array substrate 101 of this embodiment includes a array units, the array substrate 101 of the related art includes b array units, and the total number of fan-out lines in the array substrate 101 of this embodiment is the same as the total number of fan-out lines in the array substrate 101 of the related art.

[0117] because Figure 10 The middle array unit includes one first sector output line 11 and two second sector output lines 21. Figure 10 The middle array unit includes 3 fan-out lines. Figure 7 The array unit includes two fan-out lines, and the total number of fan-out lines in the array substrate 101 of this embodiment is the same as the total number of fan-out lines in the array substrate 101 of related technologies, so 3a = 2b.

[0118] Along the first direction X, Figure 7 The size of the fan-out region in the array substrate 101 shown is b*wz=b*(2*W1+2*Δ). Figure 10 The size of the fan-out region in the array substrate 101 shown is a*Wz=a*(W1+2*W2+D2+2*Δ). The difference between the two is δ=b*wz-a*Wz=b*(2*W1+2*Δ)-a*(W1+2*W2+D2+2*Δ). Substituting 3a=2b into the above formula, we get δ=2a*W1 -2a*W2-a*D2-a*Δ.

[0119] When W1-W2>1 / 2*(D2+Δ), δ>0. That is, when the difference in line width between the first sector line 11 and the second sector line 21 is greater than half the sum of the width of the second gap D2 and Δ, Figure 10 The size of the fan-out region is smaller than that in related technologies, which reduces the size of the non-display area NA in the array substrate 101. When the process precision is high and Δ is small, Δ can be ignored, and the difference in linewidth between the first fan-out line 11 and the second fan-out line 21 is greater than half the width of the second gap D2.

[0120] Additionally, when δ > 0, 2*W1 > 2*W2 + D2 + Δ. Since 2*W2 + D2 is approximately equal to D1, and Δ is greater than zero, then 2*W1 > D1, meaning the width of the first gap D1 is less than twice the width of the first fan-out line 11.

[0121] Figure 11 This is a partial structural diagram of an array substrate 101 provided in an embodiment of the present disclosure, for example... Figure 11 for Figure 4 A cross-sectional view of BB. (See attached image.) Figure 11 As shown, the first line group 21a may include three second fan-out lines 21.

[0122] Figure 12 This is a partial structural diagram of an array substrate 101 provided in an embodiment of the present disclosure, for example... Figure 12 for Figure 4 A cross-sectional view of BB. (See attached image.) Figure 12 As shown, when the second conductive layer 20 includes a plurality of first line groups 21a, the plurality of first line groups 21a are arranged at intervals, and the orthographic projection of the first fan-out line 11 on the second conductive layer 20 is located between two adjacent first line groups 21a.

[0123] For example, such as Figure 12 As shown, along the first direction X, the first line group 21a and the first fan-out line 11 are arranged alternately. For example, a first fan-out line 11 and a first line group 21a adjacent to this first fan-out line 11 form an array unit, and the array unit is arranged in an array along the first direction X.

[0124] This allows for a greater number of fan-out lines within the second conductive layer 20. With a fixed fan-out area size, a larger number of fan-out lines within the second conductive layer 20 results in a denser arrangement of these lines. A denser arrangement of the fan-out lines leads to smaller gaps between adjacent lines, resulting in lower surface roughness and consequently, a lower surface roughness for the second conductive layer 20.

[0125] Continue to refer to Figure 11 and Figure 12 The width of the first fan-out line 11 is W1, the width of the second fan-out line 21 is W2, the width of the first gap D1 is D1, the width of the second gap D2 is D2, and the width of the array unit along the first direction X is Wz = W1 + 3*W2 + 2*D2 + 2*Δ.

[0126] Continue to refer to Figure 7In related technologies, the width of the fan-out line is w, the spacing between two adjacent fan-out lines is d, and the array unit includes two fan-out lines. The width of the array unit along the first direction X is wz = 2*w + 2*d. In practical applications, Δ and d depend on the alignment accuracy between different film layers. It can be assumed that Δ and d are equal. The fabrication process of the first fan-out line 11 can be the same as the fabrication process of the fan-out line in related technologies. Therefore, the linewidth of the first fan-out line 11 can be equal to the linewidth of the fan-out line in related technologies, i.e., W1 = w. In this case, wz = 2*W1 + 2Δ.

[0127] Assume that the array substrate 101 of this embodiment includes a array units, the array substrate 101 of the related art includes b array units, and the total number of fan-out lines in the array substrate 101 of this embodiment is the same as the total number of fan-out lines in the array substrate 101 of the related art.

[0128] because Figure 10 The middle array unit includes one first sector output line 11 and two second sector output lines 21. Figure 10 The middle array unit includes 4 fan-out lines. Figure 7 The array unit includes two fan-out lines, and the total number of fan-out lines in the array substrate 101 of this embodiment is the same as the total number of fan-out lines in the array substrate 101 of related technologies, so 4a = 2b.

[0129] Along the first direction X, Figure 7 The size of the fan-out region in the array substrate 101 shown is b*wz=b*(2*W1+2*Δ). Figure 10 The size of the fan-out region in the array substrate 101 shown is a*Wz=a*(W1+3*W2+2*D2+2*Δ). The difference between the two is δ=b*wz-a*Wz=b*(2*W1+2*Δ)-a*(W1+3*W2+2*D2+2*Δ). Substituting 4a=2b into the above formula, we get δ=3a*W1-3a*W2-2a*D2-2a*Δ.

[0130] When W1-W2>2 / 3*(D2+Δ), δ>0. That is, when the difference in line width between the first exit line 11 and the second exit line 21 is greater than two-thirds of the sum of the width of the second gap D2 and Δ, Figure 12 The size of the fan-out region is smaller than that in related technologies, which reduces the size of the non-display area NA in the array substrate 101. When the process precision is high and Δ is small, Δ can be ignored, and the difference in linewidth between the first fan-out line 11 and the second fan-out line 21 is greater than half the width of the second gap D2.

[0131] Additionally, when δ > 0, 3*W1 > 3*W2 + 2*D2 + 2*Δ. Since 3*W2 + 2*D2 is approximately equal to D1, and Δ is greater than zero, then 3*W1 > D1, meaning the width of the first gap D1 is less than three times the width of the first fan-out line 11.

[0132] Figure 13 This is a partial structural diagram of an array substrate 101 provided in an embodiment of the present disclosure, for example... Figure 13 for Figure 4 A cross-sectional view of BB. (See attached image.) Figure 13 As shown, the first line group 21a may include four or more second fan-out lines 21. When the number of second fan-out lines 21 in the first line group 21a is four or more, the relationship between the difference in line width of the first fan-out line 11 and the second fan-out line 21 and the width of the second gap D2, as well as the relationship between the width of the first gap D1 and the line width of the first fan-out line 11, are derived by similar principles and will not be listed here.

[0133] Figure 14 This is a partial structural diagram of an array substrate 101 provided in an embodiment of the present disclosure, for example... Figure 14 for Figure 4 A cross-sectional view of BB. (See attached image.) Figure 14 As shown, multiple second-fan outgoing lines 21 may also include a first line group 21a and a second line group 21b. The number of second-fan outgoing lines 21 in the second line group 21b is different from the number of second-fan outgoing lines 21 in the first line group 21a.

[0134] in, Figure 14 The diagram shows that the second line group 21b includes one second sector outgoing line 21. Of course, the second line group 21b can also include multiple second sector outgoing lines 21. When the second line group 21b includes multiple second sector outgoing lines 21, the multiple second sector outgoing lines 21 are sequentially adjacent to each other.

[0135] The number of second-fan outgoing lines 21 in the second line group 21b can be greater than or less than the number of second-fan outgoing lines 21 in the first line group 21a.

[0136] The second wire group 21b is projected onto the first conductive layer 10 within the range of the first gap D1, and the first wire group 21a and the second wire group 21b are located in different first gaps D1. For example, the first gap D1 includes gap one d1 and gap two d2, the first wire group 21a is projected onto the first conductive layer 10 within the range of gap one d1, and the second wire group 21b is projected onto the first conductive layer 10 within the range of gap two d2.

[0137] Continue to refer to Figure 14The width of gap 2 d2 can be equal to the width of gap 1 d1, allowing multiple first fan-out lines 11 to be arranged at equal intervals, thereby reducing the graphic complexity of the first conductive layer 10. Furthermore, when the number of second fan-out lines 21 in the second line group 21b is less than the number of second fan-out lines 21 in the first line group 21a, the number of second fan-out lines 21 opposite to gap 1 d1 is smaller, which can reduce the alignment accuracy requirements between the first conductive layer 10 and the second conductive layer 20.

[0138] Of course, when the number of second fan-out lines 21 in the second line group 21b is less than the number of second fan-out lines 21 in the first line group 21a, the width of gap 2 d2 can also be less than the width of gap 1 d1, so as to reduce the size of the fan-out area.

[0139] Figure 15 This is a partial structural diagram of an array substrate 101 provided in an embodiment of the present disclosure, for example... Figure 15 for Figure 4 A cross-sectional view of BB. (See attached image.) Figure 15 As shown, the first line group 21a and the second line group 21b can be arranged alternately, and the first fan-out line 11 is projected onto the second conductive layer 20 between the first line group 21a and the second line group 21b.

[0140] A first conductive layer 10, a second conductive layer 20, and an insulating layer 30 are stacked on a substrate 110. Either the first conductive layer 10 or the second conductive layer 20 may be closer to the substrate 110. Because the fan-out lines in the second conductive layer 20 are more densely arranged and have a lower surface roughness, when the second conductive layer 20 is closer to the substrate 110, the film formed on the second conductive layer 20 is smoother.

[0141] Figure 16 This is a partial structural cross-sectional view of an array substrate 101 provided in an embodiment of this disclosure. (See attached image.) Figure 16 As shown, a transistor 40 is provided in the display area AA. The gate 41 of the transistor 40 is located in the second conductive layer 20, and the source 41 and drain 42 of the transistor 40 are located in the first conductive layer 10. That is, the first conductive layer 10 is the source-drain layer, and the second conductive layer 20 is the gate layer.

[0142] For example, the array substrate 101 includes a substrate 110 and a second conductive layer 20, a gate insulating layer 31, a channel layer 50, a source-drain insulating layer 32, and a first conductive layer 10 sequentially stacked on the substrate 110. The first conductive layer 10 includes the gate 41 of a transistor and a second fan-out line 21, the channel layer 50 includes the channel of the transistor 40, the gate insulating layer 31 and the source-drain insulating layer 32 together form the insulating layer 30, and the first conductive layer 10 includes the source 42, the drain 43 of the transistor, and the first fan-out line 11.

[0143] The display area AA contains multiple transistors. It is possible that the gates of all transistors are located in the second conductive layer and the source and drain are located in the first conductive layer; or it is possible that the gates of some transistors are located in the second conductive layer and the source and drain are located in the first conductive layer.

[0144] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: A first conductive layer is provided, wherein a plurality of first fan-out lines are provided in the first conductive layer, a first gap is formed between two adjacent first fan-out lines, and the plurality of first fan-out lines form a plurality of first gaps; The second conductive layer has multiple second fan-out lines. The multiple second fan-out lines include a first line group, which includes multiple adjacent second fan-out lines. The orthographic projection of the first line group onto the first conductive layer is located within the first gap.

2. The array substrate according to claim 1, characterized in that, The line width of the second fan-out line is smaller than that of the first fan-out line.

3. The array substrate according to claim 2, characterized in that, The gap between two adjacent second fan-out lines in the first line group is the second gap, and the width of the second gap refers to the size of the second gap along the line width direction of the second fan-out line. The difference in linewidth between the first fan-out line and the second fan-out line is greater than half the width of the second gap.

4. The array substrate according to claim 3, characterized in that, The width of the second gap is greater than 0 micrometers and less than or equal to 10 micrometers.

5. The array substrate according to claim 2, characterized in that, The linewidth of the first fan-out line is greater than 0 micrometers and less than or equal to 5 micrometers; and / or, the linewidth of the second fan-out line is greater than 0 micrometers and less than or equal to 3 micrometers.

6. The array substrate according to claim 2, characterized in that, The width of the first gap is less than twice the width of the first fan-out line; the width of the first gap refers to the dimension of the first gap along the line width direction of the first fan-out line.

7. The array substrate according to claim 1, characterized in that, The first line group includes two second fan-out lines.

8. The array substrate according to claim 1, characterized in that, The first line group includes three or more second fan-out lines.

9. The array substrate according to any one of claims 1 to 8, characterized in that, The multiple second fan-out lines include multiple first line groups, which are arranged at intervals. The orthogonal projection of the first fan-out line on the second conductive layer is located between two adjacent first line groups.

10. The array substrate according to any one of claims 1 to 8, characterized in that, The plurality of second fan-out lines also include a second line group, wherein the number of second fan-out lines in the second line group is different from the number of second fan-out lines in the first line group, the orthographic projection of the second line group on the first conductive layer is located within the first gap range, and the first line group and the second line group are located in different first gaps.

11. The array substrate according to claim 10, characterized in that, The second line group includes one second fan-out line.

12. The array substrate according to claim 11, characterized in that, The first gap includes gap one and gap two. The orthographic projection of the first line group onto the first conductive layer is located within the range of gap one, and the orthographic projection of the second line group onto the first conductive layer is located within the range of gap two. The width of gap two is less than or equal to the width of gap one.

13. The array substrate according to claim 10, characterized in that, The first line group and the second line group are arranged alternately, and the orthogonal projection of the first fan-out line on the second conductive layer is located between the first line group and the second line group.

14. The array substrate according to claim 1, characterized in that, The array substrate further includes a substrate, wherein the first conductive layer, the second conductive layer and the insulating layer are stacked on the substrate, and the second conductive layer is closer to the substrate.

15. The array substrate according to claim 1, characterized in that, The array substrate has a display area and a non-display area. The first fan-out line and the second fan-out line are located in the non-display area. The display area is provided with a plurality of transistors. At least some of the gates of the transistors are located in the second conductive layer, and at least some of the source and drain terminals of the transistors are located in the first conductive layer.

16. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 15.

17. The display device according to claim 16, characterized in that, The display device further includes a paper film layer disposed on the surface of the array substrate.

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