RISC-V collaborative protection device and method based on tag bit extension
By introducing tag bit extension and metadata management into the RISC-V processor, the performance and protection capabilities of memory protection in the existing RISC-V architecture are addressed, achieving low-overhead, high-efficiency memory security protection and fine-grained policy adaptability, suitable for multi-core environments.
Patent Information
- Application Number
- CN202511080003.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-04
- Publication Date
- 2025-11-14
AI Technical Summary
Existing memory protection technologies for the RISC-V architecture suffer from high performance overhead, limited protection capabilities, high deployment costs, and difficulty in comprehensively protecting against memory security threats, especially attacks such as buffer overflows, out-of-bounds access, and information leakage.
Employing a RISC-V processor based on tag bit extension, it achieves pointer integrity and information flow tracking by setting tag bits, metadata memory management, metadata caching, and data verification modules. It provides fine-grained security policies and real-time verification, and supports dynamic configuration and cache consistency maintenance in multi-core environments.
It achieves comprehensive memory safety protection with low performance overhead on the RISC-V architecture, preventing buffer overflows, out-of-bounds access and information leakage, reducing deployment costs, and supporting fine-grained security policy adaptability and alias pointer state synchronization in multi-core environments.
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Figure CN120951379A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of processor security architecture design, and in particular to a RISC-V collaborative protection device and method based on tag bit extension. Background Technology
[0002] RISC-V is an open-source instruction set architecture. Unlike traditional commercial instruction set architectures, RISC-V is provided in an open-source manner. Its design is simple, modular, and efficient, making it suitable for a wide range of applications, from microcontrollers to high-performance computing. As RISC-V is deployed in critical infrastructure, its security requirements are also increasing.
[0003] Current data breach threats exhibit a complex mix of characteristics: a broadened attack surface, higher-value targets, and intensified technological confrontation. The widespread deployment of cloud-native architectures and IoT devices, along with complex software supply chains, has significantly weakened the effectiveness of traditional perimeter defense systems. This has shifted the threat model from simple system intrusions to persistent penetration centered on data breaches. Achieving visibility and access control over highly mobile data throughout its entire lifecycle has become a core technological challenge that modern security systems must address.
[0004] Memory safety vulnerabilities are among the most serious security threats facing computer systems today. The vast majority of software security vulnerabilities originate from memory safety issues, including attack patterns such as buffer overflows, out-of-bounds access, dangling pointer dereferences, and double-freeing. These attacks can bypass existing software protection mechanisms, directly manipulate program execution flow, and lead to serious consequences such as data leaks, privilege escalation, and system crashes. Current memory protection technologies generally suffer from the following problems:
[0005] While providing strong security guarantees, existing solutions often introduce significant performance overhead, affecting the feasibility of practical deployment; most existing technologies can only protect against specific types of attacks and lack comprehensive protection against memory security threats and information flow control; many existing hardware security solutions require significant modifications to the existing software stack, including compilers, operating systems, and applications, resulting in extremely high deployment costs.
[0006] Therefore, researching a collaborative protection method for information flow tracing and pointer integrity based on the RISC-V architecture is of great theoretical significance and practical value for improving the overall security of computing systems. Through innovative architecture design and algorithm optimization, a balance between security and performance can be achieved. Summary of the Invention
[0007] To address the shortcomings of existing technologies, this application provides a collaborative protection device for information flow tracking and pointer integrity of RISC-V processors based on tag bit extension.
[0008] This invention is achieved through the following technical solution:
[0009] A RISC-V collaborative protection device based on tag bit extension includes a processor security extension module, which includes a tag architecture module, a metadata memory management module, a metadata cache module, a data verification module, and a security instruction execution module.
[0010] The tag architecture module sets tags for each general-purpose register and memory location in RISC-V, including pointer bits, trust bits, and security level bits, which are used to identify the data type, trust level, and security level, respectively, and stores the tags in metadata memory.
[0011] The metadata memory management module includes metadata memory and metadata base address register. The metadata memory uniformly stores the base address, boundary value and corresponding label of all pointers, while the metadata base address register stores the base address of the metadata memory.
[0012] The metadata caching module includes a metadata lookup table and a metadata index table. The metadata lookup table stores the base address, boundary value, pointer identifier, tag, and valid bit of the active pointer, while the metadata index table stores the index and valid bit of the pointer to the metadata lookup table entry.
[0013] The data verification module is used to obtain data flow information and tags from the processor execution unit in RISC-V, calculate the tag value after data processing according to the preset tag operation rules, track the propagation of trust and the flow of security levels, and generate information flow tracking reports.
[0014] The security instruction execution module obtains pointer information from the metadata cache module by executing security extension instructions. When dereferencing the pointer, it verifies whether the access address is within its boundary range and checks whether the trust bit and security level bit meet the access permission requirements.
[0015] As a further improvement, the pointer bit in the tag architecture module of the present invention includes data of pointer type and data of regular data type; the trust bit includes data source trustworthy and data source untrustworthy; the security level bit supports several security levels, and the higher the value, the higher the security level.
[0016] As a further improvement, the tag operation rules implemented by the data verification module of the present invention include a trust propagation rule and a security level control rule. The trust propagation rule is that untrusted data and any other data will produce an untrusted result, and trusted data and trusted data will produce a trusted result (the result trust bit = data 1 trust bit AND data 1 trust bit; the result is trusted only if both data are trusted, and data cannot be written to a memory location with a lower trust level). The security level control rule is that data cannot flow to a location with a lower security level, and the security level of the data flowing to the operation result is the highest security level among the operands (the result security level = max(data 1 security level, data 2 security level); data cannot flow to a memory location with a lower security level; the target memory security level is determined by the base address pointer).
[0017] As a further improvement, each entry in the metadata lookup table of the metadata caching module described in this invention includes a base address value, a boundary value, a pointer identifier, a label, and a valid flag bit; the metadata index table corresponds one-to-one with the general-purpose register file, and each entry includes an index value pointing to the metadata lookup table entry and a 1-bit valid flag bit.
[0018] As a further improvement, the data verification module of the present invention detects the following violations: untrusted data flowing to a trusted location, data flowing to a location with a lower security level, pointer violation calculations (including two pointers cannot be added; ordinary values cannot be subtracted from pointers; subtracting two pointers will result in an ordinary integer; pointers are prohibited from participating in multiplication and division operations), unauthorized pointer dereferencing operations, and out-of-bounds memory access operations.
[0019] As a further improvement, the metadata caching module of the present invention adopts a tag-aware replacement strategy. When there is no available space to store a new base address boundary entry, it prioritizes replacing the entry with the lowest security level or the lowest trust level, and invalidates all indexes in the metadata index table that point to the replaced entry.
[0020] As a further improvement, the metadata caching module of this invention uses a cache consistency maintenance mechanism to automatically send an invalidation signal to all relevant base address boundary cache entries when a change in tag information in the metadata memory is detected, forcing a reloading of the latest tag and boundary information from the metadata memory, thus ensuring that the tag status of all alias pointers in the system remains consistent.
[0021] As a further improvement, the metadata memory management module of the present invention provides optimized storage management for alias pointer scenarios. For n alias pointers pointing to the same memory region, only one base address boundary and label need to be stored in the metadata memory. Each pointer shares metadata through the same pointer identifier, which significantly reduces storage overhead.
[0022] As a further improvement, the secure instruction execution module of the present invention comprehensively checks pointer integrity when performing memory access, including boundary policy checks to ensure that the access address is within the base address and boundary range, permission checks to ensure that the current context has the permission to access the memory region, trust matching checks to ensure that the data flow meets the trust policy, and security level compatibility checks to ensure that the data flow does not violate security level constraints.
[0023] As a further improvement, the method described in this invention supports dynamic security policy configuration, allowing the trust propagation rules and security level mapping relationship to be adjusted at runtime according to application requirements, and controlling the tag operation behavior through a dedicated configuration register to achieve flexible security policy adaptability.
[0024] As a further improvement, the method described in this invention provides a complete exception handling mechanism. When a tag violation, boundary violation, insufficient permissions, or security level violation is detected, a corresponding security exception will be generated. The exception handling program can obtain detailed violation information, including the violation type, the tag value involved, the memory address, and the instruction information, which facilitates security auditing and attack analysis.
[0025] This invention also provides a RISC-V cooperative protection method based on tag bit extension, comprising the following steps:
[0026] Step 1: Use extended instructions to set labels for each register and memory location, store the base address, boundary value and label of the pointer in metadata memory, and assign a unique pointer ID to the pointer.
[0027] Step 2: When loading a pointer using extended instructions, first check if there is a corresponding pointer ID entry in the metadata cache. If the cache is hit, obtain the base address, boundary value, and tag information; otherwise, retrieve from the metadata memory and update the metadata cache, while verifying the pointer's trust bit and security level bit.
[0028] Step 3: Dynamically calculate the tags of the operation results according to the tag operation rules, record the trust level propagation and security level flow; and continuously track the flow of data between registers to detect operations that violate trust policies and security level constraints.
[0029] Step 4: Save and restore complete tag information using extended instructions in conjunction with the metadata temporary stack.
[0030] Step 5: During memory read and write operations, check pointer integrity, access permissions, trust level matching, and security level compatibility; when the tags or boundary information in the metadata memory are updated, automatically invalidate the relevant entries in the metadata cache and resynchronize them.
[0031] Step 6: Perform boundary policy checks by executing security extension instructions.
[0032] As a further improvement, the instructions described in this invention perform the following verification steps when loading a pointer: checking the pointer bits of the pointer to confirm the pointer type, verifying whether the trust level of the current execution context meets the requirements for accessing the pointer, checking whether the security level of the current execution context is not lower than the security level of the pointer, and verifying the validity of the pointer's base address boundary information.
[0033] Beneficial effects of this invention:
[0034] This invention integrates a 4-bit tag architecture and metadata management mechanism at the RISC-V processor hardware level, achieving collaborative protection of pointer integrity and information flow tracking. Compared to traditional software implementations, hardware-accelerated security checks reduce performance overhead while providing real-time security verification. The 4-bit tag system supports fine-grained data type identification and security policy enforcement, preventing attacks such as buffer overflows, out-of-bounds access, information leakage, and privilege escalation. Storage optimization mechanisms for aliased pointer scenarios significantly reduce memory overhead through shared metadata, and metadata caching employs a tag-aware replacement strategy to improve access efficiency. Dynamic security policy configuration allows runtime adjustment of trust propagation rules and security level mappings, enhancing system adaptability. A cache consistency maintenance mechanism ensures aliased pointer state synchronization in multi-core environments, and a complete exception handling mechanism provides detailed violation information for easy security auditing. This solution has good compatibility with existing software stacks, low deployment costs, and provides a practical hardware security solution for the RISC-V ecosystem. Attached Figure Description
[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0036] Figure 1 This is an extended diagram of the processor architecture used in a RISC-V cooperative protection device and method based on tag bit extension, according to an exemplary embodiment.
[0037] Figure 2 This is a flowchart illustrating a RISC-V cooperative protection device and method based on tag bit extension, according to an exemplary embodiment. Detailed Implementation
[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.
[0039] The invention discloses a RISC-V collaborative protection device and method based on tag bit extension. Figure 1 This is a processor architecture extension diagram used in a RISC-V cooperative protection device and method based on tag bit extension. (Refer to...) Figure 1 The device may include: a tag architecture module, a metadata memory management module, a metadata caching module, a data verification module, and a security instruction execution module.
[0040] The tag architecture module sets a 4-bit tag for each register and memory location, including a 1-bit pointer bit, a 1-bit trust bit, and a 2-bit security level bit, which are used to identify the data type, trust level, and security level, respectively.
[0041] The metadata memory management module includes metadata memory and metadata base address register. The metadata memory uniformly stores the base address, boundary value, and corresponding 4-bit tag information of all pointers, while the metadata base address register stores the base address of the metadata memory. The metadata cache module includes a metadata lookup table and a metadata index table. The metadata lookup table stores the base address, boundary value, pointer identifier, 4-bit tag information, and valid bit of active pointers, while the metadata index table stores the index and valid bit of the entry in the metadata lookup table.
[0042] The data verification module obtains data flow information and 4-bit tag information from the processor execution unit, calculates the tag value after data processing according to the preset tag propagation rules, tracks the propagation of trust and the flow of security levels, and generates an information flow tracking report. The security instruction execution module obtains pointer information and tag information from the metadata cache module by executing security extension instructions, verifies whether the access address is within its boundary range when the pointer is dereferenced, and checks whether the trust bit and security level bit meet the access permission requirements.
[0043] This extended architecture diagram illustrates a microarchitecture design for a RISC-V collaborative protection device and method based on tag bit extension. The entire pipeline adopts a classic three-level structure and integrates comprehensive security protection mechanisms. In the instruction fetch stage, the PC register generates the instruction address and passes the instruction to the decode stage via the If_id inter-level buffer. The decode stage's read module handles instruction parsing, the global branch prediction version provides control flow prediction, and the register file and CSR register manage the architecture state. Each register is appended with 4 bits of tag information (including 1 pointer bit, 1 trust bit, and 2 security level bits) to identify data attributes. The execution stage is the core implementation area of the security mechanism, integrating an arithmetic logic unit, boundary check line code block, data metadata storage, and memory access metadata management unit. These components work together to implement pointer integrity verification and information flow tracking. The execution stage uses the base address and boundary information in the metadata cache for real-time space memory protection through the boundary check module. The data metadata storage unit maintains the propagation and calculation of the 4-bit tag, and the memory access metadata management unit ensures tag consistency and permission verification during memory access. The entire system is connected to the underlying ROM, RAM and dedicated metadata storage via a bus. The metadata storage uniformly manages the base address boundaries and tag information of all pointers, thereby providing comprehensive protection against space attacks, time attacks, information leakage and privilege escalation at the hardware level. At the same time, it achieves fine-grained security policy execution through tag-aware data flow control.
[0044] The data verification module, a core security component of a RISC-V collaborative protection device and method based on tag bit extension, is responsible for dynamically calculating and propagating tag information during instruction execution, enabling fine-grained information flow control and pointer integrity protection. This module receives the instruction code, operand values, and corresponding 4-bit tag information (including pointer bits, trust bits, and 2 security level bits), and performs tag operations according to a predefined security policy. Regarding trust propagation, the data verification module strictly adheres to AND logic; the result is only assigned a trust attribute when both operands are marked as trustworthy, effectively preventing untrusted data from contaminating the trusted computing environment. In terms of security level control, the data verification module adopts a "highest priority" strategy, where the result inherits the highest security level from the operands, ensuring that sensitive information is not downgraded due to the operation. For pointer arithmetic operations, the data verification module implements a strict type checking mechanism: adding integers to pointers to produce pointer results and subtracting pointers to produce integer results are allowed, but pointers are prohibited from participating in multiplication, division, or other operations that may violate address semantics. For memory access instructions, the data verification module mandates that base operands must be marked as pointer types. Simultaneously, it checks the security compliance of data flow during storage operations, prohibiting high-security-level data from flowing to low-security-level locations and prohibiting untrusted data from being written to trusted locations. This module supports dynamic switching of security checks via the `safety_check_en_i` signal, allowing selective disabling of some security constraints during debugging or in specific application scenarios, enhancing system flexibility. Furthermore, the `illegal_op_o` output flag provides real-time feedback on violations, offering precise event triggering information for subsequent anomaly handling and security auditing.
[0045] This application provides an embodiment of a RISC-V collaborative protection device and method based on tag bit extension.
[0046] Figure 2 This is a flowchart illustrating a RISC-V cooperative protection device and method based on tag bit extension, according to an exemplary embodiment. Figure 1 As shown, this method, when applied to a terminal, may include the following steps:
[0047] Step 1: Initialization of the 4-bit tag architecture and metadata storage management. Extended sptag, setrust, and setsl instructions are used to set a 4-bit tag system for each register and memory location. The pointer bit uses 1-bit encoding (1 indicates the data is a pointer type, 0 indicates a regular data type), the trust bit also uses 1-bit encoding (1 indicates the data source is trustworthy, 0 indicates the data source is untrustworthy), and the security level bit uses 2-bit encoding to support four security levels, with higher values indicating higher security levels. The wrapaite memory instruction is used to uniformly store the pointer's base address, boundary values, and tag information in metadata memory, assigning a unique pointer identifier to each pointer. For alias pointer scenarios, the system provides an optimized storage management mechanism. For n alias pointers pointing to the same memory region, only one copy of the base address, boundary values, and 4-bit tag information needs to be stored in metadata memory. Each pointer shares metadata through the same pointer identifier, significantly reducing storage overhead and improving memory utilization efficiency.
[0048] Step 2: Metadata Cache Management and Pointer Load Verification. When loading a pointer using the extended secld instruction, the system first checks if a corresponding pointer identifier entry exists in the metadata cache. Each entry in the metadata lookup table contains a 32-bit base address value, a 32-bit boundary value, a 32-bit pointer identifier, 4-bit tag information, and a 1-bit valid flag. The metadata index table corresponds one-to-one with the general-purpose register file, and each entry contains an index value pointing to the metadata lookup table entry and a 1-bit valid flag. If the cache is hit, the base address, boundary value, and tag information are directly retrieved; if the cache is not hit, the metadata is retrieved from the metadata memory and the metadata cache is updated. During pointer loading, the secld instruction executes a complete verification process: checking the pointer bits to confirm it is a pointer type, verifying whether the trust level of the current execution context meets the requirements for accessing the pointer, checking whether the security level of the current execution context is not lower than the security level of the pointer, and verifying the validity of the pointer's base address boundary information. The metadata cache module adopts a tag-aware replacement strategy. When a new base address boundary entry needs to be stored but there is no available space, entries with lower security levels and lower trust levels are replaced first, and all indexes in the metadata index table pointing to the replaced entry become invalid.
[0049] Step 3: Tag Propagation Rules and Data Calculation Verification. The data verification module dynamically calculates the tag value of the calculation result according to the preset 4-bit tag calculation rules, and records the trust propagation and security level flow process. Trust propagation rules are strictly enforced: untrusted data operating on any other data produces an untrusted result, while trusted data operating on trusted data produces a trusted result. Security level control rules ensure that high-security-level data cannot flow to low-security-level locations, and the security level of the calculation result is the highest security level among the operands. The security instruction execution module performs boundary policy checks by executing security extension instructions to ensure that all data operations comply with the established security policy. The system supports dynamic security policy configuration, allowing runtime adjustments to the trust propagation rules and security level mapping relationship according to application requirements. Tag calculation behavior is controlled through dedicated configuration registers, achieving flexible security policy adaptability and meeting the protection requirements of different security scenarios.
[0050] Step 4: Violation Detection and Anomaly Handling. This step continuously tracks data flow between registers, detects operations that violate trust policies and security level constraints, and prevents sensitive information leakage and privilege escalation attacks. Violations detected by the data verification module include: untrusted data flowing to trusted locations, high-security-level data flowing to low-security-level locations, unauthorized pointer calculations, unauthorized pointer dereferences, and out-of-bounds memory access. The system provides a complete anomaly handling mechanism; when tag violations, boundary violations, insufficient permissions, or security level violations are detected, the system generates corresponding security anomalies. The anomaly handler can obtain detailed violation information, including violation type, involved tag values, memory addresses, and instruction information, facilitating security auditing and attack analysis. The dynamic security policy configuration function enables the system to adjust detection sensitivity and response strategies according to the actual operating environment, improving the targeting and effectiveness of security protection.
[0051] Step 5: Context Switching and Tag Integrity Maintenance. The extended ctxpush / ctxpop instructions, in conjunction with the metadata temporary stack, save and restore complete 4-bit tag information, ensuring the integrity of tag information during function calls. During context switching, the system not only saves the values of general-purpose registers but also the corresponding 4-bit tag information, including the pointer bit, trust bit, and security level bit. The temporary stack is designed to accommodate nested function calls, supporting multi-level context saving and restoration. The restoration operation strictly verifies the consistency of tag information to prevent malicious code from tampering with the tag state through context operations. This method ensures the continuity of security state throughout the program execution flow, avoiding the loss or corruption of security information due to context switching.
[0052] Step Six: Comprehensive Security Check and Memory Access Control. During memory read / write operations, a comprehensive check is performed using preset rules from the data verification module, covering pointer integrity, access permissions, trust level matching, and security level compatibility. The secure instruction execution module implements multi-dimensional security verification during memory access: boundary policy checks ensure the accessed address is within the base address and boundary range; permission checks ensure the current context has permission to access the memory region; trust level matching checks ensure data flow meets trust policies; and security level compatibility checks ensure data flow does not violate security level constraints. This method forms a multi-layered security protection system, ensuring both the security of pointer dereferencing and maintaining the overall information flow security of the system. Any violations detected during the check process will trigger corresponding security response measures, including blocking operation execution, logging security events, and initiating exception handling procedures.
[0053] Step 7: Cache Consistency Maintenance and Alias Pointer Synchronization. When the tag or boundary information in the metadata memory is updated, the cache consistency maintenance mechanism automatically invalidates and resynchronizes the relevant entries in the metadata cache, ensuring that all alias pointers are aware of the change in permission and trust status. When a change in tag information in the metadata memory is detected, the system automatically sends an invalidation signal to all relevant base address boundary cache entries, forcing a reloading of the latest tag and boundary information from the metadata memory, ensuring that the tag status of all alias pointers in the system remains consistent. This invention solves the cache consistency problem in a multi-processor environment and prevents security vulnerabilities caused by cache inconsistency. The synchronization operation adopts an optimized batch update strategy to reduce the impact of frequent synchronization on system performance, while ensuring the timeliness and accuracy of security status updates.
[0054] To demonstrate the effectiveness of the proposed RISC-V collaborative protection device and method based on tag bit extension, experimental verification was conducted: An extended RISC-V RV32IM core, integrating a 4-bit tag architecture, was deployed on a Xilinx Zynq-7020 FPGA platform. The protection capability was verified by constructing typical memory security vulnerability scenarios. In the pointer boundary check experiment, normal array access operations passed boundary verification smoothly, while out-of-bounds access triggered a boundary out-of-bounds exception within one clock cycle and prevented write operations. The dangling pointer detection test showed that pointer dereferencing after a free() operation was immediately detected as an illegal access. The information flow tracing verification experiment used the setrust and setsl instructions to set data sources with different trust levels and security levels. This verified the propagation rules of maintaining trust attributes in operations between trusted data, preventing untrusted data from polluting all operation results, and the control mechanism that security level operations follow a "high-level" strategy and prohibit flow to lower-level locations. The collaborative protection mechanism test uses the sptag instruction to mark pointer types, verifying that forced dereferencing of non-pointer data and pointer participation in multiplication and division operations are correctly identified as type violations. Multi-dimensional security checks simultaneously verify the composite constraints of four attributes: boundary, pointer, trust, and level. Experimental results show that this scheme can detect and prevent buffer overflows, dangling pointers, information leakage, and privilege escalation attacks, verifying the effectiveness and engineering feasibility of the hardware security extension.
Claims
1. A RISC-V cooperative protection device based on tag bit extension, characterized in that, Includes the following modules; The tag architecture module sets tags for each general-purpose register and memory location in RISC-V and stores the tags in metadata memory; Metadata memory management module, including metadata memory and metadata base address register; Metadata caching module, including metadata lookup table and metadata index table; The data verification module is used to obtain data flow information and tags from the processor execution unit in RISC-V, calculate the tag value after data operation according to the tag operation rules, and generate an information flow tracking report. The security instruction execution module obtains pointer information from the metadata cache module by executing security extension instructions. When dereferencing the pointer, it verifies whether the access address is within its boundary range and checks whether the trust bit and security level bit meet the access permission requirements.
2. The RISC-V cooperative protection device based on tag bit extension according to claim 1, characterized in that, The tag architecture module sets tags to include pointer bits, trust bits, and security level bits, which identify data type, trust level, and security level. Pointer bits include data that is pointer type and data that is regular data type; The trust bit indicates whether the data source is trustworthy or not; the security level bit supports several security levels, with higher values indicating higher security levels.
3. The RISC-V cooperative protection device based on tag bit extension according to claim 1, characterized in that, In the metadata memory management module, the metadata memory uniformly stores the base address, boundary value and corresponding label of all pointers, and the metadata base address register stores the base address of the metadata memory; In the metadata caching module, the metadata lookup table stores pointer information, including the base address, boundary value, pointer identifier, tag, and valid bits of the active pointer; The metadata index table stores the index and valid bits that point to entries in the metadata lookup table.
4. The RISC-V cooperative protection device based on tag bit extension according to claim 1, characterized in that, The tag operation rules implemented by the data verification module include trust propagation rules and security level control rules. The trust propagation rules stipulate that untrusted data will produce an untrusted result when operated with any other data, and trusted data will produce a trusted result when operated with trusted data. The security level control rules stipulate that data cannot flow to a location with a lower security level than itself, and the security level of the data flow to the operation result is the highest security level among the operands.
5. The RISC-V cooperative protection device based on tag bit extension according to claim 3, characterized in that, The metadata caching module adopts a tag-aware replacement strategy. When there is no available space to store a new base address boundary entry, it prioritizes replacing the entry with the lowest security level or the lowest trust level, and invalidates all indexes in the metadata index table that point to the replaced entry.
6. The RISC-V cooperative protection device based on tag bit extension according to claim 5, characterized in that, The metadata caching module uses a cache consistency maintenance mechanism to automatically send an invalidation signal to all relevant base address boundary cache entries when a change in tag information in the metadata memory is detected. This forces a reloading of the latest tag and boundary information from the metadata memory, ensuring that the tag status of all alias pointers remains consistent.
7. The RISC-V cooperative protection device based on tag bit extension according to claim 3, characterized in that, The metadata memory management module provides optimized storage management for alias pointer scenarios. For n alias pointers pointing to the same memory region, only one copy of the base address boundary and label is stored in the metadata memory, and each pointer shares the metadata through the same pointer identifier.
8. The RISC-V cooperative protection device based on tag bit extension according to claim 1, characterized in that, The secure instruction execution module performs a comprehensive check of pointer integrity when performing memory access, including boundary policy checks to ensure that the accessed address is within the base address and boundary range, permission checks to ensure that the current context has the permission to access the memory region, trust matching checks to ensure that the data flow meets the trust policy, and security level compatibility checks to ensure that the data flow does not violate security level constraints.
9. The RISC-V cooperative protection device based on tag bit extension according to claim 8, characterized in that, The security instruction execution module also supports dynamic security policy configuration, allowing the trust propagation rules and security level mapping relationship to be adjusted at runtime according to application requirements, and controlling the tag operation behavior through a dedicated configuration register.
10. The RISC-V cooperative protection device based on tag bit extension according to claim 9, characterized in that, The security instruction execution module also provides an exception handling mechanism. When a tag violation, boundary overrun, insufficient permissions, or security level violation is detected, a corresponding security exception is generated. The obtained violation information includes the violation type, the tag value involved, the memory address, and the instruction information.
11. A RISC-V cooperative protection method based on tag bit extension, used to implement the RISC-V cooperative protection device shown in any one of claims 1 to 10, characterized in that, Includes the following steps: Step 1: Use extended instructions to set labels for each register and memory location, store the base address, boundary value and label of the pointer in metadata memory, and assign a unique pointer ID to the pointer; Step 2: When loading a pointer using extended instructions, first check if there is a corresponding pointer ID entry in the metadata cache. If the cache is hit, obtain the base address, boundary value, and tag information; otherwise, retrieve from the metadata memory and update the metadata cache, while verifying the pointer's trust bit and security level bit. Step 3: Dynamically calculate the tags of the operation results according to the tag operation rules, record the trust level propagation and security level flow; and continuously track the flow of data between registers to detect operations that violate trust policies and security level constraints; Step 4: Save and restore complete tag information using extended instructions in conjunction with a metadata temporary storage stack; Step 5: During memory read / write operations, check pointer integrity, access permissions, trust level matching, and security level compatibility. When the tags or boundary information in the metadata memory are updated, the relevant entries in the metadata cache are automatically invalidated and resynchronized. Step 6: Perform boundary policy checks by executing security extension instructions.