Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes: first pixels arranged in rows and odd columns; and second pixels arranged in the row and even columns. Each of the first pixel and the second pixel includes: a light emitting diode; a first transistor configured to output a current corresponding to the data signal; a second transistor transmitting a data signal to the first transistor; and a distribution transistor connected in series between the second transistor and a data line configured to supply a data signal. The distribution transistors of the first pixel and the distribution transistors of the second pixel are sequentially activated when the second transistor of the first pixel and the second transistor of the second pixel are simultaneously activated.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0062766, filed on May 13, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display device and pixels included in the display device. Background Technology

[0004] Display devices include multiple gate lines, multiple data lines, and multiple pixels connected to them. To apply data signals to each of the multiple data lines, the data driving circuitry must provide multiple output lines, the number of which corresponds to the number of data lines. This necessitates the use of multiple integrated circuits, leading to increased manufacturing costs. Summary of the Invention

[0005] One or more embodiments include a display device configured to reduce the number of output lines of a data driving circuit and a method of operating the display device. However, these are examples and do not limit the scope of this disclosure.

[0006] Other aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0007] According to one or more embodiments, a display device includes: a first pixel arranged in an odd-numbered column; and a second pixel arranged in an even-numbered column and in the same row as the first pixel, wherein each of the first pixel and the second pixel includes: a light-emitting diode; a first transistor configured to output a current corresponding to a data signal; a second transistor for transmitting the data signal to the first transistor; and a distribution transistor connected in series between the second transistor and a data line configured to supply the data signal, wherein the distribution transistor of the first pixel and the distribution transistor of the second pixel are sequentially activated when the second transistor of the first pixel and the second transistor of the second pixel are activated simultaneously.

[0008] The display device may further include: a first data line connected to a first pixel; a second data line connected to a second pixel; an output line connected to the first data line and the second data line; and a driving circuit connected to the output line and configured to supply data signals through the output line.

[0009] Each of the first pixel and the second pixel may further include: a third transistor connected to the gate of the first transistor and a first terminal of the first transistor; a fourth transistor connected to the gate of the first transistor and a first initialization voltage line; a fifth transistor connected to a driving voltage line and a first terminal of the first transistor; a sixth transistor connected to a second terminal of the first transistor and a light-emitting diode; a seventh transistor connected to the light-emitting diode and a second initialization voltage line; and a capacitor connected to the gate of the first transistor and the light-emitting diode.

[0010] The first transistor of each of the first pixel and the second pixel may be connected to a light-emitting diode, and the first transistor may further include a back gate facing the gate of the first transistor.

[0011] The display device may further include: a first gate line, a second transistor and a third transistor configured to supply a first gate signal to a first pixel and to a second pixel; a second gate line configured to supply a second gate signal to a fourth transistor of the first pixel and to a fourth transistor of the second pixel; a third gate line configured to supply a third gate signal to a fifth transistor and a sixth transistor of the first pixel and to a fifth transistor and a sixth transistor of the second pixel; and a fourth gate line configured to supply a fourth gate signal to a seventh transistor of the first pixel and to a seventh transistor of the second pixel.

[0012] The conductivity type of the allocation transistor for the first pixel can be the same as that of the allocation transistor for the second pixel.

[0013] The fourth gate signal supplied to the seventh transistor of the second pixel can be delayed from the fourth gate signal supplied to the seventh transistor of the first pixel. The fourth gate signal supplied to the seventh transistor of the first pixel and the fourth gate signal supplied to the allocation transistor of the first pixel can have the same timing as each other.

[0014] The first gate signal, which is the voltage level used to activate the second transistor, may include a first sub-period and a second sub-period following the first sub-period. The fourth gate signal, which is the voltage level used to activate the allocation transistor of the first pixel, may overlap with the first sub-period. The fourth gate signal, which is the voltage level used to activate the allocation transistor of the second pixel, may overlap with the second sub-period. The fourth gate signal, which is the voltage level used to activate the allocation transistor of the first pixel, and the fourth gate signal, which is the voltage level used to activate the allocation transistor of the second pixel, may not overlap with each other.

[0015] A first-second gate signal delayed from the second gate signal supplied to the fourth transistor of the first pixel can be supplied to the allocation transistor of the first pixel, and a second-second gate signal delayed from the second gate signal supplied to the fourth transistor of the second pixel can be supplied to the allocation transistor of the second pixel. The second gate signal supplied to the fourth transistor of the first pixel and the second gate signal supplied to the fourth transistor of the second pixel can have the same timing as each other, and the second-second gate signal supplied to the allocation transistor of the second pixel can be delayed from the first-second gate signal supplied to the allocation transistor of the first pixel.

[0016] The first gate signal, which is the voltage level used to activate the second transistor, may include a first sub-period and a second sub-period following the first sub-period. The first-second gate signal, which is the voltage level used to activate the allocation transistor of the first pixel, may overlap with the first sub-period. The second-second gate signal, which is the voltage level used to activate the allocation transistor of the second pixel, may overlap with the second sub-period. The first-second gate signal and the second-second gate signal do not overlap.

[0017] The period during which the fourth gate signal is the voltage level used to activate the seventh transistor can overlap with the period during which the first gate signal is the voltage level used to activate the second transistor.

[0018] The conductivity type of the allocation transistor for the first pixel can be different from the conductivity type of the allocation transistor for the second pixel.

[0019] The first-third gate signal, which is delayed from the third gate signal supplied to the fifth transistor of the first pixel, can be supplied to the allocation transistor of the first pixel and the allocation transistor of the second pixel.

[0020] During the period when the first gate signal is the voltage level used to activate the second transistor, the voltage levels of the first-third gate signals supplied to the allocation transistor of the first pixel and the allocation transistor of the second pixel can be changed.

[0021] The period during which the fourth gate signal is the voltage level used to activate the seventh transistor can overlap with the period during which the first gate signal is the voltage level used to activate the second transistor.

[0022] The conductivity type of the seventh transistor can be different from that of the second transistor.

[0023] According to one or more embodiments, a display device includes: a pixel region including first pixels arranged in an odd-numbered column and second pixels arranged in an even-numbered column and in the same row as the first pixels; and a gate driving circuit configured to output a gate signal to the first pixel and the second pixel. Each of the first pixel and the second pixel may include: a light-emitting diode; a first transistor configured to output a current corresponding to a data signal; a second transistor that transmits the data signal to the first transistor and is configured to receive the first gate signal; and a distribution transistor connected in series between the second transistor and a data line configured to supply a data signal, and configured to receive a second gate signal. The conductivity type of the distribution transistor of the first pixel may be the same as the conductivity type of the distribution transistor of the second pixel. The second gate signal output by the gate driving circuit to the distribution transistor of the second pixel may be delayed from the second gate signal output to the distribution transistor of the first pixel. During a first sub-period in which the second transistors of the first pixel and the second pixel are simultaneously activated in response to a first gate signal output by the gate driving circuit, the allocation transistor of the first pixel may be activated and the allocation transistor of the second pixel may be deactivated, and during a second sub-period in that period, the allocation transistor of the first pixel may be deactivated and the allocation transistor of the second pixel may be activated.

[0024] The display device may further include: a first data line connected to a first pixel; a second data line connected to a second pixel; an output line connected to the first data line and the second data line; and a data driving circuit connected to the output line and configured to supply data signals through the output line.

[0025] According to one or more embodiments, a display device includes: a pixel region including first pixels arranged in odd-numbered columns and second pixels arranged in even-numbered columns and in the same row as the first pixels; and a gate driving circuit configured to output a gate signal to the first pixel and the second pixel. Each of the first pixel and the second pixel may include: a light-emitting diode; a first transistor configured to output a current corresponding to a data signal; a second transistor transmitting the data signal to the first transistor and configured to receive the first gate signal; and a distribution transistor connected in series between the second transistor and a data line configured to supply a data signal and configured to receive a third gate signal. The conductivity type of the distribution transistor of the first pixel may be different from the conductivity type of the distribution transistor of the second pixel. During a period in which the second transistors of the first pixel and the second pixel are simultaneously activated in response to the first gate signal output by the gate driving circuit, the voltage level of the third gate signal output by the gate driving circuit may be changed. In a first sub-period of this period, the distribution transistor of the first pixel may be activated and the distribution transistor of the second pixel may be deactivated, and in a second sub-period of this period, the distribution transistor of the first pixel may be deactivated and the distribution transistor of the second pixel may be activated.

[0026] The display device may further include: a first data line connected to a first pixel; a second data line connected to a second pixel; an output line connected to the first data line and the second data line; and a data driving circuit connected to the output line and configured to supply data signals through the output line.

[0027] According to embodiments of this disclosure, an electronic device including the display device is provided. Attached Figure Description

[0028] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1A and Figure 1B This is a schematic diagram of a display device according to an embodiment;

[0030] Figure 2 This is a schematic diagram of a display device according to an embodiment;

[0031] Figure 3 This is a schematic diagram of the gate driving circuit and the pixel according to an embodiment;

[0032] Figure 4 and Figure 5 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment;

[0033] Figure 6A and Figure 6BThese are schematic diagrams of a switching device and a control signal (part of a pixel) according to an embodiment;

[0034] Figure 7A and Figure 7B These are schematic diagrams of a switching device and a control signal (part of a pixel) according to an embodiment;

[0035] Figure 8 This is a schematic circuit diagram of odd-numbered and even-numbered columns of pixels according to an embodiment;

[0036] Figure 9 It is used to describe Figure 8 Timing diagram of operations on odd-numbered and even-numbered pixel columns;

[0037] Figure 10 This is a schematic circuit diagram of odd-numbered and even-numbered columns of pixels according to an embodiment;

[0038] Figure 11 It is used to describe Figure 10 Timing diagram of operations on odd-numbered and even-numbered pixel columns;

[0039] Figure 12 This is a schematic circuit diagram of odd-numbered and even-numbered pixel columns according to an embodiment; and

[0040] Figure 13 It is used to describe Figure 12 Timing diagram of operations on odd-numbered and even-numbered pixel columns. Detailed Implementation

[0041] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, wherein the same reference numerals denote the same elements throughout. In this respect, the present embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, embodiments are described below only with reference to the figures to illustrate aspects of the present description.

[0042] As used herein, the word “or” means logical “or”, such that the expression “A, B, or C” means “A and B and C”, “A and B but no C”, “A and C but no B”, “B and C but no A”, “A but no B and no C”, “B but no A and no C”, and “C but no A and no B”, unless the context otherwise indicates. Throughout the disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0043] While this disclosure may have various modifications and alternative forms, embodiments thereof are illustrated by way of example in the accompanying drawings and will be described in detail herein. The effects and features of this disclosure, as well as methods for achieving these effects and features, will become apparent from the embodiments described in detail below, together with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below and can be implemented in various forms.

[0044] In the embodiments described below, the terms "first," "second," etc., are used to distinguish one element from another, rather than being used in a restrictive sense.

[0045] As used herein, the singular expressions “a” and “the (said)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0046] It will be further understood that the terms “comprising” and “including” (including variations such as “containing”) used herein specify the presence of the stated feature or element, but do not exclude the presence or addition of one or more other features or elements.

[0047] It will be understood that when a layer, region, or element is referred to as being formed "on" another layer, region, or element, it can be formed directly or indirectly on that other layer, region, or element. That is, for example, an intermediary layer, region, or element may exist.

[0048] For ease of illustration, the dimensions of the elements in the accompanying drawings may be exaggerated. For example, the dimensions and thicknesses of the elements in the drawings are represented randomly for ease of illustration, and therefore, this disclosure is not necessarily limited to the illustrations in the drawings.

[0049] In the embodiments described below, when X and Y are referred to as being connected to each other, it can mean that X and Y are physically connected, functionally connected, or electrically connected. Furthermore, when X and Y are referred to as being connected to each other, it can mean that X and Y are directly connected or indirectly connected with another component arranged between them. Here, X and Y can be elements (e.g., devices, components, circuits, lines, electrodes, terminals, films, layers, regions, etc.).

[0050] For example, when X and Y are referred to as being electrically connected to each other, it can indicate either a direct electrical connection between X and Y or an indirect connection between X and Y with another component arranged between them. An indirect connection between X and Y may include at least one device (e.g., a switch, transistor, capacitor, inductor, resistor, diode, etc.) connected between X and Y to allow the electrical connection. Therefore, X and Y are not limited to the predetermined connection relationships shown, such as those indicated in the accompanying drawings or detailed description. Instead, X and Y may include other connection relationships besides those shown in the accompanying drawings or detailed description.

[0051] In the embodiments described below, the terms "on" and "off" used in relation to device states refer to the active state and inactive state of the device, respectively. The terms "on" and "off" used in relation to signals received by the device can refer to signals configured to activate and deactivate the device, respectively. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) can be activated by a low-level voltage, and an N-channel transistor (N-type transistor) can be activated by a high-level voltage. Therefore, it should be understood that the "on" voltage relative to a P-type transistor and an N-type transistor can be opposite voltages (low to high).

[0052] In the embodiments described below, the x, y, and z directions are not limited to directions on the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can refer to different directions that are not perpendicular to each other.

[0053] Figure 1A and Figure 1B This is a schematic diagram of the display device 10 according to an embodiment. Figure 2 This is a schematic diagram of the display device 10 according to an embodiment.

[0054] refer to Figure 1A and Figure 1B The display device 10 may include a display area DA for displaying images and a peripheral area PA surrounding the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0055] In a plan view, the display area DA can be rectangular. According to another embodiment, the display area DA can be polygonal, circular, elliptical, or amorphous, such as a triangle, pentagon, or hexagon. The display area DA can have rounded corners. According to an embodiment, such as... Figure 1A As illustrated, the display device 10 may have a display area DA, wherein the length of the display area DA in the x-direction is greater than the length of the display area DA in the y-direction. According to another embodiment, as... Figure 1B As illustrated, the display device 10 may have a display area DA, which has a shape in which the length of the display area DA in the y direction is greater than the length of the display area DA in the x direction.

[0056] refer to Figure 2 The display device 10 according to the embodiment may include a pixel area 110, a gate driving circuit 130, a data driving circuit 150, and a controller 170. The display device 10 may include a display panel, and the display panel may include a substrate.

[0057] Pixel area 110 can correspond to display area DA of the substrate. Multiple gate lines GL1 to GLn, multiple data lines DL1 to DLm, and multiple pixels PX connected to them can be arranged in pixel area 110. Multiple pixels PX can be arranged in various forms, such as stripe, honeycomb, diamond, mosaic, etc.

[0058] According to an embodiment, when the display device 10 is an organic electroluminescent display device, the pixel PX can be driven by receiving a driving voltage ELVDD and a common voltage ELVSS. The pixel PX may include an organic light-emitting diode as a display element (light-emitting device), and the organic light-emitting diode may be connected to the pixel circuit. The pixel PX may emit, for example, red, green, blue, or white light through the organic light-emitting diode. The pixel PX may be connected to corresponding gate lines among multiple gate lines GL1 to GLn and corresponding data lines among multiple data lines DL1 to DLm.

[0059] A pixel circuit may include a plurality of transistors and at least one capacitor. According to one embodiment, some of the transistors included in the pixel circuit may be P-type transistors, and the others may be N-type transistors. According to another embodiment, the plurality of transistors included in the pixel circuit may be P-type transistors. According to yet another embodiment, the plurality of transistors included in the pixel circuit may be N-type transistors. P-type transistors may include silicon transistors. N-type transistors may include oxide transistors.

[0060] Silicon transistors may include low-temperature polycrystalline silicon (LTPS) thin-film transistors, which include a semiconductor layer comprising amorphous silicon, polycrystalline silicon, etc. Oxide transistors may include low-temperature polycrystalline oxide (LTPO) thin-film transistors, which include a semiconductor layer comprising an oxide. However, these are merely examples, and N-type transistors are not limited thereto. For example, the semiconductor layer included in an N-type transistor may include inorganic semiconductors (e.g., amorphous silicon, polycrystalline silicon, etc.) or organic semiconductors.

[0061] Each of the gate lines GL1 to GLn can extend in the x-direction (row direction) and can be connected to pixels PX arranged in the same row (horizontal line). Each of the gate lines GL can be configured to transmit a gate signal to the pixels PX arranged in the same row. Each of the data lines DL1 to DLm can extend in the y-direction (column direction) and can be connected to pixels PX arranged in the same column (vertical line). Each of the data lines DL1 to DLm can be configured to transmit a data signal synchronously with the gate signal to the pixels PX in the same column.

[0062] According to an embodiment, the peripheral region PA may be a non-display area in which no pixels PX are disposed. Within the peripheral region PA of the substrate, various conductive lines configured to transmit electrical signals to be applied to the display region DA, external circuitry electrically connected to the pixel circuitry, or pads to which a printed circuit board or driver integrated circuit (IC) chip is attached may be positioned. For example, a gate drive circuit 130, a data drive circuit 150, and a controller 170 may be provided in the peripheral region PA.

[0063] Gate drive circuit 130 can be connected to multiple gate lines GL1 to GLn, configured to generate gate signals in response to drive control signals GCS from controller 170, and configured to sequentially supply gate signals to gate lines GL1 to GLn. Each of the gate lines GL1 to GLn can be connected to the gate of a transistor included in pixel PX. The gate signal can be a gate control signal configured to control the on and off states of the transistors connected to gate lines GL1 to GLn. The gate signal can be a signal including a gate on-voltage for turning on the transistors and a gate off-voltage for turning off the transistors. As used herein, "on" can be referred to as "activated".

[0064] Figure 2 The illustrated pixel PX is connected to one gate line. However, this is merely an example, and pixel PX can be connected to two or more gate lines, and the gate drive circuit 130 can be configured to supply two or more gate signals with different timings for applying gate on voltages to the corresponding gate lines.

[0065] The data driving circuit 150 can be connected to multiple output lines OL1 to OLm / 2, and these output lines OL1 to OLm / 2 can be connected to multiple data lines DL1 to DLm. Each of the multiple output lines OL1 to OLm / 2 can be connected to two data lines. Because the number of output lines is less than the number of data lines, the number of output lines connected to the data driving circuit 150 can be reduced, which can lead to a reduction in manufacturing costs. The data driving circuit 150 can be configured to supply data signals to the data lines DL1 to DLm via the output lines OL1 to OLm / 2 in response to a drive control signal DCS from the controller 170. The data signals supplied to the data lines DL1 to DLm can be supplied to pixels PX that have gate signals supplied. The data driving circuit 150 can be configured to convert grayscale input image data input from the controller 170 into data signals in the form of voltage or current.

[0066] The controller 170 can be configured to generate drive control signals GCS and DCS based on an externally input synchronization signal, and supply the drive control signals GCS and DCS to the gate drive circuit 130 and the data drive circuit 150. The drive control signal GCS output to the gate drive circuit 130 may include multiple clock signals and a gate start signal. The drive control signal DCS output to the data drive circuit 150 may include multiple clock signals and a data start signal.

[0067] According to an embodiment, during the process of forming transistors including pixel circuits in the display area DA of the substrate, a portion or all of the gate drive circuit 130 can be directly formed in the peripheral area PA of the substrate. The data drive circuit 150 and the controller 170 can be formed as discrete IC chips or single IC chips and can be arranged on a flexible printed circuit board (FPCB) electrically connected to pads arranged on one side of the substrate. According to another embodiment, the data drive circuit 150 and the controller 170 can be directly arranged on the substrate using chip-on-glass (COG) or chip-on-plastic (COP) methods.

[0068] Figure 3 This is a schematic diagram of the gate driving circuit 130 and the pixel PX according to an embodiment. Figure 4 and Figure 5 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0069] According to an embodiment, Figure 4 It can display pixels arranged in odd-numbered columns, and Figure 5 Pixels arranged in even-numbered columns can be shown. According to another embodiment, Figure 4 It can display pixels arranged in even-numbered columns, and Figure 5 Pixels arranged in odd-numbered columns can be displayed. The following describes... Figure 4 An example of pixels PXo arranged in an odd number of columns is shown. Figure 5 An example of a pixel PXe arranged in an even column is shown, and pixels PXo arranged in an odd column and pixels PXe arranged in an even column are generally referred to as pixels PX.

[0070] refer to Figure 3 Pixel PX can be connected to the first gate line GWL, the second gate line GIL, the third gate line EML, the fourth gate line GBL, the control line CSL, and the data line DL.

[0071] The gate drive circuit 130 may include a first drive circuit 131, a second drive circuit 133, a third drive circuit 135, and a fourth drive circuit 137.

[0072] A first drive circuit 131 can be connected to multiple first gate lines GWL and can be configured to sequentially supply first gate signals GW to the first gate lines GWL. A second drive circuit 133 can be connected to multiple second gate lines GIL and can be configured to sequentially supply second gate signals GI to the second gate lines GIL. A third drive circuit 135 can be connected to multiple third gate lines EML and can be configured to sequentially supply third gate signals EM to the third gate lines EML. A fourth drive circuit 137 can be connected to multiple fourth gate lines GBL and can be configured to sequentially supply fourth gate signals GB to the fourth gate lines GBL.

[0073] According to an embodiment, the control line CSL can be one of the first gate line GWL, the second gate line GIL, the third gate line EML, and the fourth gate line GBL. The control signal supplied to the control line CSL can be a gate signal output by one of the first drive circuit 131, the second drive circuit 133, the third drive circuit 135, and the fourth drive circuit 137. One of the first drive circuit 131, the second drive circuit 133, the third drive circuit 135, and the fourth drive circuit 137 can be connected to multiple control lines CSL and can be configured to supply the gate signal as a control signal to the control line CSL.

[0074] refer to Figure 3 , Figure 4 and Figure 5 The control signals may include a first control signal CSA supplied to the control line CSL of pixels PXo arranged in odd columns (hereinafter referred to as "odd column pixels") and a second control signal CSB supplied to the control line CSL of pixels PXe arranged in even columns (hereinafter referred to as "even column pixels"). The first control signal CSA and the second control signal CSB may be supplied to the odd column pixels PXo and the even column pixels PXe respectively, and may not overlap with each other.

[0075] According to an embodiment, the control lines CSL for odd-numbered columns of pixels PXo and even-numbered columns of pixels PXe can be provided separately. The first control signal CSA and the second control signal CSB can be gate signals with a time difference and a delay, supplied from the same driving circuit.

[0076] According to an embodiment, the control line CSL for odd-numbered column pixels PXo and the control line CSL for even-numbered column pixels PXe can be provided integrally with each other, and the odd-numbered column pixels PXo and the even-numbered column pixels PXe can be connected to a single control line CSL. The first control signal CSA and the second control signal CSB can be a single signal, and can be a gate signal supplied from the driving circuit to the control line CSL.

[0077] refer to Figure 4 and Figure 5 According to an embodiment, a pixel PX may include a pixel circuit PC and a light-emitting device connected to the pixel circuit PC. According to an embodiment, the light-emitting device may include an organic light-emitting diode (OLED).

[0078] The pixel circuit PC may include first transistors T1 through T7, capacitor Cst, and switching device SD. First transistor T1 may be a drive transistor configured to output a drive current corresponding to a data signal, and second transistors T2 through T7 may be switching transistors configured to transmit signals. Depending on the voltage at the first and second terminals, the first terminal (first electrode) and second terminal (second electrode) of each of the first transistors T1 through T7 and the switching device SD may be either a source or a drain. For example, depending on the voltage at the first and second terminals, the first terminal may be a drain and the second terminal may be a source, or vice versa. The node to which the gate of the first transistor T1 is connected may be defined as a first node N1, the node to which the first terminal of the first transistor T1 is connected may be defined as a second node N2, and the node to which the second terminal of the first transistor T1 is connected may be defined as a third node N3.

[0079] The first transistor T1 to the fourth transistor T4 and the seventh transistor T7 can be N-type transistors, and the fifth transistor T5 and the sixth transistor T6 can be P-type transistors.

[0080] A first transistor T1 can be connected between the driving voltage line PL and the organic light-emitting diode (OLED). The first transistor T1 can be connected to a fifth transistor T5 and a sixth transistor T6. The first transistor T1 may include a gate (or a first gate) connected to a first node N1, a first terminal connected to a second node N2, and a second terminal connected to a third node N3. The first terminal of the first transistor T1 can be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal of the first transistor T1 can be connected to the pixel electrode of the OLED via the sixth transistor T6.

[0081] The first transistor T1 may further include a back gate (or a second gate) connected to the pixel electrode of the organic light-emitting diode (OLED). The gate and the back gate may be arranged in different layers to face each other. For example, the gate and the back gate of the first transistor T1 may overlap with the channel region with a semiconductor layer between them, and may be arranged to face each other.

[0082] A second transistor T2 can be connected between the data line DL and the third node N3. The second transistor T2 can be connected to the switching device SD and the third node N3. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the switching device SD, and a second terminal connected to the third node N3. The second transistor T2 can be turned on in response to a first gate signal GW supplied from the first gate line GWL, and can be configured to electrically connect the data line DL to the third node N3 when the switching device SD is turned on, and to transmit the data signal DATA transmitted through the data line DL to the third node N3.

[0083] As used in this article, “conduction” can be referred to as “activation” and “deactivation” can be referred to as “inactivation”.

[0084] A third transistor T3 may be connected to the gate and a first terminal of the first transistor T1. The third transistor T3 may include a gate connected to a first gate line GWL, a first terminal connected to a second node N2, and a second terminal connected to the first node N1. The third transistor T3 may be turned on in response to a first gate signal GW supplied from the first gate line GWL, and may be configured to diode-connect the first transistor T1 and compensate for the threshold voltage of the first transistor T1.

[0085] A fourth transistor T4 may be connected to the gate of the first transistor T1 and the first initialization voltage line VIL1. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the first node N1, and a second terminal connected to the first initialization voltage line VIL1. The fourth transistor T4 may be turned on in response to a second gate signal GI supplied from the second gate line GIL, and may be configured to transmit an initialization voltage Vint transmitted through the first initialization voltage line VIL1 to the first node N1.

[0086] The fifth transistor T5 can be connected to the drive voltage line PL and the first terminal of the first transistor T1. The fifth transistor T5 may include a gate connected to the third gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the second node N2. The fifth transistor T5 can be turned on or off in response to the third gate signal EM supplied from the third gate line EML.

[0087] The sixth transistor T6 can be connected to the first transistor T1 and the organic light-emitting diode (OLED). The sixth transistor T6 can also be connected to the third node N3 and the OLED. The sixth transistor T6 may include a gate connected to the third gate line EML, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the OLED. The sixth transistor T6 can be turned on or off in response to a third gate signal EM supplied from the third gate line EML.

[0088] The seventh transistor T7 can be connected to the organic light-emitting diode (OLED) and the second initialization voltage line VIL2. The seventh transistor T7 may include a gate connected to the fourth gate line GBL, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the OLED, and a second terminal connected to the second initialization voltage line VIL2. The seventh transistor T7 can be turned on in response to the fourth gate signal GB received through the fourth gate line GBL, and can be configured to transmit the second initialization voltage Vaint to the pixel electrode of the OLED to initialize the pixel electrode of the OLED.

[0089] The capacitor Cst can be connected to the gate of the first transistor T1 and the organic light-emitting diode (OLED). The first electrode of the capacitor Cst can be connected to the first node N1, and the second electrode can be connected to the pixel electrode of the OLED. The capacitor Cst can be a storage capacitor and can be configured to store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal DATA.

[0090] An organic light-emitting diode (OLED) can be connected to a first transistor T1 via a sixth transistor T6. The OLED may include a pixel electrode (anode) connected to the second terminal of the sixth transistor T6 and the second electrode of a capacitor Cst, and a counter electrode (cathode) facing the pixel electrode, which is capable of receiving a common voltage ELVSS. The counter electrode may be a common electrode shared by multiple pixels PX. The driving current output from the first transistor T1 can flow through the OLED via the conducting fifth transistor T5 and the conducting sixth transistor T6, and the OLED can emit light with a brightness corresponding to the magnitude of the driving current.

[0091] A switching device SD can be connected to a data line DL and a second transistor T2. The switching device SD may include a switching transistor with a gate connected to a control line CSL. The switching device SD of odd-numbered column pixels PXo can be turned on in response to a first control signal CSA and can be configured to transmit the data signal DATA transmitted via the data line DL to a first terminal of the second transistor T2. The switching device SD of even-numbered column pixels PXe can be turned on in response to a second control signal CSB and can be configured to transmit the data signal DATA transmitted via the data line DL to a first terminal of the second transistor T2.

[0092] Figure 6A and Figure 6B These are schematic diagrams of a switching device and a control signal (which are part of a pixel) according to an embodiment. Figure 7A and Figure 7B These are schematic diagrams of a switching device and a control signal (which are part of a pixel) according to an embodiment.

[0093] The switching device SD can be connected to the data line DL and the second transistor T2, and can be implemented as an N-type transistor or a P-type transistor (hereinafter referred to as "distribution transistor TD").

[0094] According to an embodiment, the allocation transistors TD for odd-numbered column pixels PXo and even-numbered column pixels PXe can be transistors of the same conductivity type (e.g., impurity conductivity type). For example, as... Figure 6A As illustrated, each of the allocation transistors TD for odd-numbered pixel PXo and even-numbered pixel PXe can be an N-type transistor. Figure 6B As illustrated in the figure, when the first gate signal GW is being supplied to both odd-numbered column pixels PXo and even-numbered column pixels PXe simultaneously, the first control signal CSA and the second control signal CSB can be supplied to the odd-numbered column pixels PXo and even-numbered column pixels PXe sequentially, respectively.

[0095] In the following text, for ease of explanation, supplying any signal may mean supplying a gate turn-on voltage (e.g., a low-level voltage supplied to a P-type transistor or a high-level voltage supplied to an N-type transistor), and not supplying any signal may mean supplying a gate turn-off voltage (e.g., a high-level voltage supplied to a P-type transistor or a low-level voltage supplied to an N-type transistor).

[0096] During the first sub-segment P1 of segment Pon, where the second transistor T2 of odd-numbered pixel PXo and even-numbered pixel PXe is turned on in response to the first gate signal GW, the allocation transistor TD of odd-numbered pixel PXo can be turned on in response to the first control signal CSA, and the allocation transistor TD of even-numbered pixel PXe can be turned off in response to the second control signal CSB. During the second sub-segment P2 following the first sub-segment P1, the allocation transistor TD of even-numbered pixel PXe can be turned on in response to the second control signal CSB, and the allocation transistor TD of odd-numbered pixel PXo can be turned off in response to the first control signal CSA.

[0097] As used in this document, "segment" may be referred to as "time period", and "first sub-segment of segment" and "second sub-segment of segment" may be referred to as "first sub-time period of time" and "second sub-time period of time", respectively.

[0098] Each of the segments where the first control signal CSA is the gate on-voltage and the second control signal CSB is the gate on-voltage can overlap at least with the segment Pon where the first gate signal GW is the gate on-voltage. The segments where the first control signal CSA is the gate on-voltage and the second control signal CSB is the gate on-voltage can not overlap with each other. The duration (or width) W1 of maintaining the gate on-voltage of the first control signal CSA during this period can not overlap with the second sub-segment P2 and can be greater than the length of the first sub-segment P1. The width W2 of the gate on-voltage of the second control signal CSB can not overlap with the first sub-segment P1 and can be greater than the length of the second sub-segment P2. The width W1 of the gate on-voltage of the first control signal CSA and the width W2 of the gate on-voltage of the second control signal CSB can be the same as each other.

[0099] According to an embodiment, the allocation transistors TD for odd-numbered column pixels PXo and even-numbered column pixels PXe can be transistors of different conductivity types. For example, such as Figure 7A As illustrated in the diagram, the allocation transistor TD for odd-numbered pixel columns PXo can be a P-type transistor, and the allocation transistor TD for even-numbered pixel columns PXe can be an N-type transistor. Figure 7BAs illustrated in the figure, when the first gate signal GW is being supplied to both odd-column pixels PXo and even-column pixels PXe simultaneously, the control signal CS can be supplied to both odd-column pixels PXo and even-column pixels PXe simultaneously.

[0100] During segment Pon, where the second transistor T2 of odd-column pixels PXo and even-column pixels PXe is turned on in response to the first gate signal GW, the voltage level of the control signal CS can be changed. During the first sub-segment P1, in response to the low-level control signal CS, the allocation transistor TD of odd-column pixels PXo can be turned on and the allocation transistor TD of even-column pixels PXe can be turned off. The low-level control signal CS can correspond to the gate turn-on voltage of the P-type transistor and the gate turn-off voltage of the N-type transistor. Next, during the second sub-segment P2, in response to the high-level control signal CS, the allocation transistor TD of odd-column pixels PXo can be turned off and the allocation transistor TD of even-column pixels PXe can be turned on. The high-level control signal CS can correspond to the gate turn-off voltage of the P-type transistor and the gate turn-on voltage of the N-type transistor.

[0101] Based on the time point tt where the control signal CS changes from a low voltage to a high voltage, each of the segments where the control signal CS is a low voltage and the segments where the control signal CS is a high voltage can overlap at least with the segment Pon where the first gate signal GW is a gate on voltage. The width W of the high voltage of the control signal CS can be greater than the length of the second sub-segment P2. The lengths of the segments where the high voltage of the first gate signal GW and the low voltage of the control signal CS overlap and the lengths of the segments where the high voltage of the first gate signal GW and the high voltage of the control signal CS overlap can be the same.

[0102] In the following text, the time-division writing of data signals to pixels will be described using a pair of adjacent odd-column pixels PXo and even-column pixels PXe in the k-th row (pixel row) as an example.

[0103] The (k-1)th gate signal can be the gate signal output by the gate drive circuit 130 in the (k-1)th iteration, the kth gate signal can be the gate signal output by the gate drive circuit 130 in the kth iteration, the (k+1)th gate signal can be the gate signal output by the gate drive circuit 130 in the (k+1)th iteration, and the (k+2)th gate signal can be the gate signal output by the gate drive circuit 130 in the (k+2)th iteration.

[0104] The (k-1)th gate signal (previous gate signal) can be output from the gate lines in the (k-1)th row, the kth gate signal (current gate signal) can be output from the gate lines in the kth row, the (k+1)th gate signal (next gate signal) can be output from the gate lines in the (k+1)th row, and the (k+2)th gate signal (next gate signal) can be output from the gate lines in the (k+2)th row. According to an embodiment, the gate lines connected to the gate lines in the (k-1)th row (previous row), or connected to the gate lines in the (k+1)th row (next row) or the (k+2)th row (row after the next row), can be further arranged in the kth row (current row).

[0105] Figure 8 This is a schematic circuit diagram of odd-numbered and even-numbered pixel columns according to an embodiment. Figure 9 It is used to describe Figure 8 Timing diagram of operations on odd-numbered and even-numbered pixel columns.

[0106] According to an embodiment, the allocation transistor TD for odd-numbered pixel PXo and the allocation transistor TD for even-numbered pixel PXe can be N-type transistors. The control line CSL connected to the allocation transistor TD can be the fourth gate line GBL, and the control signal CS can be the fourth gate signal GB output by the fourth drive circuit 137.

[0107] refer to Figure 8 The output line OL can be connected to a first data line DLo and a second data line DLe. The first data line DLo is connected to the odd-numbered column pixels PXo, and the second data line DLe is connected to the even-numbered column pixels PXe. The output line OL can be configured to sequentially supply the first data signal DATA1 to the first data line DLo and sequentially supply the second data signal DATA2 to the second data line DLe.

[0108] refer to Figure 9 The driving periods for odd-numbered pixel PXo and even-numbered pixel PXe may include a first initialization segment INT1, a second initialization segment INT2, a data write and compensation segment DC, and a transmission segment EP. The second initialization segment INT2 may include a second-first initialization segment INT21 and a second-second initialization segment INT22. The data write and compensation segment DC may include a first data write segment DW1 and a second data write segment DW2. The first data write segment DW1 and the second data write segment DW2 can be collectively referred to as the data write segment DW.

[0109] As used in this document, “initialization segment”, “data writing and compensation segment”, “transmission segment” and “data writing segment” can be referred to as “initialization period”, “data writing and compensation period”, “transmission period” and “data writing period”, respectively.

[0110] The second transistor T2 and the third transistor T3 of the odd-column pixel PXo and the even-column pixel PXe can be configured to simultaneously receive the k-th first gate signal GW[k] from the first gate line GWL. The k-th first gate signal GW[k] can be a high-level voltage (hereinafter referred to as the "first level voltage") in the data writing and compensation segment DC, and a low-level voltage (hereinafter referred to as the "second level voltage") in the remaining segment. The period (duration or width) during which the k-th first gate signal GW[k] maintains the first level voltage can be approximately the first horizontal period 1H. When the k-th first gate signal GW[k] is the first level voltage, the second transistor T2 and the third transistor T3 can be turned on, and when the k-th first gate signal GW[k] is the second level voltage, the second transistor T2 and the third transistor T3 can be turned off.

[0111] The fourth transistor T4 of both odd-column pixels PXo and even-column pixels PXe can be configured to simultaneously receive the k-th second gate signal GI[k] from the second gate line GIL. The k-th second gate signal GI[k] can be a first-level voltage in the first initialization segment INT1 and a second-level voltage in the remaining segments. When the k-th second gate signal GI[k] is a first-level voltage, the fourth transistor T4 can be turned on, and when the k-th second gate signal GI[k] is a second-level voltage, the fourth transistor T4 can be turned off.

[0112] The fifth transistor T5 and the sixth transistor T6 of the odd-column pixel PXo and the even-column pixel PXe can be configured to simultaneously receive the k-th third gate signal EM[k] from the third gate line EML. The k-th third gate signal EM[k] can be a second-level voltage in the transmit section EP and a first-level voltage in the remaining sections. When the k-th third gate signal EM[k] is a second-level voltage, the fifth transistor T5 and the sixth transistor T6 can be turned on, and when the k-th third gate signal EM[k] is a first-level voltage, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0113] The fourth gate line GBL may include the 4-1 gate line GBL1 and the 4-2 gate line GBL2. According to an embodiment, the 4-2 gate line GBL2 in the k-th row may be connected to the 4-1 gate line GBL1 in the k+1-th row.

[0114] The seventh transistor T7 and the allocation transistor TD of the odd-numbered column pixels PXo can be configured to simultaneously receive the k-th fourth gate signal GB[k] from the 4-1 gate line GBL1. The k-th fourth gate signal GB[k] can be a first-level voltage in the 2-1 initialization segment INT21 and a second-level voltage in the remaining segments. When the k-th fourth gate signal GB[k] is a first-level voltage, the seventh transistor T7 and the allocation transistor TD can be turned on, and when the k-th fourth gate signal GB[k] is a second-level voltage, the seventh transistor T7 and the allocation transistor TD can be turned off.

[0115] The seventh transistor T7 and the allocation transistor TD of the even-numbered column pixel PXe can be configured to simultaneously receive the (k+1)th fourth gate signal GB[k+1] from the 4-2 gate line GBL2. The (k+1)th fourth gate signal GB[k+1] can be supplied with a specific time delay DT from the k-th fourth gate signal GB[k]. The (k+1)th fourth gate signal GB[k+1] can be a first level voltage in the 2-2 initialization segment INT22 and a second level voltage in the remaining segments. When the (k+1)th fourth gate signal GB[k+1] is a first level voltage, the seventh transistor T7 and the allocation transistor TD can be turned on, and when the (k+1)th fourth gate signal GB[k+1] is a second level voltage, the seventh transistor T7 and the allocation transistor TD can be turned off.

[0116] The initialization section INT21 and the first data write section DW1 can partially overlap each other, and in the overlapping section, the first level voltage of the k-th first gate signal GW[k] and the first level voltage of the k-th fourth gate signal GB[k] can overlap each other.

[0117] The initialization section INT22 and the second data writing section DW2 can partially overlap each other, and in the overlapping section, the first level voltage of the first gate signal GW[k] and the first level voltage of the (k+1)th gate signal GB[k+1] can overlap each other.

[0118] The first initialization segment INT1 can be the segment in which the gate voltage of the first transistor T1 is initialized. In the first initialization segment INT1, the fourth transistor T4 of each of the odd-column pixels PXo and even-column pixels PXe can be turned on in response to the k-th second gate signal GI[k] of the first level voltage. The gate voltage of the first transistor T1 can be initialized to the first initialization voltage Vint by the turned-on fourth transistor T4.

[0119] The second initialization section INT2 can be the section where the voltage of the pixel electrode of the OLED is initialized. The second-first initialization section INT21 can be the section where the voltage of the pixel electrode of the OLED in the odd-numbered column of pixels PXo is initialized. The second-second initialization section INT22 can be the section where the voltage of the pixel electrode of the OLED in the even-numbered column of pixels PXe is initialized.

[0120] In the initialization section INT21 (2-1), the seventh transistor T7 can be turned on in response to the k-th fourth gate signal GB[k] of the first voltage level. The voltage of the pixel electrode of the organic light-emitting diode (OLED) can be initialized to the second initialization voltage Vaint by the turned-on seventh transistor T7.

[0121] In the initialization section INT22 (2-2), the seventh transistor T7 can be turned on in response to the (k+1)th gate signal GB[k+1] of the first voltage level. The voltage of the pixel electrode of the organic light-emitting diode (OLED) can be initialized to the second initialization voltage Vaint by the turned-on seventh transistor T7.

[0122] The data writing and compensation segment DC can be a segment in which data signals are written to pixels PX and the threshold voltage Vth of the first transistor T1 is compensated. Data signals can be written to odd-numbered column pixels PXo in the first data writing segment DW1, and data signals can be written to even-numbered column pixels PXe in the second data writing segment DW2.

[0123] In the data writing and compensation section DC, the second transistor T2 and the third transistor T3 of each of the odd-column pixels PXo and the even-column pixels PXe can be turned on in response to the k-th first gate signal GW[k] of the first level voltage. The first transistor T1 can be connected to a diode through the turned-on third transistor T3.

[0124] In the first data write segment DW1, the allocation transistor TD of the odd-numbered column pixels PXo can be turned on in response to the kth fourth gate signal GB[k] of the first level voltage. The first data signal DATA1 supplied from the first data line DLo can be transmitted to the third node N3 through the turned-on allocation transistor TD and the second transistor T2. The voltage corresponding to the first data signal DATA1 and the threshold voltage Vth of the first transistor T1 can be stored in the capacitor Cst through the operation of the diode-connected first transistor T1. In the first data write segment DW1, the allocation transistor TD of the even-numbered column pixels PXe can be turned off in response to the (k+1)th fourth gate signal GB[k+1] of the second level voltage.

[0125] In the second data write section DW2, the allocation transistor TD of even-numbered column pixels PXe can be turned on in response to the (k+1)th fourth gate signal GB[k+1] of the first level voltage. The second data signal DATA2 supplied from the second data line DLe can be transmitted to the third node N3 through the turned-on allocation transistor TD and the second transistor T2. The voltage corresponding to the second data signal DATA2 and the threshold voltage Vth of the first transistor T1 can be stored in the capacitor Cst through the operation of the diode-connected first transistor T1. In the second data write section DW2, the allocation transistor TD of odd-numbered column pixels PXo can be turned off in response to the kth fourth gate signal GB[k] of the second level voltage.

[0126] The emission segment EP can be the segment in which the organic light-emitting diode (OLED) emits light. In the emission segment EP, the fifth transistor T5 and the sixth transistor T6 of each of the odd-numbered pixel columns PXo and the even-numbered pixel columns PXe can be turned on in response to the k-th third gate signal EM[k] of the second voltage level. The current path from the driving voltage line PL to the OLED can be formed by the turned-on fifth transistor T5 and sixth transistor T6. The OLED can emit light with a brightness corresponding to the driving current output by the first transistor T1.

[0127] Figure 10 This is a schematic circuit diagram of odd-numbered and even-numbered pixel columns according to an embodiment. Figure 11 It is used to describe Figure 10 Timing diagram of operations on odd-numbered and even-numbered pixel columns.

[0128] According to an embodiment, the allocation transistor TD for odd-numbered pixel PXo and the allocation transistor TD for even-numbered pixel PXe can be N-type transistors. The control line CSL connected to the allocation transistor TD can be the second gate line GIL, and the control signal CS can be the second gate signal GI output by the second driving circuit 133.

[0129] refer to Figure 10 The output line OL can be connected to a first data line DLo and a second data line DLe. The first data line DLo is connected to the odd-numbered column pixels PXo, and the second data line DLe is connected to the even-numbered column pixels PXe. The output line OL can be configured to supply a first data signal DATA1 to the first data line DLo and a second data signal DATA2 to the second data line DLe.

[0130] refer to Figure 11The driving periods for odd-numbered pixel PXo and even-numbered pixel PXe may include a first initialization segment INT1, a second initialization segment INT2, a data write and compensation segment DC, and a transmission segment EP. The data write and compensation segment DC may include a first data write segment DW1 and a second data write segment DW2.

[0131] The second transistor T2 and the third transistor T3 of the odd-column pixel PXo and the even-column pixel PXe can be configured to simultaneously receive the k-th first gate signal GW[k] from the first gate line GWL. The k-th first gate signal GW[k] can be a first level voltage in the data writing and compensation segment DC, and a second level voltage in the remaining segment. The period during which the k-th first gate signal GW[k] maintains the first level voltage can be approximately a first level period 1H. When the k-th first gate signal GW[k] is at the first level voltage, the second transistor T2 and the third transistor T3 can be turned on, and when the k-th first gate signal GW[k] is at the second level voltage, the second transistor T2 and the third transistor T3 can be turned off.

[0132] The second gate line GIL may include gate line 2-1 GIL1, gate line 2-2 GIL2, and gate line 2-3 GIL3. According to an embodiment, gate line 2-2 GIL2 in row k may be connected to gate line 2-1 GIL1 in row k-1. Gate line 2-3 GIL3 in row k may be connected to gate line 2-1 GIL1 in row k+1.

[0133] The fourth transistor T4 of the odd-column pixel PXo and the even-column pixel PXe can be configured to simultaneously receive the (k-1)th second gate signal GI[k-1] from the (2-2)th gate line GIL2. The (k-1)th second gate signal GI[k-1] can be a first-level voltage in the first initialization segment INT1 and a second-level voltage in the remaining segments. When the (k-1)th second gate signal GI[k-1] is a first-level voltage, the fourth transistor T4 can be turned on, and when the (k-1)th second gate signal GI[k-1] is a second-level voltage, the fourth transistor T4 can be turned off.

[0134] The allocation transistor TD of the odd-numbered column pixels PXo can be configured to receive the k-th second gate signal GI[k] from the (2-1)-th gate line GIL1. The k-th second gate signal GI[k] can be supplied with a specific time delay DT from the (k-1)-th second gate signal GI[k-1]. The k-th second gate signal GI[k] can be a first level voltage in segment A, including the first data write segment DW1, and a second level voltage in the remaining segment. When the k-th second gate signal GI[k] is the first level voltage, the allocation transistor TD can be turned on, and when the k-th second gate signal GI[k] is the second level voltage, the allocation transistor TD can be turned off.

[0135] The allocation transistor TD of the even-numbered column pixels PXe can be configured to receive the (k+1)th second gate signal GI[k+1] from the second-third gate line GIL3. The (k+1)th second gate signal GI[k+1] can be supplied with a specific time delay DT from the kth second gate signal GI[k]. The (k+1)th second gate signal GI[k+1] can be a first level voltage in segment B, including the second data write segment DW2, and a second level voltage in the remaining segment. When the (k+1)th second gate signal GI[k+1] is at the first level voltage, the allocation transistor TD can be turned on, and when the (k+1)th second gate signal GI[k+1] is at the second level voltage, the allocation transistor TD can be turned off.

[0136] The fifth transistor T5 and the sixth transistor T6 of the odd-column pixel PXo and the even-column pixel PXe can be configured to simultaneously receive the k-th third gate signal EM[k] from the third gate line EML. The k-th third gate signal EM[k] can be a second-level voltage in the transmit section EP and a first-level voltage in the remaining sections. When the k-th third gate signal EM[k] is a second-level voltage, the fifth transistor T5 and the sixth transistor T6 can be turned on, and when the k-th third gate signal EM[k] is a first-level voltage, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0137] The seventh transistor T7 of both odd-column pixels PXo and even-column pixels PXe can be configured to simultaneously receive the k-th fourth gate signal GB[k] from the fourth gate line GBL. The k-th fourth gate signal GB[k] can be a first-level voltage in the second initialization segment INT2 and a second-level voltage in the remaining segments. When the k-th fourth gate signal GB[k] is at the first-level voltage, the seventh transistor T7 can be turned on, and when the k-th fourth gate signal GB[k] is at the second-level voltage, the seventh transistor T7 can be turned off.

[0138] The data writing and compensation section DC can overlap with the second initialization section INT2, and within the overlapping section, the first level voltage of the k-th first gate signal GW[k] and the first level voltage of the k-th fourth gate signal GB[k] can overlap with each other. The first level voltage of the k-th first gate signal GW[k] and the first level voltage of the k-th second gate signal GI[k] can overlap with each other in the first data writing section DW1. The first level voltage of the k-th first gate signal GW[k] and the first level voltage of the (k+1)-th second gate signal GI[k+1] can overlap with each other in the second data writing section DW2.

[0139] In the first initialization segment INT1, the fourth transistor T4 of each of the odd-numbered pixel PXo and even-numbered pixel PXe can be turned on in response to the (k-1)th second gate signal GI[k-1] of the first level voltage. The gate voltage of the first transistor T1 can be initialized to the first initialization voltage Vint by the turned-on fourth transistor T4.

[0140] In the second initialization section INT2, the seventh transistor T7 of each of the odd-numbered pixel PXo and even-numbered pixel PXe can be turned on in response to the k-th fourth gate signal GB[k] of the first level voltage. The voltage of the pixel electrode of the organic light-emitting diode OLED can be initialized to the second initialization voltage Vaint by the turned-on seventh transistor T7.

[0141] In the data writing and compensation section DC, the second transistor T2 and the third transistor T3 of each of the odd-column pixels PXo and the even-column pixels PXe can be turned on in response to the k-th first gate signal GW[k] of the first level voltage. The first transistor T1 can be connected to a diode through the turned-on third transistor T3.

[0142] In the first data write segment DW1, the allocation transistor TD of the odd-numbered column pixels PXo can be turned on in response to the k-th second gate signal GI[k] of the first level voltage. The first data signal DATA1 supplied from the first data line DLo can be transmitted to the third node N3 through the turned-on allocation transistor TD and the second transistor T2. The voltage corresponding to the first data signal DATA1 and the threshold voltage Vth of the first transistor T1 can be stored in the capacitor Cst through the operation of the diode-connected first transistor T1. In the first data write segment DW1, the allocation transistor TD of the even-numbered column pixels PXe can be turned off in response to the (k+1)-th second gate signal GI[k+1] of the second level voltage.

[0143] In the second data write section DW2, the allocation transistor TD of even-numbered column pixels PXe can be turned on in response to the (k+1)th second gate signal GI[k+1] of the first level voltage. The second data signal DATA2 supplied from the second data line DLe can be transmitted to the third node N3 through the turned-on allocation transistor TD and the second transistor T2. The voltage corresponding to the second data signal DATA2 and the threshold voltage Vth of the first transistor T1 can be stored in the capacitor Cst through the operation of the diode-connected first transistor T1. In the second data write section DW2, the allocation transistor TD of odd-numbered column pixels PXo can be turned off in response to the kth second gate signal GI[k] of the second level voltage.

[0144] In the emission section EP, the fifth transistor T5 and the sixth transistor T6 of each of the odd-numbered pixel columns PXo and the even-numbered pixel columns PXe can be turned on in response to the k-th third gate signal EM[k] of the second voltage level. The current path from the driving voltage line PL to the organic light-emitting diode OLED can be formed by the turned-on fifth transistor T5 and sixth transistor T6. The organic light-emitting diode OLED can emit light with a brightness corresponding to the driving current output by the first transistor T1.

[0145] Figure 12 This is a schematic circuit diagram of odd-numbered and even-numbered pixel columns according to an embodiment. Figure 13 It is used to describe Figure 12 Timing diagram of operations on odd-numbered and even-numbered pixel columns.

[0146] According to an embodiment, the allocation transistor TD for odd-numbered column pixels PXo can be a P-type transistor, and the allocation transistor for even-numbered column pixels PXe can be an N-type transistor. The control line CSL connected to the allocation transistor TD can be a third gate line EML, and the control signal CS can be a third gate signal EM output by the third drive circuit 135.

[0147] refer to Figure 12 The output line OL can be connected to the first data line DLo and the second data line DLe. The first data line DLo is connected to the odd-numbered column pixels PXo, and the second data line DLe is connected to the even-numbered column pixels PXe. The data driving circuit can be configured to supply the first data signal DATA1 to the first data line DLo and the second data signal DATA2 to the second data line DLe via the output line OL.

[0148] refer to Figure 13The driving periods for odd-numbered pixel PXo and even-numbered pixel PXe may include a first initialization segment INT1, a second initialization segment INT2, a data write and compensation segment DC, and a transmission segment EP. The data write and compensation segment DC may include a first data write segment DW1 and a second data write segment DW2.

[0149] The second transistor T2 and the third transistor T3 of the odd-column pixel PXo and the even-column pixel PXe can be configured to simultaneously receive the k-th first gate signal GW[k] from the first gate line GWL. The k-th first gate signal GW[k] can be a first level voltage in the data writing and compensation segment DC, and a second level voltage in the remaining segment. The period during which the k-th first gate signal GW[k] maintains the first level voltage can be approximately a first level period 1H. When the k-th first gate signal GW[k] is at the first level voltage, the second transistor T2 and the third transistor T3 can be turned on, and when the k-th first gate signal GW[k] is at the second level voltage, the second transistor T2 and the third transistor T3 can be turned off.

[0150] The fourth transistor T4 of both odd-column pixels PXo and even-column pixels PXe can be configured to simultaneously receive the k-th second gate signal GI[k] from the second gate line GIL. The k-th second gate signal GI[k] can be a first-level voltage in the first initialization segment INT1 and a second-level voltage in the remaining segments. When the k-th second gate signal GI[k] is a first-level voltage, the fourth transistor T4 can be turned on, and when the k-th second gate signal GI[k] is a second-level voltage, the fourth transistor T4 can be turned off.

[0151] The third gate line EML may include gate line 3-1 EML1 and gate line 3-2 EML2. According to an embodiment, gate line 3-2 EML2 in row k may be connected to gate line 3-1 EML1 in row k+2.

[0152] The fifth transistor T5 and the sixth transistor T6 of the odd-column pixel PXo and the even-column pixel PXe can be configured to simultaneously receive the k-th third gate signal EM[k] from the 3-1 gate line EML1. The k-th third gate signal EM[k] can be a second-level voltage in the transmit section EP and a first-level voltage in the remaining sections. When the k-th third gate signal EM[k] is a second-level voltage, the fifth transistor T5 and the sixth transistor T6 can be turned on, and when the k-th third gate signal EM[k] is a first-level voltage, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0153] The allocation transistor TD for odd-column pixels PXo and even-column pixels PXe can be configured to simultaneously receive the (k+2)th third gate signal EM[k+2] from gate line EML2. The (k+2)th third gate signal EM[k+2] can be supplied with a specific time delay DT from the (k)th third gate signal EM[k]. The (k+2)th third gate signal EM[k+2] can be a first-level voltage in some portions from the second data write section DW2 to the transmit section EP, and a second-level voltage in the remaining portions.

[0154] When the (k+2)th third gate signal EM[k+2] is a second level voltage, the allocation transistor TD of the odd-numbered pixel PXo can be turned on, and the allocation transistor TD of the even-numbered pixel PXe can be turned off. When the (k+2)th third gate signal EM[k+2] is a first level voltage, the allocation transistor TD of the odd-numbered pixel PXo can be turned off, and the allocation transistor TD of the even-numbered pixel PXe can be turned on.

[0155] The seventh transistor T7 of both odd-column pixels PXo and even-column pixels PXe can be configured to simultaneously receive the k-th fourth gate signal GB[k] from the fourth gate line GBL. The k-th fourth gate signal GB[k] can be a first-level voltage in the second initialization segment INT2 and a second-level voltage in the remaining segments. When the k-th fourth gate signal GB[k] is at the first-level voltage, the seventh transistor T7 can be turned on, and when the k-th fourth gate signal GB[k] is at the second-level voltage, the seventh transistor T7 can be turned off.

[0156] The data writing and compensation section DC can overlap with the second initialization section INT2, and in the overlapping section, the first level voltage of the k-th first gate signal GW[k] and the first level voltage of the k-th fourth gate signal GB[k] can overlap with each other.

[0157] In the data writing and compensation section DC, the (k+2)th third gate signal EM[k+2] can change from a second level voltage to a first level voltage. The first level voltage of the kth first gate signal GW[k] and the second level voltage of the (k+2)th third gate signal EM[k+2] can overlap with each other in the first data writing section DW1. The first level voltage of the kth first gate signal GW[k] and the first level voltage of the (k+2)th third gate signal EM[k+2] can overlap with each other in the second data writing section DW2. The length of the segment in which the first level voltage of the kth first gate signal GW[k] and the second level voltage of the (k+2)th third gate signal EM[k+2] overlap with each other can be the same as the length of the segment in which the first level voltage of the kth first gate signal GW[k] and the first level voltage of the (k+2)th third gate signal EM[k+2] overlap with each other.

[0158] In the first initialization segment INT1, the fourth transistor T4 of each of the odd-column pixels PXo and even-column pixels PXe can be turned on in response to the k-th second gate signal GI[k] of the first level voltage. The gate voltage of the first transistor T1 can be initialized to the first initialization voltage Vint by the turned-on fourth transistor T4.

[0159] In the second initialization section INT2, the seventh transistor T7 of each of the odd-numbered pixel PXo and even-numbered pixel PXe can be turned on in response to the k-th fourth gate signal GB[k] of the first level voltage. The voltage of the pixel electrode of the organic light-emitting diode OLED can be initialized to the second initialization voltage Vaint by the turned-on seventh transistor T7.

[0160] In the data writing and compensation section DC, the second transistor T2 and the third transistor T3 of each of the odd-column pixels PXo and the even-column pixels PXe can be turned on in response to the k-th first gate signal GW[k] of the first level voltage. The first transistor T1 can be connected to a diode through the turned-on third transistor T3.

[0161] In the first data write segment DW1, in response to the (k+2)th third gate signal EM[k+2] of the second level voltage, the allocation transistor TD of the odd-numbered column pixel PXo can be turned on, and the allocation transistor TD of the even-numbered column pixel PXe can be turned off. The first data signal DATA1 supplied from the first data line DLo can be transmitted to the third node N3 through the turned-on allocation transistor TD of the odd-numbered column pixel PXo and the second transistor T2. The voltage corresponding to the threshold voltage Vth of the first data signal DATA1 and the first transistor T1 can be stored in the capacitor Cst through the operation of the diode-connected first transistor T1.

[0162] In the second data write section DW2, in response to the (k+2)th third gate signal EM[k+2] of the first level voltage, the allocation transistor TD of the even-numbered column pixel PXe can be turned on, and the allocation transistor TD of the odd-numbered column pixel PXo can be turned off. The second data signal DATA2 supplied from the second data line DLe can be transmitted to the third node N3 through the turned-on allocation transistor TD of the even-numbered column pixel PXe and the second transistor T2. The voltage corresponding to the second data signal DATA2 and the threshold voltage Vth of the first transistor T1 can be stored in the capacitor Cst through the operation of the diode-connected first transistor T1.

[0163] In the emission section EP, the fifth transistor T5 and the sixth transistor T6 of each of the odd-numbered pixel columns PXo and the even-numbered pixel columns PXe can be turned on in response to the k-th third gate signal EM[k] of the second voltage level. The current path from the driving voltage line PL to the organic light-emitting diode OLED can be formed by the turned-on fifth transistor T5 and sixth transistor T6. The organic light-emitting diode OLED can emit light with a brightness corresponding to the driving current output by the first transistor T1.

[0164] According to an embodiment, odd-column pixels PXo and even-column pixels PXe may include allocation transistors TD having the same conductivity type. While the first gate signal GW is being supplied, the allocation transistors TD can be alternately turned on at different timing points by using a second gate signal GI or a fourth gate signal GB. Therefore, the odd-column data signal DATA and the even-column data signal DATA supplied from the output line OL can be sequentially supplied to the odd-column pixels PXo and the even-column pixels PXe.

[0165] According to an embodiment, odd-column pixels PXo and even-column pixels PXe may include allocation transistors TD that have different conductivity types from each other. While the first gate signal GW is being supplied, the allocation transistors TD can be alternately turned on at different timing points by using a third gate signal EM. Therefore, the odd-column data signal DATA and the even-column data signal DATA supplied from the output line OL can be sequentially supplied to the odd-column pixels PXo and the even-column pixels PXe.

[0166] The display device according to an embodiment may include allocation transistors in pixels, and therefore, data lines DL1 to DLm can be selectively connected to pixel circuitry. Thus, two or more data signals supplied via one output line can be supplied to two or more data lines in a time-division manner. Accordingly, there is no need to provide additional drive circuitry configured to supply data signals between the data drive circuitry and the data lines in a time-division manner, and therefore, the peripheral area can be reduced and manufacturing costs can be lowered.

[0167] According to the display device of the embodiment, for the control signals of the allocation transistors used to control the odd-numbered and even-numbered columns of pixels, the gate signals of the transistors supplied to the pixel circuits can be used, and therefore, power consumption can be reduced without the need to supply additional control signals. According to the above embodiment, in the display device, two data lines arranged in two columns are connected to one output line. However, the embodiment is not limited to this. For example, three or more data lines arranged in three or more columns can be connected to one output line, and the allocation transistors of the pixels arranged in three or more columns can be sequentially turned on using three or more gate signals, each having a time difference delay, so that the gate turn-on voltages do not overlap, and therefore, data signals can be supplied to the three or more columns in a time-division manner.

[0168] The display device according to the embodiments can be implemented as an electronic device such as a smartphone, cellular phone, smartwatch, navigation device, game console, television (TV), in-vehicle unit, laptop computer, tablet computer, personal media player (PMP), personal digital assistant (PDA), etc. Furthermore, the electronic device can be a flexible device.

[0169] According to embodiments, the number of output lines of the data driving circuit can be reduced, and therefore, the manufacturing cost of the display device can be reduced. However, the above effects do not limit the scope of this disclosure.

[0170] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although embodiments have been described with reference to the figures, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: The first pixel is placed in an odd-numbered column; as well as The second pixel is arranged in an even-numbered column and in the same row as the first pixel, wherein each of the first pixel and the second pixel includes: Light-emitting diode; The first transistor is configured to output a current corresponding to the data signal; The second transistor transmits the data signal to the first transistor; and A distribution transistor is connected between the second transistor and a data line configured to supply the data signal. Specifically, when the second transistor of the first pixel and the second transistor of the second pixel are activated simultaneously, the allocation transistor of the first pixel and the allocation transistor of the second pixel are activated sequentially.

2. The display device according to claim 1, further comprising: The first data line is connected to the first pixel; The second data line is connected to the second pixel; The output line is connected to the first data line and the second data line; as well as A drive circuit is connected to the output line and configured to supply the data signal through the output line.

3. The display device according to claim 1, wherein, Each of the first pixel and the second pixel further includes: The third transistor is connected to the gate of the first transistor and the first terminal of the first transistor; A fourth transistor is connected to the gate of the first transistor and the first initialization voltage line; The fifth transistor is connected to the drive voltage line and the first terminal of the first transistor; The sixth transistor is connected to the second terminal of the first transistor and the light-emitting diode; The seventh transistor is connected to the light-emitting diode and the second initialization voltage line; and A capacitor is connected to the gate of the first transistor and the light-emitting diode.

4. The display device according to claim 3, wherein, The first transistor of each of the first pixel and the second pixel is connected to the light-emitting diode, and The first transistor further includes a back gate facing the gate of the first transistor.

5. The display device according to claim 3, further comprising: A first gate line is configured to supply a first gate signal to the second transistor and the third transistor of the first pixel, and to supply a first gate signal to the second transistor and the third transistor of the second pixel; The second gate line is configured to supply a second gate signal to the fourth transistor of the first pixel and the fourth transistor of the second pixel; The third gate line is configured to supply a third gate signal to the fifth and sixth transistors of the first pixel and to the fifth and sixth transistors of the second pixel; as well as A fourth gate line is configured to supply a fourth gate signal to the seventh transistor of the first pixel and the seventh transistor of the second pixel.

6. The display device according to claim 5, wherein, The conductivity type of the allocation transistor of the first pixel is the same as that of the allocation transistor of the second pixel.

7. The display device according to claim 6, wherein, The fourth gate signal supplied to the seventh transistor of the second pixel is delayed from the fourth gate signal supplied to the seventh transistor of the first pixel. The fourth gate signal supplied to the seventh transistor of the first pixel and the fourth gate signal supplied to the allocation transistor of the first pixel have the same timing sequence, and The fourth gate signal of the seventh transistor supplied to the second pixel and the fourth gate signal of the allocation transistor supplied to the second pixel have the same timing.

8. The display device according to claim 7, wherein, The first gate signal is the voltage level used to activate the second transistor. The time period includes a first sub-time period and a second sub-time period after the first sub-time period. The fourth gate signal is the time period during which the voltage level of the allocation transistor used to activate the first pixel overlaps with the first sub-time period. The fourth gate signal is the time period during which the level voltage of the allocation transistor used to activate the second pixel overlaps with the second sub-time period, and The fourth gate signal being the time period of the level voltage used to activate the allocation transistor of the first pixel and the time period of the fourth gate signal being the level voltage used to activate the allocation transistor of the second pixel do not overlap with each other.

9. The display device according to claim 6, wherein, A first-second gate signal, delayed from the second gate signal supplied to the fourth transistor of the first pixel, is supplied to the allocation transistor of the first pixel. A second-second gate signal, delayed from the second gate signal supplied to the fourth transistor of the second pixel, is supplied to the allocation transistor of the second pixel. The second gate signal supplied to the fourth transistor of the first pixel and the second gate signal supplied to the fourth transistor of the second pixel have the same timing. The second-second gate signal supplied to the allocation transistor of the second pixel is delayed from the first-second gate signal supplied to the allocation transistor of the first pixel.

10. The display device according to claim 9, wherein, The first gate signal is the voltage level used to activate the second transistor. The time period includes a first sub-time period and a second sub-time period after the first sub-time period. The first-second gate signal is the time period during which the voltage level of the allocated transistor for activating the first pixel overlaps with the first sub-time period. The second-second gate signal is the time period during which the voltage level of the allocated transistor used to activate the second pixel overlaps with the second sub-time period, and The first-second gate signal is the time period of the level voltage used to activate the allocation transistor of the first pixel, and the second-second gate signal is the time period of the level voltage used to activate the allocation transistor of the second pixel, which do not overlap with each other.

11. The display device according to claim 10, wherein, The period during which the fourth gate signal is the voltage level used to activate the seventh transistor overlaps with the period during which the first gate signal is the voltage level used to activate the second transistor.

12. The display device according to claim 5, wherein, The conductivity type of the allocation transistor of the first pixel is different from that of the allocation transistor of the second pixel.

13. The display device according to claim 12, wherein, A first-third gate signal, delayed from the third gate signal supplied to the fifth transistor of the first pixel, is supplied to the allocation transistor of the first pixel and the allocation transistor of the second pixel.

14. The display device according to claim 13, wherein, During the period in which the first gate signal is the level voltage used to activate the second transistor, the voltage levels of the first-third gate signals supplied to the allocation transistor of the first pixel and the allocation transistor of the second pixel are changed.

15. The display device according to claim 14, wherein, The period during which the fourth gate signal is the voltage level used to activate the seventh transistor overlaps with the period during which the first gate signal is the voltage level used to activate the second transistor.

16. The display device according to claim 12, wherein, The fifth transistor has a different conductivity type than the second transistor.

17. A display device, comprising: The pixel region includes a first pixel arranged in an odd-numbered column and a second pixel arranged in an even-numbered column and in the same row as the first pixel; as well as A gate driving circuit is configured to output a gate signal to the first pixel and the second pixel, wherein each of the first pixel and the second pixel includes: Light-emitting diode; The first transistor is configured to output a current corresponding to the data signal; The second transistor transmits the data signal to the first transistor and is configured to receive the first gate signal; and A distribution transistor is connected between the second transistor and a data line configured to supply the data signal, and is configured to receive a second gate signal. Wherein, the conductivity type of the allocation transistor of the first pixel is the same as the conductivity type of the allocation transistor of the second pixel. The second gate signal output from the gate driving circuit to the allocation transistor of the second pixel is delayed from the second gate signal output to the allocation transistor of the first pixel, and During a first sub-period in which the second transistors of the first pixel and the second pixel are simultaneously activated in response to the first gate signal output by the gate driving circuit, the allocation transistor of the first pixel is activated and the allocation transistor of the second pixel is not activated, and during a second sub-period in the same period, the allocation transistor of the first pixel is not activated and the allocation transistor of the second pixel is activated.

18. The display device according to claim 17, further comprising: The first data line is connected to the first pixel; The second data line is connected to the second pixel; The output line is connected to the first data line and the second data line; as well as A data driving circuit is connected to the output line and configured to supply the data signal through the output line.

19. A display device, comprising: The pixel region includes a first pixel arranged in an odd-numbered column and a second pixel arranged in an even-numbered column and in the same row as the first pixel; as well as A gate driving circuit is configured to output a gate signal to the first pixel and the second pixel, wherein each of the first pixel and the second pixel includes: Light-emitting diode; The first transistor is configured to output a current corresponding to the data signal; The second transistor transmits the data signal to the first transistor and is configured to receive the first gate signal; and A distribution transistor is connected between the second transistor and a data line configured to supply the data signal, and is configured to receive a third gate signal. Wherein, the conductivity type of the allocation transistor of the first pixel is different from the conductivity type of the allocation transistor of the second pixel. During the period in which the second transistors of the first pixel and the second pixel are simultaneously activated in response to the first gate signal output by the gate driving circuit, the voltage level of the third gate signal output by the gate driving circuit is changed, and In the first sub-period of the time period, the allocation transistor of the first pixel is activated and the allocation transistor of the second pixel is not activated, and in the second sub-period of the time period, the allocation transistor of the first pixel is not activated and the allocation transistor of the second pixel is activated.

20. The display device according to claim 19, further comprising: The first data line is connected to the first pixel; The second data line is connected to the second pixel; The output line is connected to the first data line and the second data line; as well as A data driving circuit is connected to the output line and configured to supply the data signal through the output line.

21. An electronic device comprising a display device according to any one of claims 1 to 20.

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