Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided, the display device including: a substrate including a display area in which an emission area is arranged and a non-display area disposed around the display area; the circuit layer is arranged on the substrate; and an element layer disposed on the circuit layer and including a light emitting element disposed in the emission region. The circuit layer includes: a light emitting pixel driver electrically connected to the light emitting element and arranged in a first direction and a second direction; a data line extending in a second direction and transmitting a data signal to the light emitting pixel driver; a first auxiliary line extending in a first direction; a second auxiliary line extending in the second direction and adjacent to the data line; and auxiliary connection electrodes disposed between adjacent ones of the first auxiliary lines, and spaced apart from the adjacent first auxiliary lines.

Description

Technical Field

[0001] The disclosure relates to a display device and an electronic device including the display device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] Display devices may include flat panel displays such as liquid crystal displays, field emission displays, or light-emitting displays. Light-emitting displays may include organic light-emitting displays that include organic light-emitting elements, inorganic light-emitting displays that include inorganic light-emitting elements such as inorganic semiconductors, and micro-light-emitting displays or nano-light-emitting displays that include micro-light-emitting elements or nano-light-emitting elements.

[0004] Organic light-emitting display devices use light-emitting elements to display images, each of which includes a light-emitting layer formed of organic light-emitting materials. Compared to other display devices, organic light-emitting display devices using self-emissive elements can offer improved performance in terms of power consumption, response speed, luminous efficiency, brightness, or wide viewing angle.

[0005] The display surface of a display device may include a display area for displaying images and a non-display area surrounding the display area. Within the display area, emitting areas that emit light with various brightness and colors may be arranged. Summary of the Invention

[0006] The display device may include a light-emitting element disposed in the emission area and a light-emitting pixel driver electrically connected to the light-emitting element. The light-emitting pixel driver may supply driving current to the light-emitting element.

[0007] Each of the light-emitting pixel drivers may include a first transistor that generates a drive current and a second transistor electrically connected between a data line transmitting a data signal and the first transistor, and may also include transistors for selectively electrically connecting, initializing, or resetting some nodes.

[0008] When the channel portion of the first transistor comprises an oxide semiconductor, the width of the first transistor may be increased beyond a critical value to ensure the current characteristics of the first transistor, thereby increasing the width of each of the light-emitting pixel drivers.

[0009] Therefore, there may be limitations to increasing the performance or resolution of a display device.

[0010] The disclosed aspect may provide a display device that can achieve high resolution by improving the integration density of the light-emitting pixel drivers.

[0011] According to the disclosed aspects, a display device is provided, which may include: a substrate including a display area and a non-display area, an emitting area disposed in the display area, and a non-display area disposed around the display area; a circuit layer disposed on the substrate; and an element layer disposed on the circuit layer, and including light-emitting elements disposed in the emitting area. The circuit layer may include: a light-emitting pixel driver electrically connected to the light-emitting element and disposed in a first direction and a second direction; a data line extending in the second direction and transmitting data signals to the light-emitting pixel driver; a first auxiliary line extending in the first direction; a second auxiliary line extending in the second direction and adjacent to the data line; and an auxiliary connection electrode disposed between adjacent first auxiliary lines and spaced apart from adjacent first auxiliary lines.

[0012] The light-emitting pixel driver may include: a first light-emitting pixel driver, a second light-emitting pixel driver, a third light-emitting pixel driver, and a fourth light-emitting pixel driver, superimposed on a first data line in the data lines and arranged side-by-side in a second direction; and a fifth light-emitting pixel driver and a sixth light-emitting pixel driver, superimposed on a second data line in the data lines and arranged side-by-side with the first and second light-emitting pixel drivers respectively in a first direction, and adjacent to each other in a second direction. One of the adjacent first auxiliary lines may be superimposed on the first and fifth light-emitting pixel drivers, while the other of the adjacent first auxiliary lines may be superimposed on the second and sixth light-emitting pixel drivers. The adjacent first auxiliary lines may be adjacent to the boundary between the first and second light-emitting pixel drivers, and the boundary between the fifth and sixth light-emitting pixel drivers. One of the auxiliary connection electrodes may be superimposed on the boundary between the first and second light-emitting pixel drivers, and the other of the auxiliary connection electrodes may be superimposed on the boundary between the fifth and sixth light-emitting pixel drivers.

[0013] The first data line may include: a first main extension portion extending in a second direction; a first sub-protrusion portion protruding from the first main extension portion, superimposed on a first light-emitting pixel driver, and spaced apart from an auxiliary connection electrode; and a second sub-protrusion portion protruding from the first main extension portion, superimposed on a second light-emitting pixel driver, and spaced apart from an auxiliary connection electrode.

[0014] The data line and the second auxiliary line can be disposed on at least one insulating layer covering the first auxiliary line and the auxiliary connection electrode, and one of the second auxiliary lines can be adjacent to the second data line and superimposed on the fifth and sixth light-emitting pixel drivers. A second auxiliary line may include: a second main extension portion extending in a second direction; and a third sub-protrusion portion protruding from the second main extension portion and superimposed on another auxiliary connection electrode. The third sub-protrusion portion can be electrically connected to the other auxiliary connection electrode through an auxiliary connection hole.

[0015] The circuit layer may also include a first auxiliary connection line that extends from one of the adjacent first auxiliary lines in a second direction and is connected to another auxiliary connection electrode.

[0016] A first auxiliary line can be electrically connected to a second auxiliary line via a first auxiliary connecting line, another auxiliary connecting electrode, and an auxiliary connecting hole.

[0017] The circuit layer may further include data connection electrodes superimposed on the first sub-protrusion and the second sub-protrusion. The data line and the second auxiliary line may be disposed on at least one insulating layer covering the first auxiliary line, the auxiliary connection electrode and the data connection electrode, and each of the data connection electrodes may be electrically connected to the first data line through an auxiliary data connection hole.

[0018] The circuit layer may further include a second auxiliary connection line extending in a second direction from one of the adjacent first auxiliary lines and connecting to a data connection electrode in the data connection electrodes. A first auxiliary line may be electrically connected to a first data line via the second auxiliary connection line, a data connection electrode, and an auxiliary data connection via.

[0019] The data line and the second auxiliary line can be disposed on at least one insulating layer covering the first auxiliary line and the auxiliary connection electrode, and the auxiliary connection electrode can be electrically connected to the second auxiliary line through the auxiliary connection hole.

[0020] Another adjacent first auxiliary line in the first auxiliary line can be set to be adjacent to the boundary between the third and fourth light-emitting pixel drivers.

[0021] The display device may further include a display driving circuit that supplies data signals to the data lines. The circuit layer may also include data supply lines disposed in the non-display area and electrically connected between the data lines and the display driving circuit. A bypass area located on one side of the display area may include: a bypass intermediate area; a first bypass side area disposed alongside the bypass intermediate area in a first direction and contacting the non-display area; and a second bypass side area disposed between the bypass intermediate area and the first bypass side area. The data supply lines may extend to the bypass intermediate area and the second bypass side area. A first data line may be disposed in the first bypass side area, and a second data line may be disposed in the second bypass side area. A first auxiliary line may include a first bypass auxiliary line electrically connected to the first data line and a first transmission auxiliary line other than the first bypass auxiliary line. A second auxiliary line may include a second bypass auxiliary line electrically connected to the first bypass auxiliary line and adjacent to the second data line, and a second transmission auxiliary line other than the second bypass auxiliary line. The first data supply line that transmits the data signal of the first data line can be electrically connected to the first data line through a first bypass auxiliary line and a second bypass auxiliary line, and the second data supply line that transmits the data signal of the second data line can be directly connected and / or electrically connected to the second data line.

[0022] The circuit layer may further include: a first power line for transmitting a first power to a light-emitting pixel driver; a second power line for transmitting a second power to a light-emitting element; a reference voltage line for transmitting a reference voltage to a light-emitting pixel driver; and an initialization voltage line for transmitting an initialization voltage to a light-emitting pixel driver.

[0023] Each of the first and second transmission auxiliary lines can be electrically connected to one of the first power line, the second power line, the reference voltage line, and the initialization voltage line.

[0024] Each of the light-emitting pixel drivers may include: a first transistor; a second transistor electrically connected between the gate electrode of the first transistor and a data line; a third transistor electrically connected between the gate electrode of the first transistor and a reference voltage line; a fourth transistor electrically connected between a light-emitting element and an initialization voltage line; a fifth transistor electrically connected between the first electrode of the first transistor and a first power line; a sixth transistor electrically connected between the second electrode of the first transistor and a light-emitting element; a first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; and a second capacitor electrically connected between the first power line and the second electrode of the first transistor.

[0025] According to another aspect of the disclosure, an electronic device is provided, which may include: a display device for displaying images; a memory for storing applications; a processor for executing applications and transmitting image data signals and input control signals to the display device; and a power module for supplying power to the display device. The display device may include: a substrate including a display area and a non-display area, an emitting area disposed in the display area, and a non-display area disposed around the display area; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer, including light-emitting elements disposed in the emitting area. The circuit layer may include: a light-emitting pixel driver electrically connected to a light-emitting element and arranged in a first direction and a second direction; a data line extending in the second direction and transmitting data signals to the light-emitting pixel driver; a first bypassing auxiliary line extending in the first direction and electrically connected to a first data line in the data line adjacent to a non-display area in the first direction; a second bypassing auxiliary line extending in the second direction, adjacent to a second data line in the data line and electrically connected to the first bypassing auxiliary line, the second data line being further away from the non-display area in the first direction than the first data line; and an auxiliary connection electrode disposed between two first bypassing auxiliary lines adjacent to each other in the second direction and spaced apart from the two first bypassing auxiliary lines.

[0026] The display device may further include a display driving circuit that supplies data signals to the data lines. The circuit layer may also include data supply lines disposed in the non-display area and electrically connected between the data lines and the display driving circuit. A bypass area located on one side of the display area may include: a bypass intermediate area; a first bypass side area disposed alongside the bypass intermediate area in a first direction and contacting the non-display area; and a second bypass side area disposed between the bypass intermediate area and the first bypass side area. The data supply lines may extend to the bypass intermediate area and the second bypass side area. A first data line may be disposed in the first bypass side area, and a second data line and a second bypass auxiliary line may be disposed in the second bypass side area. The first data supply line transmitting data signals of the first data line may be electrically connected to the first data line via the first and second bypass auxiliary lines, and the second data supply line transmitting data signals of the second data line may be directly connected and / or electrically connected to the second data line.

[0027] The light-emitting pixel drivers may include: a first light-emitting pixel driver, a second light-emitting pixel driver, a third light-emitting pixel driver, and a fourth light-emitting pixel driver, disposed in a first bypass side region, superimposed on one of the first data lines, and arranged side-by-side in a second direction; and a fifth light-emitting pixel driver and a sixth light-emitting pixel driver, disposed in the second bypass side region, superimposed on one of the second data lines and one of the second bypass auxiliary lines, and adjacent to each other in a second direction. The fifth and sixth light-emitting pixel drivers may be arranged side-by-side with the first and second light-emitting pixel drivers in a first direction. One of the two first bypass auxiliary lines may be superimposed on the first and fifth light-emitting pixel drivers, while the other of the two first bypass auxiliary lines may be superimposed on the second and sixth light-emitting pixel drivers. The two first bypass auxiliary lines may be adjacent to the boundary between the first and second light-emitting pixel drivers, and the boundary between the fifth and sixth light-emitting pixel drivers. One of the auxiliary connection electrodes can be superimposed on the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and the other auxiliary connection electrode can be superimposed on the boundary between the fifth light-emitting pixel driver and the sixth light-emitting pixel driver.

[0028] A data line and a second bypass auxiliary line may be disposed on at least one insulating layer covering the first bypass auxiliary line. A first data line may include: a first main extension portion extending in a second direction; a first sub-protrusion portion protruding from the first main extension portion, superimposed on a first light-emitting pixel driver and spaced apart from an auxiliary connection electrode; and a second sub-protrusion portion protruding from the first main extension portion, superimposed on a second light-emitting pixel driver and spaced apart from the same auxiliary connection electrode. A second bypass auxiliary line may include: a second main extension portion extending in a second direction; and a third sub-protrusion portion protruding from the second main extension portion and superimposed on another auxiliary connection electrode. The third sub-protrusion portion may be electrically connected to the other auxiliary connection electrode through an auxiliary connection hole.

[0029] The circuit layer may further include a first auxiliary connection line extending in a second direction from one of two first bypass auxiliary lines and connecting to the other auxiliary connection electrode. A first bypass auxiliary line may be electrically connected to a second bypass auxiliary line via the first auxiliary connection line, the other auxiliary connection electrode, and an auxiliary connection via.

[0030] The circuit layer may further include: a data connection electrode, stacked with the first sub-protrusion and the second sub-protrusion, and electrically connected to a first data line via an auxiliary data connection hole; and a second auxiliary connection line, extending from a first bypass auxiliary line in a second direction, and connected to one of the data connection electrodes. A first bypass auxiliary line may be electrically connected to a first data line via the second auxiliary connection line, a data connection electrode, and the auxiliary data connection hole. Attached Figure Description

[0031] These and other aspects, features, and advantages of the embodiments will become more apparent and readily understood from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic perspective view of a display device according to an embodiment; Figure 2 yes Figure 1 A schematic plan view of the display device; Figure 3 It is along Figure 2 A schematic cross-sectional view taken by line A-A'; Figure 4 yes Figure 2 A schematic layout diagram of part B; Figure 5 According to the embodiments Figure 4 A schematic equivalent circuit diagram of the light-emitting pixel driver; Figure 6 It is shown Figure 5 A schematic cross-sectional view of the first transistor, the second transistor, the sixth transistor, the first capacitor, the second capacitor, and the light-emitting element; Figure 7 According to the embodiments Figure 3 A schematic plan view of the base; Figure 8 yes Figure 7 A schematic layout diagram of the circuit layers in part C; Figure 9 yes Figure 7 A schematic layout diagram of the circuit layers in part D; Figure 10 According to the embodiments Figure 8 A schematic plan view of part E; Figure 11 It is along Figure 10 A schematic cross-sectional view taken by line G-G'; Figure 12 According to the embodiments Figure 9 A schematic plan view of part F; Figure 13 According to the embodiments Figure 8A schematic plan view of part E; Figure 14 According to the embodiments Figure 9 A schematic plan view of part F; Figure 15 A block diagram of an electronic device according to embodiments of the present disclosure; and Figure 16 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0032] The disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The various embodiments are not necessarily exclusive, nor are they intended to limit the disclosure. For example, a particular shape, construction (configuration), and characteristic of an embodiment may be used or implemented in another embodiment.

[0033] In the accompanying drawings, the size, thickness, ratio, and dimensions of elements may be exaggerated for ease of description and clarity. The same reference numerals and / or figure marks always denote the same elements.

[0034] Some parts that are not relevant to the description may be omitted in order to describe the disclosed embodiments.

[0035] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood as equivalent to "and / or".

[0036] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one of the group consisting of…”. For example, “at least one of A and B” can be understood to mean “A, B or A and B”.

[0037] When an element, layer, region, or portion is referred to as being "on," "connected to," or "bonded to" another element or layer, the element, layer, region, or portion may be directly on, directly connected to, or directly bonded to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without an intermediary element.

[0038] The phrase "in a plan view" refers to viewing a portion of an object from above, while the phrase "in a schematic sectional view" refers to viewing a schematic section taken by vertically cutting through a portion of the object and viewed from the side. The term "overlay" or variations thereof means that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, as will be understood by those skilled in the art, the term "overlay" can include meanings such as stacking, overlapping, facing (facing), extending over, covering, or partially covering. The expression "not overlay" can include meanings such as "spaced apart from," "offset from," or "offset from," and any other suitable equivalent as will be understood by those skilled in the art. The terms "facing" and "facing" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can still be understood as indirectly opposite and facing each other.

[0039] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element or feature to another, as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the term “below” can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0040] When the terms “comprising,” “including,” “having,” and / or “possessing,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0041] It will be understood that although the terms “first,” “second,” “third,” etc., may be used here to describe various elements, these elements should not be limited by these terms. For ease of description and interpretation, these terms are used only to distinguish one element from another. For example, without departing from the scope of disclosure, a “first element” may be referred to as a “second element” or a “third element,” and similarly, a “second element” or a “third element” may be referred to as a “first element.”

[0042] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well.

[0043] As used herein, the terms “about” or “approximately” include the stated value and mean: within an acceptable deviation of the specific value as determined by one of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (e.g., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0044] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined in the specification.

[0045] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic perspective view of the display device 100 according to an embodiment. Figure 2 yes Figure 1 A schematic plan view of the display device 100. Figure 3 It is along Figure 2 A schematic cross-sectional view taken by line A-A'.

[0047] Reference Figure 1 and Figure 2The display device 100 can display moving or still images. The display device 100 can be used as a display screen in portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs) as well as in various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices.

[0048] Display device 100 can be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes (OLEDs), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, or a micro-light-emitting display device or nano-light-emitting display device using micro-LEDs or nano-LEDs. For example, the case where display device 100 is an organic light-emitting display device will be described below. However, this disclosure is not limited thereto and can also be applied to display devices including organic insulating materials, organic light-emitting materials, or metallic materials.

[0049] The display device 100 may be flat, but this disclosure is not limited thereto. For example, the display device 100 may include curved portions with constant or varying curvature at the left and right ends. The display device 100 may be flexible, such that it can be bent, folded, rolled up, or bent.

[0050] like Figures 1 to 3 As shown, the display device 100 includes a substrate 110.

[0051] The substrate 110 may include a main region MA corresponding to the display surface of the display device 100 and a sub-region SBA protruding from one side of the main region MA.

[0052] like Figure 2 As shown, the main area MA may include a display area DA located in the center area and a non-display area NDA located around the display area DA.

[0053] The display area DA can be shaped as a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. Each corner where the short side extending in the first direction DR1 intersects the long side extending in the second direction DR2 can be rounded to have a selected curvature, or it can be a right angle. The planar shape of the display area DA is not limited to a quadrilateral shape, but can also be other polygonal shapes, circular shapes, or elliptical shapes.

[0054] The non-display area NDA can be set at the edge of the main area MA and can surround the display area DA.

[0055] The subregion SBA can be extended from a portion of the side of the main region MA that extends in the first direction DR1 in the second direction DR2.

[0056] Subregion SBA may include curved regions BA deformed into curved shapes (see Figure 7 ).

[0057] Figure 2 and Figure 3 The display device 100 is shown in the case where a portion of the sub-region SBA is bent.

[0058] Subregion SBA may include a curved region BA deformed into a curved shape, and a first subregion SB1 disposed between one side of the main region MA and one side of the curved region BA (see...). Figure 7 ) and the second sub-region SB2 extending from the other side of the curved region BA (see Figure 7 ).

[0059] like Figure 3 As shown, in the case of bending of the bending region BA, the second sub-region SB2 can be placed on the rear surface of the display device 100 on the third-direction DR3 and can be superimposed on the main region MA.

[0060] The display driver circuit 200, configured as an integrated circuit chip, can be installed in the second sub-region SB2.

[0061] Circuit board 300 can be attached to one side of the second sub-region SB2.

[0062] The touch driver circuit 400, which is configured as an integrated circuit chip, can be mounted on the circuit board 300.

[0063] Reference Figure 3 The display device 100 according to the embodiment includes a substrate 110, a circuit layer 120 disposed on the substrate 110, and a component layer 130 disposed on the circuit layer 120.

[0064] The display device 100 according to an embodiment may further include a sealing layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the sealing layer 140. The display device 100 according to an embodiment may further include a polarizing layer 160 disposed on the touch sensor layer 150 to reduce the reflection of external light.

[0065] The substrate 110 may be made of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled up.

[0066] In another embodiment, the substrate 110 may be made of an insulating material such as glass.

[0067] The substrate 110 may include a main region MA and a sub-region SBA. The main region MA may include a display region DA and a non-display region NDA.

[0068] Component layer 130 may include components disposed in the emission region EA (see Figure 4 The light-emitting element LE in ) (see Figure 5 and Figure 6 ).

[0069] Circuit layer 120 may include a light-emitting pixel driver EPD electrically connected to the light-emitting element LE of element layer 130 (see [link to component layer 130]). Figure 4 ).

[0070] The sealing layer 140 may be disposed on the element layer 130 and may have a structure in which at least one organic layer is disposed between two or more inorganic layers.

[0071] The touch sensor layer 150 may include touch electrodes for sensing points in the main area MA where a person or object has touched the object by detecting signals that change according to the touch of a person or object.

[0072] The polarization layer 160 can prevent the degradation of image visibility due to the reflection of external light by blocking external light reflected from the touch sensor layer 150, the sealing layer 140, the component layer 130, the circuit layer 120 and their interfaces.

[0073] According to an embodiment, the display device 100 may further include a display driving circuit 200, which is configured as an integrated circuit chip and mounted on a sub-region SBA of the substrate 110.

[0074] The display driver circuit 200 can send data to the data line DL of the circuit layer 120 (see...). Figure 5 and Figure 6 Supply data signal Vdata (see) Figure 5 ).

[0075] According to an embodiment, the display device 100 may further include a circuit board 300 bonded to a sub-region SBA of the substrate 110. The circuit board 300 may be bonded to a pad (also known as a "soldering pad" or "soldering pad") disposed on the sub-region SBA of the substrate 110 using a low-resistance, high-reliability material such as anisotropic conductive film or SAP.

[0076] The touch driver circuit 400 can be mounted on the circuit board 300.

[0077] When the touch sensor layer 150 includes capacitive touch electrodes and sensing electrodes, the touch driving circuit 400 can detect a touch based on changes in capacitance. However, this is merely an example, and Figure 3 The touch sensor layer 150 and touch driving circuit 400 can use touch sensing methods other than capacitive methods.

[0078] Figure 4 yes Figure 2 A schematic layout diagram of part B.

[0079] Reference Figure 4 According to an embodiment, the display area DA of the display device 100 may include an emission area EA. The display area DA may also include non-emission areas disposed between the emission areas EA.

[0080] The light-emitting pixel drivers EPDs, each corresponding to the emitting region EA, can be arranged side-by-side in the display region DA along the first direction DR1 and the second direction DR2. The light-emitting pixel drivers EPDs can be electrically connected to the light-emitting elements LEs (see [reference]) arranged in the emitting region EA on the element layer 130. Figure 5 and Figure 6 ).

[0081] The emission region EA can have a rhomboid planar shape or a rectangular planar shape. However, this is merely an example, and the planar shape of the emission region EA according to the embodiment is not limited to this. Figure 4 The planar shape shown is illustrated. For example, the emission area EA can also have a polygonal shape such as a quadrilateral, pentagon, or hexagon, or it can have a circular or elliptical planar shape including curved edges.

[0082] The emission region EA may include a first emission region EA1 that emits light in a first band, a second emission region EA2 that emits light in a second band below the first band, and a third emission region EA3 that emits light in a third band below the second band.

[0083] For example, the first band can correspond to red and is in the range of approximately 600 nm to approximately 750 nm. The second band can correspond to green and is in the range of approximately 480 nm to approximately 560 nm. The third band can correspond to blue and is in the range of approximately 370 nm to approximately 460 nm.

[0084] The first launch area EA1 and the third launch area EA3 can be arranged alternately in the first direction DR1 or the second direction DR2.

[0085] The second launch area EA2 can be arranged side by side on either the first direction DR1 or the second direction DR2.

[0086] The second launch area EA2 can be adjacent to the first launch area EA1 and the third launch area EA3 on the diagonal directions DR4 and DR5 that intersect the first direction DR1 and the second direction DR2.

[0087] Among these emission regions EA, the first emission region EA1, the second emission region EA2, and the third emission region EA3 that are adjacent to each other can form pixels PX that display their respective brightness and color.

[0088] For example, each pixel PX can be a basic unit that displays various colors (including white) at a selected brightness level.

[0089] Each pixel PX may include at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 that are adjacent to each other. Therefore, each pixel PX can display various colors by mixing the light emitted from the adjacent first emission regions EA1 to the third emission regions EA3.

[0090] Figure 5 According to the embodiments Figure 4 A schematic equivalent circuit diagram of the light-emitting pixel driver EPD in the diagram.

[0091] Reference Figure 5 Circuit layer 120 (see Figure 3 It may include a first power line VDL that transmits a first power ELVDD to the light-emitting pixel driver EPD, a second power line ELVSS that transmits a second power to the light-emitting element LE, a reference voltage line VRL that transmits a reference voltage VREF to the light-emitting pixel driver EPD, and an initialization voltage line VAIL that transmits an initialization voltage VAINT.

[0092] Component layer 130 (see Figure 3 The light-emitting element LE can be electrically connected between the light-emitting pixel driver EPD and the second power ELVSS.

[0093] For example, one of the light-emitting elements LE can be electrically connected between one of the light-emitting pixel drivers EPD in circuit layer 120 and the second power ELVSS.

[0094] The second power supply, ELVSS, can be at a lower voltage level than the first power supply, ELVDD.

[0095] For example, the anode of the light-emitting element LE can be electrically connected to the light-emitting pixel driver EPD, and a second power ELVSS having a voltage level lower than the first power ELVDD can be applied to the cathode of the light-emitting element LE.

[0096] The capacitor Cel connected in parallel with the light-emitting element LE can be a parasitic capacitor between the anode and the cathode.

[0097] The circuit layer 120 may include a scan write line GWL for transmitting a scan write signal GW, a reset control line GRL for transmitting a reset control signal GR, a bias control line GBL for transmitting a bias control signal GB, a first transmit control line ECL1 for transmitting a first transmit control signal EC1, and a second transmit control line ECL2 for transmitting a second transmit control signal EC2.

[0098] The light-emitting pixel driver EPD of circuit layer 120 may include a first transistor T1 that generates a drive current for driving the light-emitting element LE, two or more transistors T2 to T6 electrically connected to the first transistor T1, and one or more capacitors C1 and C2.

[0099] The second transistor T2 can be electrically connected between the gate electrode of the first transistor T1 and the data line DL.

[0100] The second transistor T2 can be turned on by the scan write signal GW of the scan write line GWL.

[0101] When the second transistor T2 is turned on, the data signal Vdata from the data line DL can be transmitted to the gate electrode of the first transistor T1.

[0102] When the voltage difference between the gate electrode and the second electrode of the first transistor T1 becomes greater than the threshold voltage of the first transistor T1 due to the data signal Vdata transmitted to the gate electrode of the first transistor T1, the first transistor T1 can be turned on. Therefore, the drain-source current of the first transistor T1 can be generated in proportion to the data signal Vdata.

[0103] The third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the reference voltage line VRL.

[0104] The third transistor T3 can be turned on by the reset control signal GR of the reset control line GRL.

[0105] When the third transistor T3 is turned on, the potential of the gate electrode of the first transistor T1 can be reset to the reference voltage VREF of the reference voltage line VRL.

[0106] The fourth transistor T4 can be electrically connected between the light-emitting element LE and the initialization voltage line VAIL.

[0107] The fourth transistor T4 can be turned on by the bias control signal GB of the bias control line GBL.

[0108] When the fourth transistor T4 is turned on, the potential of the anode of the light-emitting element LE can be initialized to the initial voltage VAINT of the initial voltage line VAIL.

[0109] The fifth transistor T5 can be electrically connected between the first electrode of the first transistor T1 and the first electric field line VDL.

[0110] The fifth transistor T5 can be turned on by the first transmit control signal EC1 of the first transmit control line ECL1.

[0111] When the fifth transistor T5 is turned on, the first power ELVDD of the first power line VDL can be transmitted to the first electrode of the first transistor T1.

[0112] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the light-emitting element LE.

[0113] The sixth transistor T6 can be turned on by the second emit control signal EC2 of the second emit control line ECL2.

[0114] When the sixth transistor T6 is turned on, the drain-source current generated by the first transistor T1 in proportion to the data signal Vdata can be transmitted to the light-emitting element LE through the sixth transistor T6.

[0115] Therefore, the light-emitting element LE can emit light at a brightness level corresponding to the data signal Vdata.

[0116] The first capacitor C1 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0117] Therefore, the first capacitor C1 can be charged with a voltage corresponding to the data signal Vdata transmitted to the gate electrode of the first transistor T1, and the first transistor T1 can be kept on for a selected time period by the voltage charged in the first capacitor C1.

[0118] The second capacitor C2 can be electrically connected between the second electrode of the first transistor T1 and the first power line VDL.

[0119] The voltage of the first capacitor C1 corresponding to the potential difference between the gate electrode and the second electrode of the first transistor T1 can vary based on the data signal Vdata, and can be divided by the second capacitor C2. Therefore, the threshold voltage of the first transistor T1 can be compensated.

[0120] According to an embodiment, the first transistor T1 may include a gate electrode and an auxiliary gate electrode facing each other on both sides of the channel portion.

[0121] The gate electrode of the first transistor T1 can be electrically connected to the second transistor T2.

[0122] The auxiliary gate electrode of the first transistor T1 can be electrically connected to the second electrode of the first transistor T1.

[0123] Therefore, when the first transistor T1 is turned on by the data signal Vdata transmitted to the gate electrode of the first transistor T1, the portion of the channel portion of the first transistor T1 that is adjacent to the auxiliary gate electrode and that is different from the portion of the channel portion of the first transistor T1 that is adjacent to the gate electrode may not be activated.

[0124] Therefore, since the electron mobility in the channel portion of the first transistor T1 decreases, the slope of the current curve representing the relationship between the gate voltage and the source-drain current of the first transistor T1 can become flatter. This allows for a wider driving voltage range for the first transistor T1, thereby improving the ease of brightness control.

[0125] like Figure 5 As shown, the first transistor T1 can be an N-type MOSFET. At least some of the second transistors T2 to the sixth transistor T6 can be P-type MOSFETs. For example, the fifth transistor T5 and the sixth transistor T6 can be P-type MOSFETs, and the second transistor T2, the third transistor T3, and the fourth transistor T4 can be N-type MOSFETs.

[0126] Therefore, according to an embodiment, circuit layer 120 may include a first semiconductor layer for setting a P-type MOSFET (e.g., Figure 6 CH6, E16, and E26) and a second semiconductor layer for setting up the N-type MOSFET (e.g., Figure 6 CH1, E11, E21, CH2, E12, and E22).

[0127] Figure 6 It is shown Figure 5 A schematic cross-sectional view of the first transistor T1, the second transistor T2, the sixth transistor T6, the first capacitor C1, the second capacitor C2, and the light-emitting element LE.

[0128] Reference Figure 6 The display device 100 according to the embodiment may include a substrate 110, a circuit layer 120 on the substrate 110 and a component layer 130 on the circuit layer 120.

[0129] The display device 100 may also include a sealing layer 140 on the component layer 130.

[0130] According to an embodiment, circuit layer 120 may include a first semiconductor layer (e.g., CH6, E16, and E26) disposed on substrate 110, a first gate insulating layer 122 covering the first semiconductor layer (e.g., CH6, E16, and E26), a first gate conductive layer (e.g., G6, ECL2, VDAL, and CAE1) disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer (e.g., G6, ECL2, VDAL, and CAE1), a second gate conductive layer (e.g., CAE2) disposed on the second gate insulating layer 123, a second gate conductive layer (e.g., CAE2) disposed on the second gate conductive layer 123, a first interlayer insulating layer 124 covering the second gate conductive layer (e.g., CAE2), a second semiconductor layer (e.g., CH1, E11, E21, CH2, E12, and E22) disposed on the first interlayer insulating layer 124, and a second semiconductor layer covering the second semiconductor layer. The third gate insulating layer 125 (e.g., CH1, E11, E21, CH2, E12, and E22), the third gate conductive layer (e.g., G1 and G2) disposed on the third gate insulating layer 125, the second interlayer insulating layer 126 covering the third gate conductive layer (e.g., G1 and G2), the first source-drain conductive layer (e.g., ANCE1, VDEL, NCE1, NCE2, and DCE) disposed on the second interlayer insulating layer 126, the first planarization layer 127 covering the first source-drain conductive layer (e.g., ANCE1, VDEL, NCE1, NCE2, and DCE), the second source-drain conductive layer (e.g., ANCE2, VDL, and DL) disposed on the first planarization layer 127, and the second planarization layer 128 covering the second source-drain conductive layer (e.g., ANCE2, VDL, and DL).

[0131] According to an embodiment, circuit layer 120 may further include a buffer layer 121 covering substrate 110. A first semiconductor layer (e.g., CH6, E16, and E26) may be disposed on buffer layer 121.

[0132] As shown above (refer to the reference) Figure 5 As described, the light-emitting pixel driver EPD may include a first transistor T1 and two or more transistors T2 to T6 electrically connected to the first transistor T1.

[0133] The first transistor T1 to the fourth transistor T4 can be N-type MOSFETs, and the fifth transistor T5 and the sixth transistor T6 can be P-type MOSFETs.

[0134] Each of the fifth transistor T5 and the sixth transistor T6, which are configured as P-type MOSFETs, may include a channel portion disposed in the first semiconductor layer, a first electrode and a second electrode, and a gate electrode disposed in the first gate conductive layer and superimposed on the channel portion.

[0135] For example, the first semiconductor layer may include a silicon semiconductor material such as polycrystalline silicon or amorphous silicon.

[0136] For example, the sixth transistor T6 may include a channel portion CH6 disposed in the first semiconductor layer, a first electrode E16 disposed in the first semiconductor layer and connected to one side of the channel portion CH6, a second electrode E26 disposed in the first semiconductor layer and connected to the other side of the channel portion CH6, and a gate electrode G6 disposed in the first gate conductive layer and stacked with the channel portion CH6.

[0137] The fifth transistor T5 can be the same P-type MOSFET as the sixth transistor T6, so its redundant description will be omitted below.

[0138] Each of the first transistor T1 to the fourth transistor T4, configured as an N-type MOSFET, may include a channel portion disposed in a second semiconductor layer, a first electrode and a second electrode, and a gate electrode disposed in a third gate conductive layer and superimposed on the channel portion.

[0139] For example, the second semiconductor layer may include an oxide semiconductor material.

[0140] For example, the first transistor T1 may include a channel portion CH1 disposed in the second semiconductor layer, a first electrode E11 disposed in the second semiconductor layer and connected to one side of the channel portion CH1, a second electrode E21 disposed in the second semiconductor layer and connected to the other side of the channel portion CH1, and a gate electrode G1 disposed in the third gate conductive layer and superimposed on the channel portion CH1.

[0141] The upper surface of the channel portion CH1 of the first transistor T1 can face the gate electrode G1.

[0142] The lower surface of the channel portion CH1 of the first transistor T1 may face the second capacitor electrode CAE2, which is electrically connected to the second electrode E21 of the first transistor T1.

[0143] For example, the second capacitor electrode CAE2 can be the auxiliary gate electrode of the first transistor T1.

[0144] The second transistor T2 may include a channel portion CH2 disposed in a second semiconductor layer, a first electrode E12 disposed in the second semiconductor layer and connected to one side of the channel portion CH2, a second electrode E22 disposed in the second semiconductor layer and connected to the other side of the channel portion CH2, and a gate electrode G2 disposed in a third gate conductive layer and stacked with the channel portion CH2.

[0145] The first electrode E12 of the second transistor T2 can be electrically connected to the data line DL via the data connection electrode DCE.

[0146] The data connection electrode DCE can be disposed on the second interlayer insulating layer 126 in the first source-drain conductive layer, and can be electrically connected to the first electrode E12 of the second transistor T2 through the data connection hole DCH.

[0147] The data connection hole DCH can penetrate the second interlayer insulating layer 126 and the third gate insulating layer 125.

[0148] The data line DL can be disposed on the first planarization layer 127 in the second source-drain conductive layer, and can be electrically connected to the data connection electrode DCE through the auxiliary data connection hole DCAH that penetrates the first planarization layer 127.

[0149] The second electrode E22 of the second transistor T2 can be electrically connected to the gate electrode G1 of the first transistor T1 through the first node connection electrode NCE1.

[0150] The first node connecting electrode NCE1 can be disposed on the second interlayer insulating layer 126 in the first source-drain conductive layer.

[0151] The first node connection electrode NCE1 can be electrically connected to the gate electrode G1 of the first transistor T1 through the first node connection hole NCH1, electrically connected to the first capacitor electrode CAE1 through the second node connection hole NCH2, and electrically connected to the second electrode E22 of the second transistor T2 through the third node connection hole NCH3.

[0152] The first capacitor electrode CAE1 can be disposed on the first gate insulating layer 122 within the first gate conductive layer.

[0153] The second electrode E21 of the first transistor T1 can be electrically connected to the first electrode E16 of the sixth transistor T6 through the second node connection electrode NCE2.

[0154] The second node connecting electrode NCE2 can be disposed on the second interlayer insulating layer 126 within the first source-drain conductive layer.

[0155] The second node connection electrode NCE2 can be electrically connected to the second electrode E21 of the first transistor T1 through the fourth node connection hole NCH4, electrically connected to the second capacitor electrode CAE2 through the fifth node connection hole NCH5, and electrically connected to the first electrode E16 of the sixth transistor T6 through the sixth node connection hole NCH6.

[0156] The second capacitor electrode CAE2 can be disposed on the second gate insulating layer 123 within the second gate conductive layer.

[0157] Since the first capacitor electrode CAE1 is electrically connected to the gate electrode G1 of the first transistor T1 and the second capacitor electrode CAE2 is electrically connected to the second electrode E21 of the first transistor T1, the first capacitor C1 can be configured in the area where the first capacitor electrode CAE1 and the second capacitor electrode CAE2 are superimposed on each other.

[0158] The first electric field line VDL can be disposed on the first planarization layer 127 in the second source-drain conductive layer.

[0159] In order to apply the first power line ELVDD with relatively uniform resistance to the entire display area DA, the first power line VDL can be electrically connected to the first power auxiliary line VDAL and the first power extension line VDEL, which extend in the direction intersecting the first power line VDL.

[0160] The first power auxiliary line VDAL can be disposed on the first gate insulating layer 122 within the first gate conductive layer.

[0161] The first power extension line VDEL can be disposed on the second interlayer insulating layer 126 within the first source-drain conductive layer.

[0162] A portion of the second capacitor electrode CAE2 can be superimposed on the first power auxiliary line VDAL.

[0163] A portion of the first electrode E16 of the sixth transistor T6 may be superimposed with the first power auxiliary line VDAL.

[0164] The second capacitor electrode CAE2 can be electrically connected to the second electrode E21 of the first transistor T1 and the first electrode E16 of the sixth transistor T6.

[0165] Therefore, the second capacitor C2 can be configured by the region of each of the first electrode E16 and the second capacitor electrode CAE2 of the sixth transistor T6 that overlaps with the first power auxiliary line VDAL.

[0166] The second electrode E26 of the sixth transistor T6 can be electrically connected to the anode 131 of the light-emitting element LE through the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2.

[0167] The first anode connection electrode ANCE1 can be disposed on the second interlayer insulating layer 126 in the first source-drain conductive layer, and can be electrically connected to the second electrode E26 of the sixth transistor T6 through the first anode contact hole ANCH1.

[0168] The first anode contact hole ANCH1 can penetrate the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0169] The second anode connection electrode ANCE2 can be disposed on the first planarization layer 127 in the second source-drain conductive layer, and can be electrically connected to the first anode connection electrode ANCE1 through the second anode contact hole ANCH2 penetrating the first planarization layer 127.

[0170] The anode 131 can be disposed on the second planarization layer 128 and can be electrically connected to the second anode connection electrode ANCE2 through the third anode contact hole ANCH3 penetrating the second planarization layer 128.

[0171] The component layer 130 can be disposed on the circuit layer 120 and can include a light-emitting element LE corresponding to the emission region EA.

[0172] Each of the light-emitting elements LE may include an anode 131 and a cathode 134 facing each other, and a light-emitting layer 133 disposed between the anode 131 and the cathode 134.

[0173] For example, element layer 130 may include an anode 131 disposed in the emission region EA, a pixel defining layer 132 disposed in the non-emission region and covering the edge of the anode 131, an emissive layer 133 disposed on the anode 131, and a cathode 134 disposed on the emissive layer 133 and the pixel defining layer 132.

[0174] The pixel defining layer 132 may include a first pixel defining layer 1321 disposed on the second planarization layer 128, a second pixel defining layer 1322 disposed on the first pixel defining layer 1321, and a spacer layer 1323 disposed on a portion of the second pixel defining layer 1322.

[0175] For example, the first pixel defining layer 1321 may include a light-absorbing insulating material that absorbs light or a light-blocking insulating material that blocks light.

[0176] In another embodiment, each of the light-emitting elements LE may further include a first common layer disposed between the anode 131 and the light-emitting layer 133 and a second common layer disposed between the light-emitting layer 133 and the cathode 134.

[0177] Anode 131 can be disposed in each of the emission regions EA and can be electrically connected to the light-emitting pixel driver EPD of circuit layer 120. Anode 131 can also be referred to as pixel electrode.

[0178] The light-emitting layer 133 may include an organic light-emitting material that converts electron-hole pairs into light.

[0179] Cathode 134 can be positioned within the display area DA, which includes the emission area EA. Second power ELVSS (see...) Figure 5It can be commonly applied to cathode 134. Cathode 134 can also be referred to as the common electrode.

[0180] The sealing layer 140 can be disposed on the circuit layer 120 and can cover the component layer 130.

[0181] For example, the sealing layer 140 may include: a first sealing layer disposed on the element layer 130 and made of an inorganic insulating material; a second sealing layer disposed on the first sealing layer, stacked with the element layer 130, and made of an organic insulating material; and a third sealing layer disposed on the first sealing layer, covering the second sealing layer, and made of an inorganic insulating material.

[0182] Figure 7 According to the embodiments Figure 3 A schematic plan view of the base 110.

[0183] Reference Figure 7 According to an embodiment, the substrate 110 of the display device 100 includes a main region MA corresponding to the display surface and a sub-region SBA protruding from a portion of one side of the main region MA.

[0184] The main area MA includes the display area DA, which is mainly located in the center, and the non-display area NDA, which is located at the edge and surrounds the display area DA.

[0185] The display area DA may include a bypass area BYA located on the side adjacent to the sub-area SBA, and a normal area GA located in the area other than the bypass area BYA.

[0186] The bypass area BYA may include: a bypass middle area BMA, which is located in the middle of the first direction DR1; a first bypass side area BSA1, which is located side by side with the bypass middle area BMA in the first direction DR1 and contacts the non-display area NDA; and a second bypass side area BSA2, which is located between the bypass middle area BMA and the first bypass side area BSA1.

[0187] The first bypass side region BSA1 can be set to be closer to the corner of the base 110 than the bypass middle region BMA and the second bypass side region BSA2.

[0188] The first bypass side region BSA1 and the second bypass side region BSA2 can be located between each side of the bypass middle region BMA on the first direction DR1 and the non-display region NDA.

[0189] The normal region GA may include: a normal intermediate region GMA, which is connected to the bypass intermediate region BMA of the bypass region BYA in the second direction DR2; a first normal side region GSA1, which is connected to the first bypass side region BSA1 of the bypass region BYA in the second direction DR2; and a second normal side region GSA2, which is connected to the second bypass side region BSA2 of the bypass region BYA in the second direction DR2.

[0190] The non-display area NDA may include the gate drive circuit area GDRA in which the gate drive circuit is disposed.

[0191] The gate drive circuit region GDRA in the non-display area NDA can face the side of the display area DA that extends in the second direction DR2. However, this is just an example, and the gate drive circuit region GDRA can also be separated and disposed in a portion of the display area DA, instead of being disposed in the non-display area NDA.

[0192] The gate drive circuitry in the gate drive region (GDRA) can sequentially transmit gate signals to the gate lines. The gate lines may include the transmission scan write signal GW (see...). Figure 5 The scan write line GWL (see) Figure 5 ), transmit reset control signal GR (see Figure 5 The reset control line GRL (see) Figure 5 ), transmission bias control signal GB (see Figure 5 The bias control line GBL (see) Figure 5 ), transmit the first transmit control signal EC1 (see Figure 5 The first launch control line ECL1 (see) Figure 5 ) and transmit the second transmit control signal EC2 (see Figure 5 The second launch control line ECL2 (see) Figure 5 ).

[0193] The sub-region SBA may include a curved region BA that is transformed into a curved shape, a first sub-region SB1 located between one side of the curved region BA and the main region MA, and a second sub-region SB2 connected to the other side of the curved region BA.

[0194] When the curved region BA transforms into a curved shape, the second sub-region SB2 can be placed below the base 110 and superimposed on the main region MA.

[0195] The display driver circuit 200 can be set in the second sub-region SB2.

[0196] Joined to circuit board 300 (see Figure 3 The signal pad SPD can be set on the edge of the second sub-region SB2.

[0197] Figure 8 yes Figure 7 A schematic layout diagram of circuit layer 120 in part C. Figure 9 yes Figure 7 A schematic layout diagram of circuit layer 120 in part D.

[0198] Reference Figure 8 and Figure 9 The circuit layer 120 of the display device 100 according to the embodiment (see Figure 3 It may include: an emitting pixel driver EPD, electrically connected to element layer 130 (see...). Figure 3 The light-emitting element LE (see) Figure 5 ), and is arranged side by side on the first direction DR1 and the second direction DR2; the data line DL extends on the second direction DR2 and carries the data signal Vdata (see Figure 5 The data is transmitted to the light-emitting pixel driver EPD; a first auxiliary line ASL1 extends in the first direction DR1; and a second auxiliary line ASL2 extends in the second direction DR2 and is adjacent to the data line DL.

[0199] The first auxiliary line ASL1 may include a first detour auxiliary line BASL1 and a first transmission auxiliary line TASL1 other than the first detour auxiliary line BASL1. The first detour auxiliary line BASL1 is electrically connected to the first data line DL1 in the first direction DR1 that is adjacent to the non-display area NDA.

[0200] The second auxiliary line ASL2 may include a second detour auxiliary line BASL2 electrically connected to the first detour auxiliary line BASL1, and a second transmission auxiliary line TASL2 other than the second detour auxiliary line BASL2.

[0201] The second detour auxiliary line BASL2 can be adjacent to the second data line DL2, which is farther apart from the first data line DL1 and the non-display area NDA in the first direction DR1.

[0202] The first data line DL1 can be set in the first bypass side area BSA1.

[0203] The second data line DL2 and the second detour auxiliary line BASL2 can be set in the second detour side area BSA2.

[0204] The first detour auxiliary line BASL1 can be set in the first detour side area BSA1 and the second detour side area BSA2.

[0205] The data line DL may include a first data line DL1 disposed in the first bypass side region BSA1 and a second data line DL2 disposed in the second bypass side region BSA2.

[0206] According to an embodiment, the circuit layer 120 may further include a data supply line DSPL, which is disposed in the non-display area NDA and electrically connected between the display driving circuit 200 and the data line DL.

[0207] The data supply line DSPL can extend around the intermediate region BMA and the second bypass side region BSA2.

[0208] The data supply line DSPL may include a first data supply line DSPL1 that transmits data signals of a first data line DL1 and a second data supply line DSPL2 that transmits data signals of a second data line DL2.

[0209] The first data supply line DSPL1 can extend to the second bypass auxiliary line BASL2 in the second bypass side region BSA2, and can be electrically connected to the first data line DL1 through the second bypass auxiliary line BASL2 and the first bypass auxiliary line BASL1.

[0210] The second data supply line DSPL2 can extend to the second bypass side area BSA2 and can be directly connected and / or electrically connected to the second data line DL2.

[0211] As described above, since the first data supply line DSPL1 extends to the second bypass auxiliary line BASL2 in the second bypass side region BSA2, instead of extending to the first data line DL1 in the first bypass side region BSA1, the length of the first data supply line DSPL1 extension can be reduced. Therefore, the width of the area required to place the data supply line DSPL can be reduced, thereby reducing the width of the non-display area NDA.

[0212] Since the data supply line DSPL is not located in the portion of the non-display area NDA adjacent to the corner of the substrate 110, the width of the non-display area NDA can be further reduced.

[0213] The data line DL may also include a third data line DL3 disposed in the intermediate region BMA. The data supply line DSPL may also include a third data supply line DSPL3 that transmits the data signal of the third data line DL3.

[0214] The third data supply line DSPL3 can extend around the intermediate area BMA and can be directly connected and / or electrically connected to the third data line DL3.

[0215] The first detour guide line BASL1 can be set between the first data line DL1 and the second detour guide line BASL2.

[0216] The second detour auxiliary line BASL2 can be set between the first data supply line DSPL1 in the non-display area NDA and the first detour auxiliary line BASL1.

[0217] As described above, since the first detour guide line BASL1 and the second detour guide line BASL2 are only provided in the detour area BYA and the ends of the first detour guide line BASL1 and the second detour guide line BASL2 are provided in the display area DA, the visibility of the first detour guide line BASL1 and the second detour guide line BASL2 will be increased.

[0218] To prevent this, the first auxiliary line ASL1 may also include a first transmission auxiliary line TASL1 in addition to the first detour auxiliary line BASL1. The second auxiliary line ASL2 may also include a second transmission auxiliary line TASL2 in addition to the first detour auxiliary line BASL1.

[0219] Two of the first transmission auxiliary lines TASL1 can extend from both ends of the first detour auxiliary line BASL1 in the display area DA.

[0220] One of the second transmission auxiliary lines TASL2 can extend from one end of the second bypass auxiliary line BASL2 in the display area DA in a direction away from the sub-area SBA.

[0221] Since the second bypass auxiliary line BASL2 is only set in the second bypass side region BSA2, each of the first data line DL1 in the first bypass side region BSA1 and the third data line DL3 in the bypass intermediate region BMA can be adjacent to the second transmission auxiliary line TASL2.

[0222] According to an embodiment, each of the first transmission auxiliary line TASL1 and the second transmission auxiliary line TASL2 can be electrically connected to transmit the first power ELVDD (see embodiment). Figure 5 The first power line VDL (see) Figure 5 ), transmission of second power ELVSS (see Figure 5 The second power line, transmission initialization voltage VAINT (see) Figure 5 The initial voltage line VAIL (see) Figure 5 ) and the transmission reference voltage VREF (see Figure 5 The reference voltage line VRL (see) Figure 5 One of them. The resistance of the path through which power or constant voltage is transmitted can be reduced by using the first transmission auxiliary line TASL1 and the second transmission auxiliary line TASL2.

[0223] According to an embodiment, the circuit layer 120 may further include a first power line VDSPL and a second power line VSSPL disposed in the non-display area NDA and extending to the sub-area SBA.

[0224] The first power line VDSPL can transmit the first power ELVDD (see...). Figure 5 The second power line VSSPL can transmit a second power ELVSS (see...). Figure 5 ).

[0225] The first power line VDSPL can be electrically connected to the signal pad SPD located in the second sub-region SB2 (see...). Figure 7 The first power transmission ELVDD (see) Figure 5 The first power pad.

[0226] The second power line VSSPL can be electrically connected to the signal pad SPD located in the second sub-area SB2 (see...). Figure 7 The ELVSS used for transmitting the second power (see) Figure 5 The second power pad.

[0227] For example, at least some of the first transmission auxiliary lines TASL1 can be electrically connected to the second power line VSSPL.

[0228] At least some of the second transmission auxiliary lines TASL2 can be electrically connected to at least some of the first transmission auxiliary lines TASL1 and the second power line VSSPL.

[0229] According to an embodiment, circuit layer 120 may further include a first power ELVDD (see Figure 5 The first power line VDL is transmitted to the light-emitting pixel driver EPD.

[0230] The first power line VDL can extend in the second direction DR2 and can be electrically connected to the first power line VDSPL.

[0231] Each of the first power lines VDL can be positioned between two adjacent second auxiliary lines ASL2 in the first direction DR1.

[0232] According to an embodiment, circuit layer 120 may further include a reference voltage VREF (see...) Figure 5 The reference voltage line VRL is transmitted to the light-emitting pixel driver EPD.

[0233] The reference voltage line VRL can be extended in the second direction DR2.

[0234] Each of the reference voltage lines VRL can be positioned between two adjacent data lines DL on the first direction DR1.

[0235] Reference Figure 9 The first transmission auxiliary line TASL1 in the first auxiliary line ASL1 and the second transmission auxiliary line TASL2 in the second auxiliary line ASL2 can be set in the normal area GA.

[0236] Each of the first transmission auxiliary lines TASL1 can be electrically connected to at least some of the second transmission auxiliary lines TASL2.

[0237] like Figure 8 and Figure 9 As shown, according to an embodiment, two of the first auxiliary lines ASL1 can be configured to be adjacent to the boundary between two light-emitting pixel drivers EPDs that are adjacent to each other on the second direction DR2.

[0238] like Figure 8 As shown, the light-emitting pixel driver EPD may include a first light-emitting pixel driver EPD1, a second light-emitting pixel driver EPD2, a third light-emitting pixel driver EPD3 and a fourth light-emitting pixel driver EPD4 arranged side by side on the second direction DR2 and superimposed on the first data line DL1, and a fifth light-emitting pixel driver EPD5 and a sixth light-emitting pixel driver EPD6 that are adjacent to each other on the second direction DR2 and superimposed on the second data line DL2.

[0239] The fifth light-emitting pixel driver EPD5 can be arranged side by side with the first light-emitting pixel driver EPD1 on the first direction DR1, and the sixth light-emitting pixel driver EPD6 can be arranged side by side with the second light-emitting pixel driver EPD2 on the first direction DR1.

[0240] The first auxiliary line ASL1 may include two adjacent first auxiliary lines ASL1 that are adjacent to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, and the boundary between the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6.

[0241] For example, any two first bypassing auxiliary lines BASL1 in the first auxiliary line ASL1 may be adjacent to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, and the boundary between the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6.

[0242] Figure 10 According to the embodiments Figure 8 A schematic plan view of part E. Figure 11 It is along Figure 10 A schematic cross-sectional view taken by line G-G'. Figure 12 According to the embodiments Figure 9A schematic plan view of part F.

[0243] like Figure 10 and Figure 12 As shown, the circuit layer 120 of the display device 100 according to the embodiment may include an auxiliary connection electrode ACE, which is disposed between two adjacent first auxiliary lines ASL1 and spaced apart from the two adjacent first auxiliary lines ASL1.

[0244] like Figure 10 As shown, when two adjacent first auxiliary lines ASL1 are adjacent to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, and the boundary between the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6, one of the auxiliary connection electrodes ACE disposed between the two adjacent first auxiliary lines ASL1 can be superimposed on the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2. The other auxiliary connection electrode ACE disposed between the two adjacent first auxiliary lines ASL1 can be superimposed on the boundary between the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6.

[0245] According to an embodiment, any one of the first data lines DL1 disposed in the first bypass side region BSA1 can be superimposed with the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0246] The first data line DL1, which is superimposed with the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, may include: a first main extension portion MEX1 extending in a second direction DR2; a first sub-protrusion portion SPR1 protruding from the first main extension portion MEX1 and superimposed with the first light-emitting pixel driver EPD1; and a second sub-protrusion portion SPR2 protruding from the first main extension portion MEX1 and superimposed with the second light-emitting pixel driver EPD2.

[0247] Each of the first sub-protrusion SPR1 and the second sub-protrusion SPR2 can be spaced apart from an auxiliary connection electrode ACE that overlaps the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0248] Each of the first sub-protrusion SPR1 and the second sub-protrusion SPR2 can be spaced apart from two adjacent first auxiliary lines ASL1 of the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0249] According to an embodiment, the circuit layer 120 may further include a data connection electrode DCE stacked with the first sub-protrusion SPR1 and the second sub-protrusion SPR2.

[0250] Each of the data connection electrodes DCE can be electrically connected to the first data line DL1 via the auxiliary data connection hole DCAH.

[0251] like Figure 10 and Figure 12 As shown, according to an embodiment, each of the data lines DL may include a first main extension portion MEX1 and a first sub-protrusion portion SPR1 and a second sub-protrusion portion SPR2. The first sub-protrusion portion SPR1 and the second sub-protrusion portion SPR2 protrude from the first main extension portion MEX1 and are respectively stacked with two light-emitting pixel drivers EPDs that are adjacent to each other in the second direction DR2. The first sub-protrusion portion SPR1 and the second sub-protrusion portion SPR2 may be stacked with data connection electrodes DCE respectively. An auxiliary data connection hole DCAH may be formed between each of the first sub-protrusion portion SPR1 and the second sub-protrusion portion SPR2 and the data connection electrode DCE.

[0252] like Figure 10 As shown, according to an embodiment, any one of the second data lines DL2 disposed in the second bypass side region BSA2 can be superimposed with the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6.

[0253] One of the second auxiliary lines ASL2 can be superimposed with the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6, and can be adjacent to the second data line DL2.

[0254] The second auxiliary line ASL2, which is superimposed on the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6, may include: a second main extension portion MEX2, which extends in the second direction DR2; and a third sub-protrusion portion SPR3, which protrudes from the second main extension portion MEX2 and is superimposed on another auxiliary connection electrode ACE disposed at the boundary between the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6.

[0255] The third protruding part SPR3 can be electrically connected to another auxiliary connection electrode ACE through the auxiliary connection hole ACH.

[0256] For example, such as Figure 10 and Figure 12As shown, according to an embodiment, each of the second auxiliary lines ASL2 may include a second main extension portion MEX2 and a third sub-protrusion portion SPR3, the third sub-protrusion portion SPR3 protruding from the second main extension portion MEX2 and overlapping with the boundary between two adjacent light-emitting pixel drivers EPDs in the second direction DR2. The third sub-protrusion portion SPR3 may be overlapped with the auxiliary connection electrode ACE.

[0257] According to an embodiment, the auxiliary connection hole ACH can be selectively formed between the third sub-protrusion SPR3 and the auxiliary connection electrode ACE.

[0258] For example, according to an embodiment, the auxiliary connection hole ACH may not be formed on each of all auxiliary connection electrodes ACE, but may be selectively formed on some auxiliary connection electrodes ACE that electrically connect the first auxiliary line ASL1 and the second auxiliary line ASL2.

[0259] like Figure 10 and Figure 12 As shown in the embodiment, the circuit layer 120 may further include a first auxiliary connection line ACL1, which extends in the second direction DR2 from one of two adjacent first auxiliary lines ASL1 and connects to another auxiliary connection electrode ACE.

[0260] For example, another auxiliary connection electrode ACE, which is superimposed on the boundary between the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6, can be electrically connected to a second auxiliary line ASL2 through the auxiliary connection hole ACH, and can be electrically connected to a first auxiliary line ASL1 through the first auxiliary connection line ACL1.

[0261] Therefore, the first auxiliary line ASL1 can be electrically connected to the second auxiliary line ASL2 through the first auxiliary connection line ACL1, another auxiliary connection electrode ACE, and the auxiliary connection hole ACH.

[0262] For example, another auxiliary connection electrode ACE, which is superimposed on the boundary between the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6, can be electrically connected to a second bypass auxiliary line BASL2 through the auxiliary connection hole ACH, and can be electrically connected to a first bypass auxiliary line BASL1 through the first auxiliary connection line ACL1.

[0263] Therefore, the first bypass auxiliary line BASL1 can be electrically connected to the second bypass auxiliary line BASL2 through the first auxiliary connection line ACL1, another auxiliary connection electrode ACE, and the auxiliary connection hole ACH.

[0264] like Figure 10As shown, according to an embodiment, circuit layer 120 may further include a second auxiliary connection line ACL2, which extends in the second direction DR2 from one of two adjacent first auxiliary lines ASL1 and connects to one of the data connection electrodes DCE.

[0265] For example, one of the two data connection electrodes DCE disposed in the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 can be electrically connected to the first data line DL1 through the auxiliary data connection hole DCAH, and can be electrically connected to a first auxiliary line ASL1 through the second auxiliary connection line ACL2.

[0266] Therefore, the first auxiliary line ASL1 can be electrically connected to the first data line DL1 through the second auxiliary connection line ACL2, the data connection electrode DCE, and the auxiliary data connection hole DCAH.

[0267] According to an embodiment, circuit layer 120 may further include a reference voltage connection electrode VRCE superimposed on the reference voltage line VRL.

[0268] Reference Figure 11 The data line DL and the second auxiliary line ASL2 can be disposed on at least one insulating layer (i.e., the first planarization layer 127) covering the first auxiliary line ASL1, the auxiliary connection electrode ACE, the data connection electrode DCE, the first auxiliary connection line ACL1 and the second auxiliary connection line ACL2.

[0269] The first power line VDL and the reference voltage line VRL can also be disposed on at least one insulating layer (i.e., the first planarization layer 127).

[0270] For example, the data line DL, the second auxiliary line ASL2, the first power line VDL, and the reference voltage line VRL can be disposed on the first planarization layer 127 in the second source-drain conductive layer.

[0271] The first auxiliary line ASL1, the auxiliary connection electrode ACE, the data connection electrode DCE, the first auxiliary connection line ACL1, and the second auxiliary connection line ACL2 can be disposed on the second interlayer insulating layer 126 in the first source-drain conductive layer.

[0272] Each of the auxiliary connection hole ACH and the auxiliary data connection hole DCAH can penetrate the first planarization layer 127.

[0273] like Figure 12 As shown, according to an embodiment, each of the first transmission auxiliary lines TASL1 can be electrically connected to at least one second transmission auxiliary line TASL2 via a first auxiliary connection line ACL1, an auxiliary connection electrode ACE, and an auxiliary connection hole ACH.

[0274] As described above, according to the embodiment, only one auxiliary connection electrode ACE is disposed between two adjacent light-emitting pixel drivers EPD in the second direction DR2.

[0275] Even without setting two auxiliary connection electrodes ACE corresponding to the two light-emitting pixel drivers EPD that are adjacent to each other on the second direction DR2, each of the second auxiliary line ASL2 and the first data line DL1 can be electrically connected to the first auxiliary line ASL1 by selectively placing the first auxiliary connection line ACL1 and the second auxiliary connection line ACL2.

[0276] Therefore, the total number of auxiliary connection electrodes (ACEs) disposed in the display area DA can be reduced to half the total number of light-emitting pixel drivers (EPDs), thereby improving the integration density of the light-emitting pixel drivers (EPDs). This may be advantageous for achieving high resolution in the display device 100.

[0277] Figure 13 According to the embodiments Figure 8 A schematic plan view of part E. Figure 14 According to the embodiments Figure 9 A schematic plan view of part F.

[0278] Reference Figure 13 and Figure 14 Except that the auxiliary connection hole ACH is formed in each of all auxiliary connection electrodes ACE, rather than selectively formed in only some of the auxiliary connection electrodes ACE, the display device 100 according to the embodiment can be connected to... Figures 10 to 12 The display device 100 shown in the embodiments is basically the same, so its redundant description will be omitted below.

[0279] By eliminating the difference in light emission characteristics caused by the presence or absence of the auxiliary connection hole ACH, the degradation of the display quality of the display device 100 due to the auxiliary connection hole ACH can be prevented.

[0280] The display device according to one embodiment of the present disclosure can be applied to various electronic devices. An electronic device according to one embodiment of the present disclosure includes the aforementioned display device, and may further include modules or devices with additional functions in addition to the display device.

[0281] Figure 15 This is a block diagram of an electronic device 10 according to an embodiment of the present disclosure.

[0282] Reference Figure 15 An electronic device 10 according to one embodiment of the present disclosure may include a display module 21, a processor 22, a memory 23, and a power module 24.

[0283] The processor 22 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0284] The memory 23 can store the data information required for the operation of the processor 22 or the display module 21. When the processor 22 executes the application program stored in the memory 23, image data signals and / or input control signals are transmitted to the display module 21, which can process the received signals and output image information through the display screen.

[0285] The power module 24 may include a power module such as a power adapter or battery, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0286] At least one of the components of an electronic device 10 according to an embodiment of the present disclosure may be included in a display device 100 according to an embodiment of the present disclosure. Additionally, some modules that are functionally included in a single module may be included in the display device 100, while other modules may be disposed separately from the display device 100. For example, the display device 100 may include a display module 21, and the processor 22, memory 23, and power module 24 may be disposed as other devices within the electronic device 10 besides the display device 100.

[0287] Figure 16 This is a schematic diagram of electronic devices 10_1a to 10_1e, 10_2a to 10_2c and 10_3 according to various embodiments of the present disclosure.

[0288] Reference Figure 16 Various electronic devices employing the display device 100 according to embodiments of the present disclosure may include not only image display electronic devices (such as smartphones 10_1a, tablet PCs (personal computers) 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) that include display modules, as well as vehicle electronic devices 10_3 that include display modules (such as CIDs (central information displays) and interior mirror displays arranged on the dashboard, center console panel, and instrument panel of a car).

[0289] The display device according to the embodiment may include a circuit layer and a component layer disposed on a substrate.

[0290] The element layer may include light-emitting elements disposed in the emission region.

[0291] The circuit layer may include light-emitting elements electrically connected to the element layer and arranged in a first direction and a second direction, a data line extending in the second direction and transmitting data signals to the light-emitting pixel driver, a first auxiliary line extending in the first direction, a second auxiliary line extending in the second direction and adjacent to the data line, and an auxiliary connection electrode disposed between and spaced apart from the two adjacent first auxiliary lines.

[0292] The light-emitting pixel driver may include: a first light-emitting pixel driver, a second light-emitting pixel driver, a third light-emitting pixel driver and a fourth light-emitting pixel driver, which are superimposed on the first data line of the data line and arranged side by side in a second direction; and a fifth light-emitting pixel driver and a sixth light-emitting pixel driver, which are superimposed on the second data line of the data line, arranged side by side with the first light-emitting pixel driver and the second light-emitting pixel driver respectively in a first direction, and adjacent to each other in a second direction.

[0293] According to an embodiment, two adjacent first auxiliary lines may be adjacent to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and the boundary between the fifth light-emitting pixel driver and the sixth light-emitting pixel driver.

[0294] One of the auxiliary connection electrodes may be superimposed on the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver.

[0295] Another auxiliary connection electrode in the auxiliary connection electrode can be superimposed on the boundary between the fifth light-emitting pixel driver and the sixth light-emitting pixel driver.

[0296] According to an embodiment, the circuit layer may further include a first auxiliary connection line, which extends from one of two adjacent first auxiliary lines in a second direction and is connected to another auxiliary connection electrode.

[0297] Therefore, when another auxiliary connection electrode is electrically connected to one of the second auxiliary lines through an auxiliary connection hole, a first auxiliary line can be electrically connected to a second auxiliary line through the first auxiliary connection line and the auxiliary connection hole.

[0298] According to an embodiment, the circuit layer may further include: a data connection electrode, stacked with the light-emitting pixel driver and electrically connected to the first data line through an auxiliary data connection hole; and a second auxiliary connection line, extending from one of two adjacent first auxiliary lines in a second direction and connected to one of the data connection electrodes.

[0299] Therefore, a first auxiliary line can be electrically connected to the first data line via a second auxiliary connection line, a data connection electrode, and an auxiliary data connection hole.

[0300] As described above, according to the embodiment, even when only one auxiliary connection electrode, instead of two auxiliary connection electrodes, is disposed at the boundary between two adjacent light-emitting pixel drivers in the second direction, selective electrical connection between the first auxiliary line and the second auxiliary line can be achieved through the first auxiliary connection line, and selective electrical connection between the first auxiliary line and the first data line can be achieved through the second auxiliary connection line.

[0301] Therefore, since the number of auxiliary connection electrodes can be reduced by half, the integration density of the light-emitting pixel drivers can be increased, which may be advantageous for achieving high resolution in display devices.

[0302] However, the effects of the disclosure are not limited to those described herein. The above and other effects of the disclosure will become more apparent to those skilled in the art by referring to the claims.

[0303] Embodiments have been disclosed herein, and although terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, unless otherwise indicated, features, characteristics, and / or elements described in connection with the embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the disclosure set forth in the claims.

Claims

1. A display device, the display device comprising: A substrate includes a display area and a non-display area, wherein an emission area is arranged in the display area and the non-display area is disposed around the display area; A circuit layer is disposed on the substrate; as well as A component layer is disposed on the circuit layer and includes light-emitting elements disposed in the emission region. The circuit layer includes: A light-emitting pixel driver is electrically connected to the light-emitting element and is arranged in a first direction and a second direction; A data line extends in the second direction and transmits data signals to the light-emitting pixel driver; The first auxiliary line extends in the first direction; A second auxiliary line extends in the second direction and is adjacent to the data line; and An auxiliary connection electrode is disposed between adjacent first auxiliary lines in the first auxiliary line, and is spaced apart from the adjacent first auxiliary lines.

2. The display device according to claim 1, wherein, The light-emitting pixel driver includes: a first light-emitting pixel driver, a second light-emitting pixel driver, a third light-emitting pixel driver, and a fourth light-emitting pixel driver, which are superimposed on the first data line of the data line and arranged side by side in the second direction; and a fifth light-emitting pixel driver and a sixth light-emitting pixel driver, which are superimposed on the second data line of the data line and arranged side by side with the first light-emitting pixel driver and the second light-emitting pixel driver respectively in the first direction, and adjacent to each other in the second direction. One of the adjacent first auxiliary lines is superimposed on the first light-emitting pixel driver and the fifth light-emitting pixel driver. The other first auxiliary line in the adjacent first auxiliary lines is superimposed on the second light-emitting pixel driver and the sixth light-emitting pixel driver. The adjacent first auxiliary line is adjacent to the boundary between the first and second light-emitting pixel drivers, and the boundary between the fifth and sixth light-emitting pixel drivers. One of the auxiliary connection electrodes overlaps with the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and Another auxiliary connection electrode in the auxiliary connection electrode is superimposed on the boundary between the fifth light-emitting pixel driver and the sixth light-emitting pixel driver.

3. The display device according to claim 2, wherein, The first data line includes: The first main extension portion extends in the second direction; A first sub-protrusion, protruding from the first main extension, is superimposed on the first light-emitting pixel driver and spaced apart from the auxiliary connection electrode; and The second sub-protrusion protrudes from the first main extension, is superimposed on the second light-emitting pixel driver, and is spaced apart from the one auxiliary connection electrode.

4. The display device according to claim 3, wherein, The data line and the second auxiliary line are disposed on at least one insulating layer covering the first auxiliary line and the auxiliary connection electrode, and One of the second auxiliary lines is adjacent to the second data line and is superimposed on the fifth light-emitting pixel driver and the sixth light-emitting pixel driver. The second auxiliary line includes: a second main extension portion extending in the second direction; and a third sub-protrusion portion protruding from the second main extension portion and superimposed on the other auxiliary connection electrode. The third sub-protrusion portion is electrically connected to the other auxiliary connection electrode through an auxiliary connection hole.

5. The display device according to claim 4, wherein, The circuit layer further includes a first auxiliary connection line, which extends from one of the adjacent first auxiliary lines in the second direction and is connected to the other auxiliary connection electrode.

6. The display device according to claim 5, wherein, The first auxiliary line is electrically connected to the second auxiliary line through the first auxiliary connection line, the other auxiliary connection electrode, and the auxiliary connection hole.

7. The display device according to claim 3, wherein, The circuit layer also includes data connection electrodes stacked with the first sub-protrusion and the second sub-protrusion. The data line and the second auxiliary line are disposed on at least one insulating layer covering the first auxiliary line, the auxiliary connection electrode, and the data connection electrode, and Each of the data connection electrodes is electrically connected to the first data line via an auxiliary data connection port.

8. The display device according to claim 7, wherein, The circuit layer further includes a second auxiliary connection line extending from one of the adjacent first auxiliary lines in the second direction and connected to one of the data connection electrodes. The first auxiliary line is electrically connected to the first data line via the second auxiliary connection line, the data connection electrode, and the auxiliary data connection hole.

9. The display device according to claim 3, wherein, The data line and the second auxiliary line are disposed on at least one insulating layer covering the first auxiliary line and the auxiliary connection electrode, and The auxiliary connection electrode is electrically connected to the second auxiliary line through an auxiliary connection hole.

10. The display device according to claim 3, wherein, Another adjacent first auxiliary line in the first auxiliary line is configured to be adjacent to the boundary between the third light-emitting pixel driver and the fourth light-emitting pixel driver.

11. The display device according to claim 3, further comprising: The display driver circuit supplies the data signal to the data line. The circuit layer further includes a data supply line, which is disposed in the non-display area and electrically connected between the data line and the display driving circuit. The bypass area located on one side of the display area includes: a bypass middle area; a first bypass side area, arranged side-by-side with the bypass middle area in the first direction and contacting the non-display area; and a second bypass side area, disposed between the bypass middle area and the first bypass side area. The data supply line extends to the intermediate bypass area and the second bypass side area. The first data line is located in the first bypass side area. The second data line is located in the second bypass side area. The first auxiliary line includes a first bypass auxiliary line electrically connected to the first data line and a first transmission auxiliary line other than the first bypass auxiliary line. The second auxiliary line includes a second detour auxiliary line electrically connected to the first detour auxiliary line and adjacent to the second data line, and a second transmission auxiliary line other than the second detour auxiliary line. The first data supply line, which transmits the data signal of the first data line, is electrically connected to the first data line via the first bypass auxiliary line and the second bypass auxiliary line. The second data supply line, which transmits the data signal of the second data line, is directly connected to and electrically connected to the second data line.

12. The display device according to claim 11, wherein, The circuit layer also includes: A first power line transmits a first power to the light-emitting pixel driver; The second power line transmits the second power to the light-emitting element; A reference voltage line transmits a reference voltage to the light-emitting pixel driver; and The initial voltage line is initialized, and the initial voltage is transmitted to the light-emitting pixel driver.

13. The display device according to claim 12, wherein, Each of the first transmission auxiliary line and the second transmission auxiliary line is electrically connected to one of the first power line, the second power line, the reference voltage line, and the initialization voltage line.

14. The display device according to claim 12, wherein, Each of the light-emitting pixel drivers includes: First transistor; The second transistor is electrically connected between the gate electrode of the first transistor and one of the data lines; The third transistor is electrically connected between the gate electrode of the first transistor and the reference voltage line; The fourth transistor is electrically connected between one of the light-emitting elements and the initialization voltage line; The fifth transistor is electrically connected between the first electrode of the first transistor and the first electric field line; The sixth transistor is electrically connected between the second electrode of the first transistor and the light-emitting element; A first capacitor is electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; and The second capacitor is electrically connected between the first power line and the second electrode of the first transistor.

15. An electronic device, the electronic device comprising: Display device, displaying images; Memory, storage applications; The processor executes the application and transmits image data signals and input control signals to the display device; as well as The power module supplies power to the display device. The display device includes: a substrate comprising a display area and a non-display area, wherein an emitting area is disposed in the display area and the non-display area is disposed around the display area; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer and including light-emitting elements disposed in the emitting area. The circuit layer includes: A light-emitting pixel driver is electrically connected to the light-emitting element and is arranged in a first direction and a second direction; A data line extends in the second direction and transmits data signals to the light-emitting pixel driver; A first detour auxiliary line extends in the first direction and is electrically connected to a first data line in the data line that is adjacent to the non-display area in the first direction; A second bypassing auxiliary line extends in the second direction, is adjacent to a second data line among the data lines, and is electrically connected to the first bypassing auxiliary line, wherein the second data line is spaced further from the non-display area in the first direction than the first data line; and An auxiliary connection electrode is disposed between two first winding auxiliary lines that are adjacent to each other in the second direction, and is spaced apart from the two first winding auxiliary lines.

16. The electronic device according to claim 15, wherein, The display device further includes: The display driver circuit supplies the data signal to the data line. The circuit layer further includes a data supply line, which is disposed in the non-display area and electrically connected between the data line and the display driving circuit. The bypass area located on one side of the display area includes: a bypass middle area; a first bypass side area, arranged side-by-side with the bypass middle area in the first direction and contacting the non-display area; and a second bypass side area, disposed between the bypass middle area and the first bypass side area. The data supply line extends to the intermediate bypass area and the second bypass side area. The first data line is located in the first bypass side area. The second data line and the second detour auxiliary line are disposed in the second detour side area. The first data supply line, which transmits the data signal of the first data line, is electrically connected to the first data line via the first bypass auxiliary line and the second bypass auxiliary line. The second data supply line, which transmits the data signal of the second data line, is directly connected to and electrically connected to the second data line.

17. The electronic device according to claim 16, wherein, The light-emitting pixel driver includes: a first light-emitting pixel driver, a second light-emitting pixel driver, a third light-emitting pixel driver, and a fourth light-emitting pixel driver, disposed in the first bypass side region, superimposed on one of the first data lines, and arranged side-by-side in the second direction; and a fifth light-emitting pixel driver and a sixth light-emitting pixel driver, disposed in the second bypass side region, superimposed on one of the second data lines and one of the second bypass auxiliary lines, and adjacent to each other in the second direction. The fifth and sixth light-emitting pixel drivers are arranged side-by-side with the first and second light-emitting pixel drivers in the first direction. One of the two first bypass auxiliary lines is superimposed on the first light-emitting pixel driver and the fifth light-emitting pixel driver. The other of the two first bypassing auxiliary lines is superimposed on the second light-emitting pixel driver and the sixth light-emitting pixel driver. The two first bypass auxiliary lines are adjacent to the boundary between the first and second light-emitting pixel drivers, and the boundary between the fifth and sixth light-emitting pixel drivers. One of the auxiliary connection electrodes overlaps with the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and Another auxiliary connection electrode in the auxiliary connection electrode is superimposed on the boundary between the fifth light-emitting pixel driver and the sixth light-emitting pixel driver.

18. The electronic device according to claim 17, wherein, The data line and the second bypass auxiliary line are disposed on at least one insulating layer covering the first bypass auxiliary line. The first data line includes: a first main extension portion extending in the second direction; a first sub-protrusion portion protruding from the first main extension portion, superimposed on the first light-emitting pixel driver, and spaced apart from the auxiliary connection electrode; and a second sub-protrusion portion protruding from the first main extension portion, superimposed on the second light-emitting pixel driver, and spaced apart from the auxiliary connection electrode. The second bypass auxiliary line includes: a second main extension portion extending in the second direction; and a third sub-protrusion portion protruding from the second main extension portion and overlapping with the other auxiliary connection electrode. The third sub-protrusion is electrically connected to the other auxiliary connection electrode through an auxiliary connection hole.

19. The electronic device according to claim 18, wherein, The circuit layer further includes a first auxiliary connection line, which extends from one of the two first bypassing auxiliary lines in the second direction and connects to the other auxiliary connection electrode. The first bypass auxiliary line is electrically connected to the second bypass auxiliary line through the first auxiliary connecting line, the other auxiliary connecting electrode, and the auxiliary connecting hole.

20. The electronic device according to claim 18, wherein, The circuit layer also includes: A data connection electrode, overlapping the first sub-protrusion and the second sub-protrusion, and electrically connected to the first data line via an auxiliary data connection hole; and A second auxiliary connection line extends from one of the first bypass auxiliary lines in the second direction and connects to one of the data connection electrodes. The first bypass auxiliary line is electrically connected to the first data line via the second auxiliary connecting line, the data connecting electrode, and the auxiliary data connecting hole.

Images